amdgpu_drm.h revision 106b3a8a7dc03c19a45e322de425ac56aafac358
1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef __AMDGPU_DRM_H__ 20#define __AMDGPU_DRM_H__ 21#include "drm.h" 22#ifdef __cplusplus 23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24#endif 25#define DRM_AMDGPU_GEM_CREATE 0x00 26#define DRM_AMDGPU_GEM_MMAP 0x01 27#define DRM_AMDGPU_CTX 0x02 28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29#define DRM_AMDGPU_BO_LIST 0x03 30#define DRM_AMDGPU_CS 0x04 31#define DRM_AMDGPU_INFO 0x05 32#define DRM_AMDGPU_GEM_METADATA 0x06 33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 35#define DRM_AMDGPU_GEM_VA 0x08 36#define DRM_AMDGPU_WAIT_CS 0x09 37#define DRM_AMDGPU_GEM_OP 0x10 38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39#define DRM_AMDGPU_GEM_USERPTR 0x11 40#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 41#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 42#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 45#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 46#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 47#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 50#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 51#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 52#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 55#define AMDGPU_GEM_DOMAIN_CPU 0x1 56#define AMDGPU_GEM_DOMAIN_GTT 0x2 57#define AMDGPU_GEM_DOMAIN_VRAM 0x4 58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59#define AMDGPU_GEM_DOMAIN_GDS 0x8 60#define AMDGPU_GEM_DOMAIN_GWS 0x10 61#define AMDGPU_GEM_DOMAIN_OA 0x20 62#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 65#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 66struct drm_amdgpu_gem_create_in { 67 __u64 bo_size; 68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 __u64 alignment; 70 __u64 domains; 71 __u64 domain_flags; 72}; 73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74struct drm_amdgpu_gem_create_out { 75 __u32 handle; 76 __u32 _pad; 77}; 78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79union drm_amdgpu_gem_create { 80 struct drm_amdgpu_gem_create_in in; 81 struct drm_amdgpu_gem_create_out out; 82}; 83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84#define AMDGPU_BO_LIST_OP_CREATE 0 85#define AMDGPU_BO_LIST_OP_DESTROY 1 86#define AMDGPU_BO_LIST_OP_UPDATE 2 87struct drm_amdgpu_bo_list_in { 88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 __u32 operation; 90 __u32 list_handle; 91 __u32 bo_number; 92 __u32 bo_info_size; 93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 __u64 bo_info_ptr; 95}; 96struct drm_amdgpu_bo_list_entry { 97 __u32 bo_handle; 98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 __u32 bo_priority; 100}; 101struct drm_amdgpu_bo_list_out { 102 __u32 list_handle; 103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 __u32 _pad; 105}; 106union drm_amdgpu_bo_list { 107 struct drm_amdgpu_bo_list_in in; 108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 struct drm_amdgpu_bo_list_out out; 110}; 111#define AMDGPU_CTX_OP_ALLOC_CTX 1 112#define AMDGPU_CTX_OP_FREE_CTX 2 113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114#define AMDGPU_CTX_OP_QUERY_STATE 3 115#define AMDGPU_CTX_NO_RESET 0 116#define AMDGPU_CTX_GUILTY_RESET 1 117#define AMDGPU_CTX_INNOCENT_RESET 2 118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119#define AMDGPU_CTX_UNKNOWN_RESET 3 120struct drm_amdgpu_ctx_in { 121 __u32 op; 122 __u32 flags; 123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 __u32 ctx_id; 125 __u32 _pad; 126}; 127union drm_amdgpu_ctx_out { 128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 struct { 130 __u32 ctx_id; 131 __u32 _pad; 132 } alloc; 133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 struct { 135 __u64 flags; 136 __u32 hangs; 137 __u32 reset_status; 138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 } state; 140}; 141union drm_amdgpu_ctx { 142 struct drm_amdgpu_ctx_in in; 143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 union drm_amdgpu_ctx_out out; 145}; 146#define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 147#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 150#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 151struct drm_amdgpu_gem_userptr { 152 __u64 addr; 153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 __u64 size; 155 __u32 flags; 156 __u32 handle; 157}; 158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 160#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 161#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 162#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 165#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 166#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 167#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 170#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 171#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 172#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 175#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 176#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 177#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179#define AMDGPU_TILING_SET(field,value) (((value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT) 180#define AMDGPU_TILING_GET(value,field) (((value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK) 181#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 182#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184struct drm_amdgpu_gem_metadata { 185 __u32 handle; 186 __u32 op; 187 struct { 188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 __u64 flags; 190 __u64 tiling_info; 191 __u32 data_size_bytes; 192 __u32 data[64]; 193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 } data; 195}; 196struct drm_amdgpu_gem_mmap_in { 197 __u32 handle; 198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 __u32 _pad; 200}; 201struct drm_amdgpu_gem_mmap_out { 202 __u64 addr_ptr; 203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204}; 205union drm_amdgpu_gem_mmap { 206 struct drm_amdgpu_gem_mmap_in in; 207 struct drm_amdgpu_gem_mmap_out out; 208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209}; 210struct drm_amdgpu_gem_wait_idle_in { 211 __u32 handle; 212 __u32 flags; 213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 __u64 timeout; 215}; 216struct drm_amdgpu_gem_wait_idle_out { 217 __u32 status; 218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 __u32 domain; 220}; 221union drm_amdgpu_gem_wait_idle { 222 struct drm_amdgpu_gem_wait_idle_in in; 223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 struct drm_amdgpu_gem_wait_idle_out out; 225}; 226struct drm_amdgpu_wait_cs_in { 227 __u64 handle; 228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 __u64 timeout; 230 __u32 ip_type; 231 __u32 ip_instance; 232 __u32 ring; 233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 __u32 ctx_id; 235}; 236struct drm_amdgpu_wait_cs_out { 237 __u64 status; 238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239}; 240union drm_amdgpu_wait_cs { 241 struct drm_amdgpu_wait_cs_in in; 242 struct drm_amdgpu_wait_cs_out out; 243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244}; 245#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 246#define AMDGPU_GEM_OP_SET_PLACEMENT 1 247struct drm_amdgpu_gem_op { 248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 __u32 handle; 250 __u32 op; 251 __u64 value; 252}; 253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254#define AMDGPU_VA_OP_MAP 1 255#define AMDGPU_VA_OP_UNMAP 2 256#define AMDGPU_VM_DELAY_UPDATE (1 << 0) 257#define AMDGPU_VM_PAGE_READABLE (1 << 1) 258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 260#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 261struct drm_amdgpu_gem_va { 262 __u32 handle; 263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 __u32 _pad; 265 __u32 operation; 266 __u32 flags; 267 __u64 va_address; 268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 __u64 offset_in_bo; 270 __u64 map_size; 271}; 272#define AMDGPU_HW_IP_GFX 0 273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274#define AMDGPU_HW_IP_COMPUTE 1 275#define AMDGPU_HW_IP_DMA 2 276#define AMDGPU_HW_IP_UVD 3 277#define AMDGPU_HW_IP_VCE 4 278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279#define AMDGPU_HW_IP_NUM 5 280#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 281#define AMDGPU_CHUNK_ID_IB 0x01 282#define AMDGPU_CHUNK_ID_FENCE 0x02 283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 285struct drm_amdgpu_cs_chunk { 286 __u32 chunk_id; 287 __u32 length_dw; 288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 __u64 chunk_data; 290}; 291struct drm_amdgpu_cs_in { 292 __u32 ctx_id; 293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 __u32 bo_list_handle; 295 __u32 num_chunks; 296 __u32 _pad; 297 __u64 chunks; 298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299}; 300struct drm_amdgpu_cs_out { 301 __u64 handle; 302}; 303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304union drm_amdgpu_cs { 305 struct drm_amdgpu_cs_in in; 306 struct drm_amdgpu_cs_out out; 307}; 308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309#define AMDGPU_IB_FLAG_CE (1 << 0) 310#define AMDGPU_IB_FLAG_PREAMBLE (1 << 1) 311struct drm_amdgpu_cs_chunk_ib { 312 __u32 _pad; 313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 __u32 flags; 315 __u64 va_start; 316 __u32 ib_bytes; 317 __u32 ip_type; 318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 __u32 ip_instance; 320 __u32 ring; 321}; 322struct drm_amdgpu_cs_chunk_dep { 323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 __u32 ip_type; 325 __u32 ip_instance; 326 __u32 ring; 327 __u32 ctx_id; 328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 __u64 handle; 330}; 331struct drm_amdgpu_cs_chunk_fence { 332 __u32 handle; 333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 __u32 offset; 335}; 336struct drm_amdgpu_cs_chunk_data { 337 union { 338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 struct drm_amdgpu_cs_chunk_ib ib_data; 340 struct drm_amdgpu_cs_chunk_fence fence_data; 341 }; 342}; 343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344#define AMDGPU_IDS_FLAGS_FUSION 0x1 345#define AMDGPU_INFO_ACCEL_WORKING 0x00 346#define AMDGPU_INFO_CRTC_FROM_ID 0x01 347#define AMDGPU_INFO_HW_IP_INFO 0x02 348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349#define AMDGPU_INFO_HW_IP_COUNT 0x03 350#define AMDGPU_INFO_TIMESTAMP 0x05 351#define AMDGPU_INFO_FW_VERSION 0x0e 352#define AMDGPU_INFO_FW_VCE 0x1 353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354#define AMDGPU_INFO_FW_UVD 0x2 355#define AMDGPU_INFO_FW_GMC 0x03 356#define AMDGPU_INFO_FW_GFX_ME 0x04 357#define AMDGPU_INFO_FW_GFX_PFP 0x05 358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359#define AMDGPU_INFO_FW_GFX_CE 0x06 360#define AMDGPU_INFO_FW_GFX_RLC 0x07 361#define AMDGPU_INFO_FW_GFX_MEC 0x08 362#define AMDGPU_INFO_FW_SMC 0x0a 363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364#define AMDGPU_INFO_FW_SDMA 0x0b 365#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 366#define AMDGPU_INFO_VRAM_USAGE 0x10 367#define AMDGPU_INFO_GTT_USAGE 0x11 368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369#define AMDGPU_INFO_GDS_CONFIG 0x13 370#define AMDGPU_INFO_VRAM_GTT 0x14 371#define AMDGPU_INFO_READ_MMR_REG 0x15 372#define AMDGPU_INFO_DEV_INFO 0x16 373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 375#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 376#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 377#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 380struct drm_amdgpu_info { 381 __u64 return_pointer; 382 __u32 return_size; 383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 __u32 query; 385 union { 386 struct { 387 __u32 id; 388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 __u32 _pad; 390 } mode_crtc; 391 struct { 392 __u32 type; 393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 __u32 ip_instance; 395 } query_hw_ip; 396 struct { 397 __u32 dword_offset; 398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 __u32 count; 400 __u32 instance; 401 __u32 flags; 402 } read_mmr_reg; 403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 struct { 405 __u32 fw_type; 406 __u32 ip_instance; 407 __u32 index; 408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 __u32 _pad; 410 } query_fw; 411 }; 412}; 413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414struct drm_amdgpu_info_gds { 415 __u32 gds_gfx_partition_size; 416 __u32 compute_partition_size; 417 __u32 gds_total_size; 418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 __u32 gws_per_gfx_partition; 420 __u32 gws_per_compute_partition; 421 __u32 oa_per_gfx_partition; 422 __u32 oa_per_compute_partition; 423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 __u32 _pad; 425}; 426struct drm_amdgpu_info_vram_gtt { 427 __u64 vram_size; 428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 __u64 vram_cpu_accessible_size; 430 __u64 gtt_size; 431}; 432struct drm_amdgpu_info_firmware { 433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 __u32 ver; 435 __u32 feature; 436}; 437#define AMDGPU_VRAM_TYPE_UNKNOWN 0 438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439#define AMDGPU_VRAM_TYPE_GDDR1 1 440#define AMDGPU_VRAM_TYPE_DDR2 2 441#define AMDGPU_VRAM_TYPE_GDDR3 3 442#define AMDGPU_VRAM_TYPE_GDDR4 4 443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444#define AMDGPU_VRAM_TYPE_GDDR5 5 445#define AMDGPU_VRAM_TYPE_HBM 6 446#define AMDGPU_VRAM_TYPE_DDR3 7 447struct drm_amdgpu_info_device { 448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 __u32 device_id; 450 __u32 chip_rev; 451 __u32 external_rev; 452 __u32 pci_rev; 453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 __u32 family; 455 __u32 num_shader_engines; 456 __u32 num_shader_arrays_per_engine; 457 __u32 gpu_counter_freq; 458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 __u64 max_engine_clock; 460 __u64 max_memory_clock; 461 __u32 cu_active_number; 462 __u32 cu_ao_mask; 463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 __u32 cu_bitmap[4][4]; 465 __u32 enabled_rb_pipes_mask; 466 __u32 num_rb_pipes; 467 __u32 num_hw_gfx_contexts; 468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 __u32 _pad; 470 __u64 ids_flags; 471 __u64 virtual_address_offset; 472 __u64 virtual_address_max; 473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 __u32 virtual_address_alignment; 475 __u32 pte_fragment_size; 476 __u32 gart_page_size; 477 __u32 ce_ram_size; 478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 __u32 vram_type; 480 __u32 vram_bit_width; 481 __u32 vce_harvest_config; 482}; 483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484struct drm_amdgpu_info_hw_ip { 485 __u32 hw_ip_version_major; 486 __u32 hw_ip_version_minor; 487 __u64 capabilities_flags; 488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 __u32 ib_start_alignment; 490 __u32 ib_size_alignment; 491 __u32 available_rings; 492 __u32 _pad; 493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494}; 495#define AMDGPU_FAMILY_UNKNOWN 0 496#define AMDGPU_FAMILY_CI 120 497#define AMDGPU_FAMILY_KV 125 498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499#define AMDGPU_FAMILY_VI 130 500#define AMDGPU_FAMILY_CZ 135 501#ifdef __cplusplus 502#endif 503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504#endif 505