amdgpu_drm.h revision 1308ad3ab33294c3abfd96da12b6df58b381ce52 
1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __AMDGPU_DRM_H__
20#define __AMDGPU_DRM_H__
21#include "drm.h"
22#ifdef __cplusplus
23#endif
24#define DRM_AMDGPU_GEM_CREATE 0x00
25#define DRM_AMDGPU_GEM_MMAP 0x01
26#define DRM_AMDGPU_CTX 0x02
27#define DRM_AMDGPU_BO_LIST 0x03
28#define DRM_AMDGPU_CS 0x04
29#define DRM_AMDGPU_INFO 0x05
30#define DRM_AMDGPU_GEM_METADATA 0x06
31#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
32#define DRM_AMDGPU_GEM_VA 0x08
33#define DRM_AMDGPU_WAIT_CS 0x09
34#define DRM_AMDGPU_GEM_OP 0x10
35#define DRM_AMDGPU_GEM_USERPTR 0x11
36#define DRM_AMDGPU_WAIT_FENCES 0x12
37#define DRM_AMDGPU_VM 0x13
38#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
39#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
40#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
41#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
42#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
43#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
44#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
45#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
46#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
47#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
48#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
49#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
50#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
51#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
52#define AMDGPU_GEM_DOMAIN_CPU 0x1
53#define AMDGPU_GEM_DOMAIN_GTT 0x2
54#define AMDGPU_GEM_DOMAIN_VRAM 0x4
55#define AMDGPU_GEM_DOMAIN_GDS 0x8
56#define AMDGPU_GEM_DOMAIN_GWS 0x10
57#define AMDGPU_GEM_DOMAIN_OA 0x20
58#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
59#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
60#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
61#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
62#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
63#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
64struct drm_amdgpu_gem_create_in {
65  __u64 bo_size;
66  __u64 alignment;
67  __u64 domains;
68  __u64 domain_flags;
69};
70struct drm_amdgpu_gem_create_out {
71  __u32 handle;
72  __u32 _pad;
73};
74union drm_amdgpu_gem_create {
75  struct drm_amdgpu_gem_create_in in;
76  struct drm_amdgpu_gem_create_out out;
77};
78#define AMDGPU_BO_LIST_OP_CREATE 0
79#define AMDGPU_BO_LIST_OP_DESTROY 1
80#define AMDGPU_BO_LIST_OP_UPDATE 2
81struct drm_amdgpu_bo_list_in {
82  __u32 operation;
83  __u32 list_handle;
84  __u32 bo_number;
85  __u32 bo_info_size;
86  __u64 bo_info_ptr;
87};
88struct drm_amdgpu_bo_list_entry {
89  __u32 bo_handle;
90  __u32 bo_priority;
91};
92struct drm_amdgpu_bo_list_out {
93  __u32 list_handle;
94  __u32 _pad;
95};
96union drm_amdgpu_bo_list {
97  struct drm_amdgpu_bo_list_in in;
98  struct drm_amdgpu_bo_list_out out;
99};
100#define AMDGPU_CTX_OP_ALLOC_CTX 1
101#define AMDGPU_CTX_OP_FREE_CTX 2
102#define AMDGPU_CTX_OP_QUERY_STATE 3
103#define AMDGPU_CTX_NO_RESET 0
104#define AMDGPU_CTX_GUILTY_RESET 1
105#define AMDGPU_CTX_INNOCENT_RESET 2
106#define AMDGPU_CTX_UNKNOWN_RESET 3
107struct drm_amdgpu_ctx_in {
108  __u32 op;
109  __u32 flags;
110  __u32 ctx_id;
111  __u32 _pad;
112};
113union drm_amdgpu_ctx_out {
114  struct {
115    __u32 ctx_id;
116    __u32 _pad;
117  } alloc;
118  struct {
119    __u64 flags;
120    __u32 hangs;
121    __u32 reset_status;
122  } state;
123};
124union drm_amdgpu_ctx {
125  struct drm_amdgpu_ctx_in in;
126  union drm_amdgpu_ctx_out out;
127};
128#define AMDGPU_VM_OP_RESERVE_VMID 1
129#define AMDGPU_VM_OP_UNRESERVE_VMID 2
130struct drm_amdgpu_vm_in {
131  __u32 op;
132  __u32 flags;
133};
134struct drm_amdgpu_vm_out {
135  __u64 flags;
136};
137union drm_amdgpu_vm {
138  struct drm_amdgpu_vm_in in;
139  struct drm_amdgpu_vm_out out;
140};
141#define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
142#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
143#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
144#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
145struct drm_amdgpu_gem_userptr {
146  __u64 addr;
147  __u64 size;
148  __u32 flags;
149  __u32 handle;
150};
151#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
152#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
153#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
154#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
155#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
156#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
157#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
158#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
159#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
160#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
161#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
162#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
163#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
164#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
165#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
166#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
167#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
168#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
169#define AMDGPU_TILING_SET(field,value) (((__u64) (value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT)
170#define AMDGPU_TILING_GET(value,field) (((__u64) (value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK)
171#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
172#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
173struct drm_amdgpu_gem_metadata {
174  __u32 handle;
175  __u32 op;
176  struct {
177    __u64 flags;
178    __u64 tiling_info;
179    __u32 data_size_bytes;
180    __u32 data[64];
181  } data;
182};
183struct drm_amdgpu_gem_mmap_in {
184  __u32 handle;
185  __u32 _pad;
186};
187struct drm_amdgpu_gem_mmap_out {
188  __u64 addr_ptr;
189};
190union drm_amdgpu_gem_mmap {
191  struct drm_amdgpu_gem_mmap_in in;
192  struct drm_amdgpu_gem_mmap_out out;
193};
194struct drm_amdgpu_gem_wait_idle_in {
195  __u32 handle;
196  __u32 flags;
197  __u64 timeout;
198};
199struct drm_amdgpu_gem_wait_idle_out {
200  __u32 status;
201  __u32 domain;
202};
203union drm_amdgpu_gem_wait_idle {
204  struct drm_amdgpu_gem_wait_idle_in in;
205  struct drm_amdgpu_gem_wait_idle_out out;
206};
207struct drm_amdgpu_wait_cs_in {
208  __u64 handle;
209  __u64 timeout;
210  __u32 ip_type;
211  __u32 ip_instance;
212  __u32 ring;
213  __u32 ctx_id;
214};
215struct drm_amdgpu_wait_cs_out {
216  __u64 status;
217};
218union drm_amdgpu_wait_cs {
219  struct drm_amdgpu_wait_cs_in in;
220  struct drm_amdgpu_wait_cs_out out;
221};
222struct drm_amdgpu_fence {
223  __u32 ctx_id;
224  __u32 ip_type;
225  __u32 ip_instance;
226  __u32 ring;
227  __u64 seq_no;
228};
229struct drm_amdgpu_wait_fences_in {
230  __u64 fences;
231  __u32 fence_count;
232  __u32 wait_all;
233  __u64 timeout_ns;
234};
235struct drm_amdgpu_wait_fences_out {
236  __u32 status;
237  __u32 first_signaled;
238};
239union drm_amdgpu_wait_fences {
240  struct drm_amdgpu_wait_fences_in in;
241  struct drm_amdgpu_wait_fences_out out;
242};
243#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
244#define AMDGPU_GEM_OP_SET_PLACEMENT 1
245struct drm_amdgpu_gem_op {
246  __u32 handle;
247  __u32 op;
248  __u64 value;
249};
250#define AMDGPU_VA_OP_MAP 1
251#define AMDGPU_VA_OP_UNMAP 2
252#define AMDGPU_VA_OP_CLEAR 3
253#define AMDGPU_VA_OP_REPLACE 4
254#define AMDGPU_VM_DELAY_UPDATE (1 << 0)
255#define AMDGPU_VM_PAGE_READABLE (1 << 1)
256#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
257#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
258#define AMDGPU_VM_PAGE_PRT (1 << 4)
259#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
260#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
261#define AMDGPU_VM_MTYPE_NC (1 << 5)
262#define AMDGPU_VM_MTYPE_WC (2 << 5)
263#define AMDGPU_VM_MTYPE_CC (3 << 5)
264#define AMDGPU_VM_MTYPE_UC (4 << 5)
265struct drm_amdgpu_gem_va {
266  __u32 handle;
267  __u32 _pad;
268  __u32 operation;
269  __u32 flags;
270  __u64 va_address;
271  __u64 offset_in_bo;
272  __u64 map_size;
273};
274#define AMDGPU_HW_IP_GFX 0
275#define AMDGPU_HW_IP_COMPUTE 1
276#define AMDGPU_HW_IP_DMA 2
277#define AMDGPU_HW_IP_UVD 3
278#define AMDGPU_HW_IP_VCE 4
279#define AMDGPU_HW_IP_UVD_ENC 5
280#define AMDGPU_HW_IP_VCN_DEC 6
281#define AMDGPU_HW_IP_VCN_ENC 7
282#define AMDGPU_HW_IP_NUM 8
283#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
284#define AMDGPU_CHUNK_ID_IB 0x01
285#define AMDGPU_CHUNK_ID_FENCE 0x02
286#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
287#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
288#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
289struct drm_amdgpu_cs_chunk {
290  __u32 chunk_id;
291  __u32 length_dw;
292  __u64 chunk_data;
293};
294struct drm_amdgpu_cs_in {
295  __u32 ctx_id;
296  __u32 bo_list_handle;
297  __u32 num_chunks;
298  __u32 _pad;
299  __u64 chunks;
300};
301struct drm_amdgpu_cs_out {
302  __u64 handle;
303};
304union drm_amdgpu_cs {
305  struct drm_amdgpu_cs_in in;
306  struct drm_amdgpu_cs_out out;
307};
308#define AMDGPU_IB_FLAG_CE (1 << 0)
309#define AMDGPU_IB_FLAG_PREAMBLE (1 << 1)
310#define AMDGPU_IB_FLAG_PREEMPT (1 << 2)
311struct drm_amdgpu_cs_chunk_ib {
312  __u32 _pad;
313  __u32 flags;
314  __u64 va_start;
315  __u32 ib_bytes;
316  __u32 ip_type;
317  __u32 ip_instance;
318  __u32 ring;
319};
320struct drm_amdgpu_cs_chunk_dep {
321  __u32 ip_type;
322  __u32 ip_instance;
323  __u32 ring;
324  __u32 ctx_id;
325  __u64 handle;
326};
327struct drm_amdgpu_cs_chunk_fence {
328  __u32 handle;
329  __u32 offset;
330};
331struct drm_amdgpu_cs_chunk_sem {
332  __u32 handle;
333};
334struct drm_amdgpu_cs_chunk_data {
335  union {
336    struct drm_amdgpu_cs_chunk_ib ib_data;
337    struct drm_amdgpu_cs_chunk_fence fence_data;
338  };
339};
340#define AMDGPU_IDS_FLAGS_FUSION 0x1
341#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
342#define AMDGPU_INFO_ACCEL_WORKING 0x00
343#define AMDGPU_INFO_CRTC_FROM_ID 0x01
344#define AMDGPU_INFO_HW_IP_INFO 0x02
345#define AMDGPU_INFO_HW_IP_COUNT 0x03
346#define AMDGPU_INFO_TIMESTAMP 0x05
347#define AMDGPU_INFO_FW_VERSION 0x0e
348#define AMDGPU_INFO_FW_VCE 0x1
349#define AMDGPU_INFO_FW_UVD 0x2
350#define AMDGPU_INFO_FW_GMC 0x03
351#define AMDGPU_INFO_FW_GFX_ME 0x04
352#define AMDGPU_INFO_FW_GFX_PFP 0x05
353#define AMDGPU_INFO_FW_GFX_CE 0x06
354#define AMDGPU_INFO_FW_GFX_RLC 0x07
355#define AMDGPU_INFO_FW_GFX_MEC 0x08
356#define AMDGPU_INFO_FW_SMC 0x0a
357#define AMDGPU_INFO_FW_SDMA 0x0b
358#define AMDGPU_INFO_FW_SOS 0x0c
359#define AMDGPU_INFO_FW_ASD 0x0d
360#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
361#define AMDGPU_INFO_VRAM_USAGE 0x10
362#define AMDGPU_INFO_GTT_USAGE 0x11
363#define AMDGPU_INFO_GDS_CONFIG 0x13
364#define AMDGPU_INFO_VRAM_GTT 0x14
365#define AMDGPU_INFO_READ_MMR_REG 0x15
366#define AMDGPU_INFO_DEV_INFO 0x16
367#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
368#define AMDGPU_INFO_NUM_EVICTIONS 0x18
369#define AMDGPU_INFO_MEMORY 0x19
370#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
371#define AMDGPU_INFO_VBIOS 0x1B
372#define AMDGPU_INFO_VBIOS_SIZE 0x1
373#define AMDGPU_INFO_VBIOS_IMAGE 0x2
374#define AMDGPU_INFO_NUM_HANDLES 0x1C
375#define AMDGPU_INFO_SENSOR 0x1D
376#define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
377#define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
378#define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
379#define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
380#define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
381#define AMDGPU_INFO_SENSOR_VDDNB 0x6
382#define AMDGPU_INFO_SENSOR_VDDGFX 0x7
383#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
384#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
385#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
386#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
387#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
388struct drm_amdgpu_query_fw {
389  __u32 fw_type;
390  __u32 ip_instance;
391  __u32 index;
392  __u32 _pad;
393};
394struct drm_amdgpu_info {
395  __u64 return_pointer;
396  __u32 return_size;
397  __u32 query;
398  union {
399    struct {
400      __u32 id;
401      __u32 _pad;
402    } mode_crtc;
403    struct {
404      __u32 type;
405      __u32 ip_instance;
406    } query_hw_ip;
407    struct {
408      __u32 dword_offset;
409      __u32 count;
410      __u32 instance;
411      __u32 flags;
412    } read_mmr_reg;
413    struct drm_amdgpu_query_fw query_fw;
414    struct {
415      __u32 type;
416      __u32 offset;
417    } vbios_info;
418    struct {
419      __u32 type;
420    } sensor_info;
421  };
422};
423struct drm_amdgpu_info_gds {
424  __u32 gds_gfx_partition_size;
425  __u32 compute_partition_size;
426  __u32 gds_total_size;
427  __u32 gws_per_gfx_partition;
428  __u32 gws_per_compute_partition;
429  __u32 oa_per_gfx_partition;
430  __u32 oa_per_compute_partition;
431  __u32 _pad;
432};
433struct drm_amdgpu_info_vram_gtt {
434  __u64 vram_size;
435  __u64 vram_cpu_accessible_size;
436  __u64 gtt_size;
437};
438struct drm_amdgpu_heap_info {
439  __u64 total_heap_size;
440  __u64 usable_heap_size;
441  __u64 heap_usage;
442  __u64 max_allocation;
443};
444struct drm_amdgpu_memory_info {
445  struct drm_amdgpu_heap_info vram;
446  struct drm_amdgpu_heap_info cpu_accessible_vram;
447  struct drm_amdgpu_heap_info gtt;
448};
449struct drm_amdgpu_info_firmware {
450  __u32 ver;
451  __u32 feature;
452};
453#define AMDGPU_VRAM_TYPE_UNKNOWN 0
454#define AMDGPU_VRAM_TYPE_GDDR1 1
455#define AMDGPU_VRAM_TYPE_DDR2 2
456#define AMDGPU_VRAM_TYPE_GDDR3 3
457#define AMDGPU_VRAM_TYPE_GDDR4 4
458#define AMDGPU_VRAM_TYPE_GDDR5 5
459#define AMDGPU_VRAM_TYPE_HBM 6
460#define AMDGPU_VRAM_TYPE_DDR3 7
461struct drm_amdgpu_info_device {
462  __u32 device_id;
463  __u32 chip_rev;
464  __u32 external_rev;
465  __u32 pci_rev;
466  __u32 family;
467  __u32 num_shader_engines;
468  __u32 num_shader_arrays_per_engine;
469  __u32 gpu_counter_freq;
470  __u64 max_engine_clock;
471  __u64 max_memory_clock;
472  __u32 cu_active_number;
473  __u32 cu_ao_mask;
474  __u32 cu_bitmap[4][4];
475  __u32 enabled_rb_pipes_mask;
476  __u32 num_rb_pipes;
477  __u32 num_hw_gfx_contexts;
478  __u32 _pad;
479  __u64 ids_flags;
480  __u64 virtual_address_offset;
481  __u64 virtual_address_max;
482  __u32 virtual_address_alignment;
483  __u32 pte_fragment_size;
484  __u32 gart_page_size;
485  __u32 ce_ram_size;
486  __u32 vram_type;
487  __u32 vram_bit_width;
488  __u32 vce_harvest_config;
489  __u32 gc_double_offchip_lds_buf;
490  __u64 prim_buf_gpu_addr;
491  __u64 pos_buf_gpu_addr;
492  __u64 cntl_sb_buf_gpu_addr;
493  __u64 param_buf_gpu_addr;
494  __u32 prim_buf_size;
495  __u32 pos_buf_size;
496  __u32 cntl_sb_buf_size;
497  __u32 param_buf_size;
498  __u32 wave_front_size;
499  __u32 num_shader_visible_vgprs;
500  __u32 num_cu_per_sh;
501  __u32 num_tcc_blocks;
502  __u32 gs_vgt_table_depth;
503  __u32 gs_prim_buffer_depth;
504  __u32 max_gs_waves_per_vgt;
505  __u32 _pad1;
506  __u32 cu_ao_bitmap[4][4];
507};
508struct drm_amdgpu_info_hw_ip {
509  __u32 hw_ip_version_major;
510  __u32 hw_ip_version_minor;
511  __u64 capabilities_flags;
512  __u32 ib_start_alignment;
513  __u32 ib_size_alignment;
514  __u32 available_rings;
515  __u32 _pad;
516};
517struct drm_amdgpu_info_num_handles {
518  __u32 uvd_max_handles;
519  __u32 uvd_used_handles;
520};
521#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
522struct drm_amdgpu_info_vce_clock_table_entry {
523  __u32 sclk;
524  __u32 mclk;
525  __u32 eclk;
526  __u32 pad;
527};
528struct drm_amdgpu_info_vce_clock_table {
529  struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
530  __u32 num_valid_entries;
531  __u32 pad;
532};
533#define AMDGPU_FAMILY_UNKNOWN 0
534#define AMDGPU_FAMILY_SI 110
535#define AMDGPU_FAMILY_CI 120
536#define AMDGPU_FAMILY_KV 125
537#define AMDGPU_FAMILY_VI 130
538#define AMDGPU_FAMILY_CZ 135
539#define AMDGPU_FAMILY_AI 141
540#define AMDGPU_FAMILY_RV 142
541#ifdef __cplusplus
542#endif
543#endif
544