amdgpu_drm.h revision 525ce914edf136d2bd02ac8c404d56c52e737f4d 
1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __AMDGPU_DRM_H__
20#define __AMDGPU_DRM_H__
21#include "drm.h"
22#ifdef __cplusplus
23#endif
24#define DRM_AMDGPU_GEM_CREATE 0x00
25#define DRM_AMDGPU_GEM_MMAP 0x01
26#define DRM_AMDGPU_CTX 0x02
27#define DRM_AMDGPU_BO_LIST 0x03
28#define DRM_AMDGPU_CS 0x04
29#define DRM_AMDGPU_INFO 0x05
30#define DRM_AMDGPU_GEM_METADATA 0x06
31#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
32#define DRM_AMDGPU_GEM_VA 0x08
33#define DRM_AMDGPU_WAIT_CS 0x09
34#define DRM_AMDGPU_GEM_OP 0x10
35#define DRM_AMDGPU_GEM_USERPTR 0x11
36#define DRM_AMDGPU_WAIT_FENCES 0x12
37#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
38#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
39#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
40#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
41#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
42#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
43#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
44#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
45#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
46#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
47#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
48#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
49#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
50#define AMDGPU_GEM_DOMAIN_CPU 0x1
51#define AMDGPU_GEM_DOMAIN_GTT 0x2
52#define AMDGPU_GEM_DOMAIN_VRAM 0x4
53#define AMDGPU_GEM_DOMAIN_GDS 0x8
54#define AMDGPU_GEM_DOMAIN_GWS 0x10
55#define AMDGPU_GEM_DOMAIN_OA 0x20
56#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
57#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
58#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
59#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
60#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
61#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
62struct drm_amdgpu_gem_create_in {
63  __u64 bo_size;
64  __u64 alignment;
65  __u64 domains;
66  __u64 domain_flags;
67};
68struct drm_amdgpu_gem_create_out {
69  __u32 handle;
70  __u32 _pad;
71};
72union drm_amdgpu_gem_create {
73  struct drm_amdgpu_gem_create_in in;
74  struct drm_amdgpu_gem_create_out out;
75};
76#define AMDGPU_BO_LIST_OP_CREATE 0
77#define AMDGPU_BO_LIST_OP_DESTROY 1
78#define AMDGPU_BO_LIST_OP_UPDATE 2
79struct drm_amdgpu_bo_list_in {
80  __u32 operation;
81  __u32 list_handle;
82  __u32 bo_number;
83  __u32 bo_info_size;
84  __u64 bo_info_ptr;
85};
86struct drm_amdgpu_bo_list_entry {
87  __u32 bo_handle;
88  __u32 bo_priority;
89};
90struct drm_amdgpu_bo_list_out {
91  __u32 list_handle;
92  __u32 _pad;
93};
94union drm_amdgpu_bo_list {
95  struct drm_amdgpu_bo_list_in in;
96  struct drm_amdgpu_bo_list_out out;
97};
98#define AMDGPU_CTX_OP_ALLOC_CTX 1
99#define AMDGPU_CTX_OP_FREE_CTX 2
100#define AMDGPU_CTX_OP_QUERY_STATE 3
101#define AMDGPU_CTX_NO_RESET 0
102#define AMDGPU_CTX_GUILTY_RESET 1
103#define AMDGPU_CTX_INNOCENT_RESET 2
104#define AMDGPU_CTX_UNKNOWN_RESET 3
105struct drm_amdgpu_ctx_in {
106  __u32 op;
107  __u32 flags;
108  __u32 ctx_id;
109  __u32 _pad;
110};
111union drm_amdgpu_ctx_out {
112  struct {
113    __u32 ctx_id;
114    __u32 _pad;
115  } alloc;
116  struct {
117    __u64 flags;
118    __u32 hangs;
119    __u32 reset_status;
120  } state;
121};
122union drm_amdgpu_ctx {
123  struct drm_amdgpu_ctx_in in;
124  union drm_amdgpu_ctx_out out;
125};
126#define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
127#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
128#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
129#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
130struct drm_amdgpu_gem_userptr {
131  __u64 addr;
132  __u64 size;
133  __u32 flags;
134  __u32 handle;
135};
136#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
137#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
138#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
139#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
140#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
141#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
142#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
143#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
144#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
145#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
146#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
147#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
148#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
149#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
150#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
151#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
152#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
153#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
154#define AMDGPU_TILING_SET(field,value) (((__u64) (value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT)
155#define AMDGPU_TILING_GET(value,field) (((__u64) (value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK)
156#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
157#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
158struct drm_amdgpu_gem_metadata {
159  __u32 handle;
160  __u32 op;
161  struct {
162    __u64 flags;
163    __u64 tiling_info;
164    __u32 data_size_bytes;
165    __u32 data[64];
166  } data;
167};
168struct drm_amdgpu_gem_mmap_in {
169  __u32 handle;
170  __u32 _pad;
171};
172struct drm_amdgpu_gem_mmap_out {
173  __u64 addr_ptr;
174};
175union drm_amdgpu_gem_mmap {
176  struct drm_amdgpu_gem_mmap_in in;
177  struct drm_amdgpu_gem_mmap_out out;
178};
179struct drm_amdgpu_gem_wait_idle_in {
180  __u32 handle;
181  __u32 flags;
182  __u64 timeout;
183};
184struct drm_amdgpu_gem_wait_idle_out {
185  __u32 status;
186  __u32 domain;
187};
188union drm_amdgpu_gem_wait_idle {
189  struct drm_amdgpu_gem_wait_idle_in in;
190  struct drm_amdgpu_gem_wait_idle_out out;
191};
192struct drm_amdgpu_wait_cs_in {
193  __u64 handle;
194  __u64 timeout;
195  __u32 ip_type;
196  __u32 ip_instance;
197  __u32 ring;
198  __u32 ctx_id;
199};
200struct drm_amdgpu_wait_cs_out {
201  __u64 status;
202};
203union drm_amdgpu_wait_cs {
204  struct drm_amdgpu_wait_cs_in in;
205  struct drm_amdgpu_wait_cs_out out;
206};
207struct drm_amdgpu_fence {
208  __u32 ctx_id;
209  __u32 ip_type;
210  __u32 ip_instance;
211  __u32 ring;
212  __u64 seq_no;
213};
214struct drm_amdgpu_wait_fences_in {
215  __u64 fences;
216  __u32 fence_count;
217  __u32 wait_all;
218  __u64 timeout_ns;
219};
220struct drm_amdgpu_wait_fences_out {
221  __u32 status;
222  __u32 first_signaled;
223};
224union drm_amdgpu_wait_fences {
225  struct drm_amdgpu_wait_fences_in in;
226  struct drm_amdgpu_wait_fences_out out;
227};
228#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
229#define AMDGPU_GEM_OP_SET_PLACEMENT 1
230struct drm_amdgpu_gem_op {
231  __u32 handle;
232  __u32 op;
233  __u64 value;
234};
235#define AMDGPU_VA_OP_MAP 1
236#define AMDGPU_VA_OP_UNMAP 2
237#define AMDGPU_VA_OP_CLEAR 3
238#define AMDGPU_VA_OP_REPLACE 4
239#define AMDGPU_VM_DELAY_UPDATE (1 << 0)
240#define AMDGPU_VM_PAGE_READABLE (1 << 1)
241#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
242#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
243#define AMDGPU_VM_PAGE_PRT (1 << 4)
244#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
245#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
246#define AMDGPU_VM_MTYPE_NC (1 << 5)
247#define AMDGPU_VM_MTYPE_WC (2 << 5)
248#define AMDGPU_VM_MTYPE_CC (3 << 5)
249#define AMDGPU_VM_MTYPE_UC (4 << 5)
250struct drm_amdgpu_gem_va {
251  __u32 handle;
252  __u32 _pad;
253  __u32 operation;
254  __u32 flags;
255  __u64 va_address;
256  __u64 offset_in_bo;
257  __u64 map_size;
258};
259#define AMDGPU_HW_IP_GFX 0
260#define AMDGPU_HW_IP_COMPUTE 1
261#define AMDGPU_HW_IP_DMA 2
262#define AMDGPU_HW_IP_UVD 3
263#define AMDGPU_HW_IP_VCE 4
264#define AMDGPU_HW_IP_UVD_ENC 5
265#define AMDGPU_HW_IP_NUM 6
266#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
267#define AMDGPU_CHUNK_ID_IB 0x01
268#define AMDGPU_CHUNK_ID_FENCE 0x02
269#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
270struct drm_amdgpu_cs_chunk {
271  __u32 chunk_id;
272  __u32 length_dw;
273  __u64 chunk_data;
274};
275struct drm_amdgpu_cs_in {
276  __u32 ctx_id;
277  __u32 bo_list_handle;
278  __u32 num_chunks;
279  __u32 _pad;
280  __u64 chunks;
281};
282struct drm_amdgpu_cs_out {
283  __u64 handle;
284};
285union drm_amdgpu_cs {
286  struct drm_amdgpu_cs_in in;
287  struct drm_amdgpu_cs_out out;
288};
289#define AMDGPU_IB_FLAG_CE (1 << 0)
290#define AMDGPU_IB_FLAG_PREAMBLE (1 << 1)
291#define AMDGPU_IB_FLAG_PREEMPT (1 << 2)
292struct drm_amdgpu_cs_chunk_ib {
293  __u32 _pad;
294  __u32 flags;
295  __u64 va_start;
296  __u32 ib_bytes;
297  __u32 ip_type;
298  __u32 ip_instance;
299  __u32 ring;
300};
301struct drm_amdgpu_cs_chunk_dep {
302  __u32 ip_type;
303  __u32 ip_instance;
304  __u32 ring;
305  __u32 ctx_id;
306  __u64 handle;
307};
308struct drm_amdgpu_cs_chunk_fence {
309  __u32 handle;
310  __u32 offset;
311};
312struct drm_amdgpu_cs_chunk_data {
313  union {
314    struct drm_amdgpu_cs_chunk_ib ib_data;
315    struct drm_amdgpu_cs_chunk_fence fence_data;
316  };
317};
318#define AMDGPU_IDS_FLAGS_FUSION 0x1
319#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
320#define AMDGPU_INFO_ACCEL_WORKING 0x00
321#define AMDGPU_INFO_CRTC_FROM_ID 0x01
322#define AMDGPU_INFO_HW_IP_INFO 0x02
323#define AMDGPU_INFO_HW_IP_COUNT 0x03
324#define AMDGPU_INFO_TIMESTAMP 0x05
325#define AMDGPU_INFO_FW_VERSION 0x0e
326#define AMDGPU_INFO_FW_VCE 0x1
327#define AMDGPU_INFO_FW_UVD 0x2
328#define AMDGPU_INFO_FW_GMC 0x03
329#define AMDGPU_INFO_FW_GFX_ME 0x04
330#define AMDGPU_INFO_FW_GFX_PFP 0x05
331#define AMDGPU_INFO_FW_GFX_CE 0x06
332#define AMDGPU_INFO_FW_GFX_RLC 0x07
333#define AMDGPU_INFO_FW_GFX_MEC 0x08
334#define AMDGPU_INFO_FW_SMC 0x0a
335#define AMDGPU_INFO_FW_SDMA 0x0b
336#define AMDGPU_INFO_FW_SOS 0x0c
337#define AMDGPU_INFO_FW_ASD 0x0d
338#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
339#define AMDGPU_INFO_VRAM_USAGE 0x10
340#define AMDGPU_INFO_GTT_USAGE 0x11
341#define AMDGPU_INFO_GDS_CONFIG 0x13
342#define AMDGPU_INFO_VRAM_GTT 0x14
343#define AMDGPU_INFO_READ_MMR_REG 0x15
344#define AMDGPU_INFO_DEV_INFO 0x16
345#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
346#define AMDGPU_INFO_NUM_EVICTIONS 0x18
347#define AMDGPU_INFO_MEMORY 0x19
348#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
349#define AMDGPU_INFO_VBIOS 0x1B
350#define AMDGPU_INFO_VBIOS_SIZE 0x1
351#define AMDGPU_INFO_VBIOS_IMAGE 0x2
352#define AMDGPU_INFO_NUM_HANDLES 0x1C
353#define AMDGPU_INFO_SENSOR 0x1D
354#define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
355#define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
356#define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
357#define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
358#define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
359#define AMDGPU_INFO_SENSOR_VDDNB 0x6
360#define AMDGPU_INFO_SENSOR_VDDGFX 0x7
361#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
362#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
363#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
364#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
365struct drm_amdgpu_query_fw {
366  __u32 fw_type;
367  __u32 ip_instance;
368  __u32 index;
369  __u32 _pad;
370};
371struct drm_amdgpu_info {
372  __u64 return_pointer;
373  __u32 return_size;
374  __u32 query;
375  union {
376    struct {
377      __u32 id;
378      __u32 _pad;
379    } mode_crtc;
380    struct {
381      __u32 type;
382      __u32 ip_instance;
383    } query_hw_ip;
384    struct {
385      __u32 dword_offset;
386      __u32 count;
387      __u32 instance;
388      __u32 flags;
389    } read_mmr_reg;
390    struct drm_amdgpu_query_fw query_fw;
391    struct {
392      __u32 type;
393      __u32 offset;
394    } vbios_info;
395    struct {
396      __u32 type;
397    } sensor_info;
398  };
399};
400struct drm_amdgpu_info_gds {
401  __u32 gds_gfx_partition_size;
402  __u32 compute_partition_size;
403  __u32 gds_total_size;
404  __u32 gws_per_gfx_partition;
405  __u32 gws_per_compute_partition;
406  __u32 oa_per_gfx_partition;
407  __u32 oa_per_compute_partition;
408  __u32 _pad;
409};
410struct drm_amdgpu_info_vram_gtt {
411  __u64 vram_size;
412  __u64 vram_cpu_accessible_size;
413  __u64 gtt_size;
414};
415struct drm_amdgpu_heap_info {
416  __u64 total_heap_size;
417  __u64 usable_heap_size;
418  __u64 heap_usage;
419  __u64 max_allocation;
420};
421struct drm_amdgpu_memory_info {
422  struct drm_amdgpu_heap_info vram;
423  struct drm_amdgpu_heap_info cpu_accessible_vram;
424  struct drm_amdgpu_heap_info gtt;
425};
426struct drm_amdgpu_info_firmware {
427  __u32 ver;
428  __u32 feature;
429};
430#define AMDGPU_VRAM_TYPE_UNKNOWN 0
431#define AMDGPU_VRAM_TYPE_GDDR1 1
432#define AMDGPU_VRAM_TYPE_DDR2 2
433#define AMDGPU_VRAM_TYPE_GDDR3 3
434#define AMDGPU_VRAM_TYPE_GDDR4 4
435#define AMDGPU_VRAM_TYPE_GDDR5 5
436#define AMDGPU_VRAM_TYPE_HBM 6
437#define AMDGPU_VRAM_TYPE_DDR3 7
438struct drm_amdgpu_info_device {
439  __u32 device_id;
440  __u32 chip_rev;
441  __u32 external_rev;
442  __u32 pci_rev;
443  __u32 family;
444  __u32 num_shader_engines;
445  __u32 num_shader_arrays_per_engine;
446  __u32 gpu_counter_freq;
447  __u64 max_engine_clock;
448  __u64 max_memory_clock;
449  __u32 cu_active_number;
450  __u32 cu_ao_mask;
451  __u32 cu_bitmap[4][4];
452  __u32 enabled_rb_pipes_mask;
453  __u32 num_rb_pipes;
454  __u32 num_hw_gfx_contexts;
455  __u32 _pad;
456  __u64 ids_flags;
457  __u64 virtual_address_offset;
458  __u64 virtual_address_max;
459  __u32 virtual_address_alignment;
460  __u32 pte_fragment_size;
461  __u32 gart_page_size;
462  __u32 ce_ram_size;
463  __u32 vram_type;
464  __u32 vram_bit_width;
465  __u32 vce_harvest_config;
466  __u32 gc_double_offchip_lds_buf;
467  __u64 prim_buf_gpu_addr;
468  __u64 pos_buf_gpu_addr;
469  __u64 cntl_sb_buf_gpu_addr;
470  __u64 param_buf_gpu_addr;
471  __u32 prim_buf_size;
472  __u32 pos_buf_size;
473  __u32 cntl_sb_buf_size;
474  __u32 param_buf_size;
475  __u32 wave_front_size;
476  __u32 num_shader_visible_vgprs;
477  __u32 num_cu_per_sh;
478  __u32 num_tcc_blocks;
479  __u32 gs_vgt_table_depth;
480  __u32 gs_prim_buffer_depth;
481  __u32 max_gs_waves_per_vgt;
482  __u32 _pad1;
483};
484struct drm_amdgpu_info_hw_ip {
485  __u32 hw_ip_version_major;
486  __u32 hw_ip_version_minor;
487  __u64 capabilities_flags;
488  __u32 ib_start_alignment;
489  __u32 ib_size_alignment;
490  __u32 available_rings;
491  __u32 _pad;
492};
493struct drm_amdgpu_info_num_handles {
494  __u32 uvd_max_handles;
495  __u32 uvd_used_handles;
496};
497#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
498struct drm_amdgpu_info_vce_clock_table_entry {
499  __u32 sclk;
500  __u32 mclk;
501  __u32 eclk;
502  __u32 pad;
503};
504struct drm_amdgpu_info_vce_clock_table {
505  struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
506  __u32 num_valid_entries;
507  __u32 pad;
508};
509#define AMDGPU_FAMILY_UNKNOWN 0
510#define AMDGPU_FAMILY_SI 110
511#define AMDGPU_FAMILY_CI 120
512#define AMDGPU_FAMILY_KV 125
513#define AMDGPU_FAMILY_VI 130
514#define AMDGPU_FAMILY_CZ 135
515#define AMDGPU_FAMILY_AI 141
516#ifdef __cplusplus
517#endif
518#endif
519