amdgpu_drm.h revision 6a9755d20a995756487bb1aafb7e954f4fd868a7
1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef __AMDGPU_DRM_H__ 20#define __AMDGPU_DRM_H__ 21#include "drm.h" 22#ifdef __cplusplus 23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24#endif 25#define DRM_AMDGPU_GEM_CREATE 0x00 26#define DRM_AMDGPU_GEM_MMAP 0x01 27#define DRM_AMDGPU_CTX 0x02 28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29#define DRM_AMDGPU_BO_LIST 0x03 30#define DRM_AMDGPU_CS 0x04 31#define DRM_AMDGPU_INFO 0x05 32#define DRM_AMDGPU_GEM_METADATA 0x06 33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 35#define DRM_AMDGPU_GEM_VA 0x08 36#define DRM_AMDGPU_WAIT_CS 0x09 37#define DRM_AMDGPU_GEM_OP 0x10 38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39#define DRM_AMDGPU_GEM_USERPTR 0x11 40#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 41#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 42#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 45#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 46#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 47#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 50#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 51#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 52#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 55#define AMDGPU_GEM_DOMAIN_CPU 0x1 56#define AMDGPU_GEM_DOMAIN_GTT 0x2 57#define AMDGPU_GEM_DOMAIN_VRAM 0x4 58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59#define AMDGPU_GEM_DOMAIN_GDS 0x8 60#define AMDGPU_GEM_DOMAIN_GWS 0x10 61#define AMDGPU_GEM_DOMAIN_OA 0x20 62#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 65#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 66#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 67#define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69struct drm_amdgpu_gem_create_in { 70 __u64 bo_size; 71 __u64 alignment; 72 __u64 domains; 73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 __u64 domain_flags; 75}; 76struct drm_amdgpu_gem_create_out { 77 __u32 handle; 78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 __u32 _pad; 80}; 81union drm_amdgpu_gem_create { 82 struct drm_amdgpu_gem_create_in in; 83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 struct drm_amdgpu_gem_create_out out; 85}; 86#define AMDGPU_BO_LIST_OP_CREATE 0 87#define AMDGPU_BO_LIST_OP_DESTROY 1 88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89#define AMDGPU_BO_LIST_OP_UPDATE 2 90struct drm_amdgpu_bo_list_in { 91 __u32 operation; 92 __u32 list_handle; 93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 __u32 bo_number; 95 __u32 bo_info_size; 96 __u64 bo_info_ptr; 97}; 98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99struct drm_amdgpu_bo_list_entry { 100 __u32 bo_handle; 101 __u32 bo_priority; 102}; 103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104struct drm_amdgpu_bo_list_out { 105 __u32 list_handle; 106 __u32 _pad; 107}; 108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109union drm_amdgpu_bo_list { 110 struct drm_amdgpu_bo_list_in in; 111 struct drm_amdgpu_bo_list_out out; 112}; 113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114#define AMDGPU_CTX_OP_ALLOC_CTX 1 115#define AMDGPU_CTX_OP_FREE_CTX 2 116#define AMDGPU_CTX_OP_QUERY_STATE 3 117#define AMDGPU_CTX_NO_RESET 0 118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119#define AMDGPU_CTX_GUILTY_RESET 1 120#define AMDGPU_CTX_INNOCENT_RESET 2 121#define AMDGPU_CTX_UNKNOWN_RESET 3 122struct drm_amdgpu_ctx_in { 123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 __u32 op; 125 __u32 flags; 126 __u32 ctx_id; 127 __u32 _pad; 128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129}; 130union drm_amdgpu_ctx_out { 131 struct { 132 __u32 ctx_id; 133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 __u32 _pad; 135 } alloc; 136 struct { 137 __u64 flags; 138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 __u32 hangs; 140 __u32 reset_status; 141 } state; 142}; 143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144union drm_amdgpu_ctx { 145 struct drm_amdgpu_ctx_in in; 146 union drm_amdgpu_ctx_out out; 147}; 148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149#define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 150#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 151#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 152#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154struct drm_amdgpu_gem_userptr { 155 __u64 addr; 156 __u64 size; 157 __u32 flags; 158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 __u32 handle; 160}; 161#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 162#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 165#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 166#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 167#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 170#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 171#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 172#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 175#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 176#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 177#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 180#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 181#define AMDGPU_TILING_SET(field,value) (((value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT) 182#define AMDGPU_TILING_GET(value,field) (((value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK) 183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 185#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 186struct drm_amdgpu_gem_metadata { 187 __u32 handle; 188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 __u32 op; 190 struct { 191 __u64 flags; 192 __u64 tiling_info; 193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 __u32 data_size_bytes; 195 __u32 data[64]; 196 } data; 197}; 198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199struct drm_amdgpu_gem_mmap_in { 200 __u32 handle; 201 __u32 _pad; 202}; 203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204struct drm_amdgpu_gem_mmap_out { 205 __u64 addr_ptr; 206}; 207union drm_amdgpu_gem_mmap { 208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 struct drm_amdgpu_gem_mmap_in in; 210 struct drm_amdgpu_gem_mmap_out out; 211}; 212struct drm_amdgpu_gem_wait_idle_in { 213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 __u32 handle; 215 __u32 flags; 216 __u64 timeout; 217}; 218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219struct drm_amdgpu_gem_wait_idle_out { 220 __u32 status; 221 __u32 domain; 222}; 223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224union drm_amdgpu_gem_wait_idle { 225 struct drm_amdgpu_gem_wait_idle_in in; 226 struct drm_amdgpu_gem_wait_idle_out out; 227}; 228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229struct drm_amdgpu_wait_cs_in { 230 __u64 handle; 231 __u64 timeout; 232 __u32 ip_type; 233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 __u32 ip_instance; 235 __u32 ring; 236 __u32 ctx_id; 237}; 238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239struct drm_amdgpu_wait_cs_out { 240 __u64 status; 241}; 242union drm_amdgpu_wait_cs { 243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 struct drm_amdgpu_wait_cs_in in; 245 struct drm_amdgpu_wait_cs_out out; 246}; 247#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249#define AMDGPU_GEM_OP_SET_PLACEMENT 1 250struct drm_amdgpu_gem_op { 251 __u32 handle; 252 __u32 op; 253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 __u64 value; 255}; 256#define AMDGPU_VA_OP_MAP 1 257#define AMDGPU_VA_OP_UNMAP 2 258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259#define AMDGPU_VM_DELAY_UPDATE (1 << 0) 260#define AMDGPU_VM_PAGE_READABLE (1 << 1) 261#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 262#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264struct drm_amdgpu_gem_va { 265 __u32 handle; 266 __u32 _pad; 267 __u32 operation; 268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 __u32 flags; 270 __u64 va_address; 271 __u64 offset_in_bo; 272 __u64 map_size; 273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274}; 275#define AMDGPU_HW_IP_GFX 0 276#define AMDGPU_HW_IP_COMPUTE 1 277#define AMDGPU_HW_IP_DMA 2 278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279#define AMDGPU_HW_IP_UVD 3 280#define AMDGPU_HW_IP_VCE 4 281#define AMDGPU_HW_IP_NUM 5 282#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284#define AMDGPU_CHUNK_ID_IB 0x01 285#define AMDGPU_CHUNK_ID_FENCE 0x02 286#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 287struct drm_amdgpu_cs_chunk { 288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 __u32 chunk_id; 290 __u32 length_dw; 291 __u64 chunk_data; 292}; 293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294struct drm_amdgpu_cs_in { 295 __u32 ctx_id; 296 __u32 bo_list_handle; 297 __u32 num_chunks; 298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 __u32 _pad; 300 __u64 chunks; 301}; 302struct drm_amdgpu_cs_out { 303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 __u64 handle; 305}; 306union drm_amdgpu_cs { 307 struct drm_amdgpu_cs_in in; 308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 struct drm_amdgpu_cs_out out; 310}; 311#define AMDGPU_IB_FLAG_CE (1 << 0) 312#define AMDGPU_IB_FLAG_PREAMBLE (1 << 1) 313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314struct drm_amdgpu_cs_chunk_ib { 315 __u32 _pad; 316 __u32 flags; 317 __u64 va_start; 318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 __u32 ib_bytes; 320 __u32 ip_type; 321 __u32 ip_instance; 322 __u32 ring; 323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324}; 325struct drm_amdgpu_cs_chunk_dep { 326 __u32 ip_type; 327 __u32 ip_instance; 328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 __u32 ring; 330 __u32 ctx_id; 331 __u64 handle; 332}; 333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334struct drm_amdgpu_cs_chunk_fence { 335 __u32 handle; 336 __u32 offset; 337}; 338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339struct drm_amdgpu_cs_chunk_data { 340 union { 341 struct drm_amdgpu_cs_chunk_ib ib_data; 342 struct drm_amdgpu_cs_chunk_fence fence_data; 343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 }; 345}; 346#define AMDGPU_IDS_FLAGS_FUSION 0x1 347#define AMDGPU_INFO_ACCEL_WORKING 0x00 348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349#define AMDGPU_INFO_CRTC_FROM_ID 0x01 350#define AMDGPU_INFO_HW_IP_INFO 0x02 351#define AMDGPU_INFO_HW_IP_COUNT 0x03 352#define AMDGPU_INFO_TIMESTAMP 0x05 353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354#define AMDGPU_INFO_FW_VERSION 0x0e 355#define AMDGPU_INFO_FW_VCE 0x1 356#define AMDGPU_INFO_FW_UVD 0x2 357#define AMDGPU_INFO_FW_GMC 0x03 358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359#define AMDGPU_INFO_FW_GFX_ME 0x04 360#define AMDGPU_INFO_FW_GFX_PFP 0x05 361#define AMDGPU_INFO_FW_GFX_CE 0x06 362#define AMDGPU_INFO_FW_GFX_RLC 0x07 363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364#define AMDGPU_INFO_FW_GFX_MEC 0x08 365#define AMDGPU_INFO_FW_SMC 0x0a 366#define AMDGPU_INFO_FW_SDMA 0x0b 367#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369#define AMDGPU_INFO_VRAM_USAGE 0x10 370#define AMDGPU_INFO_GTT_USAGE 0x11 371#define AMDGPU_INFO_GDS_CONFIG 0x13 372#define AMDGPU_INFO_VRAM_GTT 0x14 373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374#define AMDGPU_INFO_READ_MMR_REG 0x15 375#define AMDGPU_INFO_DEV_INFO 0x16 376#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 377#define AMDGPU_INFO_NUM_EVICTIONS 0x18 378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 380#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 381#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 382#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384struct drm_amdgpu_query_fw { 385 __u32 fw_type; 386 __u32 ip_instance; 387 __u32 index; 388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 __u32 _pad; 390}; 391struct drm_amdgpu_info { 392 __u64 return_pointer; 393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 __u32 return_size; 395 __u32 query; 396 union { 397 struct { 398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 __u32 id; 400 __u32 _pad; 401 } mode_crtc; 402 struct { 403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 __u32 type; 405 __u32 ip_instance; 406 } query_hw_ip; 407 struct { 408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 __u32 dword_offset; 410 __u32 count; 411 __u32 instance; 412 __u32 flags; 413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 } read_mmr_reg; 415 struct drm_amdgpu_query_fw query_fw; 416 }; 417}; 418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419struct drm_amdgpu_info_gds { 420 __u32 gds_gfx_partition_size; 421 __u32 compute_partition_size; 422 __u32 gds_total_size; 423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 __u32 gws_per_gfx_partition; 425 __u32 gws_per_compute_partition; 426 __u32 oa_per_gfx_partition; 427 __u32 oa_per_compute_partition; 428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 __u32 _pad; 430}; 431struct drm_amdgpu_info_vram_gtt { 432 __u64 vram_size; 433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 __u64 vram_cpu_accessible_size; 435 __u64 gtt_size; 436}; 437struct drm_amdgpu_info_firmware { 438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439 __u32 ver; 440 __u32 feature; 441}; 442#define AMDGPU_VRAM_TYPE_UNKNOWN 0 443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444#define AMDGPU_VRAM_TYPE_GDDR1 1 445#define AMDGPU_VRAM_TYPE_DDR2 2 446#define AMDGPU_VRAM_TYPE_GDDR3 3 447#define AMDGPU_VRAM_TYPE_GDDR4 4 448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449#define AMDGPU_VRAM_TYPE_GDDR5 5 450#define AMDGPU_VRAM_TYPE_HBM 6 451#define AMDGPU_VRAM_TYPE_DDR3 7 452struct drm_amdgpu_info_device { 453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 __u32 device_id; 455 __u32 chip_rev; 456 __u32 external_rev; 457 __u32 pci_rev; 458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 __u32 family; 460 __u32 num_shader_engines; 461 __u32 num_shader_arrays_per_engine; 462 __u32 gpu_counter_freq; 463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 __u64 max_engine_clock; 465 __u64 max_memory_clock; 466 __u32 cu_active_number; 467 __u32 cu_ao_mask; 468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 __u32 cu_bitmap[4][4]; 470 __u32 enabled_rb_pipes_mask; 471 __u32 num_rb_pipes; 472 __u32 num_hw_gfx_contexts; 473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 __u32 _pad; 475 __u64 ids_flags; 476 __u64 virtual_address_offset; 477 __u64 virtual_address_max; 478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 __u32 virtual_address_alignment; 480 __u32 pte_fragment_size; 481 __u32 gart_page_size; 482 __u32 ce_ram_size; 483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 __u32 vram_type; 485 __u32 vram_bit_width; 486 __u32 vce_harvest_config; 487}; 488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489struct drm_amdgpu_info_hw_ip { 490 __u32 hw_ip_version_major; 491 __u32 hw_ip_version_minor; 492 __u64 capabilities_flags; 493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494 __u32 ib_start_alignment; 495 __u32 ib_size_alignment; 496 __u32 available_rings; 497 __u32 _pad; 498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499}; 500#define AMDGPU_FAMILY_UNKNOWN 0 501#define AMDGPU_FAMILY_SI 110 502#define AMDGPU_FAMILY_CI 120 503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504#define AMDGPU_FAMILY_KV 125 505#define AMDGPU_FAMILY_VI 130 506#define AMDGPU_FAMILY_CZ 135 507#ifdef __cplusplus 508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509#endif 510#endif 511