1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef __ETNAVIV_DRM_H__ 20#define __ETNAVIV_DRM_H__ 21#include "drm.h" 22#ifdef __cplusplus 23#endif 24struct drm_etnaviv_timespec { 25 __s64 tv_sec; 26 __s64 tv_nsec; 27}; 28#define ETNAVIV_PARAM_GPU_MODEL 0x01 29#define ETNAVIV_PARAM_GPU_REVISION 0x02 30#define ETNAVIV_PARAM_GPU_FEATURES_0 0x03 31#define ETNAVIV_PARAM_GPU_FEATURES_1 0x04 32#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05 33#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06 34#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07 35#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08 36#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09 37#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10 38#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11 39#define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12 40#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13 41#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14 42#define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15 43#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16 44#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17 45#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18 46#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19 47#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a 48#define ETNA_MAX_PIPES 4 49struct drm_etnaviv_param { 50 __u32 pipe; 51 __u32 param; 52 __u64 value; 53}; 54#define ETNA_BO_CACHE_MASK 0x000f0000 55#define ETNA_BO_CACHED 0x00010000 56#define ETNA_BO_WC 0x00020000 57#define ETNA_BO_UNCACHED 0x00040000 58#define ETNA_BO_FORCE_MMU 0x00100000 59struct drm_etnaviv_gem_new { 60 __u64 size; 61 __u32 flags; 62 __u32 handle; 63}; 64struct drm_etnaviv_gem_info { 65 __u32 handle; 66 __u32 pad; 67 __u64 offset; 68}; 69#define ETNA_PREP_READ 0x01 70#define ETNA_PREP_WRITE 0x02 71#define ETNA_PREP_NOSYNC 0x04 72struct drm_etnaviv_gem_cpu_prep { 73 __u32 handle; 74 __u32 op; 75 struct drm_etnaviv_timespec timeout; 76}; 77struct drm_etnaviv_gem_cpu_fini { 78 __u32 handle; 79 __u32 flags; 80}; 81struct drm_etnaviv_gem_submit_reloc { 82 __u32 submit_offset; 83 __u32 reloc_idx; 84 __u64 reloc_offset; 85 __u32 flags; 86}; 87#define ETNA_SUBMIT_BO_READ 0x0001 88#define ETNA_SUBMIT_BO_WRITE 0x0002 89struct drm_etnaviv_gem_submit_bo { 90 __u32 flags; 91 __u32 handle; 92 __u64 presumed; 93}; 94#define ETNA_PM_PROCESS_PRE 0x0001 95#define ETNA_PM_PROCESS_POST 0x0002 96struct drm_etnaviv_gem_submit_pmr { 97 __u32 flags; 98 __u8 domain; 99 __u8 pad; 100 __u16 signal; 101 __u32 sequence; 102 __u32 read_offset; 103 __u32 read_idx; 104}; 105#define ETNA_SUBMIT_NO_IMPLICIT 0x0001 106#define ETNA_SUBMIT_FENCE_FD_IN 0x0002 107#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004 108#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | ETNA_SUBMIT_FENCE_FD_IN | ETNA_SUBMIT_FENCE_FD_OUT) 109#define ETNA_PIPE_3D 0x00 110#define ETNA_PIPE_2D 0x01 111#define ETNA_PIPE_VG 0x02 112struct drm_etnaviv_gem_submit { 113 __u32 fence; 114 __u32 pipe; 115 __u32 exec_state; 116 __u32 nr_bos; 117 __u32 nr_relocs; 118 __u32 stream_size; 119 __u64 bos; 120 __u64 relocs; 121 __u64 stream; 122 __u32 flags; 123 __s32 fence_fd; 124 __u64 pmrs; 125 __u32 nr_pmrs; 126 __u32 pad; 127}; 128#define ETNA_WAIT_NONBLOCK 0x01 129struct drm_etnaviv_wait_fence { 130 __u32 pipe; 131 __u32 fence; 132 __u32 flags; 133 __u32 pad; 134 struct drm_etnaviv_timespec timeout; 135}; 136#define ETNA_USERPTR_READ 0x01 137#define ETNA_USERPTR_WRITE 0x02 138struct drm_etnaviv_gem_userptr { 139 __u64 user_ptr; 140 __u64 user_size; 141 __u32 flags; 142 __u32 handle; 143}; 144struct drm_etnaviv_gem_wait { 145 __u32 pipe; 146 __u32 handle; 147 __u32 flags; 148 __u32 pad; 149 struct drm_etnaviv_timespec timeout; 150}; 151struct drm_etnaviv_pm_domain { 152 __u32 pipe; 153 __u8 iter; 154 __u8 id; 155 __u16 nr_signals; 156 char name[64]; 157}; 158struct drm_etnaviv_pm_signal { 159 __u32 pipe; 160 __u8 domain; 161 __u8 pad; 162 __u16 iter; 163 __u16 id; 164 char name[64]; 165}; 166#define DRM_ETNAVIV_GET_PARAM 0x00 167#define DRM_ETNAVIV_GEM_NEW 0x02 168#define DRM_ETNAVIV_GEM_INFO 0x03 169#define DRM_ETNAVIV_GEM_CPU_PREP 0x04 170#define DRM_ETNAVIV_GEM_CPU_FINI 0x05 171#define DRM_ETNAVIV_GEM_SUBMIT 0x06 172#define DRM_ETNAVIV_WAIT_FENCE 0x07 173#define DRM_ETNAVIV_GEM_USERPTR 0x08 174#define DRM_ETNAVIV_GEM_WAIT 0x09 175#define DRM_ETNAVIV_PM_QUERY_DOM 0x0a 176#define DRM_ETNAVIV_PM_QUERY_SIG 0x0b 177#define DRM_ETNAVIV_NUM_IOCTLS 0x0c 178#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param) 179#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new) 180#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info) 181#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep) 182#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini) 183#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit) 184#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence) 185#define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr) 186#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait) 187#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain) 188#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal) 189#ifdef __cplusplus 190#endif 191#endif 192