i810_drm.h revision 655a7c081f83b8351ed5f11a6c6accd9458293a8
1655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/**************************************************************************** 2655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng **************************************************************************** 3655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 4655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** This header was automatically generated from a Linux kernel header 5655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** of the same name, to make information necessary for userspace to 6655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** call into the kernel available to libc. It contains only constants, 7655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** structures, and macros generated from the original header, and thus, 8655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** contains no copyrightable information. 9655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 10655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** To edit the content of this header, modify the corresponding 11655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** source file (e.g. under external/kernel-headers/original/) then 12655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** run bionic/libc/kernel/tools/update_all.py 13655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 14655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** Any manual change here will be lost the next time this script will 15655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** be run. You've been warned! 16655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 17655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng **************************************************************************** 18655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ****************************************************************************/ 19655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#ifndef _I810_DRM_H_ 20655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define _I810_DRM_H_ 21655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#ifndef _I810_DEFINES_ 22655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define _I810_DEFINES_ 23655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_DMA_BUF_ORDER 12 25655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER) 26655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_DMA_BUF_NR 256 27655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_NR_SAREA_CLIPRECTS 8 28655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_NR_TEX_REGIONS 64 30655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_LOG_MIN_TEX_REGION_SIZE 16 31655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#endif 32655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_UPLOAD_TEX0IMAGE 0x1 33655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_UPLOAD_TEX1IMAGE 0x2 35655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_UPLOAD_CTX 0x4 36655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_UPLOAD_BUFFERS 0x8 37655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_UPLOAD_TEX0 0x10 38655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_UPLOAD_TEX1 0x20 40655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_UPLOAD_CLIPRECTS 0x40 41655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_DESTREG_DI0 0 42655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_DESTREG_DI1 1 43655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_DESTREG_DV0 2 45655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_DESTREG_DV1 3 46655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_DESTREG_DR0 4 47655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_DESTREG_DR1 5 48655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_DESTREG_DR2 6 50655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_DESTREG_DR3 7 51655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_DESTREG_DR4 8 52655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_DEST_SETUP_SIZE 10 53655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_CF0 0 55655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_CF1 1 56655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_ST0 2 57655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_ST1 3 58655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_VF 4 60655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_MT 5 61655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_MC0 6 62655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_MC1 7 63655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_MC2 8 65655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_MA0 9 66655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_MA1 10 67655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_MA2 11 68655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_SDM 12 70655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_FOG 13 71655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_B1 14 72655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_B2 15 73655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_LCS 16 75655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_PV 17 76655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_ZA 18 77655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTXREG_AA 19 78655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_CTX_SETUP_SIZE 20 80655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_TEXREG_MI0 0 81655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_TEXREG_MI1 1 82655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_TEXREG_MI2 2 83655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_TEXREG_MI3 3 85655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_TEXREG_MF 4 86655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_TEXREG_MLC 5 87655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_TEXREG_MLL 6 88655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_TEXREG_MCS 7 90655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_TEX_SETUP_SIZE 8 91655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_FRONT 0x1 92655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_BACK 0x2 93655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define I810_DEPTH 0x4 95655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef enum _drm_i810_init_func { 96655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng I810_INIT_DMA = 0x01, 97655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng I810_CLEANUP_DMA = 0x02, 98655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng I810_INIT_DMA_1_4 = 0x03 100655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_i810_init_func_t; 101655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct _drm_i810_init { 102655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng drm_i810_init_func_t func; 103655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int mmio_offset; 105655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int buffers_offset; 106655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int sarea_priv_offset; 107655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int ring_start; 108655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int ring_end; 110655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int ring_size; 111655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int front_offset; 112655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int back_offset; 113655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int depth_offset; 115655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int overlay_offset; 116655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int overlay_physical; 117655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int w; 118655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int h; 120655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int pitch; 121655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int pitch_bits; 122655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_i810_init_t; 123655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct _drm_i810_pre12_init { 125655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng drm_i810_init_func_t func; 126655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int mmio_offset; 127655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int buffers_offset; 128655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int sarea_priv_offset; 130655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int ring_start; 131655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int ring_end; 132655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int ring_size; 133655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int front_offset; 135655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int back_offset; 136655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int depth_offset; 137655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int w; 138655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int h; 140655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int pitch; 141655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int pitch_bits; 142655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_i810_pre12_init_t; 143655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct _drm_i810_tex_region { 145655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned char next, prev; 146655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned char in_use; 147655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int age; 148655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_i810_tex_region_t; 150655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct _drm_i810_sarea { 151655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int ContextState[I810_CTX_SETUP_SIZE]; 152655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int BufferState[I810_DEST_SETUP_SIZE]; 153655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int TexState[2][I810_TEX_SETUP_SIZE]; 155655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int dirty; 156655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int nbox; 157655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS]; 158655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1]; 160655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int texAge; 161655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int last_enqueue; 162655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int last_dispatch; 163655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int last_quiescent; 165655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int ctxOwner; 166655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int vertex_prim; 167655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int pf_enabled; 168655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int pf_active; 170655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int pf_current_page; 171655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_i810_sarea_t; 172655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_I810_INIT 0x00 173655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_I810_VERTEX 0x01 175655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_I810_CLEAR 0x02 176655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_I810_FLUSH 0x03 177655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_I810_GETAGE 0x04 178655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_I810_GETBUF 0x05 180655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_I810_SWAP 0x06 181655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_I810_COPY 0x07 182655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_I810_DOCOPY 0x08 183655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_I810_OV0INFO 0x09 185655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_I810_FSTATUS 0x0a 186655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_I810_OV0FLIP 0x0b 187655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_I810_MC 0x0c 188655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_I810_RSTATUS 0x0d 190655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_I810_FLIP 0x0e 191655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_I810_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t) 192655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_I810_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t) 193655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_I810_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t) 195655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_I810_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_I810_FLUSH) 196655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_I810_GETAGE DRM_IO( DRM_COMMAND_BASE + DRM_I810_GETAGE) 197655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t) 198655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_I810_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_I810_SWAP) 200655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_I810_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t) 201655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_I810_DOCOPY DRM_IO( DRM_COMMAND_BASE + DRM_I810_DOCOPY) 202655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_I810_OV0INFO DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t) 203655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_I810_FSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS) 205655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP) 206655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_I810_MC DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t) 207655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_I810_RSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS) 208655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_I810_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP) 210655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct _drm_i810_clear { 211655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int clear_color; 212655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int clear_depth; 213655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int flags; 215655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_i810_clear_t; 216655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct _drm_i810_vertex { 217655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int idx; 218655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int used; 220655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int discard; 221655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_i810_vertex_t; 222655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct _drm_i810_copy_t { 223655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int idx; 225655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int used; 226655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng void *address; 227655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_i810_copy_t; 228655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PR_TRIANGLES (0x0<<18) 230655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PR_TRISTRIP_0 (0x1<<18) 231655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PR_TRISTRIP_1 (0x2<<18) 232655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PR_TRIFAN (0x3<<18) 233655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PR_POLYGON (0x4<<18) 235655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PR_LINES (0x5<<18) 236655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PR_LINESTRIP (0x6<<18) 237655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PR_RECTS (0x7<<18) 238655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PR_MASK (0x7<<18) 240655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_i810_dma { 241655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng void *virtual; 242655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int request_idx; 243655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int request_size; 245655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int granted; 246655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_i810_dma_t; 247655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct _drm_i810_overlay_t { 248655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int offset; 250655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int physical; 251655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_i810_overlay_t; 252655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct _drm_i810_mc { 253655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int idx; 255655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int used; 256655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int num_blocks; 257655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng int *length; 258655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng unsigned int last_render; 260655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_i810_mc_t; 261655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#endif 262