i915_drm.h revision 106b3a8a7dc03c19a45e322de425ac56aafac358
1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef _UAPI_I915_DRM_H_ 20#define _UAPI_I915_DRM_H_ 21#include "drm.h" 22#ifdef __cplusplus 23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24#endif 25#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 26#define I915_ERROR_UEVENT "ERROR" 27#define I915_RESET_UEVENT "RESET" 28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29#define I915_NR_TEX_REGIONS 255 30#define I915_LOG_MIN_TEX_REGION_SIZE 14 31typedef struct _drm_i915_init { 32 enum { 33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 I915_INIT_DMA = 0x01, 35 I915_CLEANUP_DMA = 0x02, 36 I915_RESUME_DMA = 0x03 37 } func; 38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 unsigned int mmio_offset; 40 int sarea_priv_offset; 41 unsigned int ring_start; 42 unsigned int ring_end; 43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 unsigned int ring_size; 45 unsigned int front_offset; 46 unsigned int back_offset; 47 unsigned int depth_offset; 48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 unsigned int w; 50 unsigned int h; 51 unsigned int pitch; 52 unsigned int pitch_bits; 53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 unsigned int back_pitch; 55 unsigned int depth_pitch; 56 unsigned int cpp; 57 unsigned int chipset; 58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59} drm_i915_init_t; 60typedef struct _drm_i915_sarea { 61 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 62 int last_upload; 63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 int last_enqueue; 65 int last_dispatch; 66 int ctxOwner; 67 int texAge; 68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 int pf_enabled; 70 int pf_active; 71 int pf_current_page; 72 int perf_boxes; 73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 int width, height; 75 drm_handle_t front_handle; 76 int front_offset; 77 int front_size; 78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 drm_handle_t back_handle; 80 int back_offset; 81 int back_size; 82 drm_handle_t depth_handle; 83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 int depth_offset; 85 int depth_size; 86 drm_handle_t tex_handle; 87 int tex_offset; 88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 int tex_size; 90 int log_tex_granularity; 91 int pitch; 92 int rotation; 93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 int rotated_offset; 95 int rotated_size; 96 int rotated_pitch; 97 int virtualX, virtualY; 98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 unsigned int front_tiled; 100 unsigned int back_tiled; 101 unsigned int depth_tiled; 102 unsigned int rotated_tiled; 103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 unsigned int rotated2_tiled; 105 int pipeA_x; 106 int pipeA_y; 107 int pipeA_w; 108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 int pipeA_h; 110 int pipeB_x; 111 int pipeB_y; 112 int pipeB_w; 113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 int pipeB_h; 115 drm_handle_t unused_handle; 116 __u32 unused1, unused2, unused3; 117 __u32 front_bo_handle; 118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 __u32 back_bo_handle; 120 __u32 unused_bo_handle; 121 __u32 depth_bo_handle; 122} drm_i915_sarea_t; 123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124#define planeA_x pipeA_x 125#define planeA_y pipeA_y 126#define planeA_w pipeA_w 127#define planeA_h pipeA_h 128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129#define planeB_x pipeB_x 130#define planeB_y pipeB_y 131#define planeB_w pipeB_w 132#define planeB_h pipeB_h 133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134#define I915_BOX_RING_EMPTY 0x1 135#define I915_BOX_FLIP 0x2 136#define I915_BOX_WAIT 0x4 137#define I915_BOX_TEXTURE_LOAD 0x8 138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139#define I915_BOX_LOST_CONTEXT 0x10 140#define DRM_I915_INIT 0x00 141#define DRM_I915_FLUSH 0x01 142#define DRM_I915_FLIP 0x02 143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144#define DRM_I915_BATCHBUFFER 0x03 145#define DRM_I915_IRQ_EMIT 0x04 146#define DRM_I915_IRQ_WAIT 0x05 147#define DRM_I915_GETPARAM 0x06 148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149#define DRM_I915_SETPARAM 0x07 150#define DRM_I915_ALLOC 0x08 151#define DRM_I915_FREE 0x09 152#define DRM_I915_INIT_HEAP 0x0a 153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154#define DRM_I915_CMDBUFFER 0x0b 155#define DRM_I915_DESTROY_HEAP 0x0c 156#define DRM_I915_SET_VBLANK_PIPE 0x0d 157#define DRM_I915_GET_VBLANK_PIPE 0x0e 158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159#define DRM_I915_VBLANK_SWAP 0x0f 160#define DRM_I915_HWS_ADDR 0x11 161#define DRM_I915_GEM_INIT 0x13 162#define DRM_I915_GEM_EXECBUFFER 0x14 163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164#define DRM_I915_GEM_PIN 0x15 165#define DRM_I915_GEM_UNPIN 0x16 166#define DRM_I915_GEM_BUSY 0x17 167#define DRM_I915_GEM_THROTTLE 0x18 168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169#define DRM_I915_GEM_ENTERVT 0x19 170#define DRM_I915_GEM_LEAVEVT 0x1a 171#define DRM_I915_GEM_CREATE 0x1b 172#define DRM_I915_GEM_PREAD 0x1c 173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174#define DRM_I915_GEM_PWRITE 0x1d 175#define DRM_I915_GEM_MMAP 0x1e 176#define DRM_I915_GEM_SET_DOMAIN 0x1f 177#define DRM_I915_GEM_SW_FINISH 0x20 178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179#define DRM_I915_GEM_SET_TILING 0x21 180#define DRM_I915_GEM_GET_TILING 0x22 181#define DRM_I915_GEM_GET_APERTURE 0x23 182#define DRM_I915_GEM_MMAP_GTT 0x24 183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 185#define DRM_I915_GEM_MADVISE 0x26 186#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 187#define DRM_I915_OVERLAY_ATTRS 0x28 188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189#define DRM_I915_GEM_EXECBUFFER2 0x29 190#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 191#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 192#define DRM_I915_GEM_WAIT 0x2c 193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 195#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 196#define DRM_I915_GEM_SET_CACHING 0x2f 197#define DRM_I915_GEM_GET_CACHING 0x30 198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199#define DRM_I915_REG_READ 0x31 200#define DRM_I915_GET_RESET_STATS 0x32 201#define DRM_I915_GEM_USERPTR 0x33 202#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 205#define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 206#define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH) 207#define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP) 208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 210#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 211#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 212#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214#define DRM_IOCTL_I915_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 215#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 216#define DRM_IOCTL_I915_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 217#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 220#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 221#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 222#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 225#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 226#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 227#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 230#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 231#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 232#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 235#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 236#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 237#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 240#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 241#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 242#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 245#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 246#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 247#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 250#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 251#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 252#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 255#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 256#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 257#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 260#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 261#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 262#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264#define DRM_IOCTL_I915_REG_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 265#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 266#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 267#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 270typedef struct drm_i915_batchbuffer { 271 int start; 272 int used; 273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 int DR1; 275 int DR4; 276 int num_cliprects; 277 struct drm_clip_rect __user * cliprects; 278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279} drm_i915_batchbuffer_t; 280typedef struct _drm_i915_cmdbuffer { 281 char __user * buf; 282 int sz; 283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 int DR1; 285 int DR4; 286 int num_cliprects; 287 struct drm_clip_rect __user * cliprects; 288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289} drm_i915_cmdbuffer_t; 290typedef struct drm_i915_irq_emit { 291 int __user * irq_seq; 292} drm_i915_irq_emit_t; 293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294typedef struct drm_i915_irq_wait { 295 int irq_seq; 296} drm_i915_irq_wait_t; 297#define I915_PARAM_IRQ_ACTIVE 1 298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299#define I915_PARAM_ALLOW_BATCHBUFFER 2 300#define I915_PARAM_LAST_DISPATCH 3 301#define I915_PARAM_CHIPSET_ID 4 302#define I915_PARAM_HAS_GEM 5 303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304#define I915_PARAM_NUM_FENCES_AVAIL 6 305#define I915_PARAM_HAS_OVERLAY 7 306#define I915_PARAM_HAS_PAGEFLIPPING 8 307#define I915_PARAM_HAS_EXECBUF2 9 308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309#define I915_PARAM_HAS_BSD 10 310#define I915_PARAM_HAS_BLT 11 311#define I915_PARAM_HAS_RELAXED_FENCING 12 312#define I915_PARAM_HAS_COHERENT_RINGS 13 313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314#define I915_PARAM_HAS_EXEC_CONSTANTS 14 315#define I915_PARAM_HAS_RELAXED_DELTA 15 316#define I915_PARAM_HAS_GEN7_SOL_RESET 16 317#define I915_PARAM_HAS_LLC 17 318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319#define I915_PARAM_HAS_ALIASING_PPGTT 18 320#define I915_PARAM_HAS_WAIT_TIMEOUT 19 321#define I915_PARAM_HAS_SEMAPHORES 20 322#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324#define I915_PARAM_HAS_VEBOX 22 325#define I915_PARAM_HAS_SECURE_BATCHES 23 326#define I915_PARAM_HAS_PINNED_BATCHES 24 327#define I915_PARAM_HAS_EXEC_NO_RELOC 25 328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 330#define I915_PARAM_HAS_WT 27 331#define I915_PARAM_CMD_PARSER_VERSION 28 332#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334#define I915_PARAM_MMAP_VERSION 30 335#define I915_PARAM_HAS_BSD2 31 336#define I915_PARAM_REVISION 32 337#define I915_PARAM_SUBSLICE_TOTAL 33 338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339#define I915_PARAM_EU_TOTAL 34 340#define I915_PARAM_HAS_GPU_RESET 35 341#define I915_PARAM_HAS_RESOURCE_STREAMER 36 342#define I915_PARAM_HAS_EXEC_SOFTPIN 37 343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344typedef struct drm_i915_getparam { 345 __s32 param; 346 int __user * value; 347} drm_i915_getparam_t; 348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 350#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 351#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 352#define I915_SETPARAM_NUM_USED_FENCES 4 353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354typedef struct drm_i915_setparam { 355 int param; 356 int value; 357} drm_i915_setparam_t; 358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359#define I915_MEM_REGION_AGP 1 360typedef struct drm_i915_mem_alloc { 361 int region; 362 int alignment; 363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 int size; 365 int __user * region_offset; 366} drm_i915_mem_alloc_t; 367typedef struct drm_i915_mem_free { 368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 int region; 370 int region_offset; 371} drm_i915_mem_free_t; 372typedef struct drm_i915_mem_init_heap { 373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 int region; 375 int size; 376 int start; 377} drm_i915_mem_init_heap_t; 378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379typedef struct drm_i915_mem_destroy_heap { 380 int region; 381} drm_i915_mem_destroy_heap_t; 382#define DRM_I915_VBLANK_PIPE_A 1 383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384#define DRM_I915_VBLANK_PIPE_B 2 385typedef struct drm_i915_vblank_pipe { 386 int pipe; 387} drm_i915_vblank_pipe_t; 388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389typedef struct drm_i915_vblank_swap { 390 drm_drawable_t drawable; 391 enum drm_vblank_seq_type seqtype; 392 unsigned int sequence; 393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394} drm_i915_vblank_swap_t; 395typedef struct drm_i915_hws_addr { 396 __u64 addr; 397} drm_i915_hws_addr_t; 398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399struct drm_i915_gem_init { 400 __u64 gtt_start; 401 __u64 gtt_end; 402}; 403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404struct drm_i915_gem_create { 405 __u64 size; 406 __u32 handle; 407 __u32 pad; 408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409}; 410struct drm_i915_gem_pread { 411 __u32 handle; 412 __u32 pad; 413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 __u64 offset; 415 __u64 size; 416 __u64 data_ptr; 417}; 418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419struct drm_i915_gem_pwrite { 420 __u32 handle; 421 __u32 pad; 422 __u64 offset; 423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 __u64 size; 425 __u64 data_ptr; 426}; 427struct drm_i915_gem_mmap { 428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 __u32 handle; 430 __u32 pad; 431 __u64 offset; 432 __u64 size; 433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 __u64 addr_ptr; 435 __u64 flags; 436#define I915_MMAP_WC 0x1 437}; 438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439struct drm_i915_gem_mmap_gtt { 440 __u32 handle; 441 __u32 pad; 442 __u64 offset; 443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444}; 445struct drm_i915_gem_set_domain { 446 __u32 handle; 447 __u32 read_domains; 448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 __u32 write_domain; 450}; 451struct drm_i915_gem_sw_finish { 452 __u32 handle; 453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454}; 455struct drm_i915_gem_relocation_entry { 456 __u32 target_handle; 457 __u32 delta; 458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 __u64 offset; 460 __u64 presumed_offset; 461 __u32 read_domains; 462 __u32 write_domain; 463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464}; 465#define I915_GEM_DOMAIN_CPU 0x00000001 466#define I915_GEM_DOMAIN_RENDER 0x00000002 467#define I915_GEM_DOMAIN_SAMPLER 0x00000004 468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469#define I915_GEM_DOMAIN_COMMAND 0x00000008 470#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 471#define I915_GEM_DOMAIN_VERTEX 0x00000020 472#define I915_GEM_DOMAIN_GTT 0x00000040 473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474struct drm_i915_gem_exec_object { 475 __u32 handle; 476 __u32 relocation_count; 477 __u64 relocs_ptr; 478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 __u64 alignment; 480 __u64 offset; 481}; 482struct drm_i915_gem_execbuffer { 483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 __u64 buffers_ptr; 485 __u32 buffer_count; 486 __u32 batch_start_offset; 487 __u32 batch_len; 488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 __u32 DR1; 490 __u32 DR4; 491 __u32 num_cliprects; 492 __u64 cliprects_ptr; 493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494}; 495struct drm_i915_gem_exec_object2 { 496 __u32 handle; 497 __u32 relocation_count; 498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499 __u64 relocs_ptr; 500 __u64 alignment; 501 __u64 offset; 502#define EXEC_OBJECT_NEEDS_FENCE (1 << 0) 503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504#define EXEC_OBJECT_NEEDS_GTT (1 << 1) 505#define EXEC_OBJECT_WRITE (1 << 2) 506#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1 << 3) 507#define EXEC_OBJECT_PINNED (1 << 4) 508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509#define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_PINNED << 1) 510 __u64 flags; 511 __u64 rsvd1; 512 __u64 rsvd2; 513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514}; 515struct drm_i915_gem_execbuffer2 { 516 __u64 buffers_ptr; 517 __u32 buffer_count; 518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519 __u32 batch_start_offset; 520 __u32 batch_len; 521 __u32 DR1; 522 __u32 DR4; 523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524 __u32 num_cliprects; 525 __u64 cliprects_ptr; 526#define I915_EXEC_RING_MASK (7 << 0) 527#define I915_EXEC_DEFAULT (0 << 0) 528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529#define I915_EXEC_RENDER (1 << 0) 530#define I915_EXEC_BSD (2 << 0) 531#define I915_EXEC_BLT (3 << 0) 532#define I915_EXEC_VEBOX (4 << 0) 533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534#define I915_EXEC_CONSTANTS_MASK (3 << 6) 535#define I915_EXEC_CONSTANTS_REL_GENERAL (0 << 6) 536#define I915_EXEC_CONSTANTS_ABSOLUTE (1 << 6) 537#define I915_EXEC_CONSTANTS_REL_SURFACE (2 << 6) 538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 __u64 flags; 540 __u64 rsvd1; 541 __u64 rsvd2; 542}; 543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544#define I915_EXEC_GEN7_SOL_RESET (1 << 8) 545#define I915_EXEC_SECURE (1 << 9) 546#define I915_EXEC_IS_PINNED (1 << 10) 547#define I915_EXEC_NO_RELOC (1 << 11) 548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549#define I915_EXEC_HANDLE_LUT (1 << 12) 550#define I915_EXEC_BSD_SHIFT (13) 551#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 552#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 555#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 556#define I915_EXEC_RESOURCE_STREAMER (1 << 15) 557#define __I915_EXEC_UNKNOWN_FLAGS - (I915_EXEC_RESOURCE_STREAMER << 1) 558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 560#define i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 561#define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 562struct drm_i915_gem_pin { 563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564 __u32 handle; 565 __u32 pad; 566 __u64 alignment; 567 __u64 offset; 568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569}; 570struct drm_i915_gem_unpin { 571 __u32 handle; 572 __u32 pad; 573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574}; 575struct drm_i915_gem_busy { 576 __u32 handle; 577 __u32 busy; 578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579}; 580#define I915_CACHING_NONE 0 581#define I915_CACHING_CACHED 1 582#define I915_CACHING_DISPLAY 2 583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584struct drm_i915_gem_caching { 585 __u32 handle; 586 __u32 caching; 587}; 588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589#define I915_TILING_NONE 0 590#define I915_TILING_X 1 591#define I915_TILING_Y 2 592#define I915_BIT_6_SWIZZLE_NONE 0 593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594#define I915_BIT_6_SWIZZLE_9 1 595#define I915_BIT_6_SWIZZLE_9_10 2 596#define I915_BIT_6_SWIZZLE_9_11 3 597#define I915_BIT_6_SWIZZLE_9_10_11 4 598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599#define I915_BIT_6_SWIZZLE_UNKNOWN 5 600#define I915_BIT_6_SWIZZLE_9_17 6 601#define I915_BIT_6_SWIZZLE_9_10_17 7 602struct drm_i915_gem_set_tiling { 603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604 __u32 handle; 605 __u32 tiling_mode; 606 __u32 stride; 607 __u32 swizzle_mode; 608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609}; 610struct drm_i915_gem_get_tiling { 611 __u32 handle; 612 __u32 tiling_mode; 613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614 __u32 swizzle_mode; 615 __u32 phys_swizzle_mode; 616}; 617struct drm_i915_gem_get_aperture { 618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619 __u64 aper_size; 620 __u64 aper_available_size; 621}; 622struct drm_i915_get_pipe_from_crtc_id { 623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624 __u32 crtc_id; 625 __u32 pipe; 626}; 627#define I915_MADV_WILLNEED 0 628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629#define I915_MADV_DONTNEED 1 630#define __I915_MADV_PURGED 2 631struct drm_i915_gem_madvise { 632 __u32 handle; 633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634 __u32 madv; 635 __u32 retained; 636}; 637#define I915_OVERLAY_TYPE_MASK 0xff 638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639#define I915_OVERLAY_YUV_PLANAR 0x01 640#define I915_OVERLAY_YUV_PACKED 0x02 641#define I915_OVERLAY_RGB 0x03 642#define I915_OVERLAY_DEPTH_MASK 0xff00 643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644#define I915_OVERLAY_RGB24 0x1000 645#define I915_OVERLAY_RGB16 0x2000 646#define I915_OVERLAY_RGB15 0x3000 647#define I915_OVERLAY_YUV422 0x0100 648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649#define I915_OVERLAY_YUV411 0x0200 650#define I915_OVERLAY_YUV420 0x0300 651#define I915_OVERLAY_YUV410 0x0400 652#define I915_OVERLAY_SWAP_MASK 0xff0000 653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654#define I915_OVERLAY_NO_SWAP 0x000000 655#define I915_OVERLAY_UV_SWAP 0x010000 656#define I915_OVERLAY_Y_SWAP 0x020000 657#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659#define I915_OVERLAY_FLAGS_MASK 0xff000000 660#define I915_OVERLAY_ENABLE 0x01000000 661struct drm_intel_overlay_put_image { 662 __u32 flags; 663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664 __u32 bo_handle; 665 __u16 stride_Y; 666 __u16 stride_UV; 667 __u32 offset_Y; 668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669 __u32 offset_U; 670 __u32 offset_V; 671 __u16 src_width; 672 __u16 src_height; 673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674 __u16 src_scan_width; 675 __u16 src_scan_height; 676 __u32 crtc_id; 677 __u16 dst_x; 678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679 __u16 dst_y; 680 __u16 dst_width; 681 __u16 dst_height; 682}; 683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684#define I915_OVERLAY_UPDATE_ATTRS (1 << 0) 685#define I915_OVERLAY_UPDATE_GAMMA (1 << 1) 686#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1 << 2) 687struct drm_intel_overlay_attrs { 688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689 __u32 flags; 690 __u32 color_key; 691 __s32 brightness; 692 __u32 contrast; 693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694 __u32 saturation; 695 __u32 gamma0; 696 __u32 gamma1; 697 __u32 gamma2; 698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699 __u32 gamma3; 700 __u32 gamma4; 701 __u32 gamma5; 702}; 703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704#define I915_SET_COLORKEY_NONE (1 << 0) 705#define I915_SET_COLORKEY_DESTINATION (1 << 1) 706#define I915_SET_COLORKEY_SOURCE (1 << 2) 707struct drm_intel_sprite_colorkey { 708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709 __u32 plane_id; 710 __u32 min_value; 711 __u32 channel_mask; 712 __u32 max_value; 713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714 __u32 flags; 715}; 716struct drm_i915_gem_wait { 717 __u32 bo_handle; 718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719 __u32 flags; 720 __s64 timeout_ns; 721}; 722struct drm_i915_gem_context_create { 723/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724 __u32 ctx_id; 725 __u32 pad; 726}; 727struct drm_i915_gem_context_destroy { 728/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729 __u32 ctx_id; 730 __u32 pad; 731}; 732struct drm_i915_reg_read { 733/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734 __u64 offset; 735 __u64 val; 736}; 737struct drm_i915_reset_stats { 738/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739 __u32 ctx_id; 740 __u32 flags; 741 __u32 reset_count; 742 __u32 batch_active; 743/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744 __u32 batch_pending; 745 __u32 pad; 746}; 747struct drm_i915_gem_userptr { 748/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749 __u64 user_ptr; 750 __u64 user_size; 751 __u32 flags; 752#define I915_USERPTR_READ_ONLY 0x1 753/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754#define I915_USERPTR_UNSYNCHRONIZED 0x80000000 755 __u32 handle; 756}; 757struct drm_i915_gem_context_param { 758/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759 __u32 ctx_id; 760 __u32 size; 761 __u64 param; 762#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 763/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 765#define I915_CONTEXT_PARAM_GTT_SIZE 0x3 766 __u64 value; 767}; 768/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769#ifdef __cplusplus 770#endif 771#endif 772