i915_drm.h revision 48af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0
1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef _UAPI_I915_DRM_H_ 20#define _UAPI_I915_DRM_H_ 21#include "drm.h" 22#ifdef __cplusplus 23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24#endif 25#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 26#define I915_ERROR_UEVENT "ERROR" 27#define I915_RESET_UEVENT "RESET" 28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29enum i915_mocs_table_index { 30 I915_MOCS_UNCACHED, 31 I915_MOCS_PTE, 32 I915_MOCS_CACHED, 33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34}; 35#define I915_NR_TEX_REGIONS 255 36#define I915_LOG_MIN_TEX_REGION_SIZE 14 37typedef struct _drm_i915_init { 38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 enum { 40 I915_INIT_DMA = 0x01, 41 I915_CLEANUP_DMA = 0x02, 42 I915_RESUME_DMA = 0x03 43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 } func; 45 unsigned int mmio_offset; 46 int sarea_priv_offset; 47 unsigned int ring_start; 48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 unsigned int ring_end; 50 unsigned int ring_size; 51 unsigned int front_offset; 52 unsigned int back_offset; 53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 unsigned int depth_offset; 55 unsigned int w; 56 unsigned int h; 57 unsigned int pitch; 58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 unsigned int pitch_bits; 60 unsigned int back_pitch; 61 unsigned int depth_pitch; 62 unsigned int cpp; 63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 unsigned int chipset; 65} drm_i915_init_t; 66typedef struct _drm_i915_sarea { 67 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 int last_upload; 70 int last_enqueue; 71 int last_dispatch; 72 int ctxOwner; 73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 int texAge; 75 int pf_enabled; 76 int pf_active; 77 int pf_current_page; 78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 int perf_boxes; 80 int width, height; 81 drm_handle_t front_handle; 82 int front_offset; 83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 int front_size; 85 drm_handle_t back_handle; 86 int back_offset; 87 int back_size; 88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 drm_handle_t depth_handle; 90 int depth_offset; 91 int depth_size; 92 drm_handle_t tex_handle; 93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 int tex_offset; 95 int tex_size; 96 int log_tex_granularity; 97 int pitch; 98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 int rotation; 100 int rotated_offset; 101 int rotated_size; 102 int rotated_pitch; 103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 int virtualX, virtualY; 105 unsigned int front_tiled; 106 unsigned int back_tiled; 107 unsigned int depth_tiled; 108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 unsigned int rotated_tiled; 110 unsigned int rotated2_tiled; 111 int pipeA_x; 112 int pipeA_y; 113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 int pipeA_w; 115 int pipeA_h; 116 int pipeB_x; 117 int pipeB_y; 118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 int pipeB_w; 120 int pipeB_h; 121 drm_handle_t unused_handle; 122 __u32 unused1, unused2, unused3; 123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 __u32 front_bo_handle; 125 __u32 back_bo_handle; 126 __u32 unused_bo_handle; 127 __u32 depth_bo_handle; 128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129} drm_i915_sarea_t; 130#define planeA_x pipeA_x 131#define planeA_y pipeA_y 132#define planeA_w pipeA_w 133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134#define planeA_h pipeA_h 135#define planeB_x pipeB_x 136#define planeB_y pipeB_y 137#define planeB_w pipeB_w 138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139#define planeB_h pipeB_h 140#define I915_BOX_RING_EMPTY 0x1 141#define I915_BOX_FLIP 0x2 142#define I915_BOX_WAIT 0x4 143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144#define I915_BOX_TEXTURE_LOAD 0x8 145#define I915_BOX_LOST_CONTEXT 0x10 146#define DRM_I915_INIT 0x00 147#define DRM_I915_FLUSH 0x01 148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149#define DRM_I915_FLIP 0x02 150#define DRM_I915_BATCHBUFFER 0x03 151#define DRM_I915_IRQ_EMIT 0x04 152#define DRM_I915_IRQ_WAIT 0x05 153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154#define DRM_I915_GETPARAM 0x06 155#define DRM_I915_SETPARAM 0x07 156#define DRM_I915_ALLOC 0x08 157#define DRM_I915_FREE 0x09 158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159#define DRM_I915_INIT_HEAP 0x0a 160#define DRM_I915_CMDBUFFER 0x0b 161#define DRM_I915_DESTROY_HEAP 0x0c 162#define DRM_I915_SET_VBLANK_PIPE 0x0d 163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164#define DRM_I915_GET_VBLANK_PIPE 0x0e 165#define DRM_I915_VBLANK_SWAP 0x0f 166#define DRM_I915_HWS_ADDR 0x11 167#define DRM_I915_GEM_INIT 0x13 168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169#define DRM_I915_GEM_EXECBUFFER 0x14 170#define DRM_I915_GEM_PIN 0x15 171#define DRM_I915_GEM_UNPIN 0x16 172#define DRM_I915_GEM_BUSY 0x17 173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174#define DRM_I915_GEM_THROTTLE 0x18 175#define DRM_I915_GEM_ENTERVT 0x19 176#define DRM_I915_GEM_LEAVEVT 0x1a 177#define DRM_I915_GEM_CREATE 0x1b 178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179#define DRM_I915_GEM_PREAD 0x1c 180#define DRM_I915_GEM_PWRITE 0x1d 181#define DRM_I915_GEM_MMAP 0x1e 182#define DRM_I915_GEM_SET_DOMAIN 0x1f 183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184#define DRM_I915_GEM_SW_FINISH 0x20 185#define DRM_I915_GEM_SET_TILING 0x21 186#define DRM_I915_GEM_GET_TILING 0x22 187#define DRM_I915_GEM_GET_APERTURE 0x23 188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189#define DRM_I915_GEM_MMAP_GTT 0x24 190#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 191#define DRM_I915_GEM_MADVISE 0x26 192#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194#define DRM_I915_OVERLAY_ATTRS 0x28 195#define DRM_I915_GEM_EXECBUFFER2 0x29 196#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 197#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199#define DRM_I915_GEM_WAIT 0x2c 200#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 201#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 202#define DRM_I915_GEM_SET_CACHING 0x2f 203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204#define DRM_I915_GEM_GET_CACHING 0x30 205#define DRM_I915_REG_READ 0x31 206#define DRM_I915_GET_RESET_STATS 0x32 207#define DRM_I915_GEM_USERPTR 0x33 208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 210#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 211#define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 212#define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH) 213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214#define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP) 215#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 216#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 217#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 220#define DRM_IOCTL_I915_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 221#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 222#define DRM_IOCTL_I915_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 225#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 226#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 227#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 230#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 231#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 232#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 235#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 236#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 237#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 240#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 241#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 242#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 245#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 246#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 247#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 250#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 251#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 252#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 255#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 256#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 257#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 260#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 261#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 262#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 265#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 266#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 267#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 270#define DRM_IOCTL_I915_REG_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 271#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 272#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 275#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 276typedef struct drm_i915_batchbuffer { 277 int start; 278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 int used; 280 int DR1; 281 int DR4; 282 int num_cliprects; 283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 struct drm_clip_rect __user * cliprects; 285} drm_i915_batchbuffer_t; 286typedef struct _drm_i915_cmdbuffer { 287 char __user * buf; 288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 int sz; 290 int DR1; 291 int DR4; 292 int num_cliprects; 293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 struct drm_clip_rect __user * cliprects; 295} drm_i915_cmdbuffer_t; 296typedef struct drm_i915_irq_emit { 297 int __user * irq_seq; 298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299} drm_i915_irq_emit_t; 300typedef struct drm_i915_irq_wait { 301 int irq_seq; 302} drm_i915_irq_wait_t; 303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304#define I915_PARAM_IRQ_ACTIVE 1 305#define I915_PARAM_ALLOW_BATCHBUFFER 2 306#define I915_PARAM_LAST_DISPATCH 3 307#define I915_PARAM_CHIPSET_ID 4 308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309#define I915_PARAM_HAS_GEM 5 310#define I915_PARAM_NUM_FENCES_AVAIL 6 311#define I915_PARAM_HAS_OVERLAY 7 312#define I915_PARAM_HAS_PAGEFLIPPING 8 313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314#define I915_PARAM_HAS_EXECBUF2 9 315#define I915_PARAM_HAS_BSD 10 316#define I915_PARAM_HAS_BLT 11 317#define I915_PARAM_HAS_RELAXED_FENCING 12 318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319#define I915_PARAM_HAS_COHERENT_RINGS 13 320#define I915_PARAM_HAS_EXEC_CONSTANTS 14 321#define I915_PARAM_HAS_RELAXED_DELTA 15 322#define I915_PARAM_HAS_GEN7_SOL_RESET 16 323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324#define I915_PARAM_HAS_LLC 17 325#define I915_PARAM_HAS_ALIASING_PPGTT 18 326#define I915_PARAM_HAS_WAIT_TIMEOUT 19 327#define I915_PARAM_HAS_SEMAPHORES 20 328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 330#define I915_PARAM_HAS_VEBOX 22 331#define I915_PARAM_HAS_SECURE_BATCHES 23 332#define I915_PARAM_HAS_PINNED_BATCHES 24 333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334#define I915_PARAM_HAS_EXEC_NO_RELOC 25 335#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 336#define I915_PARAM_HAS_WT 27 337#define I915_PARAM_CMD_PARSER_VERSION 28 338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 340#define I915_PARAM_MMAP_VERSION 30 341#define I915_PARAM_HAS_BSD2 31 342#define I915_PARAM_REVISION 32 343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344#define I915_PARAM_SUBSLICE_TOTAL 33 345#define I915_PARAM_EU_TOTAL 34 346#define I915_PARAM_HAS_GPU_RESET 35 347#define I915_PARAM_HAS_RESOURCE_STREAMER 36 348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349#define I915_PARAM_HAS_EXEC_SOFTPIN 37 350#define I915_PARAM_HAS_POOLED_EU 38 351#define I915_PARAM_MIN_EU_IN_POOL 39 352#define I915_PARAM_MMAP_GTT_VERSION 40 353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354#define I915_PARAM_HAS_SCHEDULER 41 355typedef struct drm_i915_getparam { 356 __s32 param; 357 int __user * value; 358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359} drm_i915_getparam_t; 360#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 361#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 362#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364#define I915_SETPARAM_NUM_USED_FENCES 4 365typedef struct drm_i915_setparam { 366 int param; 367 int value; 368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369} drm_i915_setparam_t; 370#define I915_MEM_REGION_AGP 1 371typedef struct drm_i915_mem_alloc { 372 int region; 373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 int alignment; 375 int size; 376 int __user * region_offset; 377} drm_i915_mem_alloc_t; 378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379typedef struct drm_i915_mem_free { 380 int region; 381 int region_offset; 382} drm_i915_mem_free_t; 383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384typedef struct drm_i915_mem_init_heap { 385 int region; 386 int size; 387 int start; 388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389} drm_i915_mem_init_heap_t; 390typedef struct drm_i915_mem_destroy_heap { 391 int region; 392} drm_i915_mem_destroy_heap_t; 393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394#define DRM_I915_VBLANK_PIPE_A 1 395#define DRM_I915_VBLANK_PIPE_B 2 396typedef struct drm_i915_vblank_pipe { 397 int pipe; 398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399} drm_i915_vblank_pipe_t; 400typedef struct drm_i915_vblank_swap { 401 drm_drawable_t drawable; 402 enum drm_vblank_seq_type seqtype; 403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 unsigned int sequence; 405} drm_i915_vblank_swap_t; 406typedef struct drm_i915_hws_addr { 407 __u64 addr; 408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409} drm_i915_hws_addr_t; 410struct drm_i915_gem_init { 411 __u64 gtt_start; 412 __u64 gtt_end; 413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414}; 415struct drm_i915_gem_create { 416 __u64 size; 417 __u32 handle; 418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 __u32 pad; 420}; 421struct drm_i915_gem_pread { 422 __u32 handle; 423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 __u32 pad; 425 __u64 offset; 426 __u64 size; 427 __u64 data_ptr; 428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429}; 430struct drm_i915_gem_pwrite { 431 __u32 handle; 432 __u32 pad; 433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 __u64 offset; 435 __u64 size; 436 __u64 data_ptr; 437}; 438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439struct drm_i915_gem_mmap { 440 __u32 handle; 441 __u32 pad; 442 __u64 offset; 443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444 __u64 size; 445 __u64 addr_ptr; 446 __u64 flags; 447#define I915_MMAP_WC 0x1 448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449}; 450struct drm_i915_gem_mmap_gtt { 451 __u32 handle; 452 __u32 pad; 453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 __u64 offset; 455}; 456struct drm_i915_gem_set_domain { 457 __u32 handle; 458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 __u32 read_domains; 460 __u32 write_domain; 461}; 462struct drm_i915_gem_sw_finish { 463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 __u32 handle; 465}; 466struct drm_i915_gem_relocation_entry { 467 __u32 target_handle; 468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 __u32 delta; 470 __u64 offset; 471 __u64 presumed_offset; 472 __u32 read_domains; 473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 __u32 write_domain; 475}; 476#define I915_GEM_DOMAIN_CPU 0x00000001 477#define I915_GEM_DOMAIN_RENDER 0x00000002 478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479#define I915_GEM_DOMAIN_SAMPLER 0x00000004 480#define I915_GEM_DOMAIN_COMMAND 0x00000008 481#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 482#define I915_GEM_DOMAIN_VERTEX 0x00000020 483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484#define I915_GEM_DOMAIN_GTT 0x00000040 485struct drm_i915_gem_exec_object { 486 __u32 handle; 487 __u32 relocation_count; 488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 __u64 relocs_ptr; 490 __u64 alignment; 491 __u64 offset; 492}; 493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494struct drm_i915_gem_execbuffer { 495 __u64 buffers_ptr; 496 __u32 buffer_count; 497 __u32 batch_start_offset; 498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499 __u32 batch_len; 500 __u32 DR1; 501 __u32 DR4; 502 __u32 num_cliprects; 503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504 __u64 cliprects_ptr; 505}; 506struct drm_i915_gem_exec_object2 { 507 __u32 handle; 508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509 __u32 relocation_count; 510 __u64 relocs_ptr; 511 __u64 alignment; 512 __u64 offset; 513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514#define EXEC_OBJECT_NEEDS_FENCE (1 << 0) 515#define EXEC_OBJECT_NEEDS_GTT (1 << 1) 516#define EXEC_OBJECT_WRITE (1 << 2) 517#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1 << 3) 518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519#define EXEC_OBJECT_PINNED (1 << 4) 520#define EXEC_OBJECT_PAD_TO_SIZE (1 << 5) 521#define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_PAD_TO_SIZE << 1) 522 __u64 flags; 523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524 union { 525 __u64 rsvd1; 526 __u64 pad_to_size; 527 }; 528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 __u64 rsvd2; 530}; 531struct drm_i915_gem_execbuffer2 { 532 __u64 buffers_ptr; 533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534 __u32 buffer_count; 535 __u32 batch_start_offset; 536 __u32 batch_len; 537 __u32 DR1; 538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 __u32 DR4; 540 __u32 num_cliprects; 541 __u64 cliprects_ptr; 542#define I915_EXEC_RING_MASK (7 << 0) 543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544#define I915_EXEC_DEFAULT (0 << 0) 545#define I915_EXEC_RENDER (1 << 0) 546#define I915_EXEC_BSD (2 << 0) 547#define I915_EXEC_BLT (3 << 0) 548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549#define I915_EXEC_VEBOX (4 << 0) 550#define I915_EXEC_CONSTANTS_MASK (3 << 6) 551#define I915_EXEC_CONSTANTS_REL_GENERAL (0 << 6) 552#define I915_EXEC_CONSTANTS_ABSOLUTE (1 << 6) 553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554#define I915_EXEC_CONSTANTS_REL_SURFACE (2 << 6) 555 __u64 flags; 556 __u64 rsvd1; 557 __u64 rsvd2; 558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559}; 560#define I915_EXEC_GEN7_SOL_RESET (1 << 8) 561#define I915_EXEC_SECURE (1 << 9) 562#define I915_EXEC_IS_PINNED (1 << 10) 563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564#define I915_EXEC_NO_RELOC (1 << 11) 565#define I915_EXEC_HANDLE_LUT (1 << 12) 566#define I915_EXEC_BSD_SHIFT (13) 567#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 570#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 571#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 572#define I915_EXEC_RESOURCE_STREAMER (1 << 15) 573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574#define __I915_EXEC_UNKNOWN_FLAGS - (I915_EXEC_RESOURCE_STREAMER << 1) 575#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 576#define i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 577#define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579struct drm_i915_gem_pin { 580 __u32 handle; 581 __u32 pad; 582 __u64 alignment; 583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584 __u64 offset; 585}; 586struct drm_i915_gem_unpin { 587 __u32 handle; 588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589 __u32 pad; 590}; 591struct drm_i915_gem_busy { 592 __u32 handle; 593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594 __u32 busy; 595}; 596#define I915_CACHING_NONE 0 597#define I915_CACHING_CACHED 1 598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599#define I915_CACHING_DISPLAY 2 600struct drm_i915_gem_caching { 601 __u32 handle; 602 __u32 caching; 603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604}; 605#define I915_TILING_NONE 0 606#define I915_TILING_X 1 607#define I915_TILING_Y 2 608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609#define I915_TILING_LAST I915_TILING_Y 610#define I915_BIT_6_SWIZZLE_NONE 0 611#define I915_BIT_6_SWIZZLE_9 1 612#define I915_BIT_6_SWIZZLE_9_10 2 613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614#define I915_BIT_6_SWIZZLE_9_11 3 615#define I915_BIT_6_SWIZZLE_9_10_11 4 616#define I915_BIT_6_SWIZZLE_UNKNOWN 5 617#define I915_BIT_6_SWIZZLE_9_17 6 618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619#define I915_BIT_6_SWIZZLE_9_10_17 7 620struct drm_i915_gem_set_tiling { 621 __u32 handle; 622 __u32 tiling_mode; 623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624 __u32 stride; 625 __u32 swizzle_mode; 626}; 627struct drm_i915_gem_get_tiling { 628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629 __u32 handle; 630 __u32 tiling_mode; 631 __u32 swizzle_mode; 632 __u32 phys_swizzle_mode; 633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634}; 635struct drm_i915_gem_get_aperture { 636 __u64 aper_size; 637 __u64 aper_available_size; 638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639}; 640struct drm_i915_get_pipe_from_crtc_id { 641 __u32 crtc_id; 642 __u32 pipe; 643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644}; 645#define I915_MADV_WILLNEED 0 646#define I915_MADV_DONTNEED 1 647#define __I915_MADV_PURGED 2 648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649struct drm_i915_gem_madvise { 650 __u32 handle; 651 __u32 madv; 652 __u32 retained; 653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654}; 655#define I915_OVERLAY_TYPE_MASK 0xff 656#define I915_OVERLAY_YUV_PLANAR 0x01 657#define I915_OVERLAY_YUV_PACKED 0x02 658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659#define I915_OVERLAY_RGB 0x03 660#define I915_OVERLAY_DEPTH_MASK 0xff00 661#define I915_OVERLAY_RGB24 0x1000 662#define I915_OVERLAY_RGB16 0x2000 663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664#define I915_OVERLAY_RGB15 0x3000 665#define I915_OVERLAY_YUV422 0x0100 666#define I915_OVERLAY_YUV411 0x0200 667#define I915_OVERLAY_YUV420 0x0300 668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669#define I915_OVERLAY_YUV410 0x0400 670#define I915_OVERLAY_SWAP_MASK 0xff0000 671#define I915_OVERLAY_NO_SWAP 0x000000 672#define I915_OVERLAY_UV_SWAP 0x010000 673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674#define I915_OVERLAY_Y_SWAP 0x020000 675#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 676#define I915_OVERLAY_FLAGS_MASK 0xff000000 677#define I915_OVERLAY_ENABLE 0x01000000 678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679struct drm_intel_overlay_put_image { 680 __u32 flags; 681 __u32 bo_handle; 682 __u16 stride_Y; 683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684 __u16 stride_UV; 685 __u32 offset_Y; 686 __u32 offset_U; 687 __u32 offset_V; 688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689 __u16 src_width; 690 __u16 src_height; 691 __u16 src_scan_width; 692 __u16 src_scan_height; 693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694 __u32 crtc_id; 695 __u16 dst_x; 696 __u16 dst_y; 697 __u16 dst_width; 698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699 __u16 dst_height; 700}; 701#define I915_OVERLAY_UPDATE_ATTRS (1 << 0) 702#define I915_OVERLAY_UPDATE_GAMMA (1 << 1) 703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1 << 2) 705struct drm_intel_overlay_attrs { 706 __u32 flags; 707 __u32 color_key; 708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709 __s32 brightness; 710 __u32 contrast; 711 __u32 saturation; 712 __u32 gamma0; 713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714 __u32 gamma1; 715 __u32 gamma2; 716 __u32 gamma3; 717 __u32 gamma4; 718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719 __u32 gamma5; 720}; 721#define I915_SET_COLORKEY_NONE (1 << 0) 722#define I915_SET_COLORKEY_DESTINATION (1 << 1) 723/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724#define I915_SET_COLORKEY_SOURCE (1 << 2) 725struct drm_intel_sprite_colorkey { 726 __u32 plane_id; 727 __u32 min_value; 728/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729 __u32 channel_mask; 730 __u32 max_value; 731 __u32 flags; 732}; 733/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734struct drm_i915_gem_wait { 735 __u32 bo_handle; 736 __u32 flags; 737 __s64 timeout_ns; 738/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739}; 740struct drm_i915_gem_context_create { 741 __u32 ctx_id; 742 __u32 pad; 743/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744}; 745struct drm_i915_gem_context_destroy { 746 __u32 ctx_id; 747 __u32 pad; 748/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749}; 750struct drm_i915_reg_read { 751 __u64 offset; 752 __u64 val; 753/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754}; 755struct drm_i915_reset_stats { 756 __u32 ctx_id; 757 __u32 flags; 758/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759 __u32 reset_count; 760 __u32 batch_active; 761 __u32 batch_pending; 762 __u32 pad; 763/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764}; 765struct drm_i915_gem_userptr { 766 __u64 user_ptr; 767 __u64 user_size; 768/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769 __u32 flags; 770#define I915_USERPTR_READ_ONLY 0x1 771#define I915_USERPTR_UNSYNCHRONIZED 0x80000000 772 __u32 handle; 773/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774}; 775struct drm_i915_gem_context_param { 776 __u32 ctx_id; 777 __u32 size; 778/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779 __u64 param; 780#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 781#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 782#define I915_CONTEXT_PARAM_GTT_SIZE 0x3 783/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 785 __u64 value; 786}; 787#ifdef __cplusplus 788/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 789#endif 790#endif 791