i915_drm.h revision 96c1db7b9d601c31d103389cac074a6cce0d7633
1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef _UAPI_I915_DRM_H_ 20#define _UAPI_I915_DRM_H_ 21#include "drm.h" 22#ifdef __cplusplus 23#endif 24#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 25#define I915_ERROR_UEVENT "ERROR" 26#define I915_RESET_UEVENT "RESET" 27enum i915_mocs_table_index { 28 I915_MOCS_UNCACHED, 29 I915_MOCS_PTE, 30 I915_MOCS_CACHED, 31}; 32#define I915_NR_TEX_REGIONS 255 33#define I915_LOG_MIN_TEX_REGION_SIZE 14 34typedef struct _drm_i915_init { 35 enum { 36 I915_INIT_DMA = 0x01, 37 I915_CLEANUP_DMA = 0x02, 38 I915_RESUME_DMA = 0x03 39 } func; 40 unsigned int mmio_offset; 41 int sarea_priv_offset; 42 unsigned int ring_start; 43 unsigned int ring_end; 44 unsigned int ring_size; 45 unsigned int front_offset; 46 unsigned int back_offset; 47 unsigned int depth_offset; 48 unsigned int w; 49 unsigned int h; 50 unsigned int pitch; 51 unsigned int pitch_bits; 52 unsigned int back_pitch; 53 unsigned int depth_pitch; 54 unsigned int cpp; 55 unsigned int chipset; 56} drm_i915_init_t; 57typedef struct _drm_i915_sarea { 58 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 59 int last_upload; 60 int last_enqueue; 61 int last_dispatch; 62 int ctxOwner; 63 int texAge; 64 int pf_enabled; 65 int pf_active; 66 int pf_current_page; 67 int perf_boxes; 68 int width, height; 69 drm_handle_t front_handle; 70 int front_offset; 71 int front_size; 72 drm_handle_t back_handle; 73 int back_offset; 74 int back_size; 75 drm_handle_t depth_handle; 76 int depth_offset; 77 int depth_size; 78 drm_handle_t tex_handle; 79 int tex_offset; 80 int tex_size; 81 int log_tex_granularity; 82 int pitch; 83 int rotation; 84 int rotated_offset; 85 int rotated_size; 86 int rotated_pitch; 87 int virtualX, virtualY; 88 unsigned int front_tiled; 89 unsigned int back_tiled; 90 unsigned int depth_tiled; 91 unsigned int rotated_tiled; 92 unsigned int rotated2_tiled; 93 int pipeA_x; 94 int pipeA_y; 95 int pipeA_w; 96 int pipeA_h; 97 int pipeB_x; 98 int pipeB_y; 99 int pipeB_w; 100 int pipeB_h; 101 drm_handle_t unused_handle; 102 __u32 unused1, unused2, unused3; 103 __u32 front_bo_handle; 104 __u32 back_bo_handle; 105 __u32 unused_bo_handle; 106 __u32 depth_bo_handle; 107} drm_i915_sarea_t; 108#define planeA_x pipeA_x 109#define planeA_y pipeA_y 110#define planeA_w pipeA_w 111#define planeA_h pipeA_h 112#define planeB_x pipeB_x 113#define planeB_y pipeB_y 114#define planeB_w pipeB_w 115#define planeB_h pipeB_h 116#define I915_BOX_RING_EMPTY 0x1 117#define I915_BOX_FLIP 0x2 118#define I915_BOX_WAIT 0x4 119#define I915_BOX_TEXTURE_LOAD 0x8 120#define I915_BOX_LOST_CONTEXT 0x10 121#define DRM_I915_INIT 0x00 122#define DRM_I915_FLUSH 0x01 123#define DRM_I915_FLIP 0x02 124#define DRM_I915_BATCHBUFFER 0x03 125#define DRM_I915_IRQ_EMIT 0x04 126#define DRM_I915_IRQ_WAIT 0x05 127#define DRM_I915_GETPARAM 0x06 128#define DRM_I915_SETPARAM 0x07 129#define DRM_I915_ALLOC 0x08 130#define DRM_I915_FREE 0x09 131#define DRM_I915_INIT_HEAP 0x0a 132#define DRM_I915_CMDBUFFER 0x0b 133#define DRM_I915_DESTROY_HEAP 0x0c 134#define DRM_I915_SET_VBLANK_PIPE 0x0d 135#define DRM_I915_GET_VBLANK_PIPE 0x0e 136#define DRM_I915_VBLANK_SWAP 0x0f 137#define DRM_I915_HWS_ADDR 0x11 138#define DRM_I915_GEM_INIT 0x13 139#define DRM_I915_GEM_EXECBUFFER 0x14 140#define DRM_I915_GEM_PIN 0x15 141#define DRM_I915_GEM_UNPIN 0x16 142#define DRM_I915_GEM_BUSY 0x17 143#define DRM_I915_GEM_THROTTLE 0x18 144#define DRM_I915_GEM_ENTERVT 0x19 145#define DRM_I915_GEM_LEAVEVT 0x1a 146#define DRM_I915_GEM_CREATE 0x1b 147#define DRM_I915_GEM_PREAD 0x1c 148#define DRM_I915_GEM_PWRITE 0x1d 149#define DRM_I915_GEM_MMAP 0x1e 150#define DRM_I915_GEM_SET_DOMAIN 0x1f 151#define DRM_I915_GEM_SW_FINISH 0x20 152#define DRM_I915_GEM_SET_TILING 0x21 153#define DRM_I915_GEM_GET_TILING 0x22 154#define DRM_I915_GEM_GET_APERTURE 0x23 155#define DRM_I915_GEM_MMAP_GTT 0x24 156#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 157#define DRM_I915_GEM_MADVISE 0x26 158#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 159#define DRM_I915_OVERLAY_ATTRS 0x28 160#define DRM_I915_GEM_EXECBUFFER2 0x29 161#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 162#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 163#define DRM_I915_GEM_WAIT 0x2c 164#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 165#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 166#define DRM_I915_GEM_SET_CACHING 0x2f 167#define DRM_I915_GEM_GET_CACHING 0x30 168#define DRM_I915_REG_READ 0x31 169#define DRM_I915_GET_RESET_STATS 0x32 170#define DRM_I915_GEM_USERPTR 0x33 171#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 172#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 173#define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 174#define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH) 175#define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP) 176#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 177#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 178#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 179#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 180#define DRM_IOCTL_I915_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 181#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 182#define DRM_IOCTL_I915_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 183#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 184#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 185#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 186#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 187#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 188#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 189#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 190#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 191#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 192#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 193#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 194#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 195#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 196#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 197#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 198#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 199#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 200#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 201#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 202#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 203#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 204#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 205#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 206#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 207#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 208#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 209#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 210#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 211#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 212#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 213#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 214#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 215#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 216#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 217#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 218#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 219#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 220#define DRM_IOCTL_I915_REG_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 221#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 222#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 223#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 224#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 225typedef struct drm_i915_batchbuffer { 226 int start; 227 int used; 228 int DR1; 229 int DR4; 230 int num_cliprects; 231 struct drm_clip_rect __user * cliprects; 232} drm_i915_batchbuffer_t; 233typedef struct _drm_i915_cmdbuffer { 234 char __user * buf; 235 int sz; 236 int DR1; 237 int DR4; 238 int num_cliprects; 239 struct drm_clip_rect __user * cliprects; 240} drm_i915_cmdbuffer_t; 241typedef struct drm_i915_irq_emit { 242 int __user * irq_seq; 243} drm_i915_irq_emit_t; 244typedef struct drm_i915_irq_wait { 245 int irq_seq; 246} drm_i915_irq_wait_t; 247#define I915_PARAM_IRQ_ACTIVE 1 248#define I915_PARAM_ALLOW_BATCHBUFFER 2 249#define I915_PARAM_LAST_DISPATCH 3 250#define I915_PARAM_CHIPSET_ID 4 251#define I915_PARAM_HAS_GEM 5 252#define I915_PARAM_NUM_FENCES_AVAIL 6 253#define I915_PARAM_HAS_OVERLAY 7 254#define I915_PARAM_HAS_PAGEFLIPPING 8 255#define I915_PARAM_HAS_EXECBUF2 9 256#define I915_PARAM_HAS_BSD 10 257#define I915_PARAM_HAS_BLT 11 258#define I915_PARAM_HAS_RELAXED_FENCING 12 259#define I915_PARAM_HAS_COHERENT_RINGS 13 260#define I915_PARAM_HAS_EXEC_CONSTANTS 14 261#define I915_PARAM_HAS_RELAXED_DELTA 15 262#define I915_PARAM_HAS_GEN7_SOL_RESET 16 263#define I915_PARAM_HAS_LLC 17 264#define I915_PARAM_HAS_ALIASING_PPGTT 18 265#define I915_PARAM_HAS_WAIT_TIMEOUT 19 266#define I915_PARAM_HAS_SEMAPHORES 20 267#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 268#define I915_PARAM_HAS_VEBOX 22 269#define I915_PARAM_HAS_SECURE_BATCHES 23 270#define I915_PARAM_HAS_PINNED_BATCHES 24 271#define I915_PARAM_HAS_EXEC_NO_RELOC 25 272#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 273#define I915_PARAM_HAS_WT 27 274#define I915_PARAM_CMD_PARSER_VERSION 28 275#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 276#define I915_PARAM_MMAP_VERSION 30 277#define I915_PARAM_HAS_BSD2 31 278#define I915_PARAM_REVISION 32 279#define I915_PARAM_SUBSLICE_TOTAL 33 280#define I915_PARAM_EU_TOTAL 34 281#define I915_PARAM_HAS_GPU_RESET 35 282#define I915_PARAM_HAS_RESOURCE_STREAMER 36 283#define I915_PARAM_HAS_EXEC_SOFTPIN 37 284#define I915_PARAM_HAS_POOLED_EU 38 285#define I915_PARAM_MIN_EU_IN_POOL 39 286#define I915_PARAM_MMAP_GTT_VERSION 40 287#define I915_PARAM_HAS_SCHEDULER 41 288typedef struct drm_i915_getparam { 289 __s32 param; 290 int __user * value; 291} drm_i915_getparam_t; 292#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 293#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 294#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 295#define I915_SETPARAM_NUM_USED_FENCES 4 296typedef struct drm_i915_setparam { 297 int param; 298 int value; 299} drm_i915_setparam_t; 300#define I915_MEM_REGION_AGP 1 301typedef struct drm_i915_mem_alloc { 302 int region; 303 int alignment; 304 int size; 305 int __user * region_offset; 306} drm_i915_mem_alloc_t; 307typedef struct drm_i915_mem_free { 308 int region; 309 int region_offset; 310} drm_i915_mem_free_t; 311typedef struct drm_i915_mem_init_heap { 312 int region; 313 int size; 314 int start; 315} drm_i915_mem_init_heap_t; 316typedef struct drm_i915_mem_destroy_heap { 317 int region; 318} drm_i915_mem_destroy_heap_t; 319#define DRM_I915_VBLANK_PIPE_A 1 320#define DRM_I915_VBLANK_PIPE_B 2 321typedef struct drm_i915_vblank_pipe { 322 int pipe; 323} drm_i915_vblank_pipe_t; 324typedef struct drm_i915_vblank_swap { 325 drm_drawable_t drawable; 326 enum drm_vblank_seq_type seqtype; 327 unsigned int sequence; 328} drm_i915_vblank_swap_t; 329typedef struct drm_i915_hws_addr { 330 __u64 addr; 331} drm_i915_hws_addr_t; 332struct drm_i915_gem_init { 333 __u64 gtt_start; 334 __u64 gtt_end; 335}; 336struct drm_i915_gem_create { 337 __u64 size; 338 __u32 handle; 339 __u32 pad; 340}; 341struct drm_i915_gem_pread { 342 __u32 handle; 343 __u32 pad; 344 __u64 offset; 345 __u64 size; 346 __u64 data_ptr; 347}; 348struct drm_i915_gem_pwrite { 349 __u32 handle; 350 __u32 pad; 351 __u64 offset; 352 __u64 size; 353 __u64 data_ptr; 354}; 355struct drm_i915_gem_mmap { 356 __u32 handle; 357 __u32 pad; 358 __u64 offset; 359 __u64 size; 360 __u64 addr_ptr; 361 __u64 flags; 362#define I915_MMAP_WC 0x1 363}; 364struct drm_i915_gem_mmap_gtt { 365 __u32 handle; 366 __u32 pad; 367 __u64 offset; 368}; 369struct drm_i915_gem_set_domain { 370 __u32 handle; 371 __u32 read_domains; 372 __u32 write_domain; 373}; 374struct drm_i915_gem_sw_finish { 375 __u32 handle; 376}; 377struct drm_i915_gem_relocation_entry { 378 __u32 target_handle; 379 __u32 delta; 380 __u64 offset; 381 __u64 presumed_offset; 382 __u32 read_domains; 383 __u32 write_domain; 384}; 385#define I915_GEM_DOMAIN_CPU 0x00000001 386#define I915_GEM_DOMAIN_RENDER 0x00000002 387#define I915_GEM_DOMAIN_SAMPLER 0x00000004 388#define I915_GEM_DOMAIN_COMMAND 0x00000008 389#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 390#define I915_GEM_DOMAIN_VERTEX 0x00000020 391#define I915_GEM_DOMAIN_GTT 0x00000040 392struct drm_i915_gem_exec_object { 393 __u32 handle; 394 __u32 relocation_count; 395 __u64 relocs_ptr; 396 __u64 alignment; 397 __u64 offset; 398}; 399struct drm_i915_gem_execbuffer { 400 __u64 buffers_ptr; 401 __u32 buffer_count; 402 __u32 batch_start_offset; 403 __u32 batch_len; 404 __u32 DR1; 405 __u32 DR4; 406 __u32 num_cliprects; 407 __u64 cliprects_ptr; 408}; 409struct drm_i915_gem_exec_object2 { 410 __u32 handle; 411 __u32 relocation_count; 412 __u64 relocs_ptr; 413 __u64 alignment; 414 __u64 offset; 415#define EXEC_OBJECT_NEEDS_FENCE (1 << 0) 416#define EXEC_OBJECT_NEEDS_GTT (1 << 1) 417#define EXEC_OBJECT_WRITE (1 << 2) 418#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1 << 3) 419#define EXEC_OBJECT_PINNED (1 << 4) 420#define EXEC_OBJECT_PAD_TO_SIZE (1 << 5) 421#define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_PAD_TO_SIZE << 1) 422 __u64 flags; 423 union { 424 __u64 rsvd1; 425 __u64 pad_to_size; 426 }; 427 __u64 rsvd2; 428}; 429struct drm_i915_gem_execbuffer2 { 430 __u64 buffers_ptr; 431 __u32 buffer_count; 432 __u32 batch_start_offset; 433 __u32 batch_len; 434 __u32 DR1; 435 __u32 DR4; 436 __u32 num_cliprects; 437 __u64 cliprects_ptr; 438#define I915_EXEC_RING_MASK (7 << 0) 439#define I915_EXEC_DEFAULT (0 << 0) 440#define I915_EXEC_RENDER (1 << 0) 441#define I915_EXEC_BSD (2 << 0) 442#define I915_EXEC_BLT (3 << 0) 443#define I915_EXEC_VEBOX (4 << 0) 444#define I915_EXEC_CONSTANTS_MASK (3 << 6) 445#define I915_EXEC_CONSTANTS_REL_GENERAL (0 << 6) 446#define I915_EXEC_CONSTANTS_ABSOLUTE (1 << 6) 447#define I915_EXEC_CONSTANTS_REL_SURFACE (2 << 6) 448 __u64 flags; 449 __u64 rsvd1; 450 __u64 rsvd2; 451}; 452#define I915_EXEC_GEN7_SOL_RESET (1 << 8) 453#define I915_EXEC_SECURE (1 << 9) 454#define I915_EXEC_IS_PINNED (1 << 10) 455#define I915_EXEC_NO_RELOC (1 << 11) 456#define I915_EXEC_HANDLE_LUT (1 << 12) 457#define I915_EXEC_BSD_SHIFT (13) 458#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 459#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 460#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 461#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 462#define I915_EXEC_RESOURCE_STREAMER (1 << 15) 463#define __I915_EXEC_UNKNOWN_FLAGS - (I915_EXEC_RESOURCE_STREAMER << 1) 464#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 465#define i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 466#define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 467struct drm_i915_gem_pin { 468 __u32 handle; 469 __u32 pad; 470 __u64 alignment; 471 __u64 offset; 472}; 473struct drm_i915_gem_unpin { 474 __u32 handle; 475 __u32 pad; 476}; 477struct drm_i915_gem_busy { 478 __u32 handle; 479 __u32 busy; 480}; 481#define I915_CACHING_NONE 0 482#define I915_CACHING_CACHED 1 483#define I915_CACHING_DISPLAY 2 484struct drm_i915_gem_caching { 485 __u32 handle; 486 __u32 caching; 487}; 488#define I915_TILING_NONE 0 489#define I915_TILING_X 1 490#define I915_TILING_Y 2 491#define I915_TILING_LAST I915_TILING_Y 492#define I915_BIT_6_SWIZZLE_NONE 0 493#define I915_BIT_6_SWIZZLE_9 1 494#define I915_BIT_6_SWIZZLE_9_10 2 495#define I915_BIT_6_SWIZZLE_9_11 3 496#define I915_BIT_6_SWIZZLE_9_10_11 4 497#define I915_BIT_6_SWIZZLE_UNKNOWN 5 498#define I915_BIT_6_SWIZZLE_9_17 6 499#define I915_BIT_6_SWIZZLE_9_10_17 7 500struct drm_i915_gem_set_tiling { 501 __u32 handle; 502 __u32 tiling_mode; 503 __u32 stride; 504 __u32 swizzle_mode; 505}; 506struct drm_i915_gem_get_tiling { 507 __u32 handle; 508 __u32 tiling_mode; 509 __u32 swizzle_mode; 510 __u32 phys_swizzle_mode; 511}; 512struct drm_i915_gem_get_aperture { 513 __u64 aper_size; 514 __u64 aper_available_size; 515}; 516struct drm_i915_get_pipe_from_crtc_id { 517 __u32 crtc_id; 518 __u32 pipe; 519}; 520#define I915_MADV_WILLNEED 0 521#define I915_MADV_DONTNEED 1 522#define __I915_MADV_PURGED 2 523struct drm_i915_gem_madvise { 524 __u32 handle; 525 __u32 madv; 526 __u32 retained; 527}; 528#define I915_OVERLAY_TYPE_MASK 0xff 529#define I915_OVERLAY_YUV_PLANAR 0x01 530#define I915_OVERLAY_YUV_PACKED 0x02 531#define I915_OVERLAY_RGB 0x03 532#define I915_OVERLAY_DEPTH_MASK 0xff00 533#define I915_OVERLAY_RGB24 0x1000 534#define I915_OVERLAY_RGB16 0x2000 535#define I915_OVERLAY_RGB15 0x3000 536#define I915_OVERLAY_YUV422 0x0100 537#define I915_OVERLAY_YUV411 0x0200 538#define I915_OVERLAY_YUV420 0x0300 539#define I915_OVERLAY_YUV410 0x0400 540#define I915_OVERLAY_SWAP_MASK 0xff0000 541#define I915_OVERLAY_NO_SWAP 0x000000 542#define I915_OVERLAY_UV_SWAP 0x010000 543#define I915_OVERLAY_Y_SWAP 0x020000 544#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 545#define I915_OVERLAY_FLAGS_MASK 0xff000000 546#define I915_OVERLAY_ENABLE 0x01000000 547struct drm_intel_overlay_put_image { 548 __u32 flags; 549 __u32 bo_handle; 550 __u16 stride_Y; 551 __u16 stride_UV; 552 __u32 offset_Y; 553 __u32 offset_U; 554 __u32 offset_V; 555 __u16 src_width; 556 __u16 src_height; 557 __u16 src_scan_width; 558 __u16 src_scan_height; 559 __u32 crtc_id; 560 __u16 dst_x; 561 __u16 dst_y; 562 __u16 dst_width; 563 __u16 dst_height; 564}; 565#define I915_OVERLAY_UPDATE_ATTRS (1 << 0) 566#define I915_OVERLAY_UPDATE_GAMMA (1 << 1) 567#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1 << 2) 568struct drm_intel_overlay_attrs { 569 __u32 flags; 570 __u32 color_key; 571 __s32 brightness; 572 __u32 contrast; 573 __u32 saturation; 574 __u32 gamma0; 575 __u32 gamma1; 576 __u32 gamma2; 577 __u32 gamma3; 578 __u32 gamma4; 579 __u32 gamma5; 580}; 581#define I915_SET_COLORKEY_NONE (1 << 0) 582#define I915_SET_COLORKEY_DESTINATION (1 << 1) 583#define I915_SET_COLORKEY_SOURCE (1 << 2) 584struct drm_intel_sprite_colorkey { 585 __u32 plane_id; 586 __u32 min_value; 587 __u32 channel_mask; 588 __u32 max_value; 589 __u32 flags; 590}; 591struct drm_i915_gem_wait { 592 __u32 bo_handle; 593 __u32 flags; 594 __s64 timeout_ns; 595}; 596struct drm_i915_gem_context_create { 597 __u32 ctx_id; 598 __u32 pad; 599}; 600struct drm_i915_gem_context_destroy { 601 __u32 ctx_id; 602 __u32 pad; 603}; 604struct drm_i915_reg_read { 605 __u64 offset; 606 __u64 val; 607}; 608struct drm_i915_reset_stats { 609 __u32 ctx_id; 610 __u32 flags; 611 __u32 reset_count; 612 __u32 batch_active; 613 __u32 batch_pending; 614 __u32 pad; 615}; 616struct drm_i915_gem_userptr { 617 __u64 user_ptr; 618 __u64 user_size; 619 __u32 flags; 620#define I915_USERPTR_READ_ONLY 0x1 621#define I915_USERPTR_UNSYNCHRONIZED 0x80000000 622 __u32 handle; 623}; 624struct drm_i915_gem_context_param { 625 __u32 ctx_id; 626 __u32 size; 627 __u64 param; 628#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 629#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 630#define I915_CONTEXT_PARAM_GTT_SIZE 0x3 631#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 632 __u64 value; 633}; 634#ifdef __cplusplus 635#endif 636#endif 637