i915_drm.h revision ba8d4f460b51161eb82cf1006cb34a3cc1389f47 
1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_I915_DRM_H_
20#define _UAPI_I915_DRM_H_
21#include <drm/drm.h>
22#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#define I915_ERROR_UEVENT "ERROR"
25#define I915_RESET_UEVENT "RESET"
26#define I915_NR_TEX_REGIONS 255
27#define I915_LOG_MIN_TEX_REGION_SIZE 14
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29typedef struct _drm_i915_init {
30 enum {
31 I915_INIT_DMA = 0x01,
32 I915_CLEANUP_DMA = 0x02,
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34 I915_RESUME_DMA = 0x03
35 } func;
36 unsigned int mmio_offset;
37 int sarea_priv_offset;
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39 unsigned int ring_start;
40 unsigned int ring_end;
41 unsigned int ring_size;
42 unsigned int front_offset;
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44 unsigned int back_offset;
45 unsigned int depth_offset;
46 unsigned int w;
47 unsigned int h;
48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49 unsigned int pitch;
50 unsigned int pitch_bits;
51 unsigned int back_pitch;
52 unsigned int depth_pitch;
53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54 unsigned int cpp;
55 unsigned int chipset;
56} drm_i915_init_t;
57typedef struct _drm_i915_sarea {
58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
60 int last_upload;
61 int last_enqueue;
62 int last_dispatch;
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64 int ctxOwner;
65 int texAge;
66 int pf_enabled;
67 int pf_active;
68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
69 int pf_current_page;
70 int perf_boxes;
71 int width, height;
72 drm_handle_t front_handle;
73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74 int front_offset;
75 int front_size;
76 drm_handle_t back_handle;
77 int back_offset;
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
79 int back_size;
80 drm_handle_t depth_handle;
81 int depth_offset;
82 int depth_size;
83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
84 drm_handle_t tex_handle;
85 int tex_offset;
86 int tex_size;
87 int log_tex_granularity;
88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
89 int pitch;
90 int rotation;
91 int rotated_offset;
92 int rotated_size;
93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
94 int rotated_pitch;
95 int virtualX, virtualY;
96 unsigned int front_tiled;
97 unsigned int back_tiled;
98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
99 unsigned int depth_tiled;
100 unsigned int rotated_tiled;
101 unsigned int rotated2_tiled;
102 int pipeA_x;
103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
104 int pipeA_y;
105 int pipeA_w;
106 int pipeA_h;
107 int pipeB_x;
108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
109 int pipeB_y;
110 int pipeB_w;
111 int pipeB_h;
112 drm_handle_t unused_handle;
113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
114 __u32 unused1, unused2, unused3;
115 __u32 front_bo_handle;
116 __u32 back_bo_handle;
117 __u32 unused_bo_handle;
118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
119 __u32 depth_bo_handle;
120} drm_i915_sarea_t;
121#define planeA_x pipeA_x
122#define planeA_y pipeA_y
123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
124#define planeA_w pipeA_w
125#define planeA_h pipeA_h
126#define planeB_x pipeB_x
127#define planeB_y pipeB_y
128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
129#define planeB_w pipeB_w
130#define planeB_h pipeB_h
131#define I915_BOX_RING_EMPTY 0x1
132#define I915_BOX_FLIP 0x2
133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
134#define I915_BOX_WAIT 0x4
135#define I915_BOX_TEXTURE_LOAD 0x8
136#define I915_BOX_LOST_CONTEXT 0x10
137#define DRM_I915_INIT 0x00
138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
139#define DRM_I915_FLUSH 0x01
140#define DRM_I915_FLIP 0x02
141#define DRM_I915_BATCHBUFFER 0x03
142#define DRM_I915_IRQ_EMIT 0x04
143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
144#define DRM_I915_IRQ_WAIT 0x05
145#define DRM_I915_GETPARAM 0x06
146#define DRM_I915_SETPARAM 0x07
147#define DRM_I915_ALLOC 0x08
148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
149#define DRM_I915_FREE 0x09
150#define DRM_I915_INIT_HEAP 0x0a
151#define DRM_I915_CMDBUFFER 0x0b
152#define DRM_I915_DESTROY_HEAP 0x0c
153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
154#define DRM_I915_SET_VBLANK_PIPE 0x0d
155#define DRM_I915_GET_VBLANK_PIPE 0x0e
156#define DRM_I915_VBLANK_SWAP 0x0f
157#define DRM_I915_HWS_ADDR 0x11
158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
159#define DRM_I915_GEM_INIT 0x13
160#define DRM_I915_GEM_EXECBUFFER 0x14
161#define DRM_I915_GEM_PIN 0x15
162#define DRM_I915_GEM_UNPIN 0x16
163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
164#define DRM_I915_GEM_BUSY 0x17
165#define DRM_I915_GEM_THROTTLE 0x18
166#define DRM_I915_GEM_ENTERVT 0x19
167#define DRM_I915_GEM_LEAVEVT 0x1a
168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
169#define DRM_I915_GEM_CREATE 0x1b
170#define DRM_I915_GEM_PREAD 0x1c
171#define DRM_I915_GEM_PWRITE 0x1d
172#define DRM_I915_GEM_MMAP 0x1e
173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
174#define DRM_I915_GEM_SET_DOMAIN 0x1f
175#define DRM_I915_GEM_SW_FINISH 0x20
176#define DRM_I915_GEM_SET_TILING 0x21
177#define DRM_I915_GEM_GET_TILING 0x22
178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
179#define DRM_I915_GEM_GET_APERTURE 0x23
180#define DRM_I915_GEM_MMAP_GTT 0x24
181#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
182#define DRM_I915_GEM_MADVISE 0x26
183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
184#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
185#define DRM_I915_OVERLAY_ATTRS 0x28
186#define DRM_I915_GEM_EXECBUFFER2 0x29
187#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
189#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
190#define DRM_I915_GEM_WAIT 0x2c
191#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
192#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
194#define DRM_I915_GEM_SET_CACHING 0x2f
195#define DRM_I915_GEM_GET_CACHING 0x30
196#define DRM_I915_REG_READ 0x31
197#define DRM_I915_GET_RESET_STATS 0x32
198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
199#define DRM_I915_GEM_USERPTR 0x33
200#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
201#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
202#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
204#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
205#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
206#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
207#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
209#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
210#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
211#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
212#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
214#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
215#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
216#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
217#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
219#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
220#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
221#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
222#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
224#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
225#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
226#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
227#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
229#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
230#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
231#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
232#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
234#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
235#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
236#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
237#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
239#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
240#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
241#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
242#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
244#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
245#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
246#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
247#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
249#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
250#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
251#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
252#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
254#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
255#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
256#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
257#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
259#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
260#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
261#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
262typedef struct drm_i915_batchbuffer {
263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
264 int start;
265 int used;
266 int DR1;
267 int DR4;
268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
269 int num_cliprects;
270 struct drm_clip_rect __user *cliprects;
271} drm_i915_batchbuffer_t;
272typedef struct _drm_i915_cmdbuffer {
273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
274 char __user *buf;
275 int sz;
276 int DR1;
277 int DR4;
278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
279 int num_cliprects;
280 struct drm_clip_rect __user *cliprects;
281} drm_i915_cmdbuffer_t;
282typedef struct drm_i915_irq_emit {
283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
284 int __user *irq_seq;
285} drm_i915_irq_emit_t;
286typedef struct drm_i915_irq_wait {
287 int irq_seq;
288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
289} drm_i915_irq_wait_t;
290#define I915_PARAM_IRQ_ACTIVE 1
291#define I915_PARAM_ALLOW_BATCHBUFFER 2
292#define I915_PARAM_LAST_DISPATCH 3
293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
294#define I915_PARAM_CHIPSET_ID 4
295#define I915_PARAM_HAS_GEM 5
296#define I915_PARAM_NUM_FENCES_AVAIL 6
297#define I915_PARAM_HAS_OVERLAY 7
298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
299#define I915_PARAM_HAS_PAGEFLIPPING 8
300#define I915_PARAM_HAS_EXECBUF2 9
301#define I915_PARAM_HAS_BSD 10
302#define I915_PARAM_HAS_BLT 11
303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
304#define I915_PARAM_HAS_RELAXED_FENCING 12
305#define I915_PARAM_HAS_COHERENT_RINGS 13
306#define I915_PARAM_HAS_EXEC_CONSTANTS 14
307#define I915_PARAM_HAS_RELAXED_DELTA 15
308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
309#define I915_PARAM_HAS_GEN7_SOL_RESET 16
310#define I915_PARAM_HAS_LLC 17
311#define I915_PARAM_HAS_ALIASING_PPGTT 18
312#define I915_PARAM_HAS_WAIT_TIMEOUT 19
313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
314#define I915_PARAM_HAS_SEMAPHORES 20
315#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
316#define I915_PARAM_HAS_VEBOX 22
317#define I915_PARAM_HAS_SECURE_BATCHES 23
318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
319#define I915_PARAM_HAS_PINNED_BATCHES 24
320#define I915_PARAM_HAS_EXEC_NO_RELOC 25
321#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
322#define I915_PARAM_HAS_WT 27
323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
324#define I915_PARAM_CMD_PARSER_VERSION 28
325typedef struct drm_i915_getparam {
326 int param;
327 int __user *value;
328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
329} drm_i915_getparam_t;
330#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
331#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
332#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
334#define I915_SETPARAM_NUM_USED_FENCES 4
335typedef struct drm_i915_setparam {
336 int param;
337 int value;
338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
339} drm_i915_setparam_t;
340#define I915_MEM_REGION_AGP 1
341typedef struct drm_i915_mem_alloc {
342 int region;
343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
344 int alignment;
345 int size;
346 int __user *region_offset;
347} drm_i915_mem_alloc_t;
348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
349typedef struct drm_i915_mem_free {
350 int region;
351 int region_offset;
352} drm_i915_mem_free_t;
353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
354typedef struct drm_i915_mem_init_heap {
355 int region;
356 int size;
357 int start;
358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
359} drm_i915_mem_init_heap_t;
360typedef struct drm_i915_mem_destroy_heap {
361 int region;
362} drm_i915_mem_destroy_heap_t;
363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
364#define DRM_I915_VBLANK_PIPE_A 1
365#define DRM_I915_VBLANK_PIPE_B 2
366typedef struct drm_i915_vblank_pipe {
367 int pipe;
368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
369} drm_i915_vblank_pipe_t;
370typedef struct drm_i915_vblank_swap {
371 drm_drawable_t drawable;
372 enum drm_vblank_seq_type seqtype;
373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
374 unsigned int sequence;
375} drm_i915_vblank_swap_t;
376typedef struct drm_i915_hws_addr {
377 __u64 addr;
378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
379} drm_i915_hws_addr_t;
380struct drm_i915_gem_init {
381 __u64 gtt_start;
382 __u64 gtt_end;
383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
384};
385struct drm_i915_gem_create {
386 __u64 size;
387 __u32 handle;
388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
389 __u32 pad;
390};
391struct drm_i915_gem_pread {
392 __u32 handle;
393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
394 __u32 pad;
395 __u64 offset;
396 __u64 size;
397 __u64 data_ptr;
398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
399};
400struct drm_i915_gem_pwrite {
401 __u32 handle;
402 __u32 pad;
403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
404 __u64 offset;
405 __u64 size;
406 __u64 data_ptr;
407};
408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
409struct drm_i915_gem_mmap {
410 __u32 handle;
411 __u32 pad;
412 __u64 offset;
413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
414 __u64 size;
415 __u64 addr_ptr;
416};
417struct drm_i915_gem_mmap_gtt {
418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
419 __u32 handle;
420 __u32 pad;
421 __u64 offset;
422};
423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
424struct drm_i915_gem_set_domain {
425 __u32 handle;
426 __u32 read_domains;
427 __u32 write_domain;
428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
429};
430struct drm_i915_gem_sw_finish {
431 __u32 handle;
432};
433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
434struct drm_i915_gem_relocation_entry {
435 __u32 target_handle;
436 __u32 delta;
437 __u64 offset;
438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
439 __u64 presumed_offset;
440 __u32 read_domains;
441 __u32 write_domain;
442};
443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
444#define I915_GEM_DOMAIN_CPU 0x00000001
445#define I915_GEM_DOMAIN_RENDER 0x00000002
446#define I915_GEM_DOMAIN_SAMPLER 0x00000004
447#define I915_GEM_DOMAIN_COMMAND 0x00000008
448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
449#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
450#define I915_GEM_DOMAIN_VERTEX 0x00000020
451#define I915_GEM_DOMAIN_GTT 0x00000040
452struct drm_i915_gem_exec_object {
453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
454 __u32 handle;
455 __u32 relocation_count;
456 __u64 relocs_ptr;
457 __u64 alignment;
458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
459 __u64 offset;
460};
461struct drm_i915_gem_execbuffer {
462 __u64 buffers_ptr;
463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
464 __u32 buffer_count;
465 __u32 batch_start_offset;
466 __u32 batch_len;
467 __u32 DR1;
468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
469 __u32 DR4;
470 __u32 num_cliprects;
471 __u64 cliprects_ptr;
472};
473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
474struct drm_i915_gem_exec_object2 {
475 __u32 handle;
476 __u32 relocation_count;
477 __u64 relocs_ptr;
478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
479 __u64 alignment;
480 __u64 offset;
481#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
482#define EXEC_OBJECT_NEEDS_GTT (1<<1)
483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
484#define EXEC_OBJECT_WRITE (1<<2)
485#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1)
486 __u64 flags;
487 __u64 rsvd1;
488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
489 __u64 rsvd2;
490};
491struct drm_i915_gem_execbuffer2 {
492 __u64 buffers_ptr;
493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
494 __u32 buffer_count;
495 __u32 batch_start_offset;
496 __u32 batch_len;
497 __u32 DR1;
498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
499 __u32 DR4;
500 __u32 num_cliprects;
501 __u64 cliprects_ptr;
502#define I915_EXEC_RING_MASK (7<<0)
503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
504#define I915_EXEC_DEFAULT (0<<0)
505#define I915_EXEC_RENDER (1<<0)
506#define I915_EXEC_BSD (2<<0)
507#define I915_EXEC_BLT (3<<0)
508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
509#define I915_EXEC_VEBOX (4<<0)
510#define I915_EXEC_CONSTANTS_MASK (3<<6)
511#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6)
512#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
514#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6)
515 __u64 flags;
516 __u64 rsvd1;
517 __u64 rsvd2;
518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
519};
520#define I915_EXEC_GEN7_SOL_RESET (1<<8)
521#define I915_EXEC_SECURE (1<<9)
522#define I915_EXEC_IS_PINNED (1<<10)
523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
524#define I915_EXEC_NO_RELOC (1<<11)
525#define I915_EXEC_HANDLE_LUT (1<<12)
526#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
527#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
529#define i915_execbuffer2_set_context_id(eb2, context)   (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
530#define i915_execbuffer2_get_context_id(eb2)   ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
531struct drm_i915_gem_pin {
532 __u32 handle;
533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
534 __u32 pad;
535 __u64 alignment;
536 __u64 offset;
537};
538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
539struct drm_i915_gem_unpin {
540 __u32 handle;
541 __u32 pad;
542};
543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
544struct drm_i915_gem_busy {
545 __u32 handle;
546 __u32 busy;
547};
548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
549#define I915_CACHING_NONE 0
550#define I915_CACHING_CACHED 1
551#define I915_CACHING_DISPLAY 2
552struct drm_i915_gem_caching {
553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
554 __u32 handle;
555 __u32 caching;
556};
557#define I915_TILING_NONE 0
558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
559#define I915_TILING_X 1
560#define I915_TILING_Y 2
561#define I915_BIT_6_SWIZZLE_NONE 0
562#define I915_BIT_6_SWIZZLE_9 1
563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
564#define I915_BIT_6_SWIZZLE_9_10 2
565#define I915_BIT_6_SWIZZLE_9_11 3
566#define I915_BIT_6_SWIZZLE_9_10_11 4
567#define I915_BIT_6_SWIZZLE_UNKNOWN 5
568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
569#define I915_BIT_6_SWIZZLE_9_17 6
570#define I915_BIT_6_SWIZZLE_9_10_17 7
571struct drm_i915_gem_set_tiling {
572 __u32 handle;
573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
574 __u32 tiling_mode;
575 __u32 stride;
576 __u32 swizzle_mode;
577};
578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
579struct drm_i915_gem_get_tiling {
580 __u32 handle;
581 __u32 tiling_mode;
582 __u32 swizzle_mode;
583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
584};
585struct drm_i915_gem_get_aperture {
586 __u64 aper_size;
587 __u64 aper_available_size;
588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
589};
590struct drm_i915_get_pipe_from_crtc_id {
591 __u32 crtc_id;
592 __u32 pipe;
593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
594};
595#define I915_MADV_WILLNEED 0
596#define I915_MADV_DONTNEED 1
597#define __I915_MADV_PURGED 2
598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
599struct drm_i915_gem_madvise {
600 __u32 handle;
601 __u32 madv;
602 __u32 retained;
603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
604};
605#define I915_OVERLAY_TYPE_MASK 0xff
606#define I915_OVERLAY_YUV_PLANAR 0x01
607#define I915_OVERLAY_YUV_PACKED 0x02
608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
609#define I915_OVERLAY_RGB 0x03
610#define I915_OVERLAY_DEPTH_MASK 0xff00
611#define I915_OVERLAY_RGB24 0x1000
612#define I915_OVERLAY_RGB16 0x2000
613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
614#define I915_OVERLAY_RGB15 0x3000
615#define I915_OVERLAY_YUV422 0x0100
616#define I915_OVERLAY_YUV411 0x0200
617#define I915_OVERLAY_YUV420 0x0300
618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
619#define I915_OVERLAY_YUV410 0x0400
620#define I915_OVERLAY_SWAP_MASK 0xff0000
621#define I915_OVERLAY_NO_SWAP 0x000000
622#define I915_OVERLAY_UV_SWAP 0x010000
623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
624#define I915_OVERLAY_Y_SWAP 0x020000
625#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
626#define I915_OVERLAY_FLAGS_MASK 0xff000000
627#define I915_OVERLAY_ENABLE 0x01000000
628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
629struct drm_intel_overlay_put_image {
630 __u32 flags;
631 __u32 bo_handle;
632 __u16 stride_Y;
633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
634 __u16 stride_UV;
635 __u32 offset_Y;
636 __u32 offset_U;
637 __u32 offset_V;
638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
639 __u16 src_width;
640 __u16 src_height;
641 __u16 src_scan_width;
642 __u16 src_scan_height;
643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
644 __u32 crtc_id;
645 __u16 dst_x;
646 __u16 dst_y;
647 __u16 dst_width;
648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
649 __u16 dst_height;
650};
651#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
652#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
654struct drm_intel_overlay_attrs {
655 __u32 flags;
656 __u32 color_key;
657 __s32 brightness;
658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
659 __u32 contrast;
660 __u32 saturation;
661 __u32 gamma0;
662 __u32 gamma1;
663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
664 __u32 gamma2;
665 __u32 gamma3;
666 __u32 gamma4;
667 __u32 gamma5;
668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
669};
670#define I915_SET_COLORKEY_NONE (1<<0)
671#define I915_SET_COLORKEY_DESTINATION (1<<1)
672#define I915_SET_COLORKEY_SOURCE (1<<2)
673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
674struct drm_intel_sprite_colorkey {
675 __u32 plane_id;
676 __u32 min_value;
677 __u32 channel_mask;
678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
679 __u32 max_value;
680 __u32 flags;
681};
682struct drm_i915_gem_wait {
683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
684 __u32 bo_handle;
685 __u32 flags;
686 __s64 timeout_ns;
687};
688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
689struct drm_i915_gem_context_create {
690 __u32 ctx_id;
691 __u32 pad;
692};
693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
694struct drm_i915_gem_context_destroy {
695 __u32 ctx_id;
696 __u32 pad;
697};
698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
699struct drm_i915_reg_read {
700 __u64 offset;
701 __u64 val;
702};
703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
704struct drm_i915_reset_stats {
705 __u32 ctx_id;
706 __u32 flags;
707 __u32 reset_count;
708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
709 __u32 batch_active;
710 __u32 batch_pending;
711 __u32 pad;
712};
713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
714struct drm_i915_gem_userptr {
715 __u64 user_ptr;
716 __u64 user_size;
717 __u32 flags;
718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
719#define I915_USERPTR_READ_ONLY 0x1
720#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
721 __u32 handle;
722};
723/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
724#endif
725