1655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/****************************************************************************
2655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ****************************************************************************
3655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ***
4655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ***   This header was automatically generated from a Linux kernel header
5655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ***   of the same name, to make information necessary for userspace to
6655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ***   call into the kernel available to libc.  It contains only constants,
7655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ***   structures, and macros generated from the original header, and thus,
8655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ***   contains no copyrightable information.
9655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ***
10655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ***   To edit the content of this header, modify the corresponding
11655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ***   source file (e.g. under external/kernel-headers/original/) then
12655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ***   run bionic/libc/kernel/tools/update_all.py
13655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ***
14655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ***   Any manual change here will be lost the next time this script will
15655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ***   be run. You've been warned!
16655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ***
17655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ****************************************************************************
18655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ****************************************************************************/
19655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#ifndef __MGA_DRM_H__
20655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define __MGA_DRM_H__
21106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#include "drm.h"
22106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#ifdef __cplusplus
23106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#endif
24106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#ifndef __MGA_SAREA_DEFINES__
25655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define __MGA_SAREA_DEFINES__
26655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_F 0x1
27655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_A 0x2
28655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_S 0x4
29655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_T2 0x8
30655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_WARP_TGZ 0
31655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_WARP_TGZF (MGA_F)
32655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_WARP_TGZA (MGA_A)
33d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define MGA_WARP_TGZAF (MGA_F | MGA_A)
34655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_WARP_TGZS (MGA_S)
35d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define MGA_WARP_TGZSF (MGA_S | MGA_F)
36d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define MGA_WARP_TGZSA (MGA_S | MGA_A)
37d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define MGA_WARP_TGZSAF (MGA_S | MGA_F | MGA_A)
38655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_WARP_T2GZ (MGA_T2)
39d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define MGA_WARP_T2GZF (MGA_T2 | MGA_F)
40d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define MGA_WARP_T2GZA (MGA_T2 | MGA_A)
41d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define MGA_WARP_T2GZAF (MGA_T2 | MGA_A | MGA_F)
42d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define MGA_WARP_T2GZS (MGA_T2 | MGA_S)
43d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define MGA_WARP_T2GZSF (MGA_T2 | MGA_S | MGA_F)
44d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define MGA_WARP_T2GZSA (MGA_T2 | MGA_S | MGA_A)
45d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define MGA_WARP_T2GZSAF (MGA_T2 | MGA_S | MGA_F | MGA_A)
46655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_MAX_G200_PIPES 8
47655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_MAX_G400_PIPES 16
48655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
49655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_WARP_UCODE_SIZE 32768
50655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_CARD_TYPE_G200 1
51655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_CARD_TYPE_G400 2
52655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_CARD_TYPE_G450 3
53655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_CARD_TYPE_G550 4
54655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_FRONT 0x1
55655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_BACK 0x2
56655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_DEPTH 0x4
57655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_UPLOAD_CONTEXT 0x1
58655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_UPLOAD_TEX0 0x2
59655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_UPLOAD_TEX1 0x4
60655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_UPLOAD_PIPE 0x8
61655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_UPLOAD_TEX0IMAGE 0x10
62655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_UPLOAD_TEX1IMAGE 0x20
63655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_UPLOAD_2D 0x40
64655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_WAIT_AGE 0x80
65655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_UPLOAD_CLIPRECTS 0x100
66655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_BUFFER_SIZE (1 << 16)
67655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_NUM_BUFFERS 128
68655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_NR_SAREA_CLIPRECTS 8
69655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_CARD_HEAP 0
70655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_AGP_HEAP 1
71655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_NR_TEX_HEAPS 2
72655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_NR_TEX_REGIONS 16
73655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_LOG_MIN_TEX_REGION_SIZE 16
74655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_MGA_IDLE_RETRY 2048
75655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#endif
76655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct {
77d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int dstorg;
78d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int maccess;
79d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int plnwt;
80d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int dwgctl;
81d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int alphactrl;
82d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int fogcolor;
83d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int wflag;
84d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int tdualstage0;
85d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int tdualstage1;
86d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int fcol;
87d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int stencil;
88d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int stencilctl;
89655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_mga_context_regs_t;
90655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct {
91d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int pitch;
92655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_mga_server_regs_t;
93655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct {
94d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int texctl;
95d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int texctl2;
96d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int texfilter;
97d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int texbordercol;
98d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int texorg;
99d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int texwidth;
100d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int texheight;
101d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int texorg1;
102d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int texorg2;
103d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int texorg3;
104d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int texorg4;
105655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_mga_texture_regs_t;
106655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct {
107d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int head;
108d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int wrap;
109655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_mga_age_t;
110655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct _drm_mga_sarea {
111d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  drm_mga_context_regs_t context_state;
112d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  drm_mga_server_regs_t server_state;
113d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  drm_mga_texture_regs_t tex_state[2];
114d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int warp_pipe;
115d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int dirty;
116d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int vertsize;
117d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
118d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int nbox;
119d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int req_drawable;
120d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int req_draw_buffer;
121d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int exported_drawable;
122d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int exported_index;
123d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int exported_stamp;
124d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int exported_buffers;
125d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int exported_nfront;
126d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int exported_nback;
127d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int exported_back_x, exported_front_x, exported_w;
128d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int exported_back_y, exported_front_y, exported_h;
129d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
130d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int status[4];
131d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int last_wrap;
132d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  drm_mga_age_t last_frame;
133d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int last_enqueue;
134d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int last_dispatch;
135d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int last_quiescent;
136d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
137d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int texAge[MGA_NR_TEX_HEAPS];
138d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int ctxOwner;
139655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_mga_sarea_t;
140655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_MGA_INIT 0x00
141655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_MGA_FLUSH 0x01
142655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_MGA_RESET 0x02
143655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_MGA_SWAP 0x03
144655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_MGA_CLEAR 0x04
145655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_MGA_VERTEX 0x05
146655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_MGA_INDICES 0x06
147655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_MGA_ILOAD 0x07
148655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_MGA_BLIT 0x08
149655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_MGA_GETPARAM 0x09
150655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_MGA_SET_FENCE 0x0a
151655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_MGA_WAIT_FENCE 0x0b
152655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_MGA_DMA_BOOTSTRAP 0x0c
153d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_MGA_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
154d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_MGA_FLUSH DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock)
155d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_MGA_RESET DRM_IO(DRM_COMMAND_BASE + DRM_MGA_RESET)
156d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_MGA_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_MGA_SWAP)
157d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_MGA_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
158d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_MGA_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
159d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_MGA_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
160d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_MGA_ILOAD DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
161d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_MGA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
162655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
163d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
164655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
165655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
166655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct _drm_mga_warp_index {
167d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int installed;
168d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned long phys_addr;
169d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int size;
170655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_mga_warp_index_t;
171655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_mga_init {
172d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  enum {
173d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao    MGA_INIT_DMA = 0x01,
174d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao    MGA_CLEANUP_DMA = 0x02
175d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  } func;
176d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned long sarea_priv_offset;
177d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int chipset;
178d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int sgram;
179d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int maccess;
180d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int fb_cpp;
181d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int front_offset, front_pitch;
182d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int back_offset, back_pitch;
183d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int depth_cpp;
184d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int depth_offset, depth_pitch;
185d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int texture_offset[MGA_NR_TEX_HEAPS];
186d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int texture_size[MGA_NR_TEX_HEAPS];
187d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned long fb_offset;
188d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned long mmio_offset;
189d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned long status_offset;
190d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned long warp_offset;
191d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned long primary_offset;
192d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned long buffers_offset;
193655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_mga_init_t;
194655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_mga_dma_bootstrap {
195d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned long texture_handle;
196d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  __u32 texture_size;
197d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  __u32 primary_size;
198d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  __u32 secondary_bin_count;
199d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  __u32 secondary_bin_size;
200d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  __u32 agp_mode;
201d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  __u8 agp_size;
202655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_mga_dma_bootstrap_t;
203655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_mga_clear {
204d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int flags;
205d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int clear_color;
206d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int clear_depth;
207d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int color_mask;
208d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int depth_mask;
209655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_mga_clear_t;
210655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_mga_vertex {
211d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int idx;
212d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int used;
213d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int discard;
214655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_mga_vertex_t;
215655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_mga_indices {
216d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int idx;
217d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int start;
218d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int end;
219d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int discard;
220655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_mga_indices_t;
221655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_mga_iload {
222d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int idx;
223d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int dstorg;
224d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int length;
225655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_mga_iload_t;
226655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct _drm_mga_blit {
227d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int planemask;
228d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int srcorg;
229d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  unsigned int dstorg;
230d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int src_pitch, dst_pitch;
231d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int delta_sx, delta_sy;
232d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int delta_dx, delta_dy;
233d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int height, ydir;
234d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int source_pitch, dest_pitch;
235655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_mga_blit_t;
236655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_PARAM_IRQ_NR 1
237655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define MGA_PARAM_CARD_TYPE 2
238655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_mga_getparam {
239d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  int param;
240d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao  void __user * value;
241655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_mga_getparam_t;
242106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#ifdef __cplusplus
243106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#endif
244655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#endif
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