msm_drm.h revision 05d08e9716b5974d6ed08973f44930804890b902 
1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __MSM_DRM_H__
20#define __MSM_DRM_H__
21#include <stddef.h>
22#include <drm/drm.h>
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#define MSM_PIPE_NONE 0x00
25#define MSM_PIPE_2D0 0x01
26#define MSM_PIPE_2D1 0x02
27#define MSM_PIPE_3D0 0x10
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29struct drm_msm_timespec {
30  __s64 tv_sec;
31  __s64 tv_nsec;
32};
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34#define MSM_PARAM_GPU_ID 0x01
35#define MSM_PARAM_GMEM_SIZE 0x02
36#define MSM_PARAM_CHIP_ID 0x03
37struct drm_msm_param {
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39  __u32 pipe;
40  __u32 param;
41  __u64 value;
42};
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44#define MSM_BO_SCANOUT 0x00000001
45#define MSM_BO_GPU_READONLY 0x00000002
46#define MSM_BO_CACHE_MASK 0x000f0000
47#define MSM_BO_CACHED 0x00010000
48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49#define MSM_BO_WC 0x00020000
50#define MSM_BO_UNCACHED 0x00040000
51#define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED)
52struct drm_msm_gem_new {
53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54  __u64 size;
55  __u32 flags;
56  __u32 handle;
57};
58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59struct drm_msm_gem_info {
60  __u32 handle;
61  __u32 pad;
62  __u64 offset;
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64};
65#define MSM_PREP_READ 0x01
66#define MSM_PREP_WRITE 0x02
67#define MSM_PREP_NOSYNC 0x04
68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
69#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
70struct drm_msm_gem_cpu_prep {
71  __u32 handle;
72  __u32 op;
73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74  struct drm_msm_timespec timeout;
75};
76struct drm_msm_gem_cpu_fini {
77  __u32 handle;
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
79};
80struct drm_msm_gem_submit_reloc {
81  __u32 submit_offset;
82  __u32 or;
83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
84  __s32 shift;
85  __u32 reloc_idx;
86  __u64 reloc_offset;
87};
88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
89#define MSM_SUBMIT_CMD_BUF 0x0001
90#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
91#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
92struct drm_msm_gem_submit_cmd {
93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
94  __u32 type;
95  __u32 submit_idx;
96  __u32 submit_offset;
97  __u32 size;
98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
99  __u32 pad;
100  __u32 nr_relocs;
101  __u64 __user relocs;
102};
103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
104#define MSM_SUBMIT_BO_READ 0x0001
105#define MSM_SUBMIT_BO_WRITE 0x0002
106#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
107struct drm_msm_gem_submit_bo {
108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
109  __u32 flags;
110  __u32 handle;
111  __u64 presumed;
112};
113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
114struct drm_msm_gem_submit {
115  __u32 pipe;
116  __u32 fence;
117  __u32 nr_bos;
118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
119  __u32 nr_cmds;
120  __u64 __user bos;
121  __u64 __user cmds;
122};
123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
124struct drm_msm_wait_fence {
125  __u32 fence;
126  __u32 pad;
127  struct drm_msm_timespec timeout;
128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
129};
130#define DRM_MSM_GET_PARAM 0x00
131#define DRM_MSM_GEM_NEW 0x02
132#define DRM_MSM_GEM_INFO 0x03
133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
134#define DRM_MSM_GEM_CPU_PREP 0x04
135#define DRM_MSM_GEM_CPU_FINI 0x05
136#define DRM_MSM_GEM_SUBMIT 0x06
137#define DRM_MSM_WAIT_FENCE 0x07
138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
139#define DRM_MSM_NUM_IOCTLS 0x08
140#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
141#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
142#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
144#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
145#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
146#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
147#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
149#endif
150