msm_drm.h revision 1308ad3ab33294c3abfd96da12b6df58b381ce52 
1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __MSM_DRM_H__
20#define __MSM_DRM_H__
21#include "drm.h"
22#ifdef __cplusplus
23#endif
24#define MSM_PIPE_NONE 0x00
25#define MSM_PIPE_2D0 0x01
26#define MSM_PIPE_2D1 0x02
27#define MSM_PIPE_3D0 0x10
28#define MSM_PIPE_ID_MASK 0xffff
29#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
30#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
31struct drm_msm_timespec {
32  __s64 tv_sec;
33  __s64 tv_nsec;
34};
35#define MSM_PARAM_GPU_ID 0x01
36#define MSM_PARAM_GMEM_SIZE 0x02
37#define MSM_PARAM_CHIP_ID 0x03
38#define MSM_PARAM_MAX_FREQ 0x04
39#define MSM_PARAM_TIMESTAMP 0x05
40#define MSM_PARAM_GMEM_BASE 0x06
41struct drm_msm_param {
42  __u32 pipe;
43  __u32 param;
44  __u64 value;
45};
46#define MSM_BO_SCANOUT 0x00000001
47#define MSM_BO_GPU_READONLY 0x00000002
48#define MSM_BO_CACHE_MASK 0x000f0000
49#define MSM_BO_CACHED 0x00010000
50#define MSM_BO_WC 0x00020000
51#define MSM_BO_UNCACHED 0x00040000
52#define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED)
53struct drm_msm_gem_new {
54  __u64 size;
55  __u32 flags;
56  __u32 handle;
57};
58#define MSM_INFO_IOVA 0x01
59#define MSM_INFO_FLAGS (MSM_INFO_IOVA)
60struct drm_msm_gem_info {
61  __u32 handle;
62  __u32 flags;
63  __u64 offset;
64};
65#define MSM_PREP_READ 0x01
66#define MSM_PREP_WRITE 0x02
67#define MSM_PREP_NOSYNC 0x04
68#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
69struct drm_msm_gem_cpu_prep {
70  __u32 handle;
71  __u32 op;
72  struct drm_msm_timespec timeout;
73};
74struct drm_msm_gem_cpu_fini {
75  __u32 handle;
76};
77struct drm_msm_gem_submit_reloc {
78  __u32 submit_offset;
79  __u32 or;
80  __s32 shift;
81  __u32 reloc_idx;
82  __u64 reloc_offset;
83};
84#define MSM_SUBMIT_CMD_BUF 0x0001
85#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
86#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
87struct drm_msm_gem_submit_cmd {
88  __u32 type;
89  __u32 submit_idx;
90  __u32 submit_offset;
91  __u32 size;
92  __u32 pad;
93  __u32 nr_relocs;
94  __u64 relocs;
95};
96#define MSM_SUBMIT_BO_READ 0x0001
97#define MSM_SUBMIT_BO_WRITE 0x0002
98#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
99struct drm_msm_gem_submit_bo {
100  __u32 flags;
101  __u32 handle;
102  __u64 presumed;
103};
104#define MSM_SUBMIT_NO_IMPLICIT 0x80000000
105#define MSM_SUBMIT_FENCE_FD_IN 0x40000000
106#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000
107#define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | 0)
108struct drm_msm_gem_submit {
109  __u32 flags;
110  __u32 fence;
111  __u32 nr_bos;
112  __u32 nr_cmds;
113  __u64 bos;
114  __u64 cmds;
115  __s32 fence_fd;
116};
117struct drm_msm_wait_fence {
118  __u32 fence;
119  __u32 pad;
120  struct drm_msm_timespec timeout;
121};
122#define MSM_MADV_WILLNEED 0
123#define MSM_MADV_DONTNEED 1
124#define __MSM_MADV_PURGED 2
125struct drm_msm_gem_madvise {
126  __u32 handle;
127  __u32 madv;
128  __u32 retained;
129};
130#define DRM_MSM_GET_PARAM 0x00
131#define DRM_MSM_GEM_NEW 0x02
132#define DRM_MSM_GEM_INFO 0x03
133#define DRM_MSM_GEM_CPU_PREP 0x04
134#define DRM_MSM_GEM_CPU_FINI 0x05
135#define DRM_MSM_GEM_SUBMIT 0x06
136#define DRM_MSM_WAIT_FENCE 0x07
137#define DRM_MSM_GEM_MADVISE 0x08
138#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
139#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
140#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
141#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
142#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
143#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
144#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
145#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
146#ifdef __cplusplus
147#endif
148#endif
149