radeon_drm.h revision 38062f954c637861348dd8078cefb73554e6f12c
1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef __RADEON_DRM_H__ 20#define __RADEON_DRM_H__ 21#include <drm/drm.h> 22#ifndef __RADEON_SAREA_DEFINES__ 23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24#define __RADEON_SAREA_DEFINES__ 25#define RADEON_UPLOAD_CONTEXT 0x00000001 26#define RADEON_UPLOAD_VERTFMT 0x00000002 27#define RADEON_UPLOAD_LINE 0x00000004 28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29#define RADEON_UPLOAD_BUMPMAP 0x00000008 30#define RADEON_UPLOAD_MASKS 0x00000010 31#define RADEON_UPLOAD_VIEWPORT 0x00000020 32#define RADEON_UPLOAD_SETUP 0x00000040 33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34#define RADEON_UPLOAD_TCL 0x00000080 35#define RADEON_UPLOAD_MISC 0x00000100 36#define RADEON_UPLOAD_TEX0 0x00000200 37#define RADEON_UPLOAD_TEX1 0x00000400 38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39#define RADEON_UPLOAD_TEX2 0x00000800 40#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 41#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 42#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44#define RADEON_UPLOAD_CLIPRECTS 0x00008000 45#define RADEON_REQUIRE_QUIESCENCE 0x00010000 46#define RADEON_UPLOAD_ZBIAS 0x00020000 47#define RADEON_UPLOAD_ALL 0x003effff 48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 50#define RADEON_EMIT_PP_MISC 0 51#define RADEON_EMIT_PP_CNTL 1 52#define RADEON_EMIT_RB3D_COLORPITCH 2 53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54#define RADEON_EMIT_RE_LINE_PATTERN 3 55#define RADEON_EMIT_SE_LINE_WIDTH 4 56#define RADEON_EMIT_PP_LUM_MATRIX 5 57#define RADEON_EMIT_PP_ROT_MATRIX_0 6 58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59#define RADEON_EMIT_RB3D_STENCILREFMASK 7 60#define RADEON_EMIT_SE_VPORT_XSCALE 8 61#define RADEON_EMIT_SE_CNTL 9 62#define RADEON_EMIT_SE_CNTL_STATUS 10 63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64#define RADEON_EMIT_RE_MISC 11 65#define RADEON_EMIT_PP_TXFILTER_0 12 66#define RADEON_EMIT_PP_BORDER_COLOR_0 13 67#define RADEON_EMIT_PP_TXFILTER_1 14 68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69#define RADEON_EMIT_PP_BORDER_COLOR_1 15 70#define RADEON_EMIT_PP_TXFILTER_2 16 71#define RADEON_EMIT_PP_BORDER_COLOR_2 17 72#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 75#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 76#define R200_EMIT_PP_TXCBLEND_0 21 77#define R200_EMIT_PP_TXCBLEND_1 22 78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79#define R200_EMIT_PP_TXCBLEND_2 23 80#define R200_EMIT_PP_TXCBLEND_3 24 81#define R200_EMIT_PP_TXCBLEND_4 25 82#define R200_EMIT_PP_TXCBLEND_5 26 83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84#define R200_EMIT_PP_TXCBLEND_6 27 85#define R200_EMIT_PP_TXCBLEND_7 28 86#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 87#define R200_EMIT_TFACTOR_0 30 88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89#define R200_EMIT_VTX_FMT_0 31 90#define R200_EMIT_VAP_CTL 32 91#define R200_EMIT_MATRIX_SELECT_0 33 92#define R200_EMIT_TEX_PROC_CTL_2 34 93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 95#define R200_EMIT_PP_TXFILTER_0 36 96#define R200_EMIT_PP_TXFILTER_1 37 97#define R200_EMIT_PP_TXFILTER_2 38 98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99#define R200_EMIT_PP_TXFILTER_3 39 100#define R200_EMIT_PP_TXFILTER_4 40 101#define R200_EMIT_PP_TXFILTER_5 41 102#define R200_EMIT_PP_TXOFFSET_0 42 103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104#define R200_EMIT_PP_TXOFFSET_1 43 105#define R200_EMIT_PP_TXOFFSET_2 44 106#define R200_EMIT_PP_TXOFFSET_3 45 107#define R200_EMIT_PP_TXOFFSET_4 46 108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109#define R200_EMIT_PP_TXOFFSET_5 47 110#define R200_EMIT_VTE_CNTL 48 111#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 112#define R200_EMIT_PP_TAM_DEBUG3 50 113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114#define R200_EMIT_PP_CNTL_X 51 115#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 116#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 117#define R200_EMIT_RE_SCISSOR_TL_0 54 118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119#define R200_EMIT_RE_SCISSOR_TL_1 55 120#define R200_EMIT_RE_SCISSOR_TL_2 56 121#define R200_EMIT_SE_VAP_CNTL_STATUS 57 122#define R200_EMIT_SE_VTX_STATE_CNTL 58 123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124#define R200_EMIT_RE_POINTSIZE 59 125#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 126#define R200_EMIT_PP_CUBIC_FACES_0 61 127#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129#define R200_EMIT_PP_CUBIC_FACES_1 63 130#define R200_EMIT_PP_CUBIC_OFFSETS_1 64 131#define R200_EMIT_PP_CUBIC_FACES_2 65 132#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134#define R200_EMIT_PP_CUBIC_FACES_3 67 135#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 136#define R200_EMIT_PP_CUBIC_FACES_4 69 137#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139#define R200_EMIT_PP_CUBIC_FACES_5 71 140#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 141#define RADEON_EMIT_PP_TEX_SIZE_0 73 142#define RADEON_EMIT_PP_TEX_SIZE_1 74 143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144#define RADEON_EMIT_PP_TEX_SIZE_2 75 145#define R200_EMIT_RB3D_BLENDCOLOR 76 146#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 147#define RADEON_EMIT_PP_CUBIC_FACES_0 78 148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 150#define RADEON_EMIT_PP_CUBIC_FACES_1 80 151#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 152#define RADEON_EMIT_PP_CUBIC_FACES_2 82 153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 155#define R200_EMIT_PP_TRI_PERF_CNTL 84 156#define R200_EMIT_PP_AFS_0 85 157#define R200_EMIT_PP_AFS_1 86 158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159#define R200_EMIT_ATF_TFACTOR 87 160#define R200_EMIT_PP_TXCTLALL_0 88 161#define R200_EMIT_PP_TXCTLALL_1 89 162#define R200_EMIT_PP_TXCTLALL_2 90 163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164#define R200_EMIT_PP_TXCTLALL_3 91 165#define R200_EMIT_PP_TXCTLALL_4 92 166#define R200_EMIT_PP_TXCTLALL_5 93 167#define R200_EMIT_VAP_PVS_CNTL 94 168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169#define RADEON_MAX_STATE_PACKETS 95 170#define RADEON_CMD_PACKET 1 171#define RADEON_CMD_SCALARS 2 172#define RADEON_CMD_VECTORS 3 173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174#define RADEON_CMD_DMA_DISCARD 4 175#define RADEON_CMD_PACKET3 5 176#define RADEON_CMD_PACKET3_CLIP 6 177#define RADEON_CMD_SCALARS2 7 178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179#define RADEON_CMD_WAIT 8 180#define RADEON_CMD_VECLINEAR 9 181typedef union { 182 int i; 183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 struct { 185 unsigned char cmd_type, pad0, pad1, pad2; 186 } header; 187 struct { 188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 unsigned char cmd_type, packet_id, pad0, pad1; 190 } packet; 191 struct { 192 unsigned char cmd_type, offset, stride, count; 193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 } scalars; 195 struct { 196 unsigned char cmd_type, offset, stride, count; 197 } vectors; 198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 struct { 200 unsigned char cmd_type, addr_lo, addr_hi, count; 201 } veclinear; 202 struct { 203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 unsigned char cmd_type, buf_idx, pad0, pad1; 205 } dma; 206 struct { 207 unsigned char cmd_type, flags, pad0, pad1; 208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 } wait; 210} drm_radeon_cmd_header_t; 211#define RADEON_WAIT_2D 0x1 212#define RADEON_WAIT_3D 0x2 213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214#define R300_CMD_PACKET3_CLEAR 0 215#define R300_CMD_PACKET3_RAW 1 216#define R300_CMD_PACKET0 1 217#define R300_CMD_VPU 2 218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219#define R300_CMD_PACKET3 3 220#define R300_CMD_END3D 4 221#define R300_CMD_CP_DELAY 5 222#define R300_CMD_DMA_DISCARD 6 223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224#define R300_CMD_WAIT 7 225#define R300_WAIT_2D 0x1 226#define R300_WAIT_3D 0x2 227#define R300_WAIT_2D_CLEAN 0x3 228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229#define R300_WAIT_3D_CLEAN 0x4 230#define R300_NEW_WAIT_2D_3D 0x3 231#define R300_NEW_WAIT_2D_2D_CLEAN 0x4 232#define R300_NEW_WAIT_3D_3D_CLEAN 0x6 233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234#define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 235#define R300_CMD_SCRATCH 8 236#define R300_CMD_R500FP 9 237typedef union { 238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 unsigned int u; 240 struct { 241 unsigned char cmd_type, pad0, pad1, pad2; 242 } header; 243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 struct { 245 unsigned char cmd_type, count, reglo, reghi; 246 } packet0; 247 struct { 248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 unsigned char cmd_type, count, adrlo, adrhi; 250 } vpu; 251 struct { 252 unsigned char cmd_type, packet, pad0, pad1; 253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 } packet3; 255 struct { 256 unsigned char cmd_type, packet; 257 unsigned short count; 258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 } delay; 260 struct { 261 unsigned char cmd_type, buf_idx, pad0, pad1; 262 } dma; 263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 struct { 265 unsigned char cmd_type, flags, pad0, pad1; 266 } wait; 267 struct { 268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 unsigned char cmd_type, reg, n_bufs, flags; 270 } scratch; 271 struct { 272 unsigned char cmd_type, count, adrlo, adrhi_flags; 273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 } r500fp; 275} drm_r300_cmd_header_t; 276#define RADEON_FRONT 0x1 277#define RADEON_BACK 0x2 278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279#define RADEON_DEPTH 0x4 280#define RADEON_STENCIL 0x8 281#define RADEON_CLEAR_FASTZ 0x80000000 282#define RADEON_USE_HIERZ 0x40000000 283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284#define RADEON_USE_COMP_ZBUF 0x20000000 285#define R500FP_CONSTANT_TYPE (1 << 1) 286#define R500FP_CONSTANT_CLAMP (1 << 2) 287#define RADEON_POINTS 0x1 288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289#define RADEON_LINES 0x2 290#define RADEON_LINE_STRIP 0x3 291#define RADEON_TRIANGLES 0x4 292#define RADEON_TRIANGLE_FAN 0x5 293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294#define RADEON_TRIANGLE_STRIP 0x6 295#define RADEON_BUFFER_SIZE 65536 296#define RADEON_INDEX_PRIM_OFFSET 20 297#define RADEON_SCRATCH_REG_OFFSET 32 298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299#define R600_SCRATCH_REG_OFFSET 256 300#define RADEON_NR_SAREA_CLIPRECTS 12 301#define RADEON_LOCAL_TEX_HEAP 0 302#define RADEON_GART_TEX_HEAP 1 303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304#define RADEON_NR_TEX_HEAPS 2 305#define RADEON_NR_TEX_REGIONS 64 306#define RADEON_LOG_TEX_GRANULARITY 16 307#define RADEON_MAX_TEXTURE_LEVELS 12 308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309#define RADEON_MAX_TEXTURE_UNITS 3 310#define RADEON_MAX_SURFACES 8 311#define RADEON_OFFSET_SHIFT 10 312#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 315#endif 316typedef struct { 317 unsigned int red; 318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 unsigned int green; 320 unsigned int blue; 321 unsigned int alpha; 322} radeon_color_regs_t; 323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324typedef struct { 325 unsigned int pp_misc; 326 unsigned int pp_fog_color; 327 unsigned int re_solid_color; 328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 unsigned int rb3d_blendcntl; 330 unsigned int rb3d_depthoffset; 331 unsigned int rb3d_depthpitch; 332 unsigned int rb3d_zstencilcntl; 333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 unsigned int pp_cntl; 335 unsigned int rb3d_cntl; 336 unsigned int rb3d_coloroffset; 337 unsigned int re_width_height; 338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 unsigned int rb3d_colorpitch; 340 unsigned int se_cntl; 341 unsigned int se_coord_fmt; 342 unsigned int re_line_pattern; 343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 unsigned int re_line_state; 345 unsigned int se_line_width; 346 unsigned int pp_lum_matrix; 347 unsigned int pp_rot_matrix_0; 348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 unsigned int pp_rot_matrix_1; 350 unsigned int rb3d_stencilrefmask; 351 unsigned int rb3d_ropcntl; 352 unsigned int rb3d_planemask; 353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 unsigned int se_vport_xscale; 355 unsigned int se_vport_xoffset; 356 unsigned int se_vport_yscale; 357 unsigned int se_vport_yoffset; 358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 unsigned int se_vport_zscale; 360 unsigned int se_vport_zoffset; 361 unsigned int se_cntl_status; 362 unsigned int re_top_left; 363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 unsigned int re_misc; 365} drm_radeon_context_regs_t; 366typedef struct { 367 unsigned int se_zbias_factor; 368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 unsigned int se_zbias_constant; 370} drm_radeon_context2_regs_t; 371typedef struct { 372 unsigned int pp_txfilter; 373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 unsigned int pp_txformat; 375 unsigned int pp_txoffset; 376 unsigned int pp_txcblend; 377 unsigned int pp_txablend; 378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 unsigned int pp_tfactor; 380 unsigned int pp_border_color; 381} drm_radeon_texture_regs_t; 382typedef struct { 383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 unsigned int start; 385 unsigned int finish; 386 unsigned int prim:8; 387 unsigned int stateidx:8; 388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 unsigned int numverts:16; 390 unsigned int vc_format; 391} drm_radeon_prim_t; 392typedef struct { 393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 drm_radeon_context_regs_t context; 395 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 396 drm_radeon_context2_regs_t context2; 397 unsigned int dirty; 398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399} drm_radeon_state_t; 400typedef struct { 401 drm_radeon_context_regs_t context_state; 402 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 unsigned int dirty; 405 unsigned int vertsize; 406 unsigned int vc_format; 407 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; 408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 unsigned int nbox; 410 unsigned int last_frame; 411 unsigned int last_dispatch; 412 unsigned int last_clear; 413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 415 1]; 416 unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 417 int ctx_owner; 418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 int pfState; 420 int pfCurrentPage; 421 int crtc2_base; 422 int tiling_enabled; 423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424} drm_radeon_sarea_t; 425#define DRM_RADEON_CP_INIT 0x00 426#define DRM_RADEON_CP_START 0x01 427#define DRM_RADEON_CP_STOP 0x02 428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429#define DRM_RADEON_CP_RESET 0x03 430#define DRM_RADEON_CP_IDLE 0x04 431#define DRM_RADEON_RESET 0x05 432#define DRM_RADEON_FULLSCREEN 0x06 433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434#define DRM_RADEON_SWAP 0x07 435#define DRM_RADEON_CLEAR 0x08 436#define DRM_RADEON_VERTEX 0x09 437#define DRM_RADEON_INDICES 0x0A 438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439#define DRM_RADEON_NOT_USED 440#define DRM_RADEON_STIPPLE 0x0C 441#define DRM_RADEON_INDIRECT 0x0D 442#define DRM_RADEON_TEXTURE 0x0E 443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444#define DRM_RADEON_VERTEX2 0x0F 445#define DRM_RADEON_CMDBUF 0x10 446#define DRM_RADEON_GETPARAM 0x11 447#define DRM_RADEON_FLIP 0x12 448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449#define DRM_RADEON_ALLOC 0x13 450#define DRM_RADEON_FREE 0x14 451#define DRM_RADEON_INIT_HEAP 0x15 452#define DRM_RADEON_IRQ_EMIT 0x16 453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454#define DRM_RADEON_IRQ_WAIT 0x17 455#define DRM_RADEON_CP_RESUME 0x18 456#define DRM_RADEON_SETPARAM 0x19 457#define DRM_RADEON_SURF_ALLOC 0x1a 458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459#define DRM_RADEON_SURF_FREE 0x1b 460#define DRM_RADEON_GEM_INFO 0x1c 461#define DRM_RADEON_GEM_CREATE 0x1d 462#define DRM_RADEON_GEM_MMAP 0x1e 463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464#define DRM_RADEON_GEM_PREAD 0x21 465#define DRM_RADEON_GEM_PWRITE 0x22 466#define DRM_RADEON_GEM_SET_DOMAIN 0x23 467#define DRM_RADEON_GEM_WAIT_IDLE 0x24 468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469#define DRM_RADEON_CS 0x26 470#define DRM_RADEON_INFO 0x27 471#define DRM_RADEON_GEM_SET_TILING 0x28 472#define DRM_RADEON_GEM_GET_TILING 0x29 473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474#define DRM_RADEON_GEM_BUSY 0x2a 475#define DRM_RADEON_GEM_VA 0x2b 476#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 477#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) 478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 480#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 481#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 482#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) 483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 485#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) 486#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) 487#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) 488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) 490#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) 491#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) 492#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) 493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) 495#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) 496#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) 497#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) 498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) 500#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 501#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 502#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 505#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 506#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 507#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) 510#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) 511#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) 512#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) 513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) 515#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) 516#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) 517#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) 518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) 520#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) 521#define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) 522#define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) 523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) 525#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) 526typedef struct drm_radeon_init { 527 enum { 528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 RADEON_INIT_CP = 0x01, 530 RADEON_CLEANUP_CP = 0x02, 531 RADEON_INIT_R200_CP = 0x03, 532 RADEON_INIT_R300_CP = 0x04, 533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534 RADEON_INIT_R600_CP = 0x05 535 } func; 536 unsigned long sarea_priv_offset; 537 int is_pci; 538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 int cp_mode; 540 int gart_size; 541 int ring_size; 542 int usec_timeout; 543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544 unsigned int fb_bpp; 545 unsigned int front_offset, front_pitch; 546 unsigned int back_offset, back_pitch; 547 unsigned int depth_bpp; 548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549 unsigned int depth_offset, depth_pitch; 550 unsigned long fb_offset; 551 unsigned long mmio_offset; 552 unsigned long ring_offset; 553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554 unsigned long ring_rptr_offset; 555 unsigned long buffers_offset; 556 unsigned long gart_textures_offset; 557} drm_radeon_init_t; 558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559typedef struct drm_radeon_cp_stop { 560 int flush; 561 int idle; 562} drm_radeon_cp_stop_t; 563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564typedef struct drm_radeon_fullscreen { 565 enum { 566 RADEON_INIT_FULLSCREEN = 0x01, 567 RADEON_CLEANUP_FULLSCREEN = 0x02 568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569 } func; 570} drm_radeon_fullscreen_t; 571#define CLEAR_X1 0 572#define CLEAR_Y1 1 573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574#define CLEAR_X2 2 575#define CLEAR_Y2 3 576#define CLEAR_DEPTH 4 577typedef union drm_radeon_clear_rect { 578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579 float f[5]; 580 unsigned int ui[5]; 581} drm_radeon_clear_rect_t; 582typedef struct drm_radeon_clear { 583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584 unsigned int flags; 585 unsigned int clear_color; 586 unsigned int clear_depth; 587 unsigned int color_mask; 588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589 unsigned int depth_mask; 590 drm_radeon_clear_rect_t __user *depth_boxes; 591} drm_radeon_clear_t; 592typedef struct drm_radeon_vertex { 593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594 int prim; 595 int idx; 596 int count; 597 int discard; 598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599} drm_radeon_vertex_t; 600typedef struct drm_radeon_indices { 601 int prim; 602 int idx; 603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604 int start; 605 int end; 606 int discard; 607} drm_radeon_indices_t; 608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609typedef struct drm_radeon_vertex2 { 610 int idx; 611 int discard; 612 int nr_states; 613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614 drm_radeon_state_t __user *state; 615 int nr_prims; 616 drm_radeon_prim_t __user *prim; 617} drm_radeon_vertex2_t; 618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619typedef struct drm_radeon_cmd_buffer { 620 int bufsz; 621 char __user *buf; 622 int nbox; 623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624 struct drm_clip_rect __user *boxes; 625} drm_radeon_cmd_buffer_t; 626typedef struct drm_radeon_tex_image { 627 unsigned int x, y; 628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629 unsigned int width, height; 630 const void __user *data; 631} drm_radeon_tex_image_t; 632typedef struct drm_radeon_texture { 633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634 unsigned int offset; 635 int pitch; 636 int format; 637 int width; 638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639 int height; 640 drm_radeon_tex_image_t __user *image; 641} drm_radeon_texture_t; 642typedef struct drm_radeon_stipple { 643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644 unsigned int __user *mask; 645} drm_radeon_stipple_t; 646typedef struct drm_radeon_indirect { 647 int idx; 648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649 int start; 650 int end; 651 int discard; 652} drm_radeon_indirect_t; 653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654#define RADEON_CARD_PCI 0 655#define RADEON_CARD_AGP 1 656#define RADEON_CARD_PCIE 2 657#define RADEON_PARAM_GART_BUFFER_OFFSET 1 658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659#define RADEON_PARAM_LAST_FRAME 2 660#define RADEON_PARAM_LAST_DISPATCH 3 661#define RADEON_PARAM_LAST_CLEAR 4 662#define RADEON_PARAM_IRQ_NR 5 663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664#define RADEON_PARAM_GART_BASE 6 665#define RADEON_PARAM_REGISTER_HANDLE 7 666#define RADEON_PARAM_STATUS_HANDLE 8 667#define RADEON_PARAM_SAREA_HANDLE 9 668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669#define RADEON_PARAM_GART_TEX_HANDLE 10 670#define RADEON_PARAM_SCRATCH_OFFSET 11 671#define RADEON_PARAM_CARD_TYPE 12 672#define RADEON_PARAM_VBLANK_CRTC 13 673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674#define RADEON_PARAM_FB_LOCATION 14 675#define RADEON_PARAM_NUM_GB_PIPES 15 676#define RADEON_PARAM_DEVICE_ID 16 677#define RADEON_PARAM_NUM_Z_PIPES 17 678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679typedef struct drm_radeon_getparam { 680 int param; 681 void __user *value; 682} drm_radeon_getparam_t; 683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684#define RADEON_MEM_REGION_GART 1 685#define RADEON_MEM_REGION_FB 2 686typedef struct drm_radeon_mem_alloc { 687 int region; 688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689 int alignment; 690 int size; 691 int __user *region_offset; 692} drm_radeon_mem_alloc_t; 693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694typedef struct drm_radeon_mem_free { 695 int region; 696 int region_offset; 697} drm_radeon_mem_free_t; 698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699typedef struct drm_radeon_mem_init_heap { 700 int region; 701 int size; 702 int start; 703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704} drm_radeon_mem_init_heap_t; 705typedef struct drm_radeon_irq_emit { 706 int __user *irq_seq; 707} drm_radeon_irq_emit_t; 708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709typedef struct drm_radeon_irq_wait { 710 int irq_seq; 711} drm_radeon_irq_wait_t; 712typedef struct drm_radeon_setparam { 713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714 unsigned int param; 715 __s64 value; 716} drm_radeon_setparam_t; 717#define RADEON_SETPARAM_FB_LOCATION 1 718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719#define RADEON_SETPARAM_SWITCH_TILING 2 720#define RADEON_SETPARAM_PCIGART_LOCATION 3 721#define RADEON_SETPARAM_NEW_MEMMAP 4 722#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 723/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724#define RADEON_SETPARAM_VBLANK_CRTC 6 725typedef struct drm_radeon_surface_alloc { 726 unsigned int address; 727 unsigned int size; 728/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729 unsigned int flags; 730} drm_radeon_surface_alloc_t; 731typedef struct drm_radeon_surface_free { 732 unsigned int address; 733/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734} drm_radeon_surface_free_t; 735#define DRM_RADEON_VBLANK_CRTC1 1 736#define DRM_RADEON_VBLANK_CRTC2 2 737#define RADEON_GEM_DOMAIN_CPU 0x1 738/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739#define RADEON_GEM_DOMAIN_GTT 0x2 740#define RADEON_GEM_DOMAIN_VRAM 0x4 741struct drm_radeon_gem_info { 742 uint64_t gart_size; 743/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744 uint64_t vram_size; 745 uint64_t vram_visible; 746}; 747#define RADEON_GEM_NO_BACKING_STORE 1 748/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749struct drm_radeon_gem_create { 750 uint64_t size; 751 uint64_t alignment; 752 uint32_t handle; 753/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754 uint32_t initial_domain; 755 uint32_t flags; 756}; 757#define RADEON_TILING_MACRO 0x1 758/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759#define RADEON_TILING_MICRO 0x2 760#define RADEON_TILING_SWAP_16BIT 0x4 761#define RADEON_TILING_SWAP_32BIT 0x8 762#define RADEON_TILING_SURFACE 0x10 763/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764#define RADEON_TILING_MICRO_SQUARE 0x20 765#define RADEON_TILING_EG_BANKW_SHIFT 8 766#define RADEON_TILING_EG_BANKW_MASK 0xf 767#define RADEON_TILING_EG_BANKH_SHIFT 12 768/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769#define RADEON_TILING_EG_BANKH_MASK 0xf 770#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 771#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf 772#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 773/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf 775#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 776#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf 777struct drm_radeon_gem_set_tiling { 778/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779 uint32_t handle; 780 uint32_t tiling_flags; 781 uint32_t pitch; 782}; 783/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784struct drm_radeon_gem_get_tiling { 785 uint32_t handle; 786 uint32_t tiling_flags; 787 uint32_t pitch; 788/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 789}; 790struct drm_radeon_gem_mmap { 791 uint32_t handle; 792 uint32_t pad; 793/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 794 uint64_t offset; 795 uint64_t size; 796 uint64_t addr_ptr; 797}; 798/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 799struct drm_radeon_gem_set_domain { 800 uint32_t handle; 801 uint32_t read_domains; 802 uint32_t write_domain; 803/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 804}; 805struct drm_radeon_gem_wait_idle { 806 uint32_t handle; 807 uint32_t pad; 808/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 809}; 810struct drm_radeon_gem_busy { 811 uint32_t handle; 812 uint32_t domain; 813/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 814}; 815struct drm_radeon_gem_pread { 816 uint32_t handle; 817 uint32_t pad; 818/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 819 uint64_t offset; 820 uint64_t size; 821 uint64_t data_ptr; 822}; 823/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 824struct drm_radeon_gem_pwrite { 825 uint32_t handle; 826 uint32_t pad; 827 uint64_t offset; 828/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 829 uint64_t size; 830 uint64_t data_ptr; 831}; 832#define RADEON_VA_MAP 1 833/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 834#define RADEON_VA_UNMAP 2 835#define RADEON_VA_RESULT_OK 0 836#define RADEON_VA_RESULT_ERROR 1 837#define RADEON_VA_RESULT_VA_EXIST 2 838/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 839#define RADEON_VM_PAGE_VALID (1 << 0) 840#define RADEON_VM_PAGE_READABLE (1 << 1) 841#define RADEON_VM_PAGE_WRITEABLE (1 << 2) 842#define RADEON_VM_PAGE_SYSTEM (1 << 3) 843/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 844#define RADEON_VM_PAGE_SNOOPED (1 << 4) 845struct drm_radeon_gem_va { 846 uint32_t handle; 847 uint32_t operation; 848/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 849 uint32_t vm_id; 850 uint32_t flags; 851 uint64_t offset; 852}; 853/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 854#define RADEON_CHUNK_ID_RELOCS 0x01 855#define RADEON_CHUNK_ID_IB 0x02 856#define RADEON_CHUNK_ID_FLAGS 0x03 857#define RADEON_CHUNK_ID_CONST_IB 0x04 858/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 859#define RADEON_CS_KEEP_TILING_FLAGS 0x01 860#define RADEON_CS_USE_VM 0x02 861#define RADEON_CS_END_OF_FRAME 0x04 862#define RADEON_CS_RING_GFX 0 863/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 864#define RADEON_CS_RING_COMPUTE 1 865#define RADEON_CS_RING_DMA 2 866#define RADEON_CS_RING_UVD 3 867struct drm_radeon_cs_chunk { 868/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 869 uint32_t chunk_id; 870 uint32_t length_dw; 871 uint64_t chunk_data; 872}; 873/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 874struct drm_radeon_cs_reloc { 875 uint32_t handle; 876 uint32_t read_domains; 877 uint32_t write_domain; 878/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 879 uint32_t flags; 880}; 881struct drm_radeon_cs { 882 uint32_t num_chunks; 883/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 884 uint32_t cs_id; 885 uint64_t chunks; 886 uint64_t gart_limit; 887 uint64_t vram_limit; 888/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 889}; 890#define RADEON_INFO_DEVICE_ID 0x00 891#define RADEON_INFO_NUM_GB_PIPES 0x01 892#define RADEON_INFO_NUM_Z_PIPES 0x02 893/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 894#define RADEON_INFO_ACCEL_WORKING 0x03 895#define RADEON_INFO_CRTC_FROM_ID 0x04 896#define RADEON_INFO_ACCEL_WORKING2 0x05 897#define RADEON_INFO_TILING_CONFIG 0x06 898/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 899#define RADEON_INFO_WANT_HYPERZ 0x07 900#define RADEON_INFO_WANT_CMASK 0x08 901#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 902#define RADEON_INFO_NUM_BACKENDS 0x0a 903/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 904#define RADEON_INFO_NUM_TILE_PIPES 0x0b 905#define RADEON_INFO_FUSION_GART_WORKING 0x0c 906#define RADEON_INFO_BACKEND_MAP 0x0d 907#define RADEON_INFO_VA_START 0x0e 908/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 909#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f 910#define RADEON_INFO_MAX_PIPES 0x10 911#define RADEON_INFO_TIMESTAMP 0x11 912#define RADEON_INFO_MAX_SE 0x12 913/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 914#define RADEON_INFO_MAX_SH_PER_SE 0x13 915#define RADEON_INFO_FASTFB_WORKING 0x14 916#define RADEON_INFO_RING_WORKING 0x15 917#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 918/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 919#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 920#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 921#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19 922#define RADEON_INFO_MAX_SCLK 0x1a 923/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 924struct drm_radeon_info { 925 uint32_t request; 926 uint32_t pad; 927 uint64_t value; 928/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 929}; 930#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8 931#define SI_TILE_MODE_COLOR_1D 13 932#define SI_TILE_MODE_COLOR_1D_SCANOUT 9 933/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 934#define SI_TILE_MODE_COLOR_2D_8BPP 14 935#define SI_TILE_MODE_COLOR_2D_16BPP 15 936#define SI_TILE_MODE_COLOR_2D_32BPP 16 937#define SI_TILE_MODE_COLOR_2D_64BPP 17 938/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 939#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11 940#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12 941#define SI_TILE_MODE_DEPTH_STENCIL_1D 4 942#define SI_TILE_MODE_DEPTH_STENCIL_2D 0 943/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 944#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3 945#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 946#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 947#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 948/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 949#endif 950