vc4_drm.h revision 1308ad3ab33294c3abfd96da12b6df58b381ce52 
1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_VC4_DRM_H_
20#define _UAPI_VC4_DRM_H_
21#include "drm.h"
22#ifdef __cplusplus
23#endif
24#define DRM_VC4_SUBMIT_CL 0x00
25#define DRM_VC4_WAIT_SEQNO 0x01
26#define DRM_VC4_WAIT_BO 0x02
27#define DRM_VC4_CREATE_BO 0x03
28#define DRM_VC4_MMAP_BO 0x04
29#define DRM_VC4_CREATE_SHADER_BO 0x05
30#define DRM_VC4_GET_HANG_STATE 0x06
31#define DRM_VC4_GET_PARAM 0x07
32#define DRM_VC4_SET_TILING 0x08
33#define DRM_VC4_GET_TILING 0x09
34#define DRM_VC4_LABEL_BO 0x0a
35#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
36#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
37#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
38#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
39#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
40#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
41#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
42#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
43#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
44#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
45#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)
46struct drm_vc4_submit_rcl_surface {
47  __u32 hindex;
48  __u32 offset;
49  __u16 bits;
50#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)
51  __u16 flags;
52};
53struct drm_vc4_submit_cl {
54  __u64 bin_cl;
55  __u64 shader_rec;
56  __u64 uniforms;
57  __u64 bo_handles;
58  __u32 bin_cl_size;
59  __u32 shader_rec_size;
60  __u32 shader_rec_count;
61  __u32 uniforms_size;
62  __u32 bo_handle_count;
63  __u16 width;
64  __u16 height;
65  __u8 min_x_tile;
66  __u8 min_y_tile;
67  __u8 max_x_tile;
68  __u8 max_y_tile;
69  struct drm_vc4_submit_rcl_surface color_read;
70  struct drm_vc4_submit_rcl_surface color_write;
71  struct drm_vc4_submit_rcl_surface zs_read;
72  struct drm_vc4_submit_rcl_surface zs_write;
73  struct drm_vc4_submit_rcl_surface msaa_color_write;
74  struct drm_vc4_submit_rcl_surface msaa_zs_write;
75  __u32 clear_color[2];
76  __u32 clear_z;
77  __u8 clear_s;
78  __u32 pad : 24;
79#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
80#define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1)
81#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2)
82#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3)
83  __u32 flags;
84  __u64 seqno;
85};
86struct drm_vc4_wait_seqno {
87  __u64 seqno;
88  __u64 timeout_ns;
89};
90struct drm_vc4_wait_bo {
91  __u32 handle;
92  __u32 pad;
93  __u64 timeout_ns;
94};
95struct drm_vc4_create_bo {
96  __u32 size;
97  __u32 flags;
98  __u32 handle;
99  __u32 pad;
100};
101struct drm_vc4_mmap_bo {
102  __u32 handle;
103  __u32 flags;
104  __u64 offset;
105};
106struct drm_vc4_create_shader_bo {
107  __u32 size;
108  __u32 flags;
109  __u64 data;
110  __u32 handle;
111  __u32 pad;
112};
113struct drm_vc4_get_hang_state_bo {
114  __u32 handle;
115  __u32 paddr;
116  __u32 size;
117  __u32 pad;
118};
119struct drm_vc4_get_hang_state {
120  __u64 bo;
121  __u32 bo_count;
122  __u32 start_bin, start_render;
123  __u32 ct0ca, ct0ea;
124  __u32 ct1ca, ct1ea;
125  __u32 ct0cs, ct1cs;
126  __u32 ct0ra0, ct1ra0;
127  __u32 bpca, bpcs;
128  __u32 bpoa, bpos;
129  __u32 vpmbase;
130  __u32 dbge;
131  __u32 fdbgo;
132  __u32 fdbgb;
133  __u32 fdbgr;
134  __u32 fdbgs;
135  __u32 errstat;
136  __u32 pad[16];
137};
138#define DRM_VC4_PARAM_V3D_IDENT0 0
139#define DRM_VC4_PARAM_V3D_IDENT1 1
140#define DRM_VC4_PARAM_V3D_IDENT2 2
141#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3
142#define DRM_VC4_PARAM_SUPPORTS_ETC1 4
143#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
144#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6
145struct drm_vc4_get_param {
146  __u32 param;
147  __u32 pad;
148  __u64 value;
149};
150struct drm_vc4_get_tiling {
151  __u32 handle;
152  __u32 flags;
153  __u64 modifier;
154};
155struct drm_vc4_set_tiling {
156  __u32 handle;
157  __u32 flags;
158  __u64 modifier;
159};
160struct drm_vc4_label_bo {
161  __u32 handle;
162  __u32 len;
163  __u64 name;
164};
165#ifdef __cplusplus
166#endif
167#endif
168