virtgpu_drm.h revision 96c1db7b9d601c31d103389cac074a6cce0d7633 
1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef VIRTGPU_DRM_H
20#define VIRTGPU_DRM_H
21#include "drm.h"
22#ifdef __cplusplus
23#endif
24#define DRM_VIRTGPU_MAP 0x01
25#define DRM_VIRTGPU_EXECBUFFER 0x02
26#define DRM_VIRTGPU_GETPARAM 0x03
27#define DRM_VIRTGPU_RESOURCE_CREATE 0x04
28#define DRM_VIRTGPU_RESOURCE_INFO 0x05
29#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
30#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
31#define DRM_VIRTGPU_WAIT 0x08
32#define DRM_VIRTGPU_GET_CAPS 0x09
33struct drm_virtgpu_map {
34  __u64 offset;
35  __u32 handle;
36  __u32 pad;
37};
38struct drm_virtgpu_execbuffer {
39  __u32 flags;
40  __u32 size;
41  __u64 command;
42  __u64 bo_handles;
43  __u32 num_bo_handles;
44  __u32 pad;
45};
46#define VIRTGPU_PARAM_3D_FEATURES 1
47struct drm_virtgpu_getparam {
48  __u64 param;
49  __u64 value;
50};
51struct drm_virtgpu_resource_create {
52  __u32 target;
53  __u32 format;
54  __u32 bind;
55  __u32 width;
56  __u32 height;
57  __u32 depth;
58  __u32 array_size;
59  __u32 last_level;
60  __u32 nr_samples;
61  __u32 flags;
62  __u32 bo_handle;
63  __u32 res_handle;
64  __u32 size;
65  __u32 stride;
66};
67struct drm_virtgpu_resource_info {
68  __u32 bo_handle;
69  __u32 res_handle;
70  __u32 size;
71  __u32 stride;
72};
73struct drm_virtgpu_3d_box {
74  __u32 x;
75  __u32 y;
76  __u32 z;
77  __u32 w;
78  __u32 h;
79  __u32 d;
80};
81struct drm_virtgpu_3d_transfer_to_host {
82  __u32 bo_handle;
83  struct drm_virtgpu_3d_box box;
84  __u32 level;
85  __u32 offset;
86};
87struct drm_virtgpu_3d_transfer_from_host {
88  __u32 bo_handle;
89  struct drm_virtgpu_3d_box box;
90  __u32 level;
91  __u32 offset;
92};
93#define VIRTGPU_WAIT_NOWAIT 1
94struct drm_virtgpu_3d_wait {
95  __u32 handle;
96  __u32 flags;
97};
98struct drm_virtgpu_get_caps {
99  __u32 cap_set_id;
100  __u32 cap_set_ver;
101  __u64 addr;
102  __u32 size;
103  __u32 pad;
104};
105#define DRM_IOCTL_VIRTGPU_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
106#define DRM_IOCTL_VIRTGPU_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER, struct drm_virtgpu_execbuffer)
107#define DRM_IOCTL_VIRTGPU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM, struct drm_virtgpu_getparam)
108#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, struct drm_virtgpu_resource_create)
109#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, struct drm_virtgpu_resource_info)
110#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, struct drm_virtgpu_3d_transfer_from_host)
111#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, struct drm_virtgpu_3d_transfer_to_host)
112#define DRM_IOCTL_VIRTGPU_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, struct drm_virtgpu_3d_wait)
113#define DRM_IOCTL_VIRTGPU_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, struct drm_virtgpu_get_caps)
114#ifdef __cplusplus
115#endif
116#endif
117