pci_regs.h revision 48af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0
1655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/**************************************************************************** 2655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng **************************************************************************** 3655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 4655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** This header was automatically generated from a Linux kernel header 5655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** of the same name, to make information necessary for userspace to 6655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** call into the kernel available to libc. It contains only constants, 7655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** structures, and macros generated from the original header, and thus, 8655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** contains no copyrightable information. 9655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 10655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** To edit the content of this header, modify the corresponding 11655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** source file (e.g. under external/kernel-headers/original/) then 12655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** run bionic/libc/kernel/tools/update_all.py 13655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 14655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** Any manual change here will be lost the next time this script will 15655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** be run. You've been warned! 16655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 17655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng **************************************************************************** 18655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ****************************************************************************/ 19655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#ifndef LINUX_PCI_REGS_H 20655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define LINUX_PCI_REGS_H 2148af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris#define PCI_CFG_SPACE_SIZE 256 2248af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris#define PCI_CFG_SPACE_EXP_SIZE 4096 2348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STD_HEADER_SIZEOF 64 25655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VENDOR_ID 0x00 26655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_DEVICE_ID 0x02 27655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND 0x04 2848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_IO 0x1 30655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_MEMORY 0x2 31655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_MASTER 0x4 32655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_SPECIAL 0x8 3348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_INVALIDATE 0x10 35655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_VGA_PALETTE 0x20 36655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_PARITY 0x40 37655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_WAIT 0x80 3848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_SERR 0x100 40655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_FAST_BACK 0x200 41655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_INTX_DISABLE 0x400 42655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS 0x06 4348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_INTERRUPT 0x08 45655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_CAP_LIST 0x10 46655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_66MHZ 0x20 47655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_UDF 0x40 4848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_FAST_BACK 0x80 50655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_PARITY 0x100 51655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_MASK 0x600 52655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_FAST 0x000 5348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_MEDIUM 0x200 55655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_SLOW 0x400 56655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_SIG_TARGET_ABORT 0x800 57655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_REC_TARGET_ABORT 0x1000 5848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_REC_MASTER_ABORT 0x2000 60655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 61655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DETECTED_PARITY 0x8000 62655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CLASS_REVISION 0x08 6348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_REVISION_ID 0x08 65655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CLASS_PROG 0x09 66655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CLASS_DEVICE 0x0a 67655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CACHE_LINE_SIZE 0x0c 6848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LATENCY_TIMER 0x0d 70655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE 0x0e 71655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE_NORMAL 0 72655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE_BRIDGE 1 7348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE_CARDBUS 2 75655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST 0x0f 76655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST_CODE_MASK 0x0f 77655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST_START 0x40 7848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST_CAPABLE 0x80 80655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_0 0x10 81655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_1 0x14 82655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_2 0x18 8348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_3 0x1c 85655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_4 0x20 86655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_5 0x24 87655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_SPACE 0x01 8848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_SPACE_IO 0x01 90655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 91655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 92655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 9348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 95655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 96655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 97655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 9848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 100655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CARDBUS_CIS 0x28 101655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 102655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SUBSYSTEM_ID 0x2e 10348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS 0x30 105655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS_ENABLE 0x01 106655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 107655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAPABILITY_LIST 0x34 10848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_INTERRUPT_LINE 0x3c 110655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_INTERRUPT_PIN 0x3d 111655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MIN_GNT 0x3e 112655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MAX_LAT 0x3f 11348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRIMARY_BUS 0x18 115655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SECONDARY_BUS 0x19 116655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SUBORDINATE_BUS 0x1a 117655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SEC_LATENCY_TIMER 0x1b 11848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_BASE 0x1c 120655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_LIMIT 0x1d 121655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_TYPE_MASK 0x0fUL 122655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_TYPE_16 0x00 12348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_TYPE_32 0x01 125655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_MASK (~0x0fUL) 126655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_1K_RANGE_MASK (~0x03UL) 127655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SEC_STATUS 0x1e 12848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_BASE 0x20 130655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_LIMIT 0x22 131655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 132655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_RANGE_MASK (~0x0fUL) 13348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_MEMORY_BASE 0x24 135655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_MEMORY_LIMIT 0x26 136655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 137655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_TYPE_32 0x00 13848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_TYPE_64 0x01 140655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_MASK (~0x0fUL) 141655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_BASE_UPPER32 0x28 142655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_LIMIT_UPPER32 0x2c 14348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_BASE_UPPER16 0x30 145655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_LIMIT_UPPER16 0x32 146655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS1 0x38 147655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CONTROL 0x3e 14848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_PARITY 0x01 150655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_SERR 0x02 151655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_ISA 0x04 152655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_VGA 0x08 15348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 155655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_BUS_RESET 0x40 156655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_FAST_BACK 0x80 157655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_CAPABILITY_LIST 0x14 15848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SEC_STATUS 0x16 160655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_PRIMARY_BUS 0x18 161655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_CARD_BUS 0x19 162655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SUBORDINATE_BUS 0x1a 16348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_LATENCY_TIMER 0x1b 165655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_BASE_0 0x1c 166655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_LIMIT_0 0x20 167655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_BASE_1 0x24 16848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_LIMIT_1 0x28 170655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_0 0x2c 171655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_0_HI 0x2e 172655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_0 0x30 17348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_0_HI 0x32 175655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_1 0x34 176655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_1_HI 0x36 177655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_1 0x38 17848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_1_HI 0x3a 180655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_RANGE_MASK (~0x03UL) 181655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CONTROL 0x3e 182655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_PARITY 0x01 18348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_SERR 0x02 185655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_ISA 0x04 186655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_VGA 0x08 187655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 18848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 190655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 191655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 192655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 19348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 195655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 196655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SUBSYSTEM_ID 0x42 197655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_LEGACY_MODE_BASE 0x44 19848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_LIST_ID 0 200655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_PM 0x01 201655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_AGP 0x02 202655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_VPD 0x03 20348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SLOTID 0x04 205655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_MSI 0x05 206655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_CHSWP 0x06 207655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_PCIX 0x07 20848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_HT 0x08 210655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_VNDR 0x09 211655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_DBG 0x0A 212655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_CCRC 0x0B 21348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SHPC 0x0C 215655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SSVID 0x0D 216655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_AGP3 0x0E 217655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SECDEV 0x0F 21848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_EXP 0x10 220655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_MSIX 0x11 221655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SATA 0x12 222655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_AF 0x13 22348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 22405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_CAP_ID_EA 0x14 22505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_CAP_ID_MAX PCI_CAP_ID_EA 22605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_CAP_LIST_NEXT 1 227655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_FLAGS 2 22848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_SIZEOF 4 230655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_PMC 2 23105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CAP_VER_MASK 0x0007 232655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_CLOCK 0x0008 23348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_RESERVED 0x0010 235655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_DSI 0x0020 23605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CAP_AUX_POWER 0x01C0 237655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_D1 0x0200 23848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_D2 0x0400 240655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME 0x0800 24105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CAP_PME_MASK 0xF800 242655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D0 0x0800 24348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D1 0x1000 245655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D2 0x2000 24605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CAP_PME_D3 0x4000 247655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D3cold 0x8000 24848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_SHIFT 11 250655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL 4 25105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CTRL_STATE_MASK 0x0003 252655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 25348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_PME_ENABLE 0x0100 255655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 25605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 257655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_PME_STATUS 0x8000 25848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_PPB_EXTENSIONS 6 260655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_PPB_B2_B3 0x40 26105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_BPCC_ENABLE 0x80 262655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_DATA_REGISTER 7 26348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_SIZEOF 8 265655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_VERSION 2 26605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AGP_RFU 3 267655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS 4 26848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RQ_MASK 0xff000000 270655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_SBA 0x0200 27105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AGP_STATUS_64BIT 0x0020 272655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_FW 0x0010 27348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RATE4 0x0004 275655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RATE2 0x0002 27605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AGP_STATUS_RATE1 0x0001 277655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND 8 27848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 280655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_SBA 0x0200 28105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AGP_COMMAND_AGP 0x0100 282655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_64BIT 0x0020 28348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_FW 0x0010 285655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RATE4 0x0004 28605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AGP_COMMAND_RATE2 0x0002 287655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RATE1 0x0001 28848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_SIZEOF 12 290655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_ADDR 2 29105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_VPD_ADDR_MASK 0x7fff 292655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_ADDR_F 0x8000 29348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_DATA 4 295655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_VPD_SIZEOF 8 29605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_SID_ESR 2 297655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_ESR_NSLOTS 0x1f 29848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_ESR_FIC 0x20 300655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_CHASSIS_NR 3 30105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSI_FLAGS 2 302655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_ENABLE 0x0001 30348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_QMASK 0x000e 305655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_QSIZE 0x0070 30605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSI_FLAGS_64BIT 0x0080 307655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_MASKBIT 0x0100 30848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_RFU 3 310655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_ADDRESS_LO 4 31105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSI_ADDRESS_HI 8 312655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_DATA_32 8 31348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_MASK_32 12 315655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_PENDING_32 16 31605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSI_DATA_64 12 317655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_MASK_64 16 31848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_PENDING_64 20 320655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS 2 32105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSIX_FLAGS_QSIZE 0x07FF 322655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS_MASKALL 0x4000 32348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS_ENABLE 0x8000 325655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_TABLE 4 32605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSIX_TABLE_BIR 0x00000007 327655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_TABLE_OFFSET 0xfffffff8 32848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_PBA 8 330655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_PBA_BIR 0x00000007 33105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSIX_PBA_OFFSET 0xfffffff8 332915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR 33348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_MSIX_SIZEOF 12 335655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_SIZE 16 33605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSIX_ENTRY_LOWER_ADDR 0 337915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_MSIX_ENTRY_UPPER_ADDR 4 33848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_DATA 8 340655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 34105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 342915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_CHSWP_CSR 2 34348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_DHA 0x01 345655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_EIM 0x02 34605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_CHSWP_PIE 0x04 347915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_CHSWP_LOO 0x08 34848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_PI 0x30 350655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_EXT 0x40 35105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_CHSWP_INS 0x80 352915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_AF_LENGTH 2 35348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CAP 3 355655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CAP_TP 0x01 35605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AF_CAP_FLR 0x02 357915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_AF_CTRL 4 35848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CTRL_FLR 0x01 360655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_STATUS 5 36105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AF_STATUS_TP 0x01 362915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_CAP_AF_SIZEOF 6 36348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 36405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_NUM_ENT 2 36505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_NUM_ENT_MASK 0x3f 36605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_FIRST_ENT 4 36705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_FIRST_ENT_BRIDGE 8 36848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 36905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_ES 0x00000007 37005d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI 0x000000f0 37105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_BAR0 0 37205d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_BAR5 5 37348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 37405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_BRIDGE 6 37505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_ENI 7 37605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_ROM 8 37705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_VF_BAR0 9 37848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 37905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_VF_BAR5 14 38005d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_RESERVED 15 38105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_PP 0x0000ff00 38205d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_SP 0x00ff0000 38348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 38405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_MEM 0x00 38505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_MEM_PREFETCH 0x01 38605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_IO 0x02 38705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_VF_MEM_PREFETCH 0x03 38848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 38905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_VF_MEM 0x04 39005d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_BRIDGE_MEM 0x05 39105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_BRIDGE_MEM_PREFETCH 0x06 39205d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_BRIDGE_IO 0x07 39348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_MEM_RESERVED 0xfd 39505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_IO_RESERVED 0xfe 39605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_UNAVAILABLE 0xff 39705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_WRITABLE 0x40000000 39848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_ENABLE 0x80000000 40005d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BASE 4 40105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_MAX_OFFSET 8 40205d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_IS_64 0x00000002 40348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 40405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_FIELD_MASK 0xfffffffc 405655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD 2 406655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_DPERR_E 0x0001 407655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_ERO 0x0002 40848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_CMD_READ_512 0x0000 410655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_1K 0x0004 411655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_2K 0x0008 412655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_4K 0x000c 41348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_CMD_MAX_READ 0x000c 415655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_1 0x0000 416655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_2 0x0010 417655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_3 0x0020 41848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_CMD_SPLIT_4 0x0030 420655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_8 0x0040 421655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_12 0x0050 422655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_16 0x0060 42348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_CMD_SPLIT_32 0x0070 425655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_MAX_SPLIT 0x0070 426655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) 427655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS 4 42848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_STATUS_DEVFN 0x000000ff 430655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_BUS 0x0000ff00 431655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_64BIT 0x00010000 432655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_133MHZ 0x00020000 43348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_STATUS_SPL_DISC 0x00040000 435655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_UNX_SPL 0x00080000 436655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_COMPLEX 0x00100000 437655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_MAX_READ 0x00600000 43848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_STATUS_MAX_SPLIT 0x03800000 440655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_MAX_CUM 0x1c000000 441655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_SPL_ERR 0x20000000 442655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_266MHZ 0x40000000 44348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_STATUS_533MHZ 0x80000000 445655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_ECC_CSR 8 446655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_PCIX_SIZEOF_V0 8 447655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_PCIX_SIZEOF_V1 24 44848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 450655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_BRIDGE_SSTATUS 2 451655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_64BIT 0x0001 452655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_133MHZ 0x0002 45348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_SSTATUS_FREQ 0x03c0 455655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_VERS 0x3000 456655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_V1 0x1000 457655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_V2 0x2000 45848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_SSTATUS_266MHZ 0x4000 460655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_533MHZ 0x8000 461655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_BRIDGE_STATUS 4 462655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SSVID_VENDOR_ID 4 46348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SSVID_DEVICE_ID 6 465655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS 2 466655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_VERS 0x000f 467655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_TYPE 0x00f0 46848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_TYPE_ENDPOINT 0x0 470655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_LEG_END 0x1 471655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_ROOT_PORT 0x4 472655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_UPSTREAM 0x5 47348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_TYPE_DOWNSTREAM 0x6 475655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 476655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 477655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_RC_END 0x9 47848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_TYPE_RC_EC 0xa 480655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_SLOT 0x0100 481655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_IRQ 0x3e00 482655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP 4 48348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 48538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 48638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_EXT_TAG 0x00000020 48738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_L0S 0x000001c0 48848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCAP_L1 0x00000e00 49038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_ATN_BUT 0x00001000 49138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_ATN_IND 0x00002000 49238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PWR_IND 0x00004000 49348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCAP_RBER 0x00008000 49538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 49638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 497655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_FLR 0x10000000 49848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL 8 500655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_CERE 0x0001 501655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_NFERE 0x0002 502655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_FERE 0x0004 50348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL_URRE 0x0008 505655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 506655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 507655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 50848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL_PHANTOM 0x0200 510655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_AUX_PME 0x0400 511655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 512655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_READRQ 0x7000 51348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 51405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EXP_DEVCTL_READRQ_128B 0x0000 51505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 51605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 51705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 51848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 52038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA 10 52138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_CED 0x0001 52238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_NFED 0x0002 52348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVSTA_FED 0x0004 52538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_URD 0x0008 52638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_AUXPD 0x0010 52738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_TRPND 0x0020 52848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCAP 12 53038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP_SLS 0x0000000f 53138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 53238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 53348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCAP_MLW 0x000003f0 535655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 536655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_L0SEL 0x00007000 537655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_L1EL 0x00038000 53848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCAP_CLKPM 0x00040000 540655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_SDERC 0x00080000 541655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 542655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_LBNC 0x00200000 54348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCAP_PN 0xff000000 545655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL 16 546655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_ASPMC 0x0003 54738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 54848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCTL_ASPM_L1 0x0002 550655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_RCB 0x0008 551655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_LD 0x0010 552655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_RL 0x0020 55348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCTL_CCC 0x0040 555655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_ES 0x0080 55638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 557655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_HAWD 0x0200 55848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCTL_LBMIE 0x0400 560655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_LABIE 0x0800 561655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA 18 562655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_CLS 0x000f 56348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 56538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 56638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 567655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_NLW 0x03f0 56848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKSTA_NLW_X1 0x0010 57038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_NLW_X2 0x0020 57138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_NLW_X4 0x0040 57238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_NLW_X8 0x0080 57348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKSTA_NLW_SHIFT 4 575655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_LT 0x0800 576655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_SLC 0x1000 577655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_DLLLA 0x2000 57848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKSTA_LBMS 0x4000 580655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_LABS 0x8000 581655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 582655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP 20 58348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCAP_ABP 0x00000001 585655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_PCP 0x00000002 586655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_MRLSP 0x00000004 587655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_AIP 0x00000008 58848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCAP_PIP 0x00000010 590655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_HPS 0x00000020 591655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_HPC 0x00000040 592655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_SPLV 0x00007f80 59348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCAP_SPLS 0x00018000 595655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_EIP 0x00020000 596655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_NCCS 0x00040000 597655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_PSN 0xfff80000 59848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCTL 24 600655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_ABPE 0x0001 601655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PFDE 0x0002 602655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_MRLSCE 0x0004 60348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCTL_PDCE 0x0008 605655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_CCIE 0x0010 606655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_HPIE 0x0020 607655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_AIC 0x00c0 60848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 61038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 61138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 612655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PIC 0x0300 61348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 61538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 61638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 617655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PCC 0x0400 61848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCTL_PWR_ON 0x0000 62038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_PWR_OFF 0x0400 621655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_EIC 0x0800 622655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_DLLSCE 0x1000 62348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTSTA 26 625655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_ABP 0x0001 626655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_PFD 0x0002 627655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_MRLSC 0x0004 62848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTSTA_PDC 0x0008 630655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_CC 0x0010 631655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_MRLSS 0x0020 632655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_PDS 0x0040 63348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTSTA_EIS 0x0080 635655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_DLLSC 0x0100 636655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTCTL 28 63738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_SECEE 0x0001 63848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_RTCTL_SENFEE 0x0002 64038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_SEFEE 0x0004 64138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_PMEIE 0x0008 64238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_CRSSVE 0x0010 64348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_RTCAP 30 64582d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_RTCAP_CRSVIS 0x0001 646655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTSTA 32 64738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTSTA_PME 0x00010000 64848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_RTSTA_PENDING 0x00020000 65082d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_DEVCAP2 36 65138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP2_ARI 0x00000020 6526a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 65348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 6546a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 65538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP2_LTR 0x00000800 656915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 65782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 65848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 65938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 660655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL2 40 661915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f 66282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_DEVCTL2_ARI 0x0020 66348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 6646a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 66538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 66638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 667915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 66848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 66982d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 67038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 67138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 672915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVSTA2 42 67348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 67482d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 675655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP2 44 67638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 677915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 67848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 67982d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 68038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 681655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL2 48 682915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKSTA2 50 68348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 68482d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_SLTCAP2 52 685655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL2 56 68638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTSTA2 58 687915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 68848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 68982d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 690655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 691655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_ERR 0x01 692915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_VC 0x02 69348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69482d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_DSN 0x03 695655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_PWR 0x04 696655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_RCLD 0x05 697915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_RCILC 0x06 69848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69982d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_RCEC 0x07 700655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_MFVC 0x08 701655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_VC9 0x09 702915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_RCRB 0x0A 70348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 70482d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_VNDR 0x0B 705655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_CAC 0x0C 706655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_ACS 0x0D 707915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_ARI 0x0E 70848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 70982d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_ATS 0x0F 710655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_SRIOV 0x10 711655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_MRIOV 0x11 712915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_MCAST 0x12 71348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 71482d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_PRI 0x13 715655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_AMD_XXX 0x14 716655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_REBAR 0x15 717915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_DPA 0x16 71848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 71982d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_TPH 0x17 720655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_LTR 0x18 721655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_SECPCI 0x19 722915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_PMUX 0x1A 72348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 72482d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_PASID 0x1B 725106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXT_CAP_ID_DPC 0x1D 7266a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_EXT_CAP_ID_PTM 0x1F 7276a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM 72848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_DSN_SIZEOF 12 730915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 731106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_UNCOR_STATUS 4 73282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_UNC_UND 0x00000001 73348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_DLP 0x00000010 735915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_UNC_SURPDN 0x00000020 736106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_UNC_POISON_TLP 0x00001000 737655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_FCP 0x00002000 73848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_COMP_TIME 0x00004000 740915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_UNC_COMP_ABORT 0x00008000 741106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_UNC_UNX_COMP 0x00010000 742655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_RX_OVER 0x00020000 74348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_MALF_TLP 0x00040000 745915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_UNC_ECRC 0x00080000 746106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_UNC_UNSUP 0x00100000 747655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_ACSV 0x00200000 74848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_INTN 0x00400000 750915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_UNC_MCBTLP 0x00800000 751106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_UNC_ATOMEG 0x01000000 752655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_TLPPRE 0x02000000 75348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNCOR_MASK 8 755915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_UNCOR_SEVER 12 756106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_COR_STATUS 16 757655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_RCVR 0x00000001 75848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_BAD_TLP 0x00000040 760915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_COR_BAD_DLLP 0x00000080 761106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_COR_REP_ROLL 0x00000100 762655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_REP_TIMER 0x00001000 76348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_ADV_NFAT 0x00002000 765915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_COR_INTERNAL 0x00004000 766106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_COR_LOG_OVER 0x00008000 767655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_MASK 20 76848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP 24 770915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_CAP_FEP(x) ((x) & 31) 771106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_CAP_ECRC_GENC 0x00000020 772655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_ECRC_GENE 0x00000040 77348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 775915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 776106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_HEADER_LOG 28 777655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_COMMAND 44 77848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 780915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 781106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 782655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_STATUS 48 78348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_COR_RCV 0x00000001 785915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 786106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 787655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 78848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 789655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 790915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 791106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 792655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_ERR_SRC 52 79348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_PORT_CAP1 4 795915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_CAP1_EVCC 0x00000007 796106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VC_CAP1_LPEVCC 0x00000070 79738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP1_ARB_SIZE 0x00000c00 79848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_PORT_CAP2 8 800915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_CAP2_32_PHASE 0x00000002 801106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VC_CAP2_64_PHASE 0x00000004 80238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP2_128_PHASE 0x00000008 80348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 80438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP2_ARB_OFF 0xff000000 805915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_PORT_CTRL 12 806106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 807655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_PORT_STATUS 14 80848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 80938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_PORT_STATUS_TABLE 0x00000001 810915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_RES_CAP 16 811106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VC_RES_CAP_32_PHASE 0x00000002 81238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CAP_64_PHASE 0x00000004 81348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 81438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CAP_128_PHASE 0x00000008 815915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 816106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VC_RES_CAP_256_PHASE 0x00000020 81738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CAP_ARB_OFF 0xff000000 81848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 819655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_RES_CTRL 20 820915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 821106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 82238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CTRL_ID 0x07000000 82348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 82438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CTRL_ENABLE 0x80000000 825915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_RES_STATUS 26 826106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VC_RES_STATUS_TABLE 0x00000001 82738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_STATUS_NEGO 0x00000002 82848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 829655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_VC_BASE_SIZEOF 0x10 830915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C 831106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PWR_DSR 4 83238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PWR_DATA 8 83348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 834655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 835915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 836106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 83738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 83848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 839655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 840915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 841106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PWR_CAP 12 84238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) 84348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 844655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_PWR_SIZEOF 16 845915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VNDR_HEADER 4 846106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) 84738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) 84848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 849655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) 850915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_3BIT_CAP_MASK 0xE0 851106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define HT_CAPTYPE_SLAVE 0x00 85238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAPTYPE_HOST 0x20 85348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 854655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_5BIT_CAP_MASK 0xF8 855915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_CAPTYPE_IRQ 0x80 856106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define HT_CAPTYPE_REMAPPING_40 0xA0 85738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAPTYPE_REMAPPING_64 0xA2 85848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 859655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_UNITID_CLUMP 0x90 860915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_CAPTYPE_EXTCONF 0x98 861106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define HT_CAPTYPE_MSI_MAPPING 0xA8 86238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_MSI_FLAGS 0x02 86348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 864655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_FLAGS_ENABLE 0x1 865915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_MSI_FLAGS_FIXED 0x2 866106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL 86738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_MSI_ADDR_LO 0x04 86848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 869655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_ADDR_LO_MASK 0xFFF00000 870915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_MSI_ADDR_HI 0x08 871106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define HT_CAPTYPE_DIRECT_ROUTE 0xB0 87238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAPTYPE_VCSET 0xB8 87348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 874655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_ERROR_RETRY 0xC0 875915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_CAPTYPE_GEN3 0xD0 876106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define HT_CAPTYPE_PM 0xE0 87738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAP_SIZEOF_LONG 28 87848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 879655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAP_SIZEOF_SHORT 24 880915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ARI_CAP 0x04 881106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ARI_CAP_MFVC 0x0001 88238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ARI_CAP_ACS 0x0002 88348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 884655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) 885915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ARI_CTRL 0x06 886106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ARI_CTRL_MFVC 0x0001 88738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ARI_CTRL_ACS 0x0002 88848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 889655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) 890915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ARI_SIZEOF 8 891106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ATS_CAP 0x04 89238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) 89348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 894655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_MAX_QDEP 32 895915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ATS_CTRL 0x06 896106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ATS_CTRL_ENABLE 0x8000 89738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) 89848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 899655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_MIN_STU 12 900915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ATS_SIZEOF 8 901106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PRI_CTRL 0x04 90238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PRI_CTRL_ENABLE 0x01 90348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 904655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_CTRL_RESET 0x02 905915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PRI_STATUS 0x06 906106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PRI_STATUS_RF 0x001 90738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PRI_STATUS_UPRGI 0x002 90848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 909655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_STATUS_STOPPED 0x100 910915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PRI_MAX_REQ 0x08 911106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PRI_ALLOC_REQ 0x0c 91238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXT_CAP_PRI_SIZEOF 16 91348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 914655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CAP 0x04 915915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PASID_CAP_EXEC 0x02 916106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PASID_CAP_PRIV 0x04 91738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PASID_CTRL 0x06 91848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 919655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CTRL_ENABLE 0x01 920915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PASID_CTRL_EXEC 0x02 921106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PASID_CTRL_PRIV 0x04 92238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXT_CAP_PASID_SIZEOF 8 92348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 924655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CAP 0x04 925915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_CAP_VFM 0x01 926106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) 92738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_CTRL 0x08 92848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 929655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL_VFE 0x01 930915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_CTRL_VFM 0x02 931106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SRIOV_CTRL_INTR 0x04 93238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_CTRL_MSE 0x08 93348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 934655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL_ARI 0x10 935915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_STATUS 0x0a 936106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SRIOV_STATUS_VFM 0x01 93738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_INITIAL_VF 0x0c 93848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 939655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_TOTAL_VF 0x0e 940915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_NUM_VF 0x10 941106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SRIOV_FUNC_LINK 0x12 94238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_VF_OFFSET 0x14 94348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 944655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VF_STRIDE 0x16 945915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_VF_DID 0x1a 946106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SRIOV_SUP_PGSIZE 0x1c 94738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_SYS_PGSIZE 0x20 94848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 949655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_BAR 0x24 950915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_NUM_BARS 6 951106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SRIOV_VFM 0x3c 95238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) 95348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 954655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) 955915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_VFM_UA 0x0 956106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SRIOV_VFM_MI 0x1 95738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_VFM_MO 0x2 95848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 959655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_AV 0x3 960915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_SRIOV_SIZEOF 64 961106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_LTR_MAX_SNOOP_LAT 0x4 96238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_LTR_MAX_NOSNOOP_LAT 0x6 96348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 964655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LTR_VALUE_MASK 0x000003ff 965915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_LTR_SCALE_MASK 0x00001c00 966106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_LTR_SCALE_SHIFT 10 96738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXT_CAP_LTR_SIZEOF 8 96848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 969655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_CAP 0x04 970915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ACS_SV 0x01 971106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ACS_TB 0x02 97238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ACS_RR 0x04 97348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 974655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_CR 0x08 975915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ACS_UF 0x10 976106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ACS_EC 0x20 97738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ACS_DT 0x40 97848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 979655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_EGRESS_BITS 0x05 980915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ACS_CTRL 0x06 981106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ACS_EGRESS_CTL_V 0x08 98238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VSEC_HDR 4 98348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 984655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VSEC_HDR_LEN_SHIFT 20 985915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SATA_REGS 4 986106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SATA_REGS_MASK 0xF 98738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SATA_REGS_INLINE 0xF 98848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 989655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SATA_SIZEOF_SHORT 8 990915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SATA_SIZEOF_LONG 16 991106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_REBAR_CTRL 8 99238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) 99348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 994655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_REBAR_CTRL_NBAR_SHIFT 5 995915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_DPA_CAP 4 996106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F 99738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_DPA_BASE_SIZEOF 16 99848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 999655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_CAP 4 1000915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_TPH_CAP_LOC_MASK 0x600 1001106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_TPH_LOC_NONE 0x000 100238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_TPH_LOC_CAP 0x200 100348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1004655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_LOC_MSIX 0x400 1005915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_TPH_CAP_ST_MASK 0x07FF0000 1006106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_TPH_CAP_ST_SHIFT 16 100738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_TPH_BASE_SIZEOF 12 100848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1009106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CAP 4 1010106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CAP_RP_EXT 0x20 1011106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 1012106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 101348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1014106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 1015106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CTL 6 1016106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x02 1017106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CTL_INT_EN 0x08 101848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1019106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_STATUS 8 1020106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_STATUS_TRIGGER 0x01 1021106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_STATUS_INTERRUPT 0x08 1022106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_SOURCE_ID 10 102348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 10246a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_PTM_CAP 0x04 10256a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_PTM_CAP_REQ 0x00000001 10266a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_PTM_CAP_ROOT 0x00000004 10276a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_PTM_GRANULARITY_MASK 0x0000FF00 102848af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 10296a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_PTM_CTRL 0x08 10306a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_PTM_CTRL_ENABLE 0x00000001 10316a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_PTM_CTRL_ROOT 0x00000002 1032655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#endif 103348af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1034