pci_regs.h revision 655a7c081f83b8351ed5f11a6c6accd9458293a8
1655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/**************************************************************************** 2655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng **************************************************************************** 3655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 4655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** This header was automatically generated from a Linux kernel header 5655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** of the same name, to make information necessary for userspace to 6655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** call into the kernel available to libc. It contains only constants, 7655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** structures, and macros generated from the original header, and thus, 8655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** contains no copyrightable information. 9655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 10655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** To edit the content of this header, modify the corresponding 11655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** source file (e.g. under external/kernel-headers/original/) then 12655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** run bionic/libc/kernel/tools/update_all.py 13655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 14655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** Any manual change here will be lost the next time this script will 15655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** be run. You've been warned! 16655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 17655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng **************************************************************************** 18655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ****************************************************************************/ 19655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#ifndef LINUX_PCI_REGS_H 20655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define LINUX_PCI_REGS_H 21655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STD_HEADER_SIZEOF 64 22655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VENDOR_ID 0x00 23655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_DEVICE_ID 0x02 25655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND 0x04 26655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_IO 0x1 27655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_MEMORY 0x2 28655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_MASTER 0x4 30655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_SPECIAL 0x8 31655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_INVALIDATE 0x10 32655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_VGA_PALETTE 0x20 33655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_PARITY 0x40 35655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_WAIT 0x80 36655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_SERR 0x100 37655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_FAST_BACK 0x200 38655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_INTX_DISABLE 0x400 40655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS 0x06 41655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_INTERRUPT 0x08 42655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_CAP_LIST 0x10 43655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_66MHZ 0x20 45655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_UDF 0x40 46655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_FAST_BACK 0x80 47655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_PARITY 0x100 48655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_MASK 0x600 50655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_FAST 0x000 51655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_MEDIUM 0x200 52655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_SLOW 0x400 53655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_SIG_TARGET_ABORT 0x800 55655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_REC_TARGET_ABORT 0x1000 56655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_REC_MASTER_ABORT 0x2000 57655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 58655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DETECTED_PARITY 0x8000 60655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CLASS_REVISION 0x08 61655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_REVISION_ID 0x08 62655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CLASS_PROG 0x09 63655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CLASS_DEVICE 0x0a 65655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CACHE_LINE_SIZE 0x0c 66655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LATENCY_TIMER 0x0d 67655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE 0x0e 68655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE_NORMAL 0 70655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE_BRIDGE 1 71655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE_CARDBUS 2 72655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST 0x0f 73655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST_CODE_MASK 0x0f 75655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST_START 0x40 76655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST_CAPABLE 0x80 77655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_0 0x10 78655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_1 0x14 80655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_2 0x18 81655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_3 0x1c 82655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_4 0x20 83655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_5 0x24 85655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_SPACE 0x01 86655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_SPACE_IO 0x01 87655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 88655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 90655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 91655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 92655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 93655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 95655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 96655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 97655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CARDBUS_CIS 0x28 98655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 100655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SUBSYSTEM_ID 0x2e 101655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS 0x30 102655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS_ENABLE 0x01 103655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 105655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAPABILITY_LIST 0x34 106655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_INTERRUPT_LINE 0x3c 107655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_INTERRUPT_PIN 0x3d 108655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MIN_GNT 0x3e 110655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MAX_LAT 0x3f 111655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRIMARY_BUS 0x18 112655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SECONDARY_BUS 0x19 113655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SUBORDINATE_BUS 0x1a 115655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SEC_LATENCY_TIMER 0x1b 116655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_BASE 0x1c 117655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_LIMIT 0x1d 118655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_TYPE_MASK 0x0fUL 120655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_TYPE_16 0x00 121655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_TYPE_32 0x01 122655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_MASK (~0x0fUL) 123655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_1K_RANGE_MASK (~0x03UL) 125655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SEC_STATUS 0x1e 126655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_BASE 0x20 127655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_LIMIT 0x22 128655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 130655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_RANGE_MASK (~0x0fUL) 131655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_MEMORY_BASE 0x24 132655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_MEMORY_LIMIT 0x26 133655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 135655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_TYPE_32 0x00 136655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_TYPE_64 0x01 137655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_MASK (~0x0fUL) 138655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_BASE_UPPER32 0x28 140655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_LIMIT_UPPER32 0x2c 141655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_BASE_UPPER16 0x30 142655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_LIMIT_UPPER16 0x32 143655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS1 0x38 145655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CONTROL 0x3e 146655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_PARITY 0x01 147655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_SERR 0x02 148655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_ISA 0x04 150655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_VGA 0x08 151655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 152655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_BUS_RESET 0x40 153655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_FAST_BACK 0x80 155655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_CAPABILITY_LIST 0x14 156655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SEC_STATUS 0x16 157655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_PRIMARY_BUS 0x18 158655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_CARD_BUS 0x19 160655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SUBORDINATE_BUS 0x1a 161655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_LATENCY_TIMER 0x1b 162655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_BASE_0 0x1c 163655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_LIMIT_0 0x20 165655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_BASE_1 0x24 166655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_LIMIT_1 0x28 167655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_0 0x2c 168655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_0_HI 0x2e 170655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_0 0x30 171655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_0_HI 0x32 172655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_1 0x34 173655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_1_HI 0x36 175655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_1 0x38 176655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_1_HI 0x3a 177655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_RANGE_MASK (~0x03UL) 178655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CONTROL 0x3e 180655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_PARITY 0x01 181655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_SERR 0x02 182655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_ISA 0x04 183655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_VGA 0x08 185655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 186655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 187655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 188655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 190655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 191655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 192655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 193655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SUBSYSTEM_ID 0x42 195655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_LEGACY_MODE_BASE 0x44 196655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_LIST_ID 0 197655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_PM 0x01 198655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_AGP 0x02 200655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_VPD 0x03 201655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SLOTID 0x04 202655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_MSI 0x05 203655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_CHSWP 0x06 205655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_PCIX 0x07 206655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_HT 0x08 207655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_VNDR 0x09 208655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_DBG 0x0A 210655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_CCRC 0x0B 211655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SHPC 0x0C 212655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SSVID 0x0D 213655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_AGP3 0x0E 215655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SECDEV 0x0F 216655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_EXP 0x10 217655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_MSIX 0x11 218655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SATA 0x12 220655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_AF 0x13 221655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_MAX PCI_CAP_ID_AF 222655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_LIST_NEXT 1 223655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_FLAGS 2 225655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_SIZEOF 4 226655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_PMC 2 227655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_VER_MASK 0x0007 228655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_CLOCK 0x0008 230655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_RESERVED 0x0010 231655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_DSI 0x0020 232655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_AUX_POWER 0x01C0 233655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_D1 0x0200 235655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_D2 0x0400 236655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME 0x0800 237655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_MASK 0xF800 238655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D0 0x0800 240655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D1 0x1000 241655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D2 0x2000 242655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D3 0x4000 243655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D3cold 0x8000 245655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_SHIFT 11 246655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL 4 247655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_STATE_MASK 0x0003 248655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 250655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_PME_ENABLE 0x0100 251655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 252655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 253655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_PME_STATUS 0x8000 255655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_PPB_EXTENSIONS 6 256655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_PPB_B2_B3 0x40 257655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_BPCC_ENABLE 0x80 258655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_DATA_REGISTER 7 260655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_SIZEOF 8 261655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_VERSION 2 262655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_RFU 3 263655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS 4 265655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RQ_MASK 0xff000000 266655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_SBA 0x0200 267655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_64BIT 0x0020 268655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_FW 0x0010 270655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RATE4 0x0004 271655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RATE2 0x0002 272655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RATE1 0x0001 273655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND 8 275655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 276655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_SBA 0x0200 277655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_AGP 0x0100 278655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_64BIT 0x0020 280655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_FW 0x0010 281655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RATE4 0x0004 282655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RATE2 0x0002 283655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RATE1 0x0001 285655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_SIZEOF 12 286655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_ADDR 2 287655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_ADDR_MASK 0x7fff 288655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_ADDR_F 0x8000 290655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_DATA 4 291655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_VPD_SIZEOF 8 292655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_ESR 2 293655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_ESR_NSLOTS 0x1f 295655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_ESR_FIC 0x20 296655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_CHASSIS_NR 3 297655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS 2 298655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_ENABLE 0x0001 300655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_QMASK 0x000e 301655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_QSIZE 0x0070 302655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_64BIT 0x0080 303655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_MASKBIT 0x0100 305655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_RFU 3 306655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_ADDRESS_LO 4 307655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_ADDRESS_HI 8 308655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_DATA_32 8 310655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_MASK_32 12 311655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_PENDING_32 16 312655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_DATA_64 12 313655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_MASK_64 16 315655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_PENDING_64 20 316655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS 2 317655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS_QSIZE 0x07FF 318655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS_MASKALL 0x4000 320655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS_ENABLE 0x8000 321655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_TABLE 4 322655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_TABLE_BIR 0x00000007 323655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_TABLE_OFFSET 0xfffffff8 325655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_PBA 8 326655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_PBA_BIR 0x00000007 327655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_PBA_OFFSET 0xfffffff8 328655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) 330655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_MSIX_SIZEOF 12 331655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_SIZE 16 332655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_LOWER_ADDR 0 333655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_UPPER_ADDR 4 335655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_DATA 8 336655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 337655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 338655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_CSR 2 340655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_DHA 0x01 341655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_EIM 0x02 342655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_PIE 0x04 343655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_LOO 0x08 345655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_PI 0x30 346655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_EXT 0x40 347655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_INS 0x80 348655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_LENGTH 2 350655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CAP 3 351655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CAP_TP 0x01 352655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CAP_FLR 0x02 353655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CTRL 4 355655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CTRL_FLR 0x01 356655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_STATUS 5 357655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_STATUS_TP 0x01 358655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_AF_SIZEOF 6 360655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD 2 361655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_DPERR_E 0x0001 362655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_ERO 0x0002 363655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_512 0x0000 365655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_1K 0x0004 366655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_2K 0x0008 367655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_4K 0x000c 368655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_MAX_READ 0x000c 370655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_1 0x0000 371655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_2 0x0010 372655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_3 0x0020 373655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_4 0x0030 375655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_8 0x0040 376655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_12 0x0050 377655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_16 0x0060 378655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_32 0x0070 380655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_MAX_SPLIT 0x0070 381655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) 382655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS 4 383655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_DEVFN 0x000000ff 385655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_BUS 0x0000ff00 386655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_64BIT 0x00010000 387655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_133MHZ 0x00020000 388655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_SPL_DISC 0x00040000 390655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_UNX_SPL 0x00080000 391655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_COMPLEX 0x00100000 392655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_MAX_READ 0x00600000 393655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_MAX_SPLIT 0x03800000 395655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_MAX_CUM 0x1c000000 396655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_SPL_ERR 0x20000000 397655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_266MHZ 0x40000000 398655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_533MHZ 0x80000000 400655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_ECC_CSR 8 401655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_PCIX_SIZEOF_V0 8 402655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_PCIX_SIZEOF_V1 24 403655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 405655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_BRIDGE_SSTATUS 2 406655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_64BIT 0x0001 407655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_133MHZ 0x0002 408655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_FREQ 0x03c0 410655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_VERS 0x3000 411655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_V1 0x1000 412655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_V2 0x2000 413655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_266MHZ 0x4000 415655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_533MHZ 0x8000 416655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_BRIDGE_STATUS 4 417655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SSVID_VENDOR_ID 4 418655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SSVID_DEVICE_ID 6 420655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS 2 421655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_VERS 0x000f 422655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_TYPE 0x00f0 423655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_ENDPOINT 0x0 425655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_LEG_END 0x1 426655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_ROOT_PORT 0x4 427655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_UPSTREAM 0x5 428655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_DOWNSTREAM 0x6 430655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 431655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 432655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_RC_END 0x9 433655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_RC_EC 0xa 435655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_SLOT 0x0100 436655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_IRQ 0x3e00 437655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP 4 438655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_PAYLOAD 0x07 440655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_PHANTOM 0x18 441655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_EXT_TAG 0x20 442655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_L0S 0x1c0 443655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_L1 0xe00 445655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 446655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_ATN_IND 0x2000 447655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_PWR_IND 0x4000 448655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_RBER 0x8000 450655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 451655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 452655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_FLR 0x10000000 453655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL 8 455655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_CERE 0x0001 456655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_NFERE 0x0002 457655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_FERE 0x0004 458655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_URRE 0x0008 460655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 461655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 462655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 463655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_PHANTOM 0x0200 465655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_AUX_PME 0x0400 466655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 467655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_READRQ 0x7000 468655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 470655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVSTA 10 471655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVSTA_CED 0x01 472655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVSTA_NFED 0x02 473655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVSTA_FED 0x04 475655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVSTA_URD 0x08 476655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVSTA_AUXPD 0x10 477655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVSTA_TRPND 0x20 478655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP 12 480655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_SLS 0x0000000f 481655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_SLS_2_5GB 0x1 482655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_SLS_5_0GB 0x2 483655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_MLW 0x000003f0 485655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 486655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_L0SEL 0x00007000 487655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_L1EL 0x00038000 488655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_CLKPM 0x00040000 490655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_SDERC 0x00080000 491655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 492655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_LBNC 0x00200000 493655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_PN 0xff000000 495655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL 16 496655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_ASPMC 0x0003 497655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_ASPM_L0S 0x01 498655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_ASPM_L1 0x02 500655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_RCB 0x0008 501655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_LD 0x0010 502655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_RL 0x0020 503655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_CCC 0x0040 505655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_ES 0x0080 506655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 507655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_HAWD 0x0200 508655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_LBMIE 0x0400 510655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_LABIE 0x0800 511655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA 18 512655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_CLS 0x000f 513655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_CLS_2_5GB 0x01 515655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_CLS_5_0GB 0x02 516655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_NLW 0x03f0 517655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_NLW_SHIFT 4 518655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_LT 0x0800 520655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_SLC 0x1000 521655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_DLLLA 0x2000 522655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_LBMS 0x4000 523655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_LABS 0x8000 525655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 526655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP 20 527655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_ABP 0x00000001 528655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_PCP 0x00000002 530655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_MRLSP 0x00000004 531655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_AIP 0x00000008 532655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_PIP 0x00000010 533655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_HPS 0x00000020 535655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_HPC 0x00000040 536655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_SPLV 0x00007f80 537655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_SPLS 0x00018000 538655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_EIP 0x00020000 540655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_NCCS 0x00040000 541655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_PSN 0xfff80000 542655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL 24 543655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_ABPE 0x0001 545655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PFDE 0x0002 546655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_MRLSCE 0x0004 547655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PDCE 0x0008 548655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_CCIE 0x0010 550655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_HPIE 0x0020 551655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_AIC 0x00c0 552655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PIC 0x0300 553655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PCC 0x0400 555655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_EIC 0x0800 556655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_DLLSCE 0x1000 557655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA 26 558655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_ABP 0x0001 560655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_PFD 0x0002 561655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_MRLSC 0x0004 562655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_PDC 0x0008 563655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_CC 0x0010 565655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_MRLSS 0x0020 566655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_PDS 0x0040 567655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_EIS 0x0080 568655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_DLLSC 0x0100 570655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTCTL 28 571655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTCTL_SECEE 0x01 572655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTCTL_SENFEE 0x02 573655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTCTL_SEFEE 0x04 575655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTCTL_PMEIE 0x08 576655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTCTL_CRSSVE 0x10 577655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTCAP 30 578655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTSTA 32 580655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTSTA_PME 0x10000 581655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTSTA_PENDING 0x20000 582655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP2 36 583655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP2_ARI 0x20 585655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP2_LTR 0x800 586655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_OBFF_MASK 0xc0000 587655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_OBFF_MSG 0x40000 588655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_OBFF_WAKE 0x80000 590655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL2 40 591655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL2_ARI 0x20 592655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_IDO_REQ_EN 0x100 593655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_IDO_CMP_EN 0x200 595655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LTR_EN 0x400 596655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_OBFF_MSGA_EN 0x2000 597655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_OBFF_MSGB_EN 0x4000 598655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_OBFF_WAKE_EN 0x6000 600655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 601655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP2 44 602655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 603655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 605655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 606655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP2_CROSSLINK 0x100 607655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL2 48 608655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA2 50 610655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL2 56 611655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 612655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 613655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 615655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_ERR 0x01 616655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_VC 0x02 617655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_DSN 0x03 618655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_PWR 0x04 620655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_RCLD 0x05 621655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_RCILC 0x06 622655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_RCEC 0x07 623655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_MFVC 0x08 625655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_VC9 0x09 626655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_RCRB 0x0A 627655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_VNDR 0x0B 628655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_CAC 0x0C 630655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_ACS 0x0D 631655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_ARI 0x0E 632655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_ATS 0x0F 633655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_SRIOV 0x10 635655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_MRIOV 0x11 636655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_MCAST 0x12 637655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_PRI 0x13 638655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_AMD_XXX 0x14 640655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_REBAR 0x15 641655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_DPA 0x16 642655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_TPH 0x17 643655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_LTR 0x18 645655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_SECPCI 0x19 646655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_PMUX 0x1A 647655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_PASID 0x1B 648655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID 650655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_DSN_SIZEOF 12 651655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 652655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNCOR_STATUS 4 653655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_TRAIN 0x00000001 655655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_DLP 0x00000010 656655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_SURPDN 0x00000020 657655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_POISON_TLP 0x00001000 658655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_FCP 0x00002000 660655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_COMP_TIME 0x00004000 661655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_COMP_ABORT 0x00008000 662655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_UNX_COMP 0x00010000 663655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_RX_OVER 0x00020000 665655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_MALF_TLP 0x00040000 666655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_ECRC 0x00080000 667655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_UNSUP 0x00100000 668655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_ACSV 0x00200000 670655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_INTN 0x00400000 671655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_MCBTLP 0x00800000 672655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_ATOMEG 0x01000000 673655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_TLPPRE 0x02000000 675655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNCOR_MASK 8 676655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNCOR_SEVER 12 677655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_STATUS 16 678655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_RCVR 0x00000001 680655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_BAD_TLP 0x00000040 681655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_BAD_DLLP 0x00000080 682655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_REP_ROLL 0x00000100 683655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_REP_TIMER 0x00001000 685655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_ADV_NFAT 0x00002000 686655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_INTERNAL 0x00004000 687655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_LOG_OVER 0x00008000 688655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_MASK 20 690655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP 24 691655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_FEP(x) ((x) & 31) 692655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_ECRC_GENC 0x00000020 693655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_ECRC_GENE 0x00000040 695655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 696655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 697655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_HEADER_LOG 28 698655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_COMMAND 44 700655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 701655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 702655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 703655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_STATUS 48 705655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_COR_RCV 0x00000001 706655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 707655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 708655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 710655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 711655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 712655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 713655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_ERR_SRC 52 715655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_PORT_REG1 4 716655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_REG1_EVCC 0x7 717655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_PORT_REG2 8 718655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_REG2_32_PHASE 0x2 720655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_REG2_64_PHASE 0x4 721655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_REG2_128_PHASE 0x8 722655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_PORT_CTRL 12 723655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_PORT_STATUS 14 725655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_RES_CAP 16 726655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_RES_CTRL 20 727655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_RES_STATUS 26 728655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_VC_BASE_SIZEOF 0x10 730655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C 731655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DSR 4 732655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA 8 733655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 735655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 736655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 737655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 738655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 740655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 741655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_CAP 12 742655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) 743655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_PWR_SIZEOF 16 745655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VNDR_HEADER 4 746655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) 747655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) 748655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) 750655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_3BIT_CAP_MASK 0xE0 751655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_SLAVE 0x00 752655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_HOST 0x20 753655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_5BIT_CAP_MASK 0xF8 755655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_IRQ 0x80 756655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_REMAPPING_40 0xA0 757655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_REMAPPING_64 0xA2 758655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_UNITID_CLUMP 0x90 760655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_EXTCONF 0x98 761655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_MSI_MAPPING 0xA8 762655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_FLAGS 0x02 763655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_FLAGS_ENABLE 0x1 765655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_FLAGS_FIXED 0x2 766655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL 767655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_ADDR_LO 0x04 768655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_ADDR_LO_MASK 0xFFF00000 770655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_ADDR_HI 0x08 771655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_DIRECT_ROUTE 0xB0 772655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_VCSET 0xB8 773655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_ERROR_RETRY 0xC0 775655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_GEN3 0xD0 776655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_PM 0xE0 777655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAP_SIZEOF_LONG 28 778655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAP_SIZEOF_SHORT 24 780655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CAP 0x04 781655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CAP_MFVC 0x0001 782655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CAP_ACS 0x0002 783655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) 785655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CTRL 0x06 786655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CTRL_MFVC 0x0001 787655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CTRL_ACS 0x0002 788655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 789655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) 790655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ARI_SIZEOF 8 791655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_CAP 0x04 792655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) 793655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 794655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_MAX_QDEP 32 795655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_CTRL 0x06 796655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_CTRL_ENABLE 0x8000 797655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) 798655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 799655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_MIN_STU 12 800655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ATS_SIZEOF 8 801655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_CTRL 0x04 802655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_CTRL_ENABLE 0x01 803655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 804655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_CTRL_RESET 0x02 805655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_STATUS 0x06 806655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_STATUS_RF 0x001 807655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_STATUS_UPRGI 0x002 808655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 809655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_STATUS_STOPPED 0x100 810655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_MAX_REQ 0x08 811655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_ALLOC_REQ 0x0c 812655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_PRI_SIZEOF 16 813655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 814655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CAP 0x04 815655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CAP_EXEC 0x02 816655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CAP_PRIV 0x04 817655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CTRL 0x06 818655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 819655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CTRL_ENABLE 0x01 820655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CTRL_EXEC 0x02 821655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CTRL_PRIV 0x04 822655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_PASID_SIZEOF 8 823655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 824655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CAP 0x04 825655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CAP_VFM 0x01 826655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) 827655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL 0x08 828655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 829655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL_VFE 0x01 830655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL_VFM 0x02 831655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL_INTR 0x04 832655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL_MSE 0x08 833655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 834655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL_ARI 0x10 835655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_STATUS 0x0a 836655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_STATUS_VFM 0x01 837655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_INITIAL_VF 0x0c 838655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 839655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_TOTAL_VF 0x0e 840655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_NUM_VF 0x10 841655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_FUNC_LINK 0x12 842655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VF_OFFSET 0x14 843655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 844655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VF_STRIDE 0x16 845655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VF_DID 0x1a 846655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_SUP_PGSIZE 0x1c 847655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_SYS_PGSIZE 0x20 848655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 849655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_BAR 0x24 850655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_NUM_BARS 6 851655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM 0x3c 852655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) 853655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 854655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) 855655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_UA 0x0 856655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_MI 0x1 857655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_MO 0x2 858655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 859655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_AV 0x3 860655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_SRIOV_SIZEOF 64 861655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LTR_MAX_SNOOP_LAT 0x4 862655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LTR_MAX_NOSNOOP_LAT 0x6 863655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 864655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LTR_VALUE_MASK 0x000003ff 865655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LTR_SCALE_MASK 0x00001c00 866655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LTR_SCALE_SHIFT 10 867655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_LTR_SIZEOF 8 868655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 869655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_CAP 0x04 870655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_SV 0x01 871655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_TB 0x02 872655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_RR 0x04 873655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 874655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_CR 0x08 875655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_UF 0x10 876655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_EC 0x20 877655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_DT 0x40 878655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 879655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_EGRESS_BITS 0x05 880655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_CTRL 0x06 881655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_EGRESS_CTL_V 0x08 882655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VSEC_HDR 4 883655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 884655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VSEC_HDR_LEN_SHIFT 20 885655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SATA_REGS 4 886655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SATA_REGS_MASK 0xF 887655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SATA_REGS_INLINE 0xF 888655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 889655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SATA_SIZEOF_SHORT 8 890655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SATA_SIZEOF_LONG 16 891655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_REBAR_CTRL 8 892655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) 893655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 894655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_REBAR_CTRL_NBAR_SHIFT 5 895655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_DPA_CAP 4 896655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F 897655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_DPA_BASE_SIZEOF 16 898655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 899655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_CAP 4 900655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_CAP_LOC_MASK 0x600 901655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_LOC_NONE 0x000 902655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_LOC_CAP 0x200 903655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 904655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_LOC_MSIX 0x400 905655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_CAP_ST_MASK 0x07FF0000 906655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_CAP_ST_SHIFT 16 907655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_BASE_SIZEOF 12 908655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 909655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#endif 910