pci_regs.h revision 934ec9495505d234b2c2fa284470c2f44aae9de9
1655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/**************************************************************************** 2655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng **************************************************************************** 3655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 4655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** This header was automatically generated from a Linux kernel header 5655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** of the same name, to make information necessary for userspace to 6655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** call into the kernel available to libc. It contains only constants, 7655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** structures, and macros generated from the original header, and thus, 8655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** contains no copyrightable information. 9655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 10655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** To edit the content of this header, modify the corresponding 11655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** source file (e.g. under external/kernel-headers/original/) then 12655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** run bionic/libc/kernel/tools/update_all.py 13655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 14655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** Any manual change here will be lost the next time this script will 15655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** be run. You've been warned! 16655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 17655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng **************************************************************************** 18655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ****************************************************************************/ 19655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#ifndef LINUX_PCI_REGS_H 20655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define LINUX_PCI_REGS_H 2148af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris#define PCI_CFG_SPACE_SIZE 256 2248af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0Christopher Ferris#define PCI_CFG_SPACE_EXP_SIZE 4096 23655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STD_HEADER_SIZEOF 64 24655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VENDOR_ID 0x00 25655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_DEVICE_ID 0x02 26655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND 0x04 27655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_IO 0x1 28655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_MEMORY 0x2 29655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_MASTER 0x4 30655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_SPECIAL 0x8 31655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_INVALIDATE 0x10 32655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_VGA_PALETTE 0x20 33655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_PARITY 0x40 34655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_WAIT 0x80 35655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_SERR 0x100 36655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_FAST_BACK 0x200 37655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_INTX_DISABLE 0x400 38655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS 0x06 39655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_INTERRUPT 0x08 40655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_CAP_LIST 0x10 41655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_66MHZ 0x20 42655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_UDF 0x40 43655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_FAST_BACK 0x80 44655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_PARITY 0x100 45655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_MASK 0x600 46655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_FAST 0x000 47655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_MEDIUM 0x200 48655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_SLOW 0x400 49655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_SIG_TARGET_ABORT 0x800 50655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_REC_TARGET_ABORT 0x1000 51655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_REC_MASTER_ABORT 0x2000 52655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 53655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DETECTED_PARITY 0x8000 54655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CLASS_REVISION 0x08 55655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_REVISION_ID 0x08 56655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CLASS_PROG 0x09 57655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CLASS_DEVICE 0x0a 58655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CACHE_LINE_SIZE 0x0c 59655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LATENCY_TIMER 0x0d 60655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE 0x0e 61655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE_NORMAL 0 62655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE_BRIDGE 1 63655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE_CARDBUS 2 64655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST 0x0f 65655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST_CODE_MASK 0x0f 66655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST_START 0x40 67655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST_CAPABLE 0x80 68655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_0 0x10 69655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_1 0x14 70655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_2 0x18 71655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_3 0x1c 72655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_4 0x20 73655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_5 0x24 74655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_SPACE 0x01 75655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_SPACE_IO 0x01 76655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 77655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 78655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 79655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 80655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 81655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 82655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 83655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 84655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CARDBUS_CIS 0x28 85655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 86655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SUBSYSTEM_ID 0x2e 87655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS 0x30 88655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS_ENABLE 0x01 89525ce914edf136d2bd02ac8c404d56c52e737f4dChristopher Ferris#define PCI_ROM_ADDRESS_MASK (~0x7ffU) 90655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAPABILITY_LIST 0x34 91655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_INTERRUPT_LINE 0x3c 92655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_INTERRUPT_PIN 0x3d 93655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MIN_GNT 0x3e 94655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MAX_LAT 0x3f 95655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRIMARY_BUS 0x18 96655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SECONDARY_BUS 0x19 97655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SUBORDINATE_BUS 0x1a 98655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SEC_LATENCY_TIMER 0x1b 99655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_BASE 0x1c 100655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_LIMIT 0x1d 101655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_TYPE_MASK 0x0fUL 102655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_TYPE_16 0x00 103655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_TYPE_32 0x01 104655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_MASK (~0x0fUL) 105655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_1K_RANGE_MASK (~0x03UL) 106655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SEC_STATUS 0x1e 107655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_BASE 0x20 108655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_LIMIT 0x22 109655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 110655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_RANGE_MASK (~0x0fUL) 111655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_MEMORY_BASE 0x24 112655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_MEMORY_LIMIT 0x26 113655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 114655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_TYPE_32 0x00 115655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_TYPE_64 0x01 116655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_MASK (~0x0fUL) 117655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_BASE_UPPER32 0x28 118655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_LIMIT_UPPER32 0x2c 119655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_BASE_UPPER16 0x30 120655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_LIMIT_UPPER16 0x32 121655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS1 0x38 122655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CONTROL 0x3e 123655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_PARITY 0x01 124655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_SERR 0x02 125655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_ISA 0x04 126655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_VGA 0x08 127655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 128655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_BUS_RESET 0x40 129655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_FAST_BACK 0x80 130655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_CAPABILITY_LIST 0x14 131655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SEC_STATUS 0x16 132655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_PRIMARY_BUS 0x18 133655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_CARD_BUS 0x19 134655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SUBORDINATE_BUS 0x1a 135655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_LATENCY_TIMER 0x1b 136655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_BASE_0 0x1c 137655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_LIMIT_0 0x20 138655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_BASE_1 0x24 139655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_LIMIT_1 0x28 140655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_0 0x2c 141655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_0_HI 0x2e 142655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_0 0x30 143655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_0_HI 0x32 144655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_1 0x34 145655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_1_HI 0x36 146655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_1 0x38 147655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_1_HI 0x3a 148655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_RANGE_MASK (~0x03UL) 149655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CONTROL 0x3e 150655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_PARITY 0x01 151655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_SERR 0x02 152655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_ISA 0x04 153655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_VGA 0x08 154655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 155655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 156655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 157655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 158655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 159655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 160655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 161655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SUBSYSTEM_ID 0x42 162655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_LEGACY_MODE_BASE 0x44 163655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_LIST_ID 0 164655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_PM 0x01 165655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_AGP 0x02 166655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_VPD 0x03 167655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SLOTID 0x04 168655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_MSI 0x05 169655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_CHSWP 0x06 170655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_PCIX 0x07 171655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_HT 0x08 172655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_VNDR 0x09 173655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_DBG 0x0A 174655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_CCRC 0x0B 175655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SHPC 0x0C 176655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SSVID 0x0D 177655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_AGP3 0x0E 178655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SECDEV 0x0F 179655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_EXP 0x10 180655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_MSIX 0x11 181655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SATA 0x12 182655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_AF 0x13 18305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_CAP_ID_EA 0x14 18405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_CAP_ID_MAX PCI_CAP_ID_EA 18505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_CAP_LIST_NEXT 1 186655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_FLAGS 2 187655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_SIZEOF 4 188655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_PMC 2 18905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CAP_VER_MASK 0x0007 190655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_CLOCK 0x0008 191655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_RESERVED 0x0010 192655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_DSI 0x0020 19305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CAP_AUX_POWER 0x01C0 194655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_D1 0x0200 195655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_D2 0x0400 196655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME 0x0800 19705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CAP_PME_MASK 0xF800 198655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D0 0x0800 199655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D1 0x1000 200655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D2 0x2000 20105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CAP_PME_D3 0x4000 202655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D3cold 0x8000 203655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_SHIFT 11 204655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL 4 20505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CTRL_STATE_MASK 0x0003 206655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 207655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_PME_ENABLE 0x0100 208655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 20905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 210655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_PME_STATUS 0x8000 211655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_PPB_EXTENSIONS 6 212655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_PPB_B2_B3 0x40 21305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_BPCC_ENABLE 0x80 214655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_DATA_REGISTER 7 215655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_SIZEOF 8 216655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_VERSION 2 21705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AGP_RFU 3 218655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS 4 219655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RQ_MASK 0xff000000 220655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_SBA 0x0200 22105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AGP_STATUS_64BIT 0x0020 222655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_FW 0x0010 223655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RATE4 0x0004 224655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RATE2 0x0002 22505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AGP_STATUS_RATE1 0x0001 226655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND 8 227655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 228655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_SBA 0x0200 22905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AGP_COMMAND_AGP 0x0100 230655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_64BIT 0x0020 231655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_FW 0x0010 232655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RATE4 0x0004 23305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AGP_COMMAND_RATE2 0x0002 234655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RATE1 0x0001 235655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_SIZEOF 12 236655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_ADDR 2 23705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_VPD_ADDR_MASK 0x7fff 238655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_ADDR_F 0x8000 239655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_DATA 4 240655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_VPD_SIZEOF 8 24105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_SID_ESR 2 242655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_ESR_NSLOTS 0x1f 243655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_ESR_FIC 0x20 244655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_CHASSIS_NR 3 24505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSI_FLAGS 2 246655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_ENABLE 0x0001 247655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_QMASK 0x000e 248655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_QSIZE 0x0070 24905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSI_FLAGS_64BIT 0x0080 250655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_MASKBIT 0x0100 251655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_RFU 3 252655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_ADDRESS_LO 4 25305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSI_ADDRESS_HI 8 254655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_DATA_32 8 255655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_MASK_32 12 256655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_PENDING_32 16 25705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSI_DATA_64 12 258655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_MASK_64 16 259655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_PENDING_64 20 260655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS 2 26105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSIX_FLAGS_QSIZE 0x07FF 262655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS_MASKALL 0x4000 263655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS_ENABLE 0x8000 264655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_TABLE 4 26505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSIX_TABLE_BIR 0x00000007 266655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_TABLE_OFFSET 0xfffffff8 267655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_PBA 8 268655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_PBA_BIR 0x00000007 26905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSIX_PBA_OFFSET 0xfffffff8 270915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR 271655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_MSIX_SIZEOF 12 272655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_SIZE 16 27305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSIX_ENTRY_LOWER_ADDR 0 274915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_MSIX_ENTRY_UPPER_ADDR 4 275655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_DATA 8 276655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 27705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 278915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_CHSWP_CSR 2 279655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_DHA 0x01 280655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_EIM 0x02 28105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_CHSWP_PIE 0x04 282915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_CHSWP_LOO 0x08 283655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_PI 0x30 284655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_EXT 0x40 28505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_CHSWP_INS 0x80 286915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_AF_LENGTH 2 287655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CAP 3 288655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CAP_TP 0x01 28905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AF_CAP_FLR 0x02 290915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_AF_CTRL 4 291655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CTRL_FLR 0x01 292655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_STATUS 5 29305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AF_STATUS_TP 0x01 294915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_CAP_AF_SIZEOF 6 29505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_NUM_ENT 2 29605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_NUM_ENT_MASK 0x3f 29705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_FIRST_ENT 4 29805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_FIRST_ENT_BRIDGE 8 29905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_ES 0x00000007 30005d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI 0x000000f0 30105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_BAR0 0 30205d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_BAR5 5 30305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_BRIDGE 6 30405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_ENI 7 30505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_ROM 8 30605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_VF_BAR0 9 30705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_VF_BAR5 14 30805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_RESERVED 15 30905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_PP 0x0000ff00 31005d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_SP 0x00ff0000 31105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_MEM 0x00 31205d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_MEM_PREFETCH 0x01 31305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_IO 0x02 31405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_VF_MEM_PREFETCH 0x03 31505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_VF_MEM 0x04 31605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_BRIDGE_MEM 0x05 31705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_BRIDGE_MEM_PREFETCH 0x06 31805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_BRIDGE_IO 0x07 31905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_MEM_RESERVED 0xfd 32005d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_IO_RESERVED 0xfe 32105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_UNAVAILABLE 0xff 32205d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_WRITABLE 0x40000000 32305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_ENABLE 0x80000000 32405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BASE 4 32505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_MAX_OFFSET 8 32605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_IS_64 0x00000002 32705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_FIELD_MASK 0xfffffffc 328655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD 2 329655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_DPERR_E 0x0001 330655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_ERO 0x0002 331915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_CMD_READ_512 0x0000 332655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_1K 0x0004 333655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_2K 0x0008 334655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_4K 0x000c 335915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_CMD_MAX_READ 0x000c 336655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_1 0x0000 337655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_2 0x0010 338655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_3 0x0020 339915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_CMD_SPLIT_4 0x0030 340655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_8 0x0040 341655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_12 0x0050 342655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_16 0x0060 343915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_CMD_SPLIT_32 0x0070 344655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_MAX_SPLIT 0x0070 345655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) 346655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS 4 347915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_STATUS_DEVFN 0x000000ff 348655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_BUS 0x0000ff00 349655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_64BIT 0x00010000 350655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_133MHZ 0x00020000 351915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_STATUS_SPL_DISC 0x00040000 352655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_UNX_SPL 0x00080000 353655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_COMPLEX 0x00100000 354655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_MAX_READ 0x00600000 355915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_STATUS_MAX_SPLIT 0x03800000 356655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_MAX_CUM 0x1c000000 357655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_SPL_ERR 0x20000000 358655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_266MHZ 0x40000000 359915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_STATUS_533MHZ 0x80000000 360655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_ECC_CSR 8 361655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_PCIX_SIZEOF_V0 8 362655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_PCIX_SIZEOF_V1 24 363915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 364655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_BRIDGE_SSTATUS 2 365655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_64BIT 0x0001 366655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_133MHZ 0x0002 367915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_SSTATUS_FREQ 0x03c0 368655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_VERS 0x3000 369655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_V1 0x1000 370655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_V2 0x2000 371915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_SSTATUS_266MHZ 0x4000 372655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_533MHZ 0x8000 373655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_BRIDGE_STATUS 4 374655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SSVID_VENDOR_ID 4 375915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SSVID_DEVICE_ID 6 376655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS 2 377655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_VERS 0x000f 378655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_TYPE 0x00f0 379915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_TYPE_ENDPOINT 0x0 380655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_LEG_END 0x1 381655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_ROOT_PORT 0x4 382655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_UPSTREAM 0x5 383915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_TYPE_DOWNSTREAM 0x6 384655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 385655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 386655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_RC_END 0x9 387915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_TYPE_RC_EC 0xa 388655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_SLOT 0x0100 389655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_IRQ 0x3e00 390655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP 4 391915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 39238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 39338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_EXT_TAG 0x00000020 39438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_L0S 0x000001c0 395915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCAP_L1 0x00000e00 39638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_ATN_BUT 0x00001000 39738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_ATN_IND 0x00002000 39838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PWR_IND 0x00004000 399915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCAP_RBER 0x00008000 40038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 40138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 402655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_FLR 0x10000000 403915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL 8 404655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_CERE 0x0001 405655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_NFERE 0x0002 406655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_FERE 0x0004 407915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL_URRE 0x0008 408655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 409655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 410655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 411915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL_PHANTOM 0x0200 412655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_AUX_PME 0x0400 413655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 414655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_READRQ 0x7000 41505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EXP_DEVCTL_READRQ_128B 0x0000 41605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 41705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 41805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 419915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 42038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA 10 42138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_CED 0x0001 42238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_NFED 0x0002 423915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVSTA_FED 0x0004 42438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_URD 0x0008 42538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_AUXPD 0x0010 42638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_TRPND 0x0020 4271308ad3ab33294c3abfd96da12b6df58b381ce52Christopher Ferris#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 12 428915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCAP 12 42938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP_SLS 0x0000000f 43038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 43138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 4321308ad3ab33294c3abfd96da12b6df58b381ce52Christopher Ferris#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 433915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCAP_MLW 0x000003f0 434655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 435655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_L0SEL 0x00007000 436655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_L1EL 0x00038000 437915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCAP_CLKPM 0x00040000 438655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_SDERC 0x00080000 439655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 440655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_LBNC 0x00200000 441915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCAP_PN 0xff000000 442655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL 16 443655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_ASPMC 0x0003 44438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 445915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCTL_ASPM_L1 0x0002 446655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_RCB 0x0008 447655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_LD 0x0010 448655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_RL 0x0020 449915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCTL_CCC 0x0040 450655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_ES 0x0080 45138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 452655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_HAWD 0x0200 453915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCTL_LBMIE 0x0400 454655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_LABIE 0x0800 455655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA 18 456655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_CLS 0x000f 457915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 45838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 45938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 460655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_NLW 0x03f0 461915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKSTA_NLW_X1 0x0010 46238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_NLW_X2 0x0020 46338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_NLW_X4 0x0040 46438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_NLW_X8 0x0080 465915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKSTA_NLW_SHIFT 4 466655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_LT 0x0800 467655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_SLC 0x1000 468655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_DLLLA 0x2000 469915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKSTA_LBMS 0x4000 470655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_LABS 0x8000 471655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 472655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP 20 473915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCAP_ABP 0x00000001 474655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_PCP 0x00000002 475655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_MRLSP 0x00000004 476655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_AIP 0x00000008 477915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCAP_PIP 0x00000010 478655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_HPS 0x00000020 479655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_HPC 0x00000040 480655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_SPLV 0x00007f80 481915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCAP_SPLS 0x00018000 482655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_EIP 0x00020000 483655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_NCCS 0x00040000 484655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_PSN 0xfff80000 485915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCTL 24 486655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_ABPE 0x0001 487655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PFDE 0x0002 488655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_MRLSCE 0x0004 489915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCTL_PDCE 0x0008 490655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_CCIE 0x0010 491655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_HPIE 0x0020 492655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_AIC 0x00c0 493915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 49438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 49538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 496655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PIC 0x0300 497915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 49838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 49938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 500655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PCC 0x0400 501915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCTL_PWR_ON 0x0000 50238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_PWR_OFF 0x0400 503655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_EIC 0x0800 504655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_DLLSCE 0x1000 505915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTSTA 26 506655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_ABP 0x0001 507655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_PFD 0x0002 508655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_MRLSC 0x0004 509915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTSTA_PDC 0x0008 510655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_CC 0x0010 511655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_MRLSS 0x0020 512655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_PDS 0x0040 513915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTSTA_EIS 0x0080 514655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_DLLSC 0x0100 515655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTCTL 28 51638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_SECEE 0x0001 517915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_RTCTL_SENFEE 0x0002 51838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_SEFEE 0x0004 51938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_PMEIE 0x0008 52038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_CRSSVE 0x0010 521915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_RTCAP 30 52282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_RTCAP_CRSVIS 0x0001 523655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTSTA 32 52438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTSTA_PME 0x00010000 525915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_RTSTA_PENDING 0x00020000 52682d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_DEVCAP2 36 52738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP2_ARI 0x00000020 5286a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 5296a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 53038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP2_LTR 0x00000800 531915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 53282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 53338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 534655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL2 40 535915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f 53682d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_DEVCTL2_ARI 0x0020 5376a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 538525ce914edf136d2bd02ac8c404d56c52e737f4dChristopher Ferris#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 53938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 54038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 541915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 54282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 54338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 54438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 545915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVSTA2 42 5461308ad3ab33294c3abfd96da12b6df58b381ce52Christopher Ferris#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44 547655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP2 44 54838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 549915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 55082d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 55138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 552655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL2 48 553915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKSTA2 50 5541308ad3ab33294c3abfd96da12b6df58b381ce52Christopher Ferris#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 55582d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_SLTCAP2 52 556655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL2 56 55738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTSTA2 58 558915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 55982d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 560655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 561655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_ERR 0x01 562915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_VC 0x02 56382d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_DSN 0x03 564655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_PWR 0x04 565655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_RCLD 0x05 566915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_RCILC 0x06 56782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_RCEC 0x07 568655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_MFVC 0x08 569655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_VC9 0x09 570915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_RCRB 0x0A 57182d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_VNDR 0x0B 572655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_CAC 0x0C 573655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_ACS 0x0D 574915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_ARI 0x0E 57582d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_ATS 0x0F 576655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_SRIOV 0x10 577655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_MRIOV 0x11 578915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_MCAST 0x12 57982d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_PRI 0x13 580655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_AMD_XXX 0x14 581655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_REBAR 0x15 582915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_DPA 0x16 58382d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_TPH 0x17 584655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_LTR 0x18 585655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_SECPCI 0x19 586915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_PMUX 0x1A 58782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_PASID 0x1B 588106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXT_CAP_ID_DPC 0x1D 589525ce914edf136d2bd02ac8c404d56c52e737f4dChristopher Ferris#define PCI_EXT_CAP_ID_L1SS 0x1E 5906a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_EXT_CAP_ID_PTM 0x1F 5916a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM 592655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_DSN_SIZEOF 12 593915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 594106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_UNCOR_STATUS 4 59582d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_UNC_UND 0x00000001 596655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_DLP 0x00000010 597915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_UNC_SURPDN 0x00000020 598106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_UNC_POISON_TLP 0x00001000 599655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_FCP 0x00002000 600655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_COMP_TIME 0x00004000 601915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_UNC_COMP_ABORT 0x00008000 602106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_UNC_UNX_COMP 0x00010000 603655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_RX_OVER 0x00020000 604655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_MALF_TLP 0x00040000 605915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_UNC_ECRC 0x00080000 606106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_UNC_UNSUP 0x00100000 607655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_ACSV 0x00200000 608655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_INTN 0x00400000 609915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_UNC_MCBTLP 0x00800000 610106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_UNC_ATOMEG 0x01000000 611655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_TLPPRE 0x02000000 612655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNCOR_MASK 8 613915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_UNCOR_SEVER 12 614106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_COR_STATUS 16 615655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_RCVR 0x00000001 616655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_BAD_TLP 0x00000040 617915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_COR_BAD_DLLP 0x00000080 618106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_COR_REP_ROLL 0x00000100 619655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_REP_TIMER 0x00001000 620655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_ADV_NFAT 0x00002000 621915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_COR_INTERNAL 0x00004000 622106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_COR_LOG_OVER 0x00008000 623655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_MASK 20 624655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP 24 625915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_CAP_FEP(x) ((x) & 31) 626106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_CAP_ECRC_GENC 0x00000020 627655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_ECRC_GENE 0x00000040 628655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 629915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 630106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_HEADER_LOG 28 631655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_COMMAND 44 632655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 633915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 634106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 635655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_STATUS 48 636655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_COR_RCV 0x00000001 637915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 638106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 639655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 640655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 641915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 642106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 643934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 644655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_ERR_SRC 52 64538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_PORT_CAP1 4 646915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_CAP1_EVCC 0x00000007 647106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VC_CAP1_LPEVCC 0x00000070 64838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP1_ARB_SIZE 0x00000c00 64938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_PORT_CAP2 8 650915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_CAP2_32_PHASE 0x00000002 651106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VC_CAP2_64_PHASE 0x00000004 65238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP2_128_PHASE 0x00000008 65338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP2_ARB_OFF 0xff000000 654915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_PORT_CTRL 12 655106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 656655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_PORT_STATUS 14 65738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_PORT_STATUS_TABLE 0x00000001 658915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_RES_CAP 16 659106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VC_RES_CAP_32_PHASE 0x00000002 66038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CAP_64_PHASE 0x00000004 66138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CAP_128_PHASE 0x00000008 662915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 663106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VC_RES_CAP_256_PHASE 0x00000020 66438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CAP_ARB_OFF 0xff000000 665655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_RES_CTRL 20 666915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 667106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 66838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CTRL_ID 0x07000000 66938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CTRL_ENABLE 0x80000000 670915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_RES_STATUS 26 671106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VC_RES_STATUS_TABLE 0x00000001 67238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_STATUS_NEGO 0x00000002 673655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_VC_BASE_SIZEOF 0x10 674915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C 675106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PWR_DSR 4 67638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PWR_DATA 8 677655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 678915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 679106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 68038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 681655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 682915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 683106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PWR_CAP 12 68438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) 685655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_PWR_SIZEOF 16 686915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VNDR_HEADER 4 687106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) 68838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) 689655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) 690915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_3BIT_CAP_MASK 0xE0 691106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define HT_CAPTYPE_SLAVE 0x00 69238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAPTYPE_HOST 0x20 693655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_5BIT_CAP_MASK 0xF8 694915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_CAPTYPE_IRQ 0x80 695106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define HT_CAPTYPE_REMAPPING_40 0xA0 69638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAPTYPE_REMAPPING_64 0xA2 697655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_UNITID_CLUMP 0x90 698915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_CAPTYPE_EXTCONF 0x98 699106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define HT_CAPTYPE_MSI_MAPPING 0xA8 70038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_MSI_FLAGS 0x02 701655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_FLAGS_ENABLE 0x1 702915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_MSI_FLAGS_FIXED 0x2 703106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL 70438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_MSI_ADDR_LO 0x04 705655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_ADDR_LO_MASK 0xFFF00000 706915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_MSI_ADDR_HI 0x08 707106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define HT_CAPTYPE_DIRECT_ROUTE 0xB0 70838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAPTYPE_VCSET 0xB8 709655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_ERROR_RETRY 0xC0 710915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_CAPTYPE_GEN3 0xD0 711106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define HT_CAPTYPE_PM 0xE0 71238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAP_SIZEOF_LONG 28 713655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAP_SIZEOF_SHORT 24 714915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ARI_CAP 0x04 715106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ARI_CAP_MFVC 0x0001 71638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ARI_CAP_ACS 0x0002 717655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) 718915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ARI_CTRL 0x06 719106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ARI_CTRL_MFVC 0x0001 72038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ARI_CTRL_ACS 0x0002 721655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) 722915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ARI_SIZEOF 8 723106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ATS_CAP 0x04 72438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) 725655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_MAX_QDEP 32 726915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ATS_CTRL 0x06 727106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ATS_CTRL_ENABLE 0x8000 72838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) 729655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_MIN_STU 12 730915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ATS_SIZEOF 8 731106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PRI_CTRL 0x04 73238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PRI_CTRL_ENABLE 0x01 733655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_CTRL_RESET 0x02 734915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PRI_STATUS 0x06 735106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PRI_STATUS_RF 0x001 73638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PRI_STATUS_UPRGI 0x002 737655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_STATUS_STOPPED 0x100 738915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PRI_MAX_REQ 0x08 739106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PRI_ALLOC_REQ 0x0c 74038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXT_CAP_PRI_SIZEOF 16 741655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CAP 0x04 742915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PASID_CAP_EXEC 0x02 743106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PASID_CAP_PRIV 0x04 74438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PASID_CTRL 0x06 745655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CTRL_ENABLE 0x01 746915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PASID_CTRL_EXEC 0x02 747106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_PASID_CTRL_PRIV 0x04 74838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXT_CAP_PASID_SIZEOF 8 749655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CAP 0x04 750915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_CAP_VFM 0x01 751106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) 75238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_CTRL 0x08 753655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL_VFE 0x01 754915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_CTRL_VFM 0x02 755106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SRIOV_CTRL_INTR 0x04 75638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_CTRL_MSE 0x08 757655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL_ARI 0x10 758915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_STATUS 0x0a 759106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SRIOV_STATUS_VFM 0x01 76038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_INITIAL_VF 0x0c 761655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_TOTAL_VF 0x0e 762915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_NUM_VF 0x10 763106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SRIOV_FUNC_LINK 0x12 76438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_VF_OFFSET 0x14 765655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VF_STRIDE 0x16 766915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_VF_DID 0x1a 767106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SRIOV_SUP_PGSIZE 0x1c 76838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_SYS_PGSIZE 0x20 769655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_BAR 0x24 770915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_NUM_BARS 6 771106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SRIOV_VFM 0x3c 77238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) 773655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) 774915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_VFM_UA 0x0 775106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SRIOV_VFM_MI 0x1 77638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_VFM_MO 0x2 777655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_AV 0x3 778915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_SRIOV_SIZEOF 64 779106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_LTR_MAX_SNOOP_LAT 0x4 78038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_LTR_MAX_NOSNOOP_LAT 0x6 781655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LTR_VALUE_MASK 0x000003ff 782915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_LTR_SCALE_MASK 0x00001c00 783106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_LTR_SCALE_SHIFT 10 78438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXT_CAP_LTR_SIZEOF 8 785655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_CAP 0x04 786915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ACS_SV 0x01 787106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ACS_TB 0x02 78838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ACS_RR 0x04 789655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_CR 0x08 790915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ACS_UF 0x10 791106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ACS_EC 0x20 79238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ACS_DT 0x40 793655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_EGRESS_BITS 0x05 794915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ACS_CTRL 0x06 795106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_ACS_EGRESS_CTL_V 0x08 79638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VSEC_HDR 4 797655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VSEC_HDR_LEN_SHIFT 20 798915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SATA_REGS 4 799106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_SATA_REGS_MASK 0xF 80038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SATA_REGS_INLINE 0xF 801655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SATA_SIZEOF_SHORT 8 802915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SATA_SIZEOF_LONG 16 803934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_REBAR_CAP 4 804934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_REBAR_CAP_SIZES 0x00FFFFF0 805106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_REBAR_CTRL 8 806934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_REBAR_CTRL_BAR_IDX 0x00000007 807934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 808655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_REBAR_CTRL_NBAR_SHIFT 5 809934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_REBAR_CTRL_BAR_SIZE 0x00001F00 810915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_DPA_CAP 4 811106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F 81238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_DPA_BASE_SIZEOF 16 813655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_CAP 4 814915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_TPH_CAP_LOC_MASK 0x600 815106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_TPH_LOC_NONE 0x000 81638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_TPH_LOC_CAP 0x200 817655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_LOC_MSIX 0x400 818915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_TPH_CAP_ST_MASK 0x07FF0000 819106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_TPH_CAP_ST_SHIFT 16 82038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_TPH_BASE_SIZEOF 12 821106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CAP 4 822934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_EXP_DPC_IRQ 0x1f 823106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CAP_RP_EXT 0x20 824106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 825106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 8261308ad3ab33294c3abfd96da12b6df58b381ce52Christopher Ferris#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0xF00 827106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 828106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CTL 6 829106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x02 830106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_CTL_INT_EN 0x08 831106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_STATUS 8 832106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_STATUS_TRIGGER 0x01 833106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_STATUS_INTERRUPT 0x08 834525ce914edf136d2bd02ac8c404d56c52e737f4dChristopher Ferris#define PCI_EXP_DPC_RP_BUSY 0x10 835106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#define PCI_EXP_DPC_SOURCE_ID 10 8361308ad3ab33294c3abfd96da12b6df58b381ce52Christopher Ferris#define PCI_EXP_DPC_RP_PIO_STATUS 0x0C 8371308ad3ab33294c3abfd96da12b6df58b381ce52Christopher Ferris#define PCI_EXP_DPC_RP_PIO_MASK 0x10 8381308ad3ab33294c3abfd96da12b6df58b381ce52Christopher Ferris#define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 8391308ad3ab33294c3abfd96da12b6df58b381ce52Christopher Ferris#define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 8401308ad3ab33294c3abfd96da12b6df58b381ce52Christopher Ferris#define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C 8411308ad3ab33294c3abfd96da12b6df58b381ce52Christopher Ferris#define PCI_EXP_DPC_RP_PIO_HEADER_LOG 0x20 8421308ad3ab33294c3abfd96da12b6df58b381ce52Christopher Ferris#define PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG 0x30 8431308ad3ab33294c3abfd96da12b6df58b381ce52Christopher Ferris#define PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG 0x34 8446a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_PTM_CAP 0x04 8456a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_PTM_CAP_REQ 0x00000001 8466a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_PTM_CAP_ROOT 0x00000004 8476a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_PTM_GRANULARITY_MASK 0x0000FF00 8486a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_PTM_CTRL 0x08 8496a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_PTM_CTRL_ENABLE 0x00000001 8506a9755d20a995756487bb1aafb7e954f4fd868a7Christopher Ferris#define PCI_PTM_CTRL_ROOT 0x00000002 851934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CAP 0x04 852934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 853934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 854934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CAP_ASPM_L1_2 0x00000004 855934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CAP_ASPM_L1_1 0x00000008 856934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CAP_L1_PM_SS 0x00000010 857934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CAP_CM_RESTORE_TIME 0x0000ff00 858934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CAP_P_PWR_ON_SCALE 0x00030000 859934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CAP_P_PWR_ON_VALUE 0x00f80000 860934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CTL1 0x08 861934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 862934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 863934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CTL1_ASPM_L1_2 0x00000004 864934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CTL1_ASPM_L1_1 0x00000008 865934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CTL1_L1SS_MASK 0x0000000f 866934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CTL1_CM_RESTORE_TIME 0x0000ff00 867934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 868934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 869934ec9495505d234b2c2fa284470c2f44aae9de9Christopher Ferris#define PCI_L1SS_CTL2 0x0c 870655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#endif 871