pci_regs.h revision 106b3a8a7dc03c19a45e322de425ac56aafac358
1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef LINUX_PCI_REGS_H 20#define LINUX_PCI_REGS_H 21#define PCI_STD_HEADER_SIZEOF 64 22#define PCI_VENDOR_ID 0x00 23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24#define PCI_DEVICE_ID 0x02 25#define PCI_COMMAND 0x04 26#define PCI_COMMAND_IO 0x1 27#define PCI_COMMAND_MEMORY 0x2 28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29#define PCI_COMMAND_MASTER 0x4 30#define PCI_COMMAND_SPECIAL 0x8 31#define PCI_COMMAND_INVALIDATE 0x10 32#define PCI_COMMAND_VGA_PALETTE 0x20 33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34#define PCI_COMMAND_PARITY 0x40 35#define PCI_COMMAND_WAIT 0x80 36#define PCI_COMMAND_SERR 0x100 37#define PCI_COMMAND_FAST_BACK 0x200 38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39#define PCI_COMMAND_INTX_DISABLE 0x400 40#define PCI_STATUS 0x06 41#define PCI_STATUS_INTERRUPT 0x08 42#define PCI_STATUS_CAP_LIST 0x10 43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44#define PCI_STATUS_66MHZ 0x20 45#define PCI_STATUS_UDF 0x40 46#define PCI_STATUS_FAST_BACK 0x80 47#define PCI_STATUS_PARITY 0x100 48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49#define PCI_STATUS_DEVSEL_MASK 0x600 50#define PCI_STATUS_DEVSEL_FAST 0x000 51#define PCI_STATUS_DEVSEL_MEDIUM 0x200 52#define PCI_STATUS_DEVSEL_SLOW 0x400 53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54#define PCI_STATUS_SIG_TARGET_ABORT 0x800 55#define PCI_STATUS_REC_TARGET_ABORT 0x1000 56#define PCI_STATUS_REC_MASTER_ABORT 0x2000 57#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59#define PCI_STATUS_DETECTED_PARITY 0x8000 60#define PCI_CLASS_REVISION 0x08 61#define PCI_REVISION_ID 0x08 62#define PCI_CLASS_PROG 0x09 63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64#define PCI_CLASS_DEVICE 0x0a 65#define PCI_CACHE_LINE_SIZE 0x0c 66#define PCI_LATENCY_TIMER 0x0d 67#define PCI_HEADER_TYPE 0x0e 68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69#define PCI_HEADER_TYPE_NORMAL 0 70#define PCI_HEADER_TYPE_BRIDGE 1 71#define PCI_HEADER_TYPE_CARDBUS 2 72#define PCI_BIST 0x0f 73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74#define PCI_BIST_CODE_MASK 0x0f 75#define PCI_BIST_START 0x40 76#define PCI_BIST_CAPABLE 0x80 77#define PCI_BASE_ADDRESS_0 0x10 78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79#define PCI_BASE_ADDRESS_1 0x14 80#define PCI_BASE_ADDRESS_2 0x18 81#define PCI_BASE_ADDRESS_3 0x1c 82#define PCI_BASE_ADDRESS_4 0x20 83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84#define PCI_BASE_ADDRESS_5 0x24 85#define PCI_BASE_ADDRESS_SPACE 0x01 86#define PCI_BASE_ADDRESS_SPACE_IO 0x01 87#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 90#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 91#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 92#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 95#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 96#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 97#define PCI_CARDBUS_CIS 0x28 98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 100#define PCI_SUBSYSTEM_ID 0x2e 101#define PCI_ROM_ADDRESS 0x30 102#define PCI_ROM_ADDRESS_ENABLE 0x01 103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 105#define PCI_CAPABILITY_LIST 0x34 106#define PCI_INTERRUPT_LINE 0x3c 107#define PCI_INTERRUPT_PIN 0x3d 108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109#define PCI_MIN_GNT 0x3e 110#define PCI_MAX_LAT 0x3f 111#define PCI_PRIMARY_BUS 0x18 112#define PCI_SECONDARY_BUS 0x19 113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114#define PCI_SUBORDINATE_BUS 0x1a 115#define PCI_SEC_LATENCY_TIMER 0x1b 116#define PCI_IO_BASE 0x1c 117#define PCI_IO_LIMIT 0x1d 118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119#define PCI_IO_RANGE_TYPE_MASK 0x0fUL 120#define PCI_IO_RANGE_TYPE_16 0x00 121#define PCI_IO_RANGE_TYPE_32 0x01 122#define PCI_IO_RANGE_MASK (~0x0fUL) 123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124#define PCI_IO_1K_RANGE_MASK (~0x03UL) 125#define PCI_SEC_STATUS 0x1e 126#define PCI_MEMORY_BASE 0x20 127#define PCI_MEMORY_LIMIT 0x22 128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 130#define PCI_MEMORY_RANGE_MASK (~0x0fUL) 131#define PCI_PREF_MEMORY_BASE 0x24 132#define PCI_PREF_MEMORY_LIMIT 0x26 133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 135#define PCI_PREF_RANGE_TYPE_32 0x00 136#define PCI_PREF_RANGE_TYPE_64 0x01 137#define PCI_PREF_RANGE_MASK (~0x0fUL) 138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139#define PCI_PREF_BASE_UPPER32 0x28 140#define PCI_PREF_LIMIT_UPPER32 0x2c 141#define PCI_IO_BASE_UPPER16 0x30 142#define PCI_IO_LIMIT_UPPER16 0x32 143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144#define PCI_ROM_ADDRESS1 0x38 145#define PCI_BRIDGE_CONTROL 0x3e 146#define PCI_BRIDGE_CTL_PARITY 0x01 147#define PCI_BRIDGE_CTL_SERR 0x02 148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149#define PCI_BRIDGE_CTL_ISA 0x04 150#define PCI_BRIDGE_CTL_VGA 0x08 151#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 152#define PCI_BRIDGE_CTL_BUS_RESET 0x40 153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154#define PCI_BRIDGE_CTL_FAST_BACK 0x80 155#define PCI_CB_CAPABILITY_LIST 0x14 156#define PCI_CB_SEC_STATUS 0x16 157#define PCI_CB_PRIMARY_BUS 0x18 158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159#define PCI_CB_CARD_BUS 0x19 160#define PCI_CB_SUBORDINATE_BUS 0x1a 161#define PCI_CB_LATENCY_TIMER 0x1b 162#define PCI_CB_MEMORY_BASE_0 0x1c 163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164#define PCI_CB_MEMORY_LIMIT_0 0x20 165#define PCI_CB_MEMORY_BASE_1 0x24 166#define PCI_CB_MEMORY_LIMIT_1 0x28 167#define PCI_CB_IO_BASE_0 0x2c 168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169#define PCI_CB_IO_BASE_0_HI 0x2e 170#define PCI_CB_IO_LIMIT_0 0x30 171#define PCI_CB_IO_LIMIT_0_HI 0x32 172#define PCI_CB_IO_BASE_1 0x34 173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174#define PCI_CB_IO_BASE_1_HI 0x36 175#define PCI_CB_IO_LIMIT_1 0x38 176#define PCI_CB_IO_LIMIT_1_HI 0x3a 177#define PCI_CB_IO_RANGE_MASK (~0x03UL) 178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179#define PCI_CB_BRIDGE_CONTROL 0x3e 180#define PCI_CB_BRIDGE_CTL_PARITY 0x01 181#define PCI_CB_BRIDGE_CTL_SERR 0x02 182#define PCI_CB_BRIDGE_CTL_ISA 0x04 183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184#define PCI_CB_BRIDGE_CTL_VGA 0x08 185#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 186#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 187#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 190#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 191#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 192#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194#define PCI_CB_SUBSYSTEM_ID 0x42 195#define PCI_CB_LEGACY_MODE_BASE 0x44 196#define PCI_CAP_LIST_ID 0 197#define PCI_CAP_ID_PM 0x01 198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199#define PCI_CAP_ID_AGP 0x02 200#define PCI_CAP_ID_VPD 0x03 201#define PCI_CAP_ID_SLOTID 0x04 202#define PCI_CAP_ID_MSI 0x05 203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204#define PCI_CAP_ID_CHSWP 0x06 205#define PCI_CAP_ID_PCIX 0x07 206#define PCI_CAP_ID_HT 0x08 207#define PCI_CAP_ID_VNDR 0x09 208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209#define PCI_CAP_ID_DBG 0x0A 210#define PCI_CAP_ID_CCRC 0x0B 211#define PCI_CAP_ID_SHPC 0x0C 212#define PCI_CAP_ID_SSVID 0x0D 213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214#define PCI_CAP_ID_AGP3 0x0E 215#define PCI_CAP_ID_SECDEV 0x0F 216#define PCI_CAP_ID_EXP 0x10 217#define PCI_CAP_ID_MSIX 0x11 218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219#define PCI_CAP_ID_SATA 0x12 220#define PCI_CAP_ID_AF 0x13 221#define PCI_CAP_ID_EA 0x14 222#define PCI_CAP_ID_MAX PCI_CAP_ID_EA 223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224#define PCI_CAP_LIST_NEXT 1 225#define PCI_CAP_FLAGS 2 226#define PCI_CAP_SIZEOF 4 227#define PCI_PM_PMC 2 228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229#define PCI_PM_CAP_VER_MASK 0x0007 230#define PCI_PM_CAP_PME_CLOCK 0x0008 231#define PCI_PM_CAP_RESERVED 0x0010 232#define PCI_PM_CAP_DSI 0x0020 233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234#define PCI_PM_CAP_AUX_POWER 0x01C0 235#define PCI_PM_CAP_D1 0x0200 236#define PCI_PM_CAP_D2 0x0400 237#define PCI_PM_CAP_PME 0x0800 238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239#define PCI_PM_CAP_PME_MASK 0xF800 240#define PCI_PM_CAP_PME_D0 0x0800 241#define PCI_PM_CAP_PME_D1 0x1000 242#define PCI_PM_CAP_PME_D2 0x2000 243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244#define PCI_PM_CAP_PME_D3 0x4000 245#define PCI_PM_CAP_PME_D3cold 0x8000 246#define PCI_PM_CAP_PME_SHIFT 11 247#define PCI_PM_CTRL 4 248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249#define PCI_PM_CTRL_STATE_MASK 0x0003 250#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 251#define PCI_PM_CTRL_PME_ENABLE 0x0100 252#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 255#define PCI_PM_CTRL_PME_STATUS 0x8000 256#define PCI_PM_PPB_EXTENSIONS 6 257#define PCI_PM_PPB_B2_B3 0x40 258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259#define PCI_PM_BPCC_ENABLE 0x80 260#define PCI_PM_DATA_REGISTER 7 261#define PCI_PM_SIZEOF 8 262#define PCI_AGP_VERSION 2 263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264#define PCI_AGP_RFU 3 265#define PCI_AGP_STATUS 4 266#define PCI_AGP_STATUS_RQ_MASK 0xff000000 267#define PCI_AGP_STATUS_SBA 0x0200 268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269#define PCI_AGP_STATUS_64BIT 0x0020 270#define PCI_AGP_STATUS_FW 0x0010 271#define PCI_AGP_STATUS_RATE4 0x0004 272#define PCI_AGP_STATUS_RATE2 0x0002 273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274#define PCI_AGP_STATUS_RATE1 0x0001 275#define PCI_AGP_COMMAND 8 276#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 277#define PCI_AGP_COMMAND_SBA 0x0200 278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279#define PCI_AGP_COMMAND_AGP 0x0100 280#define PCI_AGP_COMMAND_64BIT 0x0020 281#define PCI_AGP_COMMAND_FW 0x0010 282#define PCI_AGP_COMMAND_RATE4 0x0004 283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284#define PCI_AGP_COMMAND_RATE2 0x0002 285#define PCI_AGP_COMMAND_RATE1 0x0001 286#define PCI_AGP_SIZEOF 12 287#define PCI_VPD_ADDR 2 288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289#define PCI_VPD_ADDR_MASK 0x7fff 290#define PCI_VPD_ADDR_F 0x8000 291#define PCI_VPD_DATA 4 292#define PCI_CAP_VPD_SIZEOF 8 293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294#define PCI_SID_ESR 2 295#define PCI_SID_ESR_NSLOTS 0x1f 296#define PCI_SID_ESR_FIC 0x20 297#define PCI_SID_CHASSIS_NR 3 298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299#define PCI_MSI_FLAGS 2 300#define PCI_MSI_FLAGS_ENABLE 0x0001 301#define PCI_MSI_FLAGS_QMASK 0x000e 302#define PCI_MSI_FLAGS_QSIZE 0x0070 303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304#define PCI_MSI_FLAGS_64BIT 0x0080 305#define PCI_MSI_FLAGS_MASKBIT 0x0100 306#define PCI_MSI_RFU 3 307#define PCI_MSI_ADDRESS_LO 4 308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309#define PCI_MSI_ADDRESS_HI 8 310#define PCI_MSI_DATA_32 8 311#define PCI_MSI_MASK_32 12 312#define PCI_MSI_PENDING_32 16 313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314#define PCI_MSI_DATA_64 12 315#define PCI_MSI_MASK_64 16 316#define PCI_MSI_PENDING_64 20 317#define PCI_MSIX_FLAGS 2 318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319#define PCI_MSIX_FLAGS_QSIZE 0x07FF 320#define PCI_MSIX_FLAGS_MASKALL 0x4000 321#define PCI_MSIX_FLAGS_ENABLE 0x8000 322#define PCI_MSIX_TABLE 4 323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324#define PCI_MSIX_TABLE_BIR 0x00000007 325#define PCI_MSIX_TABLE_OFFSET 0xfffffff8 326#define PCI_MSIX_PBA 8 327#define PCI_MSIX_PBA_BIR 0x00000007 328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329#define PCI_MSIX_PBA_OFFSET 0xfffffff8 330#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR 331#define PCI_CAP_MSIX_SIZEOF 12 332#define PCI_MSIX_ENTRY_SIZE 16 333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334#define PCI_MSIX_ENTRY_LOWER_ADDR 0 335#define PCI_MSIX_ENTRY_UPPER_ADDR 4 336#define PCI_MSIX_ENTRY_DATA 8 337#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 340#define PCI_CHSWP_CSR 2 341#define PCI_CHSWP_DHA 0x01 342#define PCI_CHSWP_EIM 0x02 343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344#define PCI_CHSWP_PIE 0x04 345#define PCI_CHSWP_LOO 0x08 346#define PCI_CHSWP_PI 0x30 347#define PCI_CHSWP_EXT 0x40 348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349#define PCI_CHSWP_INS 0x80 350#define PCI_AF_LENGTH 2 351#define PCI_AF_CAP 3 352#define PCI_AF_CAP_TP 0x01 353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354#define PCI_AF_CAP_FLR 0x02 355#define PCI_AF_CTRL 4 356#define PCI_AF_CTRL_FLR 0x01 357#define PCI_AF_STATUS 5 358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359#define PCI_AF_STATUS_TP 0x01 360#define PCI_CAP_AF_SIZEOF 6 361#define PCI_EA_NUM_ENT 2 362#define PCI_EA_NUM_ENT_MASK 0x3f 363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364#define PCI_EA_FIRST_ENT 4 365#define PCI_EA_FIRST_ENT_BRIDGE 8 366#define PCI_EA_ES 0x00000007 367#define PCI_EA_BEI 0x000000f0 368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369#define PCI_EA_BEI_BAR0 0 370#define PCI_EA_BEI_BAR5 5 371#define PCI_EA_BEI_BRIDGE 6 372#define PCI_EA_BEI_ENI 7 373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374#define PCI_EA_BEI_ROM 8 375#define PCI_EA_BEI_VF_BAR0 9 376#define PCI_EA_BEI_VF_BAR5 14 377#define PCI_EA_BEI_RESERVED 15 378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379#define PCI_EA_PP 0x0000ff00 380#define PCI_EA_SP 0x00ff0000 381#define PCI_EA_P_MEM 0x00 382#define PCI_EA_P_MEM_PREFETCH 0x01 383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384#define PCI_EA_P_IO 0x02 385#define PCI_EA_P_VF_MEM_PREFETCH 0x03 386#define PCI_EA_P_VF_MEM 0x04 387#define PCI_EA_P_BRIDGE_MEM 0x05 388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389#define PCI_EA_P_BRIDGE_MEM_PREFETCH 0x06 390#define PCI_EA_P_BRIDGE_IO 0x07 391#define PCI_EA_P_MEM_RESERVED 0xfd 392#define PCI_EA_P_IO_RESERVED 0xfe 393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394#define PCI_EA_P_UNAVAILABLE 0xff 395#define PCI_EA_WRITABLE 0x40000000 396#define PCI_EA_ENABLE 0x80000000 397#define PCI_EA_BASE 4 398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399#define PCI_EA_MAX_OFFSET 8 400#define PCI_EA_IS_64 0x00000002 401#define PCI_EA_FIELD_MASK 0xfffffffc 402#define PCI_X_CMD 2 403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404#define PCI_X_CMD_DPERR_E 0x0001 405#define PCI_X_CMD_ERO 0x0002 406#define PCI_X_CMD_READ_512 0x0000 407#define PCI_X_CMD_READ_1K 0x0004 408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409#define PCI_X_CMD_READ_2K 0x0008 410#define PCI_X_CMD_READ_4K 0x000c 411#define PCI_X_CMD_MAX_READ 0x000c 412#define PCI_X_CMD_SPLIT_1 0x0000 413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414#define PCI_X_CMD_SPLIT_2 0x0010 415#define PCI_X_CMD_SPLIT_3 0x0020 416#define PCI_X_CMD_SPLIT_4 0x0030 417#define PCI_X_CMD_SPLIT_8 0x0040 418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419#define PCI_X_CMD_SPLIT_12 0x0050 420#define PCI_X_CMD_SPLIT_16 0x0060 421#define PCI_X_CMD_SPLIT_32 0x0070 422#define PCI_X_CMD_MAX_SPLIT 0x0070 423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) 425#define PCI_X_STATUS 4 426#define PCI_X_STATUS_DEVFN 0x000000ff 427#define PCI_X_STATUS_BUS 0x0000ff00 428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429#define PCI_X_STATUS_64BIT 0x00010000 430#define PCI_X_STATUS_133MHZ 0x00020000 431#define PCI_X_STATUS_SPL_DISC 0x00040000 432#define PCI_X_STATUS_UNX_SPL 0x00080000 433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434#define PCI_X_STATUS_COMPLEX 0x00100000 435#define PCI_X_STATUS_MAX_READ 0x00600000 436#define PCI_X_STATUS_MAX_SPLIT 0x03800000 437#define PCI_X_STATUS_MAX_CUM 0x1c000000 438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439#define PCI_X_STATUS_SPL_ERR 0x20000000 440#define PCI_X_STATUS_266MHZ 0x40000000 441#define PCI_X_STATUS_533MHZ 0x80000000 442#define PCI_X_ECC_CSR 8 443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444#define PCI_CAP_PCIX_SIZEOF_V0 8 445#define PCI_CAP_PCIX_SIZEOF_V1 24 446#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 447#define PCI_X_BRIDGE_SSTATUS 2 448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449#define PCI_X_SSTATUS_64BIT 0x0001 450#define PCI_X_SSTATUS_133MHZ 0x0002 451#define PCI_X_SSTATUS_FREQ 0x03c0 452#define PCI_X_SSTATUS_VERS 0x3000 453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454#define PCI_X_SSTATUS_V1 0x1000 455#define PCI_X_SSTATUS_V2 0x2000 456#define PCI_X_SSTATUS_266MHZ 0x4000 457#define PCI_X_SSTATUS_533MHZ 0x8000 458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459#define PCI_X_BRIDGE_STATUS 4 460#define PCI_SSVID_VENDOR_ID 4 461#define PCI_SSVID_DEVICE_ID 6 462#define PCI_EXP_FLAGS 2 463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464#define PCI_EXP_FLAGS_VERS 0x000f 465#define PCI_EXP_FLAGS_TYPE 0x00f0 466#define PCI_EXP_TYPE_ENDPOINT 0x0 467#define PCI_EXP_TYPE_LEG_END 0x1 468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469#define PCI_EXP_TYPE_ROOT_PORT 0x4 470#define PCI_EXP_TYPE_UPSTREAM 0x5 471#define PCI_EXP_TYPE_DOWNSTREAM 0x6 472#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 475#define PCI_EXP_TYPE_RC_END 0x9 476#define PCI_EXP_TYPE_RC_EC 0xa 477#define PCI_EXP_FLAGS_SLOT 0x0100 478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479#define PCI_EXP_FLAGS_IRQ 0x3e00 480#define PCI_EXP_DEVCAP 4 481#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 482#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484#define PCI_EXP_DEVCAP_EXT_TAG 0x00000020 485#define PCI_EXP_DEVCAP_L0S 0x000001c0 486#define PCI_EXP_DEVCAP_L1 0x00000e00 487#define PCI_EXP_DEVCAP_ATN_BUT 0x00001000 488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489#define PCI_EXP_DEVCAP_ATN_IND 0x00002000 490#define PCI_EXP_DEVCAP_PWR_IND 0x00004000 491#define PCI_EXP_DEVCAP_RBER 0x00008000 492#define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494#define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 495#define PCI_EXP_DEVCAP_FLR 0x10000000 496#define PCI_EXP_DEVCTL 8 497#define PCI_EXP_DEVCTL_CERE 0x0001 498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499#define PCI_EXP_DEVCTL_NFERE 0x0002 500#define PCI_EXP_DEVCTL_FERE 0x0004 501#define PCI_EXP_DEVCTL_URRE 0x0008 502#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 505#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 506#define PCI_EXP_DEVCTL_PHANTOM 0x0200 507#define PCI_EXP_DEVCTL_AUX_PME 0x0400 508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 510#define PCI_EXP_DEVCTL_READRQ 0x7000 511#define PCI_EXP_DEVCTL_READRQ_128B 0x0000 512#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 515#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 516#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 517#define PCI_EXP_DEVSTA 10 518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519#define PCI_EXP_DEVSTA_CED 0x0001 520#define PCI_EXP_DEVSTA_NFED 0x0002 521#define PCI_EXP_DEVSTA_FED 0x0004 522#define PCI_EXP_DEVSTA_URD 0x0008 523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524#define PCI_EXP_DEVSTA_AUXPD 0x0010 525#define PCI_EXP_DEVSTA_TRPND 0x0020 526#define PCI_EXP_LNKCAP 12 527#define PCI_EXP_LNKCAP_SLS 0x0000000f 528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 530#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 531#define PCI_EXP_LNKCAP_MLW 0x000003f0 532#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534#define PCI_EXP_LNKCAP_L0SEL 0x00007000 535#define PCI_EXP_LNKCAP_L1EL 0x00038000 536#define PCI_EXP_LNKCAP_CLKPM 0x00040000 537#define PCI_EXP_LNKCAP_SDERC 0x00080000 538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 540#define PCI_EXP_LNKCAP_LBNC 0x00200000 541#define PCI_EXP_LNKCAP_PN 0xff000000 542#define PCI_EXP_LNKCTL 16 543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544#define PCI_EXP_LNKCTL_ASPMC 0x0003 545#define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 546#define PCI_EXP_LNKCTL_ASPM_L1 0x0002 547#define PCI_EXP_LNKCTL_RCB 0x0008 548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549#define PCI_EXP_LNKCTL_LD 0x0010 550#define PCI_EXP_LNKCTL_RL 0x0020 551#define PCI_EXP_LNKCTL_CCC 0x0040 552#define PCI_EXP_LNKCTL_ES 0x0080 553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554#define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 555#define PCI_EXP_LNKCTL_HAWD 0x0200 556#define PCI_EXP_LNKCTL_LBMIE 0x0400 557#define PCI_EXP_LNKCTL_LABIE 0x0800 558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559#define PCI_EXP_LNKSTA 18 560#define PCI_EXP_LNKSTA_CLS 0x000f 561#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 562#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 565#define PCI_EXP_LNKSTA_NLW 0x03f0 566#define PCI_EXP_LNKSTA_NLW_X1 0x0010 567#define PCI_EXP_LNKSTA_NLW_X2 0x0020 568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569#define PCI_EXP_LNKSTA_NLW_X4 0x0040 570#define PCI_EXP_LNKSTA_NLW_X8 0x0080 571#define PCI_EXP_LNKSTA_NLW_SHIFT 4 572#define PCI_EXP_LNKSTA_LT 0x0800 573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574#define PCI_EXP_LNKSTA_SLC 0x1000 575#define PCI_EXP_LNKSTA_DLLLA 0x2000 576#define PCI_EXP_LNKSTA_LBMS 0x4000 577#define PCI_EXP_LNKSTA_LABS 0x8000 578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 580#define PCI_EXP_SLTCAP 20 581#define PCI_EXP_SLTCAP_ABP 0x00000001 582#define PCI_EXP_SLTCAP_PCP 0x00000002 583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584#define PCI_EXP_SLTCAP_MRLSP 0x00000004 585#define PCI_EXP_SLTCAP_AIP 0x00000008 586#define PCI_EXP_SLTCAP_PIP 0x00000010 587#define PCI_EXP_SLTCAP_HPS 0x00000020 588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589#define PCI_EXP_SLTCAP_HPC 0x00000040 590#define PCI_EXP_SLTCAP_SPLV 0x00007f80 591#define PCI_EXP_SLTCAP_SPLS 0x00018000 592#define PCI_EXP_SLTCAP_EIP 0x00020000 593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594#define PCI_EXP_SLTCAP_NCCS 0x00040000 595#define PCI_EXP_SLTCAP_PSN 0xfff80000 596#define PCI_EXP_SLTCTL 24 597#define PCI_EXP_SLTCTL_ABPE 0x0001 598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599#define PCI_EXP_SLTCTL_PFDE 0x0002 600#define PCI_EXP_SLTCTL_MRLSCE 0x0004 601#define PCI_EXP_SLTCTL_PDCE 0x0008 602#define PCI_EXP_SLTCTL_CCIE 0x0010 603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604#define PCI_EXP_SLTCTL_HPIE 0x0020 605#define PCI_EXP_SLTCTL_AIC 0x00c0 606#define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 607#define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609#define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 610#define PCI_EXP_SLTCTL_PIC 0x0300 611#define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 612#define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614#define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 615#define PCI_EXP_SLTCTL_PCC 0x0400 616#define PCI_EXP_SLTCTL_PWR_ON 0x0000 617#define PCI_EXP_SLTCTL_PWR_OFF 0x0400 618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619#define PCI_EXP_SLTCTL_EIC 0x0800 620#define PCI_EXP_SLTCTL_DLLSCE 0x1000 621#define PCI_EXP_SLTSTA 26 622#define PCI_EXP_SLTSTA_ABP 0x0001 623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624#define PCI_EXP_SLTSTA_PFD 0x0002 625#define PCI_EXP_SLTSTA_MRLSC 0x0004 626#define PCI_EXP_SLTSTA_PDC 0x0008 627#define PCI_EXP_SLTSTA_CC 0x0010 628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629#define PCI_EXP_SLTSTA_MRLSS 0x0020 630#define PCI_EXP_SLTSTA_PDS 0x0040 631#define PCI_EXP_SLTSTA_EIS 0x0080 632#define PCI_EXP_SLTSTA_DLLSC 0x0100 633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634#define PCI_EXP_RTCTL 28 635#define PCI_EXP_RTCTL_SECEE 0x0001 636#define PCI_EXP_RTCTL_SENFEE 0x0002 637#define PCI_EXP_RTCTL_SEFEE 0x0004 638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639#define PCI_EXP_RTCTL_PMEIE 0x0008 640#define PCI_EXP_RTCTL_CRSSVE 0x0010 641#define PCI_EXP_RTCAP 30 642#define PCI_EXP_RTCAP_CRSVIS 0x0001 643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644#define PCI_EXP_RTSTA 32 645#define PCI_EXP_RTSTA_PME 0x00010000 646#define PCI_EXP_RTSTA_PENDING 0x00020000 647#define PCI_EXP_DEVCAP2 36 648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649#define PCI_EXP_DEVCAP2_ARI 0x00000020 650#define PCI_EXP_DEVCAP2_LTR 0x00000800 651#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 652#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 655#define PCI_EXP_DEVCTL2 40 656#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f 657#define PCI_EXP_DEVCTL2_ARI 0x0020 658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 660#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 661#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 662#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 665#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 666#define PCI_EXP_DEVSTA2 42 667#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669#define PCI_EXP_LNKCAP2 44 670#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 671#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 672#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 675#define PCI_EXP_LNKCTL2 48 676#define PCI_EXP_LNKSTA2 50 677#define PCI_EXP_SLTCAP2 52 678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679#define PCI_EXP_SLTCTL2 56 680#define PCI_EXP_SLTSTA2 58 681#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 682#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 685#define PCI_EXT_CAP_ID_ERR 0x01 686#define PCI_EXT_CAP_ID_VC 0x02 687#define PCI_EXT_CAP_ID_DSN 0x03 688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689#define PCI_EXT_CAP_ID_PWR 0x04 690#define PCI_EXT_CAP_ID_RCLD 0x05 691#define PCI_EXT_CAP_ID_RCILC 0x06 692#define PCI_EXT_CAP_ID_RCEC 0x07 693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694#define PCI_EXT_CAP_ID_MFVC 0x08 695#define PCI_EXT_CAP_ID_VC9 0x09 696#define PCI_EXT_CAP_ID_RCRB 0x0A 697#define PCI_EXT_CAP_ID_VNDR 0x0B 698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699#define PCI_EXT_CAP_ID_CAC 0x0C 700#define PCI_EXT_CAP_ID_ACS 0x0D 701#define PCI_EXT_CAP_ID_ARI 0x0E 702#define PCI_EXT_CAP_ID_ATS 0x0F 703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704#define PCI_EXT_CAP_ID_SRIOV 0x10 705#define PCI_EXT_CAP_ID_MRIOV 0x11 706#define PCI_EXT_CAP_ID_MCAST 0x12 707#define PCI_EXT_CAP_ID_PRI 0x13 708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709#define PCI_EXT_CAP_ID_AMD_XXX 0x14 710#define PCI_EXT_CAP_ID_REBAR 0x15 711#define PCI_EXT_CAP_ID_DPA 0x16 712#define PCI_EXT_CAP_ID_TPH 0x17 713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714#define PCI_EXT_CAP_ID_LTR 0x18 715#define PCI_EXT_CAP_ID_SECPCI 0x19 716#define PCI_EXT_CAP_ID_PMUX 0x1A 717#define PCI_EXT_CAP_ID_PASID 0x1B 718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719#define PCI_EXT_CAP_ID_DPC 0x1D 720#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DPC 721#define PCI_EXT_CAP_DSN_SIZEOF 12 722#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 723/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724#define PCI_ERR_UNCOR_STATUS 4 725#define PCI_ERR_UNC_UND 0x00000001 726#define PCI_ERR_UNC_DLP 0x00000010 727#define PCI_ERR_UNC_SURPDN 0x00000020 728/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729#define PCI_ERR_UNC_POISON_TLP 0x00001000 730#define PCI_ERR_UNC_FCP 0x00002000 731#define PCI_ERR_UNC_COMP_TIME 0x00004000 732#define PCI_ERR_UNC_COMP_ABORT 0x00008000 733/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734#define PCI_ERR_UNC_UNX_COMP 0x00010000 735#define PCI_ERR_UNC_RX_OVER 0x00020000 736#define PCI_ERR_UNC_MALF_TLP 0x00040000 737#define PCI_ERR_UNC_ECRC 0x00080000 738/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739#define PCI_ERR_UNC_UNSUP 0x00100000 740#define PCI_ERR_UNC_ACSV 0x00200000 741#define PCI_ERR_UNC_INTN 0x00400000 742#define PCI_ERR_UNC_MCBTLP 0x00800000 743/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744#define PCI_ERR_UNC_ATOMEG 0x01000000 745#define PCI_ERR_UNC_TLPPRE 0x02000000 746#define PCI_ERR_UNCOR_MASK 8 747#define PCI_ERR_UNCOR_SEVER 12 748/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749#define PCI_ERR_COR_STATUS 16 750#define PCI_ERR_COR_RCVR 0x00000001 751#define PCI_ERR_COR_BAD_TLP 0x00000040 752#define PCI_ERR_COR_BAD_DLLP 0x00000080 753/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754#define PCI_ERR_COR_REP_ROLL 0x00000100 755#define PCI_ERR_COR_REP_TIMER 0x00001000 756#define PCI_ERR_COR_ADV_NFAT 0x00002000 757#define PCI_ERR_COR_INTERNAL 0x00004000 758/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759#define PCI_ERR_COR_LOG_OVER 0x00008000 760#define PCI_ERR_COR_MASK 20 761#define PCI_ERR_CAP 24 762#define PCI_ERR_CAP_FEP(x) ((x) & 31) 763/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764#define PCI_ERR_CAP_ECRC_GENC 0x00000020 765#define PCI_ERR_CAP_ECRC_GENE 0x00000040 766#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 767#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 768/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769#define PCI_ERR_HEADER_LOG 28 770#define PCI_ERR_ROOT_COMMAND 44 771#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 772#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 773/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 775#define PCI_ERR_ROOT_STATUS 48 776#define PCI_ERR_ROOT_COR_RCV 0x00000001 777#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 778/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 780#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 781#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 782#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 783/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 785#define PCI_ERR_ROOT_ERR_SRC 52 786#define PCI_VC_PORT_CAP1 4 787#define PCI_VC_CAP1_EVCC 0x00000007 788/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 789#define PCI_VC_CAP1_LPEVCC 0x00000070 790#define PCI_VC_CAP1_ARB_SIZE 0x00000c00 791#define PCI_VC_PORT_CAP2 8 792#define PCI_VC_CAP2_32_PHASE 0x00000002 793/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 794#define PCI_VC_CAP2_64_PHASE 0x00000004 795#define PCI_VC_CAP2_128_PHASE 0x00000008 796#define PCI_VC_CAP2_ARB_OFF 0xff000000 797#define PCI_VC_PORT_CTRL 12 798/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 799#define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 800#define PCI_VC_PORT_STATUS 14 801#define PCI_VC_PORT_STATUS_TABLE 0x00000001 802#define PCI_VC_RES_CAP 16 803/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 804#define PCI_VC_RES_CAP_32_PHASE 0x00000002 805#define PCI_VC_RES_CAP_64_PHASE 0x00000004 806#define PCI_VC_RES_CAP_128_PHASE 0x00000008 807#define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 808/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 809#define PCI_VC_RES_CAP_256_PHASE 0x00000020 810#define PCI_VC_RES_CAP_ARB_OFF 0xff000000 811#define PCI_VC_RES_CTRL 20 812#define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 813/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 814#define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 815#define PCI_VC_RES_CTRL_ID 0x07000000 816#define PCI_VC_RES_CTRL_ENABLE 0x80000000 817#define PCI_VC_RES_STATUS 26 818/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 819#define PCI_VC_RES_STATUS_TABLE 0x00000001 820#define PCI_VC_RES_STATUS_NEGO 0x00000002 821#define PCI_CAP_VC_BASE_SIZEOF 0x10 822#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C 823/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 824#define PCI_PWR_DSR 4 825#define PCI_PWR_DATA 8 826#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 827#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 828/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 829#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 830#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 831#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 832#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 833/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 834#define PCI_PWR_CAP 12 835#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) 836#define PCI_EXT_CAP_PWR_SIZEOF 16 837#define PCI_VNDR_HEADER 4 838/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 839#define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) 840#define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) 841#define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) 842#define HT_3BIT_CAP_MASK 0xE0 843/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 844#define HT_CAPTYPE_SLAVE 0x00 845#define HT_CAPTYPE_HOST 0x20 846#define HT_5BIT_CAP_MASK 0xF8 847#define HT_CAPTYPE_IRQ 0x80 848/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 849#define HT_CAPTYPE_REMAPPING_40 0xA0 850#define HT_CAPTYPE_REMAPPING_64 0xA2 851#define HT_CAPTYPE_UNITID_CLUMP 0x90 852#define HT_CAPTYPE_EXTCONF 0x98 853/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 854#define HT_CAPTYPE_MSI_MAPPING 0xA8 855#define HT_MSI_FLAGS 0x02 856#define HT_MSI_FLAGS_ENABLE 0x1 857#define HT_MSI_FLAGS_FIXED 0x2 858/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 859#define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL 860#define HT_MSI_ADDR_LO 0x04 861#define HT_MSI_ADDR_LO_MASK 0xFFF00000 862#define HT_MSI_ADDR_HI 0x08 863/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 864#define HT_CAPTYPE_DIRECT_ROUTE 0xB0 865#define HT_CAPTYPE_VCSET 0xB8 866#define HT_CAPTYPE_ERROR_RETRY 0xC0 867#define HT_CAPTYPE_GEN3 0xD0 868/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 869#define HT_CAPTYPE_PM 0xE0 870#define HT_CAP_SIZEOF_LONG 28 871#define HT_CAP_SIZEOF_SHORT 24 872#define PCI_ARI_CAP 0x04 873/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 874#define PCI_ARI_CAP_MFVC 0x0001 875#define PCI_ARI_CAP_ACS 0x0002 876#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) 877#define PCI_ARI_CTRL 0x06 878/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 879#define PCI_ARI_CTRL_MFVC 0x0001 880#define PCI_ARI_CTRL_ACS 0x0002 881#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) 882#define PCI_EXT_CAP_ARI_SIZEOF 8 883/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 884#define PCI_ATS_CAP 0x04 885#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) 886#define PCI_ATS_MAX_QDEP 32 887#define PCI_ATS_CTRL 0x06 888/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 889#define PCI_ATS_CTRL_ENABLE 0x8000 890#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) 891#define PCI_ATS_MIN_STU 12 892#define PCI_EXT_CAP_ATS_SIZEOF 8 893/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 894#define PCI_PRI_CTRL 0x04 895#define PCI_PRI_CTRL_ENABLE 0x01 896#define PCI_PRI_CTRL_RESET 0x02 897#define PCI_PRI_STATUS 0x06 898/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 899#define PCI_PRI_STATUS_RF 0x001 900#define PCI_PRI_STATUS_UPRGI 0x002 901#define PCI_PRI_STATUS_STOPPED 0x100 902#define PCI_PRI_MAX_REQ 0x08 903/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 904#define PCI_PRI_ALLOC_REQ 0x0c 905#define PCI_EXT_CAP_PRI_SIZEOF 16 906#define PCI_PASID_CAP 0x04 907#define PCI_PASID_CAP_EXEC 0x02 908/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 909#define PCI_PASID_CAP_PRIV 0x04 910#define PCI_PASID_CTRL 0x06 911#define PCI_PASID_CTRL_ENABLE 0x01 912#define PCI_PASID_CTRL_EXEC 0x02 913/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 914#define PCI_PASID_CTRL_PRIV 0x04 915#define PCI_EXT_CAP_PASID_SIZEOF 8 916#define PCI_SRIOV_CAP 0x04 917#define PCI_SRIOV_CAP_VFM 0x01 918/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 919#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) 920#define PCI_SRIOV_CTRL 0x08 921#define PCI_SRIOV_CTRL_VFE 0x01 922#define PCI_SRIOV_CTRL_VFM 0x02 923/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 924#define PCI_SRIOV_CTRL_INTR 0x04 925#define PCI_SRIOV_CTRL_MSE 0x08 926#define PCI_SRIOV_CTRL_ARI 0x10 927#define PCI_SRIOV_STATUS 0x0a 928/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 929#define PCI_SRIOV_STATUS_VFM 0x01 930#define PCI_SRIOV_INITIAL_VF 0x0c 931#define PCI_SRIOV_TOTAL_VF 0x0e 932#define PCI_SRIOV_NUM_VF 0x10 933/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 934#define PCI_SRIOV_FUNC_LINK 0x12 935#define PCI_SRIOV_VF_OFFSET 0x14 936#define PCI_SRIOV_VF_STRIDE 0x16 937#define PCI_SRIOV_VF_DID 0x1a 938/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 939#define PCI_SRIOV_SUP_PGSIZE 0x1c 940#define PCI_SRIOV_SYS_PGSIZE 0x20 941#define PCI_SRIOV_BAR 0x24 942#define PCI_SRIOV_NUM_BARS 6 943/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 944#define PCI_SRIOV_VFM 0x3c 945#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) 946#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) 947#define PCI_SRIOV_VFM_UA 0x0 948/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 949#define PCI_SRIOV_VFM_MI 0x1 950#define PCI_SRIOV_VFM_MO 0x2 951#define PCI_SRIOV_VFM_AV 0x3 952#define PCI_EXT_CAP_SRIOV_SIZEOF 64 953/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 954#define PCI_LTR_MAX_SNOOP_LAT 0x4 955#define PCI_LTR_MAX_NOSNOOP_LAT 0x6 956#define PCI_LTR_VALUE_MASK 0x000003ff 957#define PCI_LTR_SCALE_MASK 0x00001c00 958/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 959#define PCI_LTR_SCALE_SHIFT 10 960#define PCI_EXT_CAP_LTR_SIZEOF 8 961#define PCI_ACS_CAP 0x04 962#define PCI_ACS_SV 0x01 963/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 964#define PCI_ACS_TB 0x02 965#define PCI_ACS_RR 0x04 966#define PCI_ACS_CR 0x08 967#define PCI_ACS_UF 0x10 968/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 969#define PCI_ACS_EC 0x20 970#define PCI_ACS_DT 0x40 971#define PCI_ACS_EGRESS_BITS 0x05 972#define PCI_ACS_CTRL 0x06 973/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 974#define PCI_ACS_EGRESS_CTL_V 0x08 975#define PCI_VSEC_HDR 4 976#define PCI_VSEC_HDR_LEN_SHIFT 20 977#define PCI_SATA_REGS 4 978/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 979#define PCI_SATA_REGS_MASK 0xF 980#define PCI_SATA_REGS_INLINE 0xF 981#define PCI_SATA_SIZEOF_SHORT 8 982#define PCI_SATA_SIZEOF_LONG 16 983/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 984#define PCI_REBAR_CTRL 8 985#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) 986#define PCI_REBAR_CTRL_NBAR_SHIFT 5 987#define PCI_DPA_CAP 4 988/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 989#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F 990#define PCI_DPA_BASE_SIZEOF 16 991#define PCI_TPH_CAP 4 992#define PCI_TPH_CAP_LOC_MASK 0x600 993/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 994#define PCI_TPH_LOC_NONE 0x000 995#define PCI_TPH_LOC_CAP 0x200 996#define PCI_TPH_LOC_MSIX 0x400 997#define PCI_TPH_CAP_ST_MASK 0x07FF0000 998/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 999#define PCI_TPH_CAP_ST_SHIFT 16 1000#define PCI_TPH_BASE_SIZEOF 12 1001#define PCI_EXP_DPC_CAP 4 1002#define PCI_EXP_DPC_CAP_RP_EXT 0x20 1003/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1004#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 1005#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 1006#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 1007#define PCI_EXP_DPC_CTL 6 1008/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1009#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x02 1010#define PCI_EXP_DPC_CTL_INT_EN 0x08 1011#define PCI_EXP_DPC_STATUS 8 1012#define PCI_EXP_DPC_STATUS_TRIGGER 0x01 1013/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1014#define PCI_EXP_DPC_STATUS_INTERRUPT 0x08 1015#define PCI_EXP_DPC_SOURCE_ID 10 1016#endif 1017