pci_regs.h revision 96c1db7b9d601c31d103389cac074a6cce0d7633
1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef LINUX_PCI_REGS_H 20#define LINUX_PCI_REGS_H 21#define PCI_CFG_SPACE_SIZE 256 22#define PCI_CFG_SPACE_EXP_SIZE 4096 23#define PCI_STD_HEADER_SIZEOF 64 24#define PCI_VENDOR_ID 0x00 25#define PCI_DEVICE_ID 0x02 26#define PCI_COMMAND 0x04 27#define PCI_COMMAND_IO 0x1 28#define PCI_COMMAND_MEMORY 0x2 29#define PCI_COMMAND_MASTER 0x4 30#define PCI_COMMAND_SPECIAL 0x8 31#define PCI_COMMAND_INVALIDATE 0x10 32#define PCI_COMMAND_VGA_PALETTE 0x20 33#define PCI_COMMAND_PARITY 0x40 34#define PCI_COMMAND_WAIT 0x80 35#define PCI_COMMAND_SERR 0x100 36#define PCI_COMMAND_FAST_BACK 0x200 37#define PCI_COMMAND_INTX_DISABLE 0x400 38#define PCI_STATUS 0x06 39#define PCI_STATUS_INTERRUPT 0x08 40#define PCI_STATUS_CAP_LIST 0x10 41#define PCI_STATUS_66MHZ 0x20 42#define PCI_STATUS_UDF 0x40 43#define PCI_STATUS_FAST_BACK 0x80 44#define PCI_STATUS_PARITY 0x100 45#define PCI_STATUS_DEVSEL_MASK 0x600 46#define PCI_STATUS_DEVSEL_FAST 0x000 47#define PCI_STATUS_DEVSEL_MEDIUM 0x200 48#define PCI_STATUS_DEVSEL_SLOW 0x400 49#define PCI_STATUS_SIG_TARGET_ABORT 0x800 50#define PCI_STATUS_REC_TARGET_ABORT 0x1000 51#define PCI_STATUS_REC_MASTER_ABORT 0x2000 52#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 53#define PCI_STATUS_DETECTED_PARITY 0x8000 54#define PCI_CLASS_REVISION 0x08 55#define PCI_REVISION_ID 0x08 56#define PCI_CLASS_PROG 0x09 57#define PCI_CLASS_DEVICE 0x0a 58#define PCI_CACHE_LINE_SIZE 0x0c 59#define PCI_LATENCY_TIMER 0x0d 60#define PCI_HEADER_TYPE 0x0e 61#define PCI_HEADER_TYPE_NORMAL 0 62#define PCI_HEADER_TYPE_BRIDGE 1 63#define PCI_HEADER_TYPE_CARDBUS 2 64#define PCI_BIST 0x0f 65#define PCI_BIST_CODE_MASK 0x0f 66#define PCI_BIST_START 0x40 67#define PCI_BIST_CAPABLE 0x80 68#define PCI_BASE_ADDRESS_0 0x10 69#define PCI_BASE_ADDRESS_1 0x14 70#define PCI_BASE_ADDRESS_2 0x18 71#define PCI_BASE_ADDRESS_3 0x1c 72#define PCI_BASE_ADDRESS_4 0x20 73#define PCI_BASE_ADDRESS_5 0x24 74#define PCI_BASE_ADDRESS_SPACE 0x01 75#define PCI_BASE_ADDRESS_SPACE_IO 0x01 76#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 77#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 78#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 79#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 80#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 81#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 82#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 83#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 84#define PCI_CARDBUS_CIS 0x28 85#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 86#define PCI_SUBSYSTEM_ID 0x2e 87#define PCI_ROM_ADDRESS 0x30 88#define PCI_ROM_ADDRESS_ENABLE 0x01 89#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 90#define PCI_CAPABILITY_LIST 0x34 91#define PCI_INTERRUPT_LINE 0x3c 92#define PCI_INTERRUPT_PIN 0x3d 93#define PCI_MIN_GNT 0x3e 94#define PCI_MAX_LAT 0x3f 95#define PCI_PRIMARY_BUS 0x18 96#define PCI_SECONDARY_BUS 0x19 97#define PCI_SUBORDINATE_BUS 0x1a 98#define PCI_SEC_LATENCY_TIMER 0x1b 99#define PCI_IO_BASE 0x1c 100#define PCI_IO_LIMIT 0x1d 101#define PCI_IO_RANGE_TYPE_MASK 0x0fUL 102#define PCI_IO_RANGE_TYPE_16 0x00 103#define PCI_IO_RANGE_TYPE_32 0x01 104#define PCI_IO_RANGE_MASK (~0x0fUL) 105#define PCI_IO_1K_RANGE_MASK (~0x03UL) 106#define PCI_SEC_STATUS 0x1e 107#define PCI_MEMORY_BASE 0x20 108#define PCI_MEMORY_LIMIT 0x22 109#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 110#define PCI_MEMORY_RANGE_MASK (~0x0fUL) 111#define PCI_PREF_MEMORY_BASE 0x24 112#define PCI_PREF_MEMORY_LIMIT 0x26 113#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 114#define PCI_PREF_RANGE_TYPE_32 0x00 115#define PCI_PREF_RANGE_TYPE_64 0x01 116#define PCI_PREF_RANGE_MASK (~0x0fUL) 117#define PCI_PREF_BASE_UPPER32 0x28 118#define PCI_PREF_LIMIT_UPPER32 0x2c 119#define PCI_IO_BASE_UPPER16 0x30 120#define PCI_IO_LIMIT_UPPER16 0x32 121#define PCI_ROM_ADDRESS1 0x38 122#define PCI_BRIDGE_CONTROL 0x3e 123#define PCI_BRIDGE_CTL_PARITY 0x01 124#define PCI_BRIDGE_CTL_SERR 0x02 125#define PCI_BRIDGE_CTL_ISA 0x04 126#define PCI_BRIDGE_CTL_VGA 0x08 127#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 128#define PCI_BRIDGE_CTL_BUS_RESET 0x40 129#define PCI_BRIDGE_CTL_FAST_BACK 0x80 130#define PCI_CB_CAPABILITY_LIST 0x14 131#define PCI_CB_SEC_STATUS 0x16 132#define PCI_CB_PRIMARY_BUS 0x18 133#define PCI_CB_CARD_BUS 0x19 134#define PCI_CB_SUBORDINATE_BUS 0x1a 135#define PCI_CB_LATENCY_TIMER 0x1b 136#define PCI_CB_MEMORY_BASE_0 0x1c 137#define PCI_CB_MEMORY_LIMIT_0 0x20 138#define PCI_CB_MEMORY_BASE_1 0x24 139#define PCI_CB_MEMORY_LIMIT_1 0x28 140#define PCI_CB_IO_BASE_0 0x2c 141#define PCI_CB_IO_BASE_0_HI 0x2e 142#define PCI_CB_IO_LIMIT_0 0x30 143#define PCI_CB_IO_LIMIT_0_HI 0x32 144#define PCI_CB_IO_BASE_1 0x34 145#define PCI_CB_IO_BASE_1_HI 0x36 146#define PCI_CB_IO_LIMIT_1 0x38 147#define PCI_CB_IO_LIMIT_1_HI 0x3a 148#define PCI_CB_IO_RANGE_MASK (~0x03UL) 149#define PCI_CB_BRIDGE_CONTROL 0x3e 150#define PCI_CB_BRIDGE_CTL_PARITY 0x01 151#define PCI_CB_BRIDGE_CTL_SERR 0x02 152#define PCI_CB_BRIDGE_CTL_ISA 0x04 153#define PCI_CB_BRIDGE_CTL_VGA 0x08 154#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 155#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 156#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 157#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 158#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 159#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 160#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 161#define PCI_CB_SUBSYSTEM_ID 0x42 162#define PCI_CB_LEGACY_MODE_BASE 0x44 163#define PCI_CAP_LIST_ID 0 164#define PCI_CAP_ID_PM 0x01 165#define PCI_CAP_ID_AGP 0x02 166#define PCI_CAP_ID_VPD 0x03 167#define PCI_CAP_ID_SLOTID 0x04 168#define PCI_CAP_ID_MSI 0x05 169#define PCI_CAP_ID_CHSWP 0x06 170#define PCI_CAP_ID_PCIX 0x07 171#define PCI_CAP_ID_HT 0x08 172#define PCI_CAP_ID_VNDR 0x09 173#define PCI_CAP_ID_DBG 0x0A 174#define PCI_CAP_ID_CCRC 0x0B 175#define PCI_CAP_ID_SHPC 0x0C 176#define PCI_CAP_ID_SSVID 0x0D 177#define PCI_CAP_ID_AGP3 0x0E 178#define PCI_CAP_ID_SECDEV 0x0F 179#define PCI_CAP_ID_EXP 0x10 180#define PCI_CAP_ID_MSIX 0x11 181#define PCI_CAP_ID_SATA 0x12 182#define PCI_CAP_ID_AF 0x13 183#define PCI_CAP_ID_EA 0x14 184#define PCI_CAP_ID_MAX PCI_CAP_ID_EA 185#define PCI_CAP_LIST_NEXT 1 186#define PCI_CAP_FLAGS 2 187#define PCI_CAP_SIZEOF 4 188#define PCI_PM_PMC 2 189#define PCI_PM_CAP_VER_MASK 0x0007 190#define PCI_PM_CAP_PME_CLOCK 0x0008 191#define PCI_PM_CAP_RESERVED 0x0010 192#define PCI_PM_CAP_DSI 0x0020 193#define PCI_PM_CAP_AUX_POWER 0x01C0 194#define PCI_PM_CAP_D1 0x0200 195#define PCI_PM_CAP_D2 0x0400 196#define PCI_PM_CAP_PME 0x0800 197#define PCI_PM_CAP_PME_MASK 0xF800 198#define PCI_PM_CAP_PME_D0 0x0800 199#define PCI_PM_CAP_PME_D1 0x1000 200#define PCI_PM_CAP_PME_D2 0x2000 201#define PCI_PM_CAP_PME_D3 0x4000 202#define PCI_PM_CAP_PME_D3cold 0x8000 203#define PCI_PM_CAP_PME_SHIFT 11 204#define PCI_PM_CTRL 4 205#define PCI_PM_CTRL_STATE_MASK 0x0003 206#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 207#define PCI_PM_CTRL_PME_ENABLE 0x0100 208#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 209#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 210#define PCI_PM_CTRL_PME_STATUS 0x8000 211#define PCI_PM_PPB_EXTENSIONS 6 212#define PCI_PM_PPB_B2_B3 0x40 213#define PCI_PM_BPCC_ENABLE 0x80 214#define PCI_PM_DATA_REGISTER 7 215#define PCI_PM_SIZEOF 8 216#define PCI_AGP_VERSION 2 217#define PCI_AGP_RFU 3 218#define PCI_AGP_STATUS 4 219#define PCI_AGP_STATUS_RQ_MASK 0xff000000 220#define PCI_AGP_STATUS_SBA 0x0200 221#define PCI_AGP_STATUS_64BIT 0x0020 222#define PCI_AGP_STATUS_FW 0x0010 223#define PCI_AGP_STATUS_RATE4 0x0004 224#define PCI_AGP_STATUS_RATE2 0x0002 225#define PCI_AGP_STATUS_RATE1 0x0001 226#define PCI_AGP_COMMAND 8 227#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 228#define PCI_AGP_COMMAND_SBA 0x0200 229#define PCI_AGP_COMMAND_AGP 0x0100 230#define PCI_AGP_COMMAND_64BIT 0x0020 231#define PCI_AGP_COMMAND_FW 0x0010 232#define PCI_AGP_COMMAND_RATE4 0x0004 233#define PCI_AGP_COMMAND_RATE2 0x0002 234#define PCI_AGP_COMMAND_RATE1 0x0001 235#define PCI_AGP_SIZEOF 12 236#define PCI_VPD_ADDR 2 237#define PCI_VPD_ADDR_MASK 0x7fff 238#define PCI_VPD_ADDR_F 0x8000 239#define PCI_VPD_DATA 4 240#define PCI_CAP_VPD_SIZEOF 8 241#define PCI_SID_ESR 2 242#define PCI_SID_ESR_NSLOTS 0x1f 243#define PCI_SID_ESR_FIC 0x20 244#define PCI_SID_CHASSIS_NR 3 245#define PCI_MSI_FLAGS 2 246#define PCI_MSI_FLAGS_ENABLE 0x0001 247#define PCI_MSI_FLAGS_QMASK 0x000e 248#define PCI_MSI_FLAGS_QSIZE 0x0070 249#define PCI_MSI_FLAGS_64BIT 0x0080 250#define PCI_MSI_FLAGS_MASKBIT 0x0100 251#define PCI_MSI_RFU 3 252#define PCI_MSI_ADDRESS_LO 4 253#define PCI_MSI_ADDRESS_HI 8 254#define PCI_MSI_DATA_32 8 255#define PCI_MSI_MASK_32 12 256#define PCI_MSI_PENDING_32 16 257#define PCI_MSI_DATA_64 12 258#define PCI_MSI_MASK_64 16 259#define PCI_MSI_PENDING_64 20 260#define PCI_MSIX_FLAGS 2 261#define PCI_MSIX_FLAGS_QSIZE 0x07FF 262#define PCI_MSIX_FLAGS_MASKALL 0x4000 263#define PCI_MSIX_FLAGS_ENABLE 0x8000 264#define PCI_MSIX_TABLE 4 265#define PCI_MSIX_TABLE_BIR 0x00000007 266#define PCI_MSIX_TABLE_OFFSET 0xfffffff8 267#define PCI_MSIX_PBA 8 268#define PCI_MSIX_PBA_BIR 0x00000007 269#define PCI_MSIX_PBA_OFFSET 0xfffffff8 270#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR 271#define PCI_CAP_MSIX_SIZEOF 12 272#define PCI_MSIX_ENTRY_SIZE 16 273#define PCI_MSIX_ENTRY_LOWER_ADDR 0 274#define PCI_MSIX_ENTRY_UPPER_ADDR 4 275#define PCI_MSIX_ENTRY_DATA 8 276#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 277#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 278#define PCI_CHSWP_CSR 2 279#define PCI_CHSWP_DHA 0x01 280#define PCI_CHSWP_EIM 0x02 281#define PCI_CHSWP_PIE 0x04 282#define PCI_CHSWP_LOO 0x08 283#define PCI_CHSWP_PI 0x30 284#define PCI_CHSWP_EXT 0x40 285#define PCI_CHSWP_INS 0x80 286#define PCI_AF_LENGTH 2 287#define PCI_AF_CAP 3 288#define PCI_AF_CAP_TP 0x01 289#define PCI_AF_CAP_FLR 0x02 290#define PCI_AF_CTRL 4 291#define PCI_AF_CTRL_FLR 0x01 292#define PCI_AF_STATUS 5 293#define PCI_AF_STATUS_TP 0x01 294#define PCI_CAP_AF_SIZEOF 6 295#define PCI_EA_NUM_ENT 2 296#define PCI_EA_NUM_ENT_MASK 0x3f 297#define PCI_EA_FIRST_ENT 4 298#define PCI_EA_FIRST_ENT_BRIDGE 8 299#define PCI_EA_ES 0x00000007 300#define PCI_EA_BEI 0x000000f0 301#define PCI_EA_BEI_BAR0 0 302#define PCI_EA_BEI_BAR5 5 303#define PCI_EA_BEI_BRIDGE 6 304#define PCI_EA_BEI_ENI 7 305#define PCI_EA_BEI_ROM 8 306#define PCI_EA_BEI_VF_BAR0 9 307#define PCI_EA_BEI_VF_BAR5 14 308#define PCI_EA_BEI_RESERVED 15 309#define PCI_EA_PP 0x0000ff00 310#define PCI_EA_SP 0x00ff0000 311#define PCI_EA_P_MEM 0x00 312#define PCI_EA_P_MEM_PREFETCH 0x01 313#define PCI_EA_P_IO 0x02 314#define PCI_EA_P_VF_MEM_PREFETCH 0x03 315#define PCI_EA_P_VF_MEM 0x04 316#define PCI_EA_P_BRIDGE_MEM 0x05 317#define PCI_EA_P_BRIDGE_MEM_PREFETCH 0x06 318#define PCI_EA_P_BRIDGE_IO 0x07 319#define PCI_EA_P_MEM_RESERVED 0xfd 320#define PCI_EA_P_IO_RESERVED 0xfe 321#define PCI_EA_P_UNAVAILABLE 0xff 322#define PCI_EA_WRITABLE 0x40000000 323#define PCI_EA_ENABLE 0x80000000 324#define PCI_EA_BASE 4 325#define PCI_EA_MAX_OFFSET 8 326#define PCI_EA_IS_64 0x00000002 327#define PCI_EA_FIELD_MASK 0xfffffffc 328#define PCI_X_CMD 2 329#define PCI_X_CMD_DPERR_E 0x0001 330#define PCI_X_CMD_ERO 0x0002 331#define PCI_X_CMD_READ_512 0x0000 332#define PCI_X_CMD_READ_1K 0x0004 333#define PCI_X_CMD_READ_2K 0x0008 334#define PCI_X_CMD_READ_4K 0x000c 335#define PCI_X_CMD_MAX_READ 0x000c 336#define PCI_X_CMD_SPLIT_1 0x0000 337#define PCI_X_CMD_SPLIT_2 0x0010 338#define PCI_X_CMD_SPLIT_3 0x0020 339#define PCI_X_CMD_SPLIT_4 0x0030 340#define PCI_X_CMD_SPLIT_8 0x0040 341#define PCI_X_CMD_SPLIT_12 0x0050 342#define PCI_X_CMD_SPLIT_16 0x0060 343#define PCI_X_CMD_SPLIT_32 0x0070 344#define PCI_X_CMD_MAX_SPLIT 0x0070 345#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) 346#define PCI_X_STATUS 4 347#define PCI_X_STATUS_DEVFN 0x000000ff 348#define PCI_X_STATUS_BUS 0x0000ff00 349#define PCI_X_STATUS_64BIT 0x00010000 350#define PCI_X_STATUS_133MHZ 0x00020000 351#define PCI_X_STATUS_SPL_DISC 0x00040000 352#define PCI_X_STATUS_UNX_SPL 0x00080000 353#define PCI_X_STATUS_COMPLEX 0x00100000 354#define PCI_X_STATUS_MAX_READ 0x00600000 355#define PCI_X_STATUS_MAX_SPLIT 0x03800000 356#define PCI_X_STATUS_MAX_CUM 0x1c000000 357#define PCI_X_STATUS_SPL_ERR 0x20000000 358#define PCI_X_STATUS_266MHZ 0x40000000 359#define PCI_X_STATUS_533MHZ 0x80000000 360#define PCI_X_ECC_CSR 8 361#define PCI_CAP_PCIX_SIZEOF_V0 8 362#define PCI_CAP_PCIX_SIZEOF_V1 24 363#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 364#define PCI_X_BRIDGE_SSTATUS 2 365#define PCI_X_SSTATUS_64BIT 0x0001 366#define PCI_X_SSTATUS_133MHZ 0x0002 367#define PCI_X_SSTATUS_FREQ 0x03c0 368#define PCI_X_SSTATUS_VERS 0x3000 369#define PCI_X_SSTATUS_V1 0x1000 370#define PCI_X_SSTATUS_V2 0x2000 371#define PCI_X_SSTATUS_266MHZ 0x4000 372#define PCI_X_SSTATUS_533MHZ 0x8000 373#define PCI_X_BRIDGE_STATUS 4 374#define PCI_SSVID_VENDOR_ID 4 375#define PCI_SSVID_DEVICE_ID 6 376#define PCI_EXP_FLAGS 2 377#define PCI_EXP_FLAGS_VERS 0x000f 378#define PCI_EXP_FLAGS_TYPE 0x00f0 379#define PCI_EXP_TYPE_ENDPOINT 0x0 380#define PCI_EXP_TYPE_LEG_END 0x1 381#define PCI_EXP_TYPE_ROOT_PORT 0x4 382#define PCI_EXP_TYPE_UPSTREAM 0x5 383#define PCI_EXP_TYPE_DOWNSTREAM 0x6 384#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 385#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 386#define PCI_EXP_TYPE_RC_END 0x9 387#define PCI_EXP_TYPE_RC_EC 0xa 388#define PCI_EXP_FLAGS_SLOT 0x0100 389#define PCI_EXP_FLAGS_IRQ 0x3e00 390#define PCI_EXP_DEVCAP 4 391#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 392#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 393#define PCI_EXP_DEVCAP_EXT_TAG 0x00000020 394#define PCI_EXP_DEVCAP_L0S 0x000001c0 395#define PCI_EXP_DEVCAP_L1 0x00000e00 396#define PCI_EXP_DEVCAP_ATN_BUT 0x00001000 397#define PCI_EXP_DEVCAP_ATN_IND 0x00002000 398#define PCI_EXP_DEVCAP_PWR_IND 0x00004000 399#define PCI_EXP_DEVCAP_RBER 0x00008000 400#define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 401#define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 402#define PCI_EXP_DEVCAP_FLR 0x10000000 403#define PCI_EXP_DEVCTL 8 404#define PCI_EXP_DEVCTL_CERE 0x0001 405#define PCI_EXP_DEVCTL_NFERE 0x0002 406#define PCI_EXP_DEVCTL_FERE 0x0004 407#define PCI_EXP_DEVCTL_URRE 0x0008 408#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 409#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 410#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 411#define PCI_EXP_DEVCTL_PHANTOM 0x0200 412#define PCI_EXP_DEVCTL_AUX_PME 0x0400 413#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 414#define PCI_EXP_DEVCTL_READRQ 0x7000 415#define PCI_EXP_DEVCTL_READRQ_128B 0x0000 416#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 417#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 418#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 419#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 420#define PCI_EXP_DEVSTA 10 421#define PCI_EXP_DEVSTA_CED 0x0001 422#define PCI_EXP_DEVSTA_NFED 0x0002 423#define PCI_EXP_DEVSTA_FED 0x0004 424#define PCI_EXP_DEVSTA_URD 0x0008 425#define PCI_EXP_DEVSTA_AUXPD 0x0010 426#define PCI_EXP_DEVSTA_TRPND 0x0020 427#define PCI_EXP_LNKCAP 12 428#define PCI_EXP_LNKCAP_SLS 0x0000000f 429#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 430#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 431#define PCI_EXP_LNKCAP_MLW 0x000003f0 432#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 433#define PCI_EXP_LNKCAP_L0SEL 0x00007000 434#define PCI_EXP_LNKCAP_L1EL 0x00038000 435#define PCI_EXP_LNKCAP_CLKPM 0x00040000 436#define PCI_EXP_LNKCAP_SDERC 0x00080000 437#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 438#define PCI_EXP_LNKCAP_LBNC 0x00200000 439#define PCI_EXP_LNKCAP_PN 0xff000000 440#define PCI_EXP_LNKCTL 16 441#define PCI_EXP_LNKCTL_ASPMC 0x0003 442#define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 443#define PCI_EXP_LNKCTL_ASPM_L1 0x0002 444#define PCI_EXP_LNKCTL_RCB 0x0008 445#define PCI_EXP_LNKCTL_LD 0x0010 446#define PCI_EXP_LNKCTL_RL 0x0020 447#define PCI_EXP_LNKCTL_CCC 0x0040 448#define PCI_EXP_LNKCTL_ES 0x0080 449#define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 450#define PCI_EXP_LNKCTL_HAWD 0x0200 451#define PCI_EXP_LNKCTL_LBMIE 0x0400 452#define PCI_EXP_LNKCTL_LABIE 0x0800 453#define PCI_EXP_LNKSTA 18 454#define PCI_EXP_LNKSTA_CLS 0x000f 455#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 456#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 457#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 458#define PCI_EXP_LNKSTA_NLW 0x03f0 459#define PCI_EXP_LNKSTA_NLW_X1 0x0010 460#define PCI_EXP_LNKSTA_NLW_X2 0x0020 461#define PCI_EXP_LNKSTA_NLW_X4 0x0040 462#define PCI_EXP_LNKSTA_NLW_X8 0x0080 463#define PCI_EXP_LNKSTA_NLW_SHIFT 4 464#define PCI_EXP_LNKSTA_LT 0x0800 465#define PCI_EXP_LNKSTA_SLC 0x1000 466#define PCI_EXP_LNKSTA_DLLLA 0x2000 467#define PCI_EXP_LNKSTA_LBMS 0x4000 468#define PCI_EXP_LNKSTA_LABS 0x8000 469#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 470#define PCI_EXP_SLTCAP 20 471#define PCI_EXP_SLTCAP_ABP 0x00000001 472#define PCI_EXP_SLTCAP_PCP 0x00000002 473#define PCI_EXP_SLTCAP_MRLSP 0x00000004 474#define PCI_EXP_SLTCAP_AIP 0x00000008 475#define PCI_EXP_SLTCAP_PIP 0x00000010 476#define PCI_EXP_SLTCAP_HPS 0x00000020 477#define PCI_EXP_SLTCAP_HPC 0x00000040 478#define PCI_EXP_SLTCAP_SPLV 0x00007f80 479#define PCI_EXP_SLTCAP_SPLS 0x00018000 480#define PCI_EXP_SLTCAP_EIP 0x00020000 481#define PCI_EXP_SLTCAP_NCCS 0x00040000 482#define PCI_EXP_SLTCAP_PSN 0xfff80000 483#define PCI_EXP_SLTCTL 24 484#define PCI_EXP_SLTCTL_ABPE 0x0001 485#define PCI_EXP_SLTCTL_PFDE 0x0002 486#define PCI_EXP_SLTCTL_MRLSCE 0x0004 487#define PCI_EXP_SLTCTL_PDCE 0x0008 488#define PCI_EXP_SLTCTL_CCIE 0x0010 489#define PCI_EXP_SLTCTL_HPIE 0x0020 490#define PCI_EXP_SLTCTL_AIC 0x00c0 491#define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 492#define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 493#define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 494#define PCI_EXP_SLTCTL_PIC 0x0300 495#define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 496#define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 497#define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 498#define PCI_EXP_SLTCTL_PCC 0x0400 499#define PCI_EXP_SLTCTL_PWR_ON 0x0000 500#define PCI_EXP_SLTCTL_PWR_OFF 0x0400 501#define PCI_EXP_SLTCTL_EIC 0x0800 502#define PCI_EXP_SLTCTL_DLLSCE 0x1000 503#define PCI_EXP_SLTSTA 26 504#define PCI_EXP_SLTSTA_ABP 0x0001 505#define PCI_EXP_SLTSTA_PFD 0x0002 506#define PCI_EXP_SLTSTA_MRLSC 0x0004 507#define PCI_EXP_SLTSTA_PDC 0x0008 508#define PCI_EXP_SLTSTA_CC 0x0010 509#define PCI_EXP_SLTSTA_MRLSS 0x0020 510#define PCI_EXP_SLTSTA_PDS 0x0040 511#define PCI_EXP_SLTSTA_EIS 0x0080 512#define PCI_EXP_SLTSTA_DLLSC 0x0100 513#define PCI_EXP_RTCTL 28 514#define PCI_EXP_RTCTL_SECEE 0x0001 515#define PCI_EXP_RTCTL_SENFEE 0x0002 516#define PCI_EXP_RTCTL_SEFEE 0x0004 517#define PCI_EXP_RTCTL_PMEIE 0x0008 518#define PCI_EXP_RTCTL_CRSSVE 0x0010 519#define PCI_EXP_RTCAP 30 520#define PCI_EXP_RTCAP_CRSVIS 0x0001 521#define PCI_EXP_RTSTA 32 522#define PCI_EXP_RTSTA_PME 0x00010000 523#define PCI_EXP_RTSTA_PENDING 0x00020000 524#define PCI_EXP_DEVCAP2 36 525#define PCI_EXP_DEVCAP2_ARI 0x00000020 526#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 527#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 528#define PCI_EXP_DEVCAP2_LTR 0x00000800 529#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 530#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 531#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 532#define PCI_EXP_DEVCTL2 40 533#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f 534#define PCI_EXP_DEVCTL2_ARI 0x0020 535#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 536#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 537#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 538#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 539#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 540#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 541#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 542#define PCI_EXP_DEVSTA2 42 543#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 544#define PCI_EXP_LNKCAP2 44 545#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 546#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 547#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 548#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 549#define PCI_EXP_LNKCTL2 48 550#define PCI_EXP_LNKSTA2 50 551#define PCI_EXP_SLTCAP2 52 552#define PCI_EXP_SLTCTL2 56 553#define PCI_EXP_SLTSTA2 58 554#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 555#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 556#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 557#define PCI_EXT_CAP_ID_ERR 0x01 558#define PCI_EXT_CAP_ID_VC 0x02 559#define PCI_EXT_CAP_ID_DSN 0x03 560#define PCI_EXT_CAP_ID_PWR 0x04 561#define PCI_EXT_CAP_ID_RCLD 0x05 562#define PCI_EXT_CAP_ID_RCILC 0x06 563#define PCI_EXT_CAP_ID_RCEC 0x07 564#define PCI_EXT_CAP_ID_MFVC 0x08 565#define PCI_EXT_CAP_ID_VC9 0x09 566#define PCI_EXT_CAP_ID_RCRB 0x0A 567#define PCI_EXT_CAP_ID_VNDR 0x0B 568#define PCI_EXT_CAP_ID_CAC 0x0C 569#define PCI_EXT_CAP_ID_ACS 0x0D 570#define PCI_EXT_CAP_ID_ARI 0x0E 571#define PCI_EXT_CAP_ID_ATS 0x0F 572#define PCI_EXT_CAP_ID_SRIOV 0x10 573#define PCI_EXT_CAP_ID_MRIOV 0x11 574#define PCI_EXT_CAP_ID_MCAST 0x12 575#define PCI_EXT_CAP_ID_PRI 0x13 576#define PCI_EXT_CAP_ID_AMD_XXX 0x14 577#define PCI_EXT_CAP_ID_REBAR 0x15 578#define PCI_EXT_CAP_ID_DPA 0x16 579#define PCI_EXT_CAP_ID_TPH 0x17 580#define PCI_EXT_CAP_ID_LTR 0x18 581#define PCI_EXT_CAP_ID_SECPCI 0x19 582#define PCI_EXT_CAP_ID_PMUX 0x1A 583#define PCI_EXT_CAP_ID_PASID 0x1B 584#define PCI_EXT_CAP_ID_DPC 0x1D 585#define PCI_EXT_CAP_ID_PTM 0x1F 586#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM 587#define PCI_EXT_CAP_DSN_SIZEOF 12 588#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 589#define PCI_ERR_UNCOR_STATUS 4 590#define PCI_ERR_UNC_UND 0x00000001 591#define PCI_ERR_UNC_DLP 0x00000010 592#define PCI_ERR_UNC_SURPDN 0x00000020 593#define PCI_ERR_UNC_POISON_TLP 0x00001000 594#define PCI_ERR_UNC_FCP 0x00002000 595#define PCI_ERR_UNC_COMP_TIME 0x00004000 596#define PCI_ERR_UNC_COMP_ABORT 0x00008000 597#define PCI_ERR_UNC_UNX_COMP 0x00010000 598#define PCI_ERR_UNC_RX_OVER 0x00020000 599#define PCI_ERR_UNC_MALF_TLP 0x00040000 600#define PCI_ERR_UNC_ECRC 0x00080000 601#define PCI_ERR_UNC_UNSUP 0x00100000 602#define PCI_ERR_UNC_ACSV 0x00200000 603#define PCI_ERR_UNC_INTN 0x00400000 604#define PCI_ERR_UNC_MCBTLP 0x00800000 605#define PCI_ERR_UNC_ATOMEG 0x01000000 606#define PCI_ERR_UNC_TLPPRE 0x02000000 607#define PCI_ERR_UNCOR_MASK 8 608#define PCI_ERR_UNCOR_SEVER 12 609#define PCI_ERR_COR_STATUS 16 610#define PCI_ERR_COR_RCVR 0x00000001 611#define PCI_ERR_COR_BAD_TLP 0x00000040 612#define PCI_ERR_COR_BAD_DLLP 0x00000080 613#define PCI_ERR_COR_REP_ROLL 0x00000100 614#define PCI_ERR_COR_REP_TIMER 0x00001000 615#define PCI_ERR_COR_ADV_NFAT 0x00002000 616#define PCI_ERR_COR_INTERNAL 0x00004000 617#define PCI_ERR_COR_LOG_OVER 0x00008000 618#define PCI_ERR_COR_MASK 20 619#define PCI_ERR_CAP 24 620#define PCI_ERR_CAP_FEP(x) ((x) & 31) 621#define PCI_ERR_CAP_ECRC_GENC 0x00000020 622#define PCI_ERR_CAP_ECRC_GENE 0x00000040 623#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 624#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 625#define PCI_ERR_HEADER_LOG 28 626#define PCI_ERR_ROOT_COMMAND 44 627#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 628#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 629#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 630#define PCI_ERR_ROOT_STATUS 48 631#define PCI_ERR_ROOT_COR_RCV 0x00000001 632#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 633#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 634#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 635#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 636#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 637#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 638#define PCI_ERR_ROOT_ERR_SRC 52 639#define PCI_VC_PORT_CAP1 4 640#define PCI_VC_CAP1_EVCC 0x00000007 641#define PCI_VC_CAP1_LPEVCC 0x00000070 642#define PCI_VC_CAP1_ARB_SIZE 0x00000c00 643#define PCI_VC_PORT_CAP2 8 644#define PCI_VC_CAP2_32_PHASE 0x00000002 645#define PCI_VC_CAP2_64_PHASE 0x00000004 646#define PCI_VC_CAP2_128_PHASE 0x00000008 647#define PCI_VC_CAP2_ARB_OFF 0xff000000 648#define PCI_VC_PORT_CTRL 12 649#define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 650#define PCI_VC_PORT_STATUS 14 651#define PCI_VC_PORT_STATUS_TABLE 0x00000001 652#define PCI_VC_RES_CAP 16 653#define PCI_VC_RES_CAP_32_PHASE 0x00000002 654#define PCI_VC_RES_CAP_64_PHASE 0x00000004 655#define PCI_VC_RES_CAP_128_PHASE 0x00000008 656#define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 657#define PCI_VC_RES_CAP_256_PHASE 0x00000020 658#define PCI_VC_RES_CAP_ARB_OFF 0xff000000 659#define PCI_VC_RES_CTRL 20 660#define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 661#define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 662#define PCI_VC_RES_CTRL_ID 0x07000000 663#define PCI_VC_RES_CTRL_ENABLE 0x80000000 664#define PCI_VC_RES_STATUS 26 665#define PCI_VC_RES_STATUS_TABLE 0x00000001 666#define PCI_VC_RES_STATUS_NEGO 0x00000002 667#define PCI_CAP_VC_BASE_SIZEOF 0x10 668#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C 669#define PCI_PWR_DSR 4 670#define PCI_PWR_DATA 8 671#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 672#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 673#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 674#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 675#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 676#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 677#define PCI_PWR_CAP 12 678#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) 679#define PCI_EXT_CAP_PWR_SIZEOF 16 680#define PCI_VNDR_HEADER 4 681#define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) 682#define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) 683#define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) 684#define HT_3BIT_CAP_MASK 0xE0 685#define HT_CAPTYPE_SLAVE 0x00 686#define HT_CAPTYPE_HOST 0x20 687#define HT_5BIT_CAP_MASK 0xF8 688#define HT_CAPTYPE_IRQ 0x80 689#define HT_CAPTYPE_REMAPPING_40 0xA0 690#define HT_CAPTYPE_REMAPPING_64 0xA2 691#define HT_CAPTYPE_UNITID_CLUMP 0x90 692#define HT_CAPTYPE_EXTCONF 0x98 693#define HT_CAPTYPE_MSI_MAPPING 0xA8 694#define HT_MSI_FLAGS 0x02 695#define HT_MSI_FLAGS_ENABLE 0x1 696#define HT_MSI_FLAGS_FIXED 0x2 697#define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL 698#define HT_MSI_ADDR_LO 0x04 699#define HT_MSI_ADDR_LO_MASK 0xFFF00000 700#define HT_MSI_ADDR_HI 0x08 701#define HT_CAPTYPE_DIRECT_ROUTE 0xB0 702#define HT_CAPTYPE_VCSET 0xB8 703#define HT_CAPTYPE_ERROR_RETRY 0xC0 704#define HT_CAPTYPE_GEN3 0xD0 705#define HT_CAPTYPE_PM 0xE0 706#define HT_CAP_SIZEOF_LONG 28 707#define HT_CAP_SIZEOF_SHORT 24 708#define PCI_ARI_CAP 0x04 709#define PCI_ARI_CAP_MFVC 0x0001 710#define PCI_ARI_CAP_ACS 0x0002 711#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) 712#define PCI_ARI_CTRL 0x06 713#define PCI_ARI_CTRL_MFVC 0x0001 714#define PCI_ARI_CTRL_ACS 0x0002 715#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) 716#define PCI_EXT_CAP_ARI_SIZEOF 8 717#define PCI_ATS_CAP 0x04 718#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) 719#define PCI_ATS_MAX_QDEP 32 720#define PCI_ATS_CTRL 0x06 721#define PCI_ATS_CTRL_ENABLE 0x8000 722#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) 723#define PCI_ATS_MIN_STU 12 724#define PCI_EXT_CAP_ATS_SIZEOF 8 725#define PCI_PRI_CTRL 0x04 726#define PCI_PRI_CTRL_ENABLE 0x01 727#define PCI_PRI_CTRL_RESET 0x02 728#define PCI_PRI_STATUS 0x06 729#define PCI_PRI_STATUS_RF 0x001 730#define PCI_PRI_STATUS_UPRGI 0x002 731#define PCI_PRI_STATUS_STOPPED 0x100 732#define PCI_PRI_MAX_REQ 0x08 733#define PCI_PRI_ALLOC_REQ 0x0c 734#define PCI_EXT_CAP_PRI_SIZEOF 16 735#define PCI_PASID_CAP 0x04 736#define PCI_PASID_CAP_EXEC 0x02 737#define PCI_PASID_CAP_PRIV 0x04 738#define PCI_PASID_CTRL 0x06 739#define PCI_PASID_CTRL_ENABLE 0x01 740#define PCI_PASID_CTRL_EXEC 0x02 741#define PCI_PASID_CTRL_PRIV 0x04 742#define PCI_EXT_CAP_PASID_SIZEOF 8 743#define PCI_SRIOV_CAP 0x04 744#define PCI_SRIOV_CAP_VFM 0x01 745#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) 746#define PCI_SRIOV_CTRL 0x08 747#define PCI_SRIOV_CTRL_VFE 0x01 748#define PCI_SRIOV_CTRL_VFM 0x02 749#define PCI_SRIOV_CTRL_INTR 0x04 750#define PCI_SRIOV_CTRL_MSE 0x08 751#define PCI_SRIOV_CTRL_ARI 0x10 752#define PCI_SRIOV_STATUS 0x0a 753#define PCI_SRIOV_STATUS_VFM 0x01 754#define PCI_SRIOV_INITIAL_VF 0x0c 755#define PCI_SRIOV_TOTAL_VF 0x0e 756#define PCI_SRIOV_NUM_VF 0x10 757#define PCI_SRIOV_FUNC_LINK 0x12 758#define PCI_SRIOV_VF_OFFSET 0x14 759#define PCI_SRIOV_VF_STRIDE 0x16 760#define PCI_SRIOV_VF_DID 0x1a 761#define PCI_SRIOV_SUP_PGSIZE 0x1c 762#define PCI_SRIOV_SYS_PGSIZE 0x20 763#define PCI_SRIOV_BAR 0x24 764#define PCI_SRIOV_NUM_BARS 6 765#define PCI_SRIOV_VFM 0x3c 766#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) 767#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) 768#define PCI_SRIOV_VFM_UA 0x0 769#define PCI_SRIOV_VFM_MI 0x1 770#define PCI_SRIOV_VFM_MO 0x2 771#define PCI_SRIOV_VFM_AV 0x3 772#define PCI_EXT_CAP_SRIOV_SIZEOF 64 773#define PCI_LTR_MAX_SNOOP_LAT 0x4 774#define PCI_LTR_MAX_NOSNOOP_LAT 0x6 775#define PCI_LTR_VALUE_MASK 0x000003ff 776#define PCI_LTR_SCALE_MASK 0x00001c00 777#define PCI_LTR_SCALE_SHIFT 10 778#define PCI_EXT_CAP_LTR_SIZEOF 8 779#define PCI_ACS_CAP 0x04 780#define PCI_ACS_SV 0x01 781#define PCI_ACS_TB 0x02 782#define PCI_ACS_RR 0x04 783#define PCI_ACS_CR 0x08 784#define PCI_ACS_UF 0x10 785#define PCI_ACS_EC 0x20 786#define PCI_ACS_DT 0x40 787#define PCI_ACS_EGRESS_BITS 0x05 788#define PCI_ACS_CTRL 0x06 789#define PCI_ACS_EGRESS_CTL_V 0x08 790#define PCI_VSEC_HDR 4 791#define PCI_VSEC_HDR_LEN_SHIFT 20 792#define PCI_SATA_REGS 4 793#define PCI_SATA_REGS_MASK 0xF 794#define PCI_SATA_REGS_INLINE 0xF 795#define PCI_SATA_SIZEOF_SHORT 8 796#define PCI_SATA_SIZEOF_LONG 16 797#define PCI_REBAR_CTRL 8 798#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) 799#define PCI_REBAR_CTRL_NBAR_SHIFT 5 800#define PCI_DPA_CAP 4 801#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F 802#define PCI_DPA_BASE_SIZEOF 16 803#define PCI_TPH_CAP 4 804#define PCI_TPH_CAP_LOC_MASK 0x600 805#define PCI_TPH_LOC_NONE 0x000 806#define PCI_TPH_LOC_CAP 0x200 807#define PCI_TPH_LOC_MSIX 0x400 808#define PCI_TPH_CAP_ST_MASK 0x07FF0000 809#define PCI_TPH_CAP_ST_SHIFT 16 810#define PCI_TPH_BASE_SIZEOF 12 811#define PCI_EXP_DPC_CAP 4 812#define PCI_EXP_DPC_CAP_RP_EXT 0x20 813#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 814#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 815#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 816#define PCI_EXP_DPC_CTL 6 817#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x02 818#define PCI_EXP_DPC_CTL_INT_EN 0x08 819#define PCI_EXP_DPC_STATUS 8 820#define PCI_EXP_DPC_STATUS_TRIGGER 0x01 821#define PCI_EXP_DPC_STATUS_INTERRUPT 0x08 822#define PCI_EXP_DPC_SOURCE_ID 10 823#define PCI_PTM_CAP 0x04 824#define PCI_PTM_CAP_REQ 0x00000001 825#define PCI_PTM_CAP_ROOT 0x00000004 826#define PCI_PTM_GRANULARITY_MASK 0x0000FF00 827#define PCI_PTM_CTRL 0x08 828#define PCI_PTM_CTRL_ENABLE 0x00000001 829#define PCI_PTM_CTRL_ROOT 0x00000002 830#endif 831