perf_event.h revision 525ce914edf136d2bd02ac8c404d56c52e737f4d 
1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_LINUX_PERF_EVENT_H
20#define _UAPI_LINUX_PERF_EVENT_H
21#include <linux/types.h>
22#include <linux/ioctl.h>
23#include <asm/byteorder.h>
24enum perf_type_id {
25  PERF_TYPE_HARDWARE = 0,
26  PERF_TYPE_SOFTWARE = 1,
27  PERF_TYPE_TRACEPOINT = 2,
28  PERF_TYPE_HW_CACHE = 3,
29  PERF_TYPE_RAW = 4,
30  PERF_TYPE_BREAKPOINT = 5,
31  PERF_TYPE_MAX,
32};
33enum perf_hw_id {
34  PERF_COUNT_HW_CPU_CYCLES = 0,
35  PERF_COUNT_HW_INSTRUCTIONS = 1,
36  PERF_COUNT_HW_CACHE_REFERENCES = 2,
37  PERF_COUNT_HW_CACHE_MISSES = 3,
38  PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,
39  PERF_COUNT_HW_BRANCH_MISSES = 5,
40  PERF_COUNT_HW_BUS_CYCLES = 6,
41  PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,
42  PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,
43  PERF_COUNT_HW_REF_CPU_CYCLES = 9,
44  PERF_COUNT_HW_MAX,
45};
46enum perf_hw_cache_id {
47  PERF_COUNT_HW_CACHE_L1D = 0,
48  PERF_COUNT_HW_CACHE_L1I = 1,
49  PERF_COUNT_HW_CACHE_LL = 2,
50  PERF_COUNT_HW_CACHE_DTLB = 3,
51  PERF_COUNT_HW_CACHE_ITLB = 4,
52  PERF_COUNT_HW_CACHE_BPU = 5,
53  PERF_COUNT_HW_CACHE_NODE = 6,
54  PERF_COUNT_HW_CACHE_MAX,
55};
56enum perf_hw_cache_op_id {
57  PERF_COUNT_HW_CACHE_OP_READ = 0,
58  PERF_COUNT_HW_CACHE_OP_WRITE = 1,
59  PERF_COUNT_HW_CACHE_OP_PREFETCH = 2,
60  PERF_COUNT_HW_CACHE_OP_MAX,
61};
62enum perf_hw_cache_op_result_id {
63  PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,
64  PERF_COUNT_HW_CACHE_RESULT_MISS = 1,
65  PERF_COUNT_HW_CACHE_RESULT_MAX,
66};
67enum perf_sw_ids {
68  PERF_COUNT_SW_CPU_CLOCK = 0,
69  PERF_COUNT_SW_TASK_CLOCK = 1,
70  PERF_COUNT_SW_PAGE_FAULTS = 2,
71  PERF_COUNT_SW_CONTEXT_SWITCHES = 3,
72  PERF_COUNT_SW_CPU_MIGRATIONS = 4,
73  PERF_COUNT_SW_PAGE_FAULTS_MIN = 5,
74  PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,
75  PERF_COUNT_SW_ALIGNMENT_FAULTS = 7,
76  PERF_COUNT_SW_EMULATION_FAULTS = 8,
77  PERF_COUNT_SW_DUMMY = 9,
78  PERF_COUNT_SW_BPF_OUTPUT = 10,
79  PERF_COUNT_SW_MAX,
80};
81enum perf_event_sample_format {
82  PERF_SAMPLE_IP = 1U << 0,
83  PERF_SAMPLE_TID = 1U << 1,
84  PERF_SAMPLE_TIME = 1U << 2,
85  PERF_SAMPLE_ADDR = 1U << 3,
86  PERF_SAMPLE_READ = 1U << 4,
87  PERF_SAMPLE_CALLCHAIN = 1U << 5,
88  PERF_SAMPLE_ID = 1U << 6,
89  PERF_SAMPLE_CPU = 1U << 7,
90  PERF_SAMPLE_PERIOD = 1U << 8,
91  PERF_SAMPLE_STREAM_ID = 1U << 9,
92  PERF_SAMPLE_RAW = 1U << 10,
93  PERF_SAMPLE_BRANCH_STACK = 1U << 11,
94  PERF_SAMPLE_REGS_USER = 1U << 12,
95  PERF_SAMPLE_STACK_USER = 1U << 13,
96  PERF_SAMPLE_WEIGHT = 1U << 14,
97  PERF_SAMPLE_DATA_SRC = 1U << 15,
98  PERF_SAMPLE_IDENTIFIER = 1U << 16,
99  PERF_SAMPLE_TRANSACTION = 1U << 17,
100  PERF_SAMPLE_REGS_INTR = 1U << 18,
101  PERF_SAMPLE_MAX = 1U << 19,
102};
103enum perf_branch_sample_type_shift {
104  PERF_SAMPLE_BRANCH_USER_SHIFT = 0,
105  PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1,
106  PERF_SAMPLE_BRANCH_HV_SHIFT = 2,
107  PERF_SAMPLE_BRANCH_ANY_SHIFT = 3,
108  PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4,
109  PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5,
110  PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6,
111  PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7,
112  PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8,
113  PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9,
114  PERF_SAMPLE_BRANCH_COND_SHIFT = 10,
115  PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11,
116  PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12,
117  PERF_SAMPLE_BRANCH_CALL_SHIFT = 13,
118  PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14,
119  PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15,
120  PERF_SAMPLE_BRANCH_MAX_SHIFT
121};
122enum perf_branch_sample_type {
123  PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT,
124  PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT,
125  PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT,
126  PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,
127  PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
128  PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
129  PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
130  PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
131  PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,
132  PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,
133  PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT,
134  PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
135  PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT,
136  PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT,
137  PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
138  PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
139  PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
140};
141#define PERF_SAMPLE_BRANCH_PLM_ALL (PERF_SAMPLE_BRANCH_USER | PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_HV)
142enum perf_sample_regs_abi {
143  PERF_SAMPLE_REGS_ABI_NONE = 0,
144  PERF_SAMPLE_REGS_ABI_32 = 1,
145  PERF_SAMPLE_REGS_ABI_64 = 2,
146};
147enum {
148  PERF_TXN_ELISION = (1 << 0),
149  PERF_TXN_TRANSACTION = (1 << 1),
150  PERF_TXN_SYNC = (1 << 2),
151  PERF_TXN_ASYNC = (1 << 3),
152  PERF_TXN_RETRY = (1 << 4),
153  PERF_TXN_CONFLICT = (1 << 5),
154  PERF_TXN_CAPACITY_WRITE = (1 << 6),
155  PERF_TXN_CAPACITY_READ = (1 << 7),
156  PERF_TXN_MAX = (1 << 8),
157  PERF_TXN_ABORT_MASK = (0xffffffffULL << 32),
158  PERF_TXN_ABORT_SHIFT = 32,
159};
160enum perf_event_read_format {
161  PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0,
162  PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1,
163  PERF_FORMAT_ID = 1U << 2,
164  PERF_FORMAT_GROUP = 1U << 3,
165  PERF_FORMAT_MAX = 1U << 4,
166};
167#define PERF_ATTR_SIZE_VER0 64
168#define PERF_ATTR_SIZE_VER1 72
169#define PERF_ATTR_SIZE_VER2 80
170#define PERF_ATTR_SIZE_VER3 96
171#define PERF_ATTR_SIZE_VER4 104
172#define PERF_ATTR_SIZE_VER5 112
173struct perf_event_attr {
174  __u32 type;
175  __u32 size;
176  __u64 config;
177  union {
178    __u64 sample_period;
179    __u64 sample_freq;
180  };
181  __u64 sample_type;
182  __u64 read_format;
183  __u64 disabled : 1, inherit : 1, pinned : 1, exclusive : 1, exclude_user : 1, exclude_kernel : 1, exclude_hv : 1, exclude_idle : 1, mmap : 1, comm : 1, freq : 1, inherit_stat : 1, enable_on_exec : 1, task : 1, watermark : 1, precise_ip : 2, mmap_data : 1, sample_id_all : 1, exclude_host : 1, exclude_guest : 1, exclude_callchain_kernel : 1, exclude_callchain_user : 1, mmap2 : 1, comm_exec : 1, use_clockid : 1, context_switch : 1, write_backward : 1, namespaces : 1, __reserved_1 : 35;
184  union {
185    __u32 wakeup_events;
186    __u32 wakeup_watermark;
187  };
188  __u32 bp_type;
189  union {
190    __u64 bp_addr;
191    __u64 config1;
192  };
193  union {
194    __u64 bp_len;
195    __u64 config2;
196  };
197  __u64 branch_sample_type;
198  __u64 sample_regs_user;
199  __u32 sample_stack_user;
200  __s32 clockid;
201  __u64 sample_regs_intr;
202  __u32 aux_watermark;
203  __u16 sample_max_stack;
204  __u16 __reserved_2;
205};
206#define perf_flags(attr) (* (& (attr)->read_format + 1))
207#define PERF_EVENT_IOC_ENABLE _IO('$', 0)
208#define PERF_EVENT_IOC_DISABLE _IO('$', 1)
209#define PERF_EVENT_IOC_REFRESH _IO('$', 2)
210#define PERF_EVENT_IOC_RESET _IO('$', 3)
211#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64)
212#define PERF_EVENT_IOC_SET_OUTPUT _IO('$', 5)
213#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *)
214#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *)
215#define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32)
216#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32)
217enum perf_event_ioc_flags {
218  PERF_IOC_FLAG_GROUP = 1U << 0,
219};
220struct perf_event_mmap_page {
221  __u32 version;
222  __u32 compat_version;
223  __u32 lock;
224  __u32 index;
225  __s64 offset;
226  __u64 time_enabled;
227  __u64 time_running;
228  union {
229    __u64 capabilities;
230    struct {
231      __u64 cap_bit0 : 1, cap_bit0_is_deprecated : 1, cap_user_rdpmc : 1, cap_user_time : 1, cap_user_time_zero : 1, cap_____res : 59;
232    };
233  };
234  __u16 pmc_width;
235  __u16 time_shift;
236  __u32 time_mult;
237  __u64 time_offset;
238  __u64 time_zero;
239  __u32 size;
240  __u8 __reserved[118 * 8 + 4];
241  __u64 data_head;
242  __u64 data_tail;
243  __u64 data_offset;
244  __u64 data_size;
245  __u64 aux_head;
246  __u64 aux_tail;
247  __u64 aux_offset;
248  __u64 aux_size;
249};
250#define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0)
251#define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0)
252#define PERF_RECORD_MISC_KERNEL (1 << 0)
253#define PERF_RECORD_MISC_USER (2 << 0)
254#define PERF_RECORD_MISC_HYPERVISOR (3 << 0)
255#define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
256#define PERF_RECORD_MISC_GUEST_USER (5 << 0)
257#define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12)
258#define PERF_RECORD_MISC_MMAP_DATA (1 << 13)
259#define PERF_RECORD_MISC_COMM_EXEC (1 << 13)
260#define PERF_RECORD_MISC_SWITCH_OUT (1 << 13)
261#define PERF_RECORD_MISC_EXACT_IP (1 << 14)
262#define PERF_RECORD_MISC_EXT_RESERVED (1 << 15)
263struct perf_event_header {
264  __u32 type;
265  __u16 misc;
266  __u16 size;
267};
268struct perf_ns_link_info {
269  __u64 dev;
270  __u64 ino;
271};
272enum {
273  NET_NS_INDEX = 0,
274  UTS_NS_INDEX = 1,
275  IPC_NS_INDEX = 2,
276  PID_NS_INDEX = 3,
277  USER_NS_INDEX = 4,
278  MNT_NS_INDEX = 5,
279  CGROUP_NS_INDEX = 6,
280  NR_NAMESPACES,
281};
282enum perf_event_type {
283  PERF_RECORD_MMAP = 1,
284  PERF_RECORD_LOST = 2,
285  PERF_RECORD_COMM = 3,
286  PERF_RECORD_EXIT = 4,
287  PERF_RECORD_THROTTLE = 5,
288  PERF_RECORD_UNTHROTTLE = 6,
289  PERF_RECORD_FORK = 7,
290  PERF_RECORD_READ = 8,
291  PERF_RECORD_SAMPLE = 9,
292  PERF_RECORD_MMAP2 = 10,
293  PERF_RECORD_AUX = 11,
294  PERF_RECORD_ITRACE_START = 12,
295  PERF_RECORD_LOST_SAMPLES = 13,
296  PERF_RECORD_SWITCH = 14,
297  PERF_RECORD_SWITCH_CPU_WIDE = 15,
298  PERF_RECORD_NAMESPACES = 16,
299  PERF_RECORD_MAX,
300};
301#define PERF_MAX_STACK_DEPTH 127
302#define PERF_MAX_CONTEXTS_PER_STACK 8
303enum perf_callchain_context {
304  PERF_CONTEXT_HV = (__u64) - 32,
305  PERF_CONTEXT_KERNEL = (__u64) - 128,
306  PERF_CONTEXT_USER = (__u64) - 512,
307  PERF_CONTEXT_GUEST = (__u64) - 2048,
308  PERF_CONTEXT_GUEST_KERNEL = (__u64) - 2176,
309  PERF_CONTEXT_GUEST_USER = (__u64) - 2560,
310  PERF_CONTEXT_MAX = (__u64) - 4095,
311};
312#define PERF_AUX_FLAG_TRUNCATED 0x01
313#define PERF_AUX_FLAG_OVERWRITE 0x02
314#define PERF_AUX_FLAG_PARTIAL 0x04
315#define PERF_FLAG_FD_NO_GROUP (1UL << 0)
316#define PERF_FLAG_FD_OUTPUT (1UL << 1)
317#define PERF_FLAG_PID_CGROUP (1UL << 2)
318#define PERF_FLAG_FD_CLOEXEC (1UL << 3)
319#ifdef __LITTLE_ENDIAN_BITFIELD
320union perf_mem_data_src {
321  __u64 val;
322  struct {
323    __u64 mem_op : 5, mem_lvl : 14, mem_snoop : 5, mem_lock : 2, mem_dtlb : 7, mem_rsvd : 31;
324  };
325};
326#elif defined(__BIG_ENDIAN_BITFIELD)
327union perf_mem_data_src {
328  __u64 val;
329  struct {
330    __u64 mem_rsvd : 31, mem_dtlb : 7, mem_lock : 2, mem_snoop : 5, mem_lvl : 14, mem_op : 5;
331  };
332};
333#else
334#error "Unknown endianness"
335#endif
336#define PERF_MEM_OP_NA 0x01
337#define PERF_MEM_OP_LOAD 0x02
338#define PERF_MEM_OP_STORE 0x04
339#define PERF_MEM_OP_PFETCH 0x08
340#define PERF_MEM_OP_EXEC 0x10
341#define PERF_MEM_OP_SHIFT 0
342#define PERF_MEM_LVL_NA 0x01
343#define PERF_MEM_LVL_HIT 0x02
344#define PERF_MEM_LVL_MISS 0x04
345#define PERF_MEM_LVL_L1 0x08
346#define PERF_MEM_LVL_LFB 0x10
347#define PERF_MEM_LVL_L2 0x20
348#define PERF_MEM_LVL_L3 0x40
349#define PERF_MEM_LVL_LOC_RAM 0x80
350#define PERF_MEM_LVL_REM_RAM1 0x100
351#define PERF_MEM_LVL_REM_RAM2 0x200
352#define PERF_MEM_LVL_REM_CCE1 0x400
353#define PERF_MEM_LVL_REM_CCE2 0x800
354#define PERF_MEM_LVL_IO 0x1000
355#define PERF_MEM_LVL_UNC 0x2000
356#define PERF_MEM_LVL_SHIFT 5
357#define PERF_MEM_SNOOP_NA 0x01
358#define PERF_MEM_SNOOP_NONE 0x02
359#define PERF_MEM_SNOOP_HIT 0x04
360#define PERF_MEM_SNOOP_MISS 0x08
361#define PERF_MEM_SNOOP_HITM 0x10
362#define PERF_MEM_SNOOP_SHIFT 19
363#define PERF_MEM_LOCK_NA 0x01
364#define PERF_MEM_LOCK_LOCKED 0x02
365#define PERF_MEM_LOCK_SHIFT 24
366#define PERF_MEM_TLB_NA 0x01
367#define PERF_MEM_TLB_HIT 0x02
368#define PERF_MEM_TLB_MISS 0x04
369#define PERF_MEM_TLB_L1 0x08
370#define PERF_MEM_TLB_L2 0x10
371#define PERF_MEM_TLB_WK 0x20
372#define PERF_MEM_TLB_OS 0x40
373#define PERF_MEM_TLB_SHIFT 26
374#define PERF_MEM_S(a,s) (((__u64) PERF_MEM_ ##a ##_ ##s) << PERF_MEM_ ##a ##_SHIFT)
375struct perf_branch_entry {
376  __u64 from;
377  __u64 to;
378  __u64 mispred : 1, predicted : 1, in_tx : 1, abort : 1, cycles : 16, reserved : 44;
379};
380#endif
381