mlx5-abi.h revision 525ce914edf136d2bd02ac8c404d56c52e737f4d 
1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef MLX5_ABI_USER_H
20#define MLX5_ABI_USER_H
21#include <linux/types.h>
22#include <linux/if_ether.h>
23enum {
24  MLX5_QP_FLAG_SIGNATURE = 1 << 0,
25  MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
26};
27enum {
28  MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
29};
30enum {
31  MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
32};
33#define MLX5_IB_UVERBS_ABI_VERSION 1
34struct mlx5_ib_alloc_ucontext_req {
35  __u32 total_num_bfregs;
36  __u32 num_low_latency_bfregs;
37};
38enum mlx5_lib_caps {
39  MLX5_LIB_CAP_4K_UAR = (__u64) 1 << 0,
40};
41struct mlx5_ib_alloc_ucontext_req_v2 {
42  __u32 total_num_bfregs;
43  __u32 num_low_latency_bfregs;
44  __u32 flags;
45  __u32 comp_mask;
46  __u8 max_cqe_version;
47  __u8 reserved0;
48  __u16 reserved1;
49  __u32 reserved2;
50  __u64 lib_caps;
51};
52enum mlx5_ib_alloc_ucontext_resp_mask {
53  MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
54};
55enum mlx5_user_cmds_supp_uhw {
56  MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
57  MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
58};
59enum mlx5_user_inline_mode {
60  MLX5_USER_INLINE_MODE_NA,
61  MLX5_USER_INLINE_MODE_NONE,
62  MLX5_USER_INLINE_MODE_L2,
63  MLX5_USER_INLINE_MODE_IP,
64  MLX5_USER_INLINE_MODE_TCP_UDP,
65};
66struct mlx5_ib_alloc_ucontext_resp {
67  __u32 qp_tab_size;
68  __u32 bf_reg_size;
69  __u32 tot_bfregs;
70  __u32 cache_line_size;
71  __u16 max_sq_desc_sz;
72  __u16 max_rq_desc_sz;
73  __u32 max_send_wqebb;
74  __u32 max_recv_wr;
75  __u32 max_srq_recv_wr;
76  __u16 num_ports;
77  __u16 reserved1;
78  __u32 comp_mask;
79  __u32 response_length;
80  __u8 cqe_version;
81  __u8 cmds_supp_uhw;
82  __u8 eth_min_inline;
83  __u8 reserved2;
84  __u64 hca_core_clock_offset;
85  __u32 log_uar_size;
86  __u32 num_uars_per_page;
87};
88struct mlx5_ib_alloc_pd_resp {
89  __u32 pdn;
90};
91struct mlx5_ib_tso_caps {
92  __u32 max_tso;
93  __u32 supported_qpts;
94};
95struct mlx5_ib_rss_caps {
96  __u64 rx_hash_fields_mask;
97  __u8 rx_hash_function;
98  __u8 reserved[7];
99};
100enum mlx5_ib_cqe_comp_res_format {
101  MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
102  MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
103  MLX5_IB_CQE_RES_RESERVED = 1 << 2,
104};
105struct mlx5_ib_cqe_comp_caps {
106  __u32 max_num;
107  __u32 supported_format;
108};
109struct mlx5_packet_pacing_caps {
110  __u32 qp_rate_limit_min;
111  __u32 qp_rate_limit_max;
112  __u32 supported_qpts;
113  __u32 reserved;
114};
115struct mlx5_ib_query_device_resp {
116  __u32 comp_mask;
117  __u32 response_length;
118  struct mlx5_ib_tso_caps tso_caps;
119  struct mlx5_ib_rss_caps rss_caps;
120  struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
121  struct mlx5_packet_pacing_caps packet_pacing_caps;
122  __u32 mlx5_ib_support_multi_pkt_send_wqes;
123  __u32 reserved;
124};
125struct mlx5_ib_create_cq {
126  __u64 buf_addr;
127  __u64 db_addr;
128  __u32 cqe_size;
129  __u8 cqe_comp_en;
130  __u8 cqe_comp_res_format;
131  __u16 reserved;
132};
133struct mlx5_ib_create_cq_resp {
134  __u32 cqn;
135  __u32 reserved;
136};
137struct mlx5_ib_resize_cq {
138  __u64 buf_addr;
139  __u16 cqe_size;
140  __u16 reserved0;
141  __u32 reserved1;
142};
143struct mlx5_ib_create_srq {
144  __u64 buf_addr;
145  __u64 db_addr;
146  __u32 flags;
147  __u32 reserved0;
148  __u32 uidx;
149  __u32 reserved1;
150};
151struct mlx5_ib_create_srq_resp {
152  __u32 srqn;
153  __u32 reserved;
154};
155struct mlx5_ib_create_qp {
156  __u64 buf_addr;
157  __u64 db_addr;
158  __u32 sq_wqe_count;
159  __u32 rq_wqe_count;
160  __u32 rq_wqe_shift;
161  __u32 flags;
162  __u32 uidx;
163  __u32 reserved0;
164  __u64 sq_buf_addr;
165};
166enum mlx5_rx_hash_function_flags {
167  MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
168};
169enum mlx5_rx_hash_fields {
170  MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
171  MLX5_RX_HASH_DST_IPV4 = 1 << 1,
172  MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
173  MLX5_RX_HASH_DST_IPV6 = 1 << 3,
174  MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
175  MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
176  MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
177  MLX5_RX_HASH_DST_PORT_UDP = 1 << 7
178};
179struct mlx5_ib_create_qp_rss {
180  __u64 rx_hash_fields_mask;
181  __u8 rx_hash_function;
182  __u8 rx_key_len;
183  __u8 reserved[6];
184  __u8 rx_hash_key[128];
185  __u32 comp_mask;
186  __u32 reserved1;
187};
188struct mlx5_ib_create_qp_resp {
189  __u32 bfreg_index;
190};
191struct mlx5_ib_alloc_mw {
192  __u32 comp_mask;
193  __u8 num_klms;
194  __u8 reserved1;
195  __u16 reserved2;
196};
197struct mlx5_ib_create_wq {
198  __u64 buf_addr;
199  __u64 db_addr;
200  __u32 rq_wqe_count;
201  __u32 rq_wqe_shift;
202  __u32 user_index;
203  __u32 flags;
204  __u32 comp_mask;
205  __u32 reserved;
206};
207struct mlx5_ib_create_ah_resp {
208  __u32 response_length;
209  __u8 dmac[ETH_ALEN];
210  __u8 reserved[6];
211};
212struct mlx5_ib_create_wq_resp {
213  __u32 response_length;
214  __u32 reserved;
215};
216struct mlx5_ib_create_rwq_ind_tbl_resp {
217  __u32 response_length;
218  __u32 reserved;
219};
220struct mlx5_ib_modify_wq {
221  __u32 comp_mask;
222  __u32 reserved;
223};
224#endif
225