1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI__SOUND_EMU10K1_H
20#define _UAPI__SOUND_EMU10K1_H
21#include <linux/types.h>
22#include <sound/asound.h>
23#define EMU10K1_CARD_CREATIVE 0x00000000
24#define EMU10K1_CARD_EMUAPS 0x00000001
25#define EMU10K1_FX8010_PCM_COUNT 8
26#define __EMU10K1_DECLARE_BITMAP(name,bits) unsigned long name[(bits) / (sizeof(unsigned long) * 8)]
27#define iMAC0 0x00
28#define iMAC1 0x01
29#define iMAC2 0x02
30#define iMAC3 0x03
31#define iMACINT0 0x04
32#define iMACINT1 0x05
33#define iACC3 0x06
34#define iMACMV 0x07
35#define iANDXOR 0x08
36#define iTSTNEG 0x09
37#define iLIMITGE 0x0a
38#define iLIMITLT 0x0b
39#define iLOG 0x0c
40#define iEXP 0x0d
41#define iINTERP 0x0e
42#define iSKIP 0x0f
43#define FXBUS(x) (0x00 + (x))
44#define EXTIN(x) (0x10 + (x))
45#define EXTOUT(x) (0x20 + (x))
46#define FXBUS2(x) (0x30 + (x))
47#define C_00000000 0x40
48#define C_00000001 0x41
49#define C_00000002 0x42
50#define C_00000003 0x43
51#define C_00000004 0x44
52#define C_00000008 0x45
53#define C_00000010 0x46
54#define C_00000020 0x47
55#define C_00000100 0x48
56#define C_00010000 0x49
57#define C_00080000 0x4a
58#define C_10000000 0x4b
59#define C_20000000 0x4c
60#define C_40000000 0x4d
61#define C_80000000 0x4e
62#define C_7fffffff 0x4f
63#define C_ffffffff 0x50
64#define C_fffffffe 0x51
65#define C_c0000000 0x52
66#define C_4f1bbcdc 0x53
67#define C_5a7ef9db 0x54
68#define C_00100000 0x55
69#define GPR_ACCU 0x56
70#define GPR_COND 0x57
71#define GPR_NOISE0 0x58
72#define GPR_NOISE1 0x59
73#define GPR_IRQ 0x5a
74#define GPR_DBAC 0x5b
75#define GPR(x) (FXGPREGBASE + (x))
76#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
77#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x))
78#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
79#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x))
80#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
81#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x))
82#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
83#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x))
84#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x))
85#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x))
86#define A_FXBUS(x) (0x00 + (x))
87#define A_EXTIN(x) (0x40 + (x))
88#define A_P16VIN(x) (0x50 + (x))
89#define A_EXTOUT(x) (0x60 + (x))
90#define A_FXBUS2(x) (0x80 + (x))
91#define A_EMU32OUTH(x) (0xa0 + (x))
92#define A_EMU32OUTL(x) (0xb0 + (x))
93#define A3_EMU32IN(x) (0x160 + (x))
94#define A3_EMU32OUT(x) (0x1E0 + (x))
95#define A_GPR(x) (A_FXGPREGBASE + (x))
96#define CC_REG_NORMALIZED C_00000001
97#define CC_REG_BORROW C_00000002
98#define CC_REG_MINUS C_00000004
99#define CC_REG_ZERO C_00000008
100#define CC_REG_SATURATE C_00000010
101#define CC_REG_NONZERO C_00000100
102#define FXBUS_PCM_LEFT 0x00
103#define FXBUS_PCM_RIGHT 0x01
104#define FXBUS_PCM_LEFT_REAR 0x02
105#define FXBUS_PCM_RIGHT_REAR 0x03
106#define FXBUS_MIDI_LEFT 0x04
107#define FXBUS_MIDI_RIGHT 0x05
108#define FXBUS_PCM_CENTER 0x06
109#define FXBUS_PCM_LFE 0x07
110#define FXBUS_PCM_LEFT_FRONT 0x08
111#define FXBUS_PCM_RIGHT_FRONT 0x09
112#define FXBUS_MIDI_REVERB 0x0c
113#define FXBUS_MIDI_CHORUS 0x0d
114#define FXBUS_PCM_LEFT_SIDE 0x0e
115#define FXBUS_PCM_RIGHT_SIDE 0x0f
116#define FXBUS_PT_LEFT 0x14
117#define FXBUS_PT_RIGHT 0x15
118#define EXTIN_AC97_L 0x00
119#define EXTIN_AC97_R 0x01
120#define EXTIN_SPDIF_CD_L 0x02
121#define EXTIN_SPDIF_CD_R 0x03
122#define EXTIN_ZOOM_L 0x04
123#define EXTIN_ZOOM_R 0x05
124#define EXTIN_TOSLINK_L 0x06
125#define EXTIN_TOSLINK_R 0x07
126#define EXTIN_LINE1_L 0x08
127#define EXTIN_LINE1_R 0x09
128#define EXTIN_COAX_SPDIF_L 0x0a
129#define EXTIN_COAX_SPDIF_R 0x0b
130#define EXTIN_LINE2_L 0x0c
131#define EXTIN_LINE2_R 0x0d
132#define EXTOUT_AC97_L 0x00
133#define EXTOUT_AC97_R 0x01
134#define EXTOUT_TOSLINK_L 0x02
135#define EXTOUT_TOSLINK_R 0x03
136#define EXTOUT_AC97_CENTER 0x04
137#define EXTOUT_AC97_LFE 0x05
138#define EXTOUT_HEADPHONE_L 0x06
139#define EXTOUT_HEADPHONE_R 0x07
140#define EXTOUT_REAR_L 0x08
141#define EXTOUT_REAR_R 0x09
142#define EXTOUT_ADC_CAP_L 0x0a
143#define EXTOUT_ADC_CAP_R 0x0b
144#define EXTOUT_MIC_CAP 0x0c
145#define EXTOUT_AC97_REAR_L 0x0d
146#define EXTOUT_AC97_REAR_R 0x0e
147#define EXTOUT_ACENTER 0x11
148#define EXTOUT_ALFE 0x12
149#define A_EXTIN_AC97_L 0x00
150#define A_EXTIN_AC97_R 0x01
151#define A_EXTIN_SPDIF_CD_L 0x02
152#define A_EXTIN_SPDIF_CD_R 0x03
153#define A_EXTIN_OPT_SPDIF_L 0x04
154#define A_EXTIN_OPT_SPDIF_R 0x05
155#define A_EXTIN_LINE2_L 0x08
156#define A_EXTIN_LINE2_R 0x09
157#define A_EXTIN_ADC_L 0x0a
158#define A_EXTIN_ADC_R 0x0b
159#define A_EXTIN_AUX2_L 0x0c
160#define A_EXTIN_AUX2_R 0x0d
161#define A_EXTOUT_FRONT_L 0x00
162#define A_EXTOUT_FRONT_R 0x01
163#define A_EXTOUT_CENTER 0x02
164#define A_EXTOUT_LFE 0x03
165#define A_EXTOUT_HEADPHONE_L 0x04
166#define A_EXTOUT_HEADPHONE_R 0x05
167#define A_EXTOUT_REAR_L 0x06
168#define A_EXTOUT_REAR_R 0x07
169#define A_EXTOUT_AFRONT_L 0x08
170#define A_EXTOUT_AFRONT_R 0x09
171#define A_EXTOUT_ACENTER 0x0a
172#define A_EXTOUT_ALFE 0x0b
173#define A_EXTOUT_ASIDE_L 0x0c
174#define A_EXTOUT_ASIDE_R 0x0d
175#define A_EXTOUT_AREAR_L 0x0e
176#define A_EXTOUT_AREAR_R 0x0f
177#define A_EXTOUT_AC97_L 0x10
178#define A_EXTOUT_AC97_R 0x11
179#define A_EXTOUT_ADC_CAP_L 0x16
180#define A_EXTOUT_ADC_CAP_R 0x17
181#define A_EXTOUT_MIC_CAP 0x18
182#define A_C_00000000 0xc0
183#define A_C_00000001 0xc1
184#define A_C_00000002 0xc2
185#define A_C_00000003 0xc3
186#define A_C_00000004 0xc4
187#define A_C_00000008 0xc5
188#define A_C_00000010 0xc6
189#define A_C_00000020 0xc7
190#define A_C_00000100 0xc8
191#define A_C_00010000 0xc9
192#define A_C_00000800 0xca
193#define A_C_10000000 0xcb
194#define A_C_20000000 0xcc
195#define A_C_40000000 0xcd
196#define A_C_80000000 0xce
197#define A_C_7fffffff 0xcf
198#define A_C_ffffffff 0xd0
199#define A_C_fffffffe 0xd1
200#define A_C_c0000000 0xd2
201#define A_C_4f1bbcdc 0xd3
202#define A_C_5a7ef9db 0xd4
203#define A_C_00100000 0xd5
204#define A_GPR_ACCU 0xd6
205#define A_GPR_COND 0xd7
206#define A_GPR_NOISE0 0xd8
207#define A_GPR_NOISE1 0xd9
208#define A_GPR_IRQ 0xda
209#define A_GPR_DBAC 0xdb
210#define A_GPR_DBACE 0xde
211#define EMU10K1_DBG_ZC 0x80000000
212#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000
213#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000
214#define EMU10K1_DBG_SINGLE_STEP 0x00008000
215#define EMU10K1_DBG_STEP 0x00004000
216#define EMU10K1_DBG_CONDITION_CODE 0x00003e00
217#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff
218#define TANKMEMADDRREG_ADDR_MASK 0x000fffff
219#define TANKMEMADDRREG_CLEAR 0x00800000
220#define TANKMEMADDRREG_ALIGN 0x00400000
221#define TANKMEMADDRREG_WRITE 0x00200000
222#define TANKMEMADDRREG_READ 0x00100000
223struct snd_emu10k1_fx8010_info {
224  unsigned int internal_tram_size;
225  unsigned int external_tram_size;
226  char fxbus_names[16][32];
227  char extin_names[16][32];
228  char extout_names[32][32];
229  unsigned int gpr_controls;
230};
231#define EMU10K1_GPR_TRANSLATION_NONE 0
232#define EMU10K1_GPR_TRANSLATION_TABLE100 1
233#define EMU10K1_GPR_TRANSLATION_BASS 2
234#define EMU10K1_GPR_TRANSLATION_TREBLE 3
235#define EMU10K1_GPR_TRANSLATION_ONOFF 4
236struct snd_emu10k1_fx8010_control_gpr {
237  struct snd_ctl_elem_id id;
238  unsigned int vcount;
239  unsigned int count;
240  unsigned short gpr[32];
241  unsigned int value[32];
242  unsigned int min;
243  unsigned int max;
244  unsigned int translation;
245  const unsigned int * tlv;
246};
247struct snd_emu10k1_fx8010_control_old_gpr {
248  struct snd_ctl_elem_id id;
249  unsigned int vcount;
250  unsigned int count;
251  unsigned short gpr[32];
252  unsigned int value[32];
253  unsigned int min;
254  unsigned int max;
255  unsigned int translation;
256};
257struct snd_emu10k1_fx8010_code {
258  char name[128];
259  __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200);
260  __u32 __user * gpr_map;
261  unsigned int gpr_add_control_count;
262  struct snd_emu10k1_fx8010_control_gpr __user * gpr_add_controls;
263  unsigned int gpr_del_control_count;
264  struct snd_ctl_elem_id __user * gpr_del_controls;
265  unsigned int gpr_list_control_count;
266  unsigned int gpr_list_control_total;
267  struct snd_emu10k1_fx8010_control_gpr __user * gpr_list_controls;
268  __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100);
269  __u32 __user * tram_data_map;
270  __u32 __user * tram_addr_map;
271  __EMU10K1_DECLARE_BITMAP(code_valid, 1024);
272  __u32 __user * code;
273};
274struct snd_emu10k1_fx8010_tram {
275  unsigned int address;
276  unsigned int size;
277  unsigned int * samples;
278};
279struct snd_emu10k1_fx8010_pcm_rec {
280  unsigned int substream;
281  unsigned int res1;
282  unsigned int channels;
283  unsigned int tram_start;
284  unsigned int buffer_size;
285  unsigned short gpr_size;
286  unsigned short gpr_ptr;
287  unsigned short gpr_count;
288  unsigned short gpr_tmpcount;
289  unsigned short gpr_trigger;
290  unsigned short gpr_running;
291  unsigned char pad;
292  unsigned char etram[32];
293  unsigned int res2;
294};
295#define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
296#define SNDRV_EMU10K1_IOCTL_INFO _IOR('H', 0x10, struct snd_emu10k1_fx8010_info)
297#define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW('H', 0x11, struct snd_emu10k1_fx8010_code)
298#define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
299#define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW('H', 0x20, int)
300#define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW('H', 0x21, struct snd_emu10k1_fx8010_tram)
301#define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
302#define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
303#define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
304#define SNDRV_EMU10K1_IOCTL_PVERSION _IOR('H', 0x40, int)
305#define SNDRV_EMU10K1_IOCTL_STOP _IO('H', 0x80)
306#define SNDRV_EMU10K1_IOCTL_CONTINUE _IO('H', 0x81)
307#define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO('H', 0x82)
308#define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW('H', 0x83, int)
309#define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR('H', 0x84, int)
310typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t;
311typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t;
312typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t;
313typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t;
314typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t;
315#endif
316