1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _DRM_MODE_H
20#define _DRM_MODE_H
21#include "drm.h"
22#ifdef __cplusplus
23#endif
24#define DRM_DISPLAY_INFO_LEN 32
25#define DRM_CONNECTOR_NAME_LEN 32
26#define DRM_DISPLAY_MODE_LEN 32
27#define DRM_PROP_NAME_LEN 32
28#define DRM_MODE_TYPE_BUILTIN (1 << 0)
29#define DRM_MODE_TYPE_CLOCK_C ((1 << 1) | DRM_MODE_TYPE_BUILTIN)
30#define DRM_MODE_TYPE_CRTC_C ((1 << 2) | DRM_MODE_TYPE_BUILTIN)
31#define DRM_MODE_TYPE_PREFERRED (1 << 3)
32#define DRM_MODE_TYPE_DEFAULT (1 << 4)
33#define DRM_MODE_TYPE_USERDEF (1 << 5)
34#define DRM_MODE_TYPE_DRIVER (1 << 6)
35#define DRM_MODE_FLAG_PHSYNC (1 << 0)
36#define DRM_MODE_FLAG_NHSYNC (1 << 1)
37#define DRM_MODE_FLAG_PVSYNC (1 << 2)
38#define DRM_MODE_FLAG_NVSYNC (1 << 3)
39#define DRM_MODE_FLAG_INTERLACE (1 << 4)
40#define DRM_MODE_FLAG_DBLSCAN (1 << 5)
41#define DRM_MODE_FLAG_CSYNC (1 << 6)
42#define DRM_MODE_FLAG_PCSYNC (1 << 7)
43#define DRM_MODE_FLAG_NCSYNC (1 << 8)
44#define DRM_MODE_FLAG_HSKEW (1 << 9)
45#define DRM_MODE_FLAG_BCAST (1 << 10)
46#define DRM_MODE_FLAG_PIXMUX (1 << 11)
47#define DRM_MODE_FLAG_DBLCLK (1 << 12)
48#define DRM_MODE_FLAG_CLKDIV2 (1 << 13)
49#define DRM_MODE_FLAG_3D_MASK (0x1f << 14)
50#define DRM_MODE_FLAG_3D_NONE (0 << 14)
51#define DRM_MODE_FLAG_3D_FRAME_PACKING (1 << 14)
52#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2 << 14)
53#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3 << 14)
54#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4 << 14)
55#define DRM_MODE_FLAG_3D_L_DEPTH (5 << 14)
56#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6 << 14)
57#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7 << 14)
58#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8 << 14)
59#define DRM_MODE_PICTURE_ASPECT_NONE 0
60#define DRM_MODE_PICTURE_ASPECT_4_3 1
61#define DRM_MODE_PICTURE_ASPECT_16_9 2
62#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F << 19)
63#define DRM_MODE_FLAG_PIC_AR_NONE (DRM_MODE_PICTURE_ASPECT_NONE << 19)
64#define DRM_MODE_FLAG_PIC_AR_4_3 (DRM_MODE_PICTURE_ASPECT_4_3 << 19)
65#define DRM_MODE_FLAG_PIC_AR_16_9 (DRM_MODE_PICTURE_ASPECT_16_9 << 19)
66#define DRM_MODE_DPMS_ON 0
67#define DRM_MODE_DPMS_STANDBY 1
68#define DRM_MODE_DPMS_SUSPEND 2
69#define DRM_MODE_DPMS_OFF 3
70#define DRM_MODE_SCALE_NONE 0
71#define DRM_MODE_SCALE_FULLSCREEN 1
72#define DRM_MODE_SCALE_CENTER 2
73#define DRM_MODE_SCALE_ASPECT 3
74#define DRM_MODE_DITHERING_OFF 0
75#define DRM_MODE_DITHERING_ON 1
76#define DRM_MODE_DITHERING_AUTO 2
77#define DRM_MODE_DIRTY_OFF 0
78#define DRM_MODE_DIRTY_ON 1
79#define DRM_MODE_DIRTY_ANNOTATE 2
80#define DRM_MODE_LINK_STATUS_GOOD 0
81#define DRM_MODE_LINK_STATUS_BAD 1
82#define DRM_MODE_ROTATE_0 (1 << 0)
83#define DRM_MODE_ROTATE_90 (1 << 1)
84#define DRM_MODE_ROTATE_180 (1 << 2)
85#define DRM_MODE_ROTATE_270 (1 << 3)
86#define DRM_MODE_ROTATE_MASK (DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270)
87#define DRM_MODE_REFLECT_X (1 << 4)
88#define DRM_MODE_REFLECT_Y (1 << 5)
89#define DRM_MODE_REFLECT_MASK (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y)
90struct drm_mode_modeinfo {
91  __u32 clock;
92  __u16 hdisplay;
93  __u16 hsync_start;
94  __u16 hsync_end;
95  __u16 htotal;
96  __u16 hskew;
97  __u16 vdisplay;
98  __u16 vsync_start;
99  __u16 vsync_end;
100  __u16 vtotal;
101  __u16 vscan;
102  __u32 vrefresh;
103  __u32 flags;
104  __u32 type;
105  char name[DRM_DISPLAY_MODE_LEN];
106};
107struct drm_mode_card_res {
108  __u64 fb_id_ptr;
109  __u64 crtc_id_ptr;
110  __u64 connector_id_ptr;
111  __u64 encoder_id_ptr;
112  __u32 count_fbs;
113  __u32 count_crtcs;
114  __u32 count_connectors;
115  __u32 count_encoders;
116  __u32 min_width;
117  __u32 max_width;
118  __u32 min_height;
119  __u32 max_height;
120};
121struct drm_mode_crtc {
122  __u64 set_connectors_ptr;
123  __u32 count_connectors;
124  __u32 crtc_id;
125  __u32 fb_id;
126  __u32 x;
127  __u32 y;
128  __u32 gamma_size;
129  __u32 mode_valid;
130  struct drm_mode_modeinfo mode;
131};
132#define DRM_MODE_PRESENT_TOP_FIELD (1 << 0)
133#define DRM_MODE_PRESENT_BOTTOM_FIELD (1 << 1)
134struct drm_mode_set_plane {
135  __u32 plane_id;
136  __u32 crtc_id;
137  __u32 fb_id;
138  __u32 flags;
139  __s32 crtc_x;
140  __s32 crtc_y;
141  __u32 crtc_w;
142  __u32 crtc_h;
143  __u32 src_x;
144  __u32 src_y;
145  __u32 src_h;
146  __u32 src_w;
147};
148struct drm_mode_get_plane {
149  __u32 plane_id;
150  __u32 crtc_id;
151  __u32 fb_id;
152  __u32 possible_crtcs;
153  __u32 gamma_size;
154  __u32 count_format_types;
155  __u64 format_type_ptr;
156};
157struct drm_mode_get_plane_res {
158  __u64 plane_id_ptr;
159  __u32 count_planes;
160};
161#define DRM_MODE_ENCODER_NONE 0
162#define DRM_MODE_ENCODER_DAC 1
163#define DRM_MODE_ENCODER_TMDS 2
164#define DRM_MODE_ENCODER_LVDS 3
165#define DRM_MODE_ENCODER_TVDAC 4
166#define DRM_MODE_ENCODER_VIRTUAL 5
167#define DRM_MODE_ENCODER_DSI 6
168#define DRM_MODE_ENCODER_DPMST 7
169#define DRM_MODE_ENCODER_DPI 8
170struct drm_mode_get_encoder {
171  __u32 encoder_id;
172  __u32 encoder_type;
173  __u32 crtc_id;
174  __u32 possible_crtcs;
175  __u32 possible_clones;
176};
177enum drm_mode_subconnector {
178  DRM_MODE_SUBCONNECTOR_Automatic = 0,
179  DRM_MODE_SUBCONNECTOR_Unknown = 0,
180  DRM_MODE_SUBCONNECTOR_DVID = 3,
181  DRM_MODE_SUBCONNECTOR_DVIA = 4,
182  DRM_MODE_SUBCONNECTOR_Composite = 5,
183  DRM_MODE_SUBCONNECTOR_SVIDEO = 6,
184  DRM_MODE_SUBCONNECTOR_Component = 8,
185  DRM_MODE_SUBCONNECTOR_SCART = 9,
186};
187#define DRM_MODE_CONNECTOR_Unknown 0
188#define DRM_MODE_CONNECTOR_VGA 1
189#define DRM_MODE_CONNECTOR_DVII 2
190#define DRM_MODE_CONNECTOR_DVID 3
191#define DRM_MODE_CONNECTOR_DVIA 4
192#define DRM_MODE_CONNECTOR_Composite 5
193#define DRM_MODE_CONNECTOR_SVIDEO 6
194#define DRM_MODE_CONNECTOR_LVDS 7
195#define DRM_MODE_CONNECTOR_Component 8
196#define DRM_MODE_CONNECTOR_9PinDIN 9
197#define DRM_MODE_CONNECTOR_DisplayPort 10
198#define DRM_MODE_CONNECTOR_HDMIA 11
199#define DRM_MODE_CONNECTOR_HDMIB 12
200#define DRM_MODE_CONNECTOR_TV 13
201#define DRM_MODE_CONNECTOR_eDP 14
202#define DRM_MODE_CONNECTOR_VIRTUAL 15
203#define DRM_MODE_CONNECTOR_DSI 16
204#define DRM_MODE_CONNECTOR_DPI 17
205struct drm_mode_get_connector {
206  __u64 encoders_ptr;
207  __u64 modes_ptr;
208  __u64 props_ptr;
209  __u64 prop_values_ptr;
210  __u32 count_modes;
211  __u32 count_props;
212  __u32 count_encoders;
213  __u32 encoder_id;
214  __u32 connector_id;
215  __u32 connector_type;
216  __u32 connector_type_id;
217  __u32 connection;
218  __u32 mm_width;
219  __u32 mm_height;
220  __u32 subpixel;
221  __u32 pad;
222};
223#define DRM_MODE_PROP_PENDING (1 << 0)
224#define DRM_MODE_PROP_RANGE (1 << 1)
225#define DRM_MODE_PROP_IMMUTABLE (1 << 2)
226#define DRM_MODE_PROP_ENUM (1 << 3)
227#define DRM_MODE_PROP_BLOB (1 << 4)
228#define DRM_MODE_PROP_BITMASK (1 << 5)
229#define DRM_MODE_PROP_LEGACY_TYPE (DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | DRM_MODE_PROP_BITMASK)
230#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
231#define DRM_MODE_PROP_TYPE(n) ((n) << 6)
232#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
233#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
234#define DRM_MODE_PROP_ATOMIC 0x80000000
235struct drm_mode_property_enum {
236  __u64 value;
237  char name[DRM_PROP_NAME_LEN];
238};
239struct drm_mode_get_property {
240  __u64 values_ptr;
241  __u64 enum_blob_ptr;
242  __u32 prop_id;
243  __u32 flags;
244  char name[DRM_PROP_NAME_LEN];
245  __u32 count_values;
246  __u32 count_enum_blobs;
247};
248struct drm_mode_connector_set_property {
249  __u64 value;
250  __u32 prop_id;
251  __u32 connector_id;
252};
253#define DRM_MODE_OBJECT_CRTC 0xcccccccc
254#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
255#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
256#define DRM_MODE_OBJECT_MODE 0xdededede
257#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
258#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
259#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
260#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
261#define DRM_MODE_OBJECT_ANY 0
262struct drm_mode_obj_get_properties {
263  __u64 props_ptr;
264  __u64 prop_values_ptr;
265  __u32 count_props;
266  __u32 obj_id;
267  __u32 obj_type;
268};
269struct drm_mode_obj_set_property {
270  __u64 value;
271  __u32 prop_id;
272  __u32 obj_id;
273  __u32 obj_type;
274};
275struct drm_mode_get_blob {
276  __u32 blob_id;
277  __u32 length;
278  __u64 data;
279};
280struct drm_mode_fb_cmd {
281  __u32 fb_id;
282  __u32 width;
283  __u32 height;
284  __u32 pitch;
285  __u32 bpp;
286  __u32 depth;
287  __u32 handle;
288};
289#define DRM_MODE_FB_INTERLACED (1 << 0)
290#define DRM_MODE_FB_MODIFIERS (1 << 1)
291struct drm_mode_fb_cmd2 {
292  __u32 fb_id;
293  __u32 width;
294  __u32 height;
295  __u32 pixel_format;
296  __u32 flags;
297  __u32 handles[4];
298  __u32 pitches[4];
299  __u32 offsets[4];
300  __u64 modifier[4];
301};
302#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
303#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
304#define DRM_MODE_FB_DIRTY_FLAGS 0x03
305#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
306struct drm_mode_fb_dirty_cmd {
307  __u32 fb_id;
308  __u32 flags;
309  __u32 color;
310  __u32 num_clips;
311  __u64 clips_ptr;
312};
313struct drm_mode_mode_cmd {
314  __u32 connector_id;
315  struct drm_mode_modeinfo mode;
316};
317#define DRM_MODE_CURSOR_BO 0x01
318#define DRM_MODE_CURSOR_MOVE 0x02
319#define DRM_MODE_CURSOR_FLAGS 0x03
320struct drm_mode_cursor {
321  __u32 flags;
322  __u32 crtc_id;
323  __s32 x;
324  __s32 y;
325  __u32 width;
326  __u32 height;
327  __u32 handle;
328};
329struct drm_mode_cursor2 {
330  __u32 flags;
331  __u32 crtc_id;
332  __s32 x;
333  __s32 y;
334  __u32 width;
335  __u32 height;
336  __u32 handle;
337  __s32 hot_x;
338  __s32 hot_y;
339};
340struct drm_mode_crtc_lut {
341  __u32 crtc_id;
342  __u32 gamma_size;
343  __u64 red;
344  __u64 green;
345  __u64 blue;
346};
347struct drm_color_ctm {
348  __s64 matrix[9];
349};
350struct drm_color_lut {
351  __u16 red;
352  __u16 green;
353  __u16 blue;
354  __u16 reserved;
355};
356#define DRM_MODE_PAGE_FLIP_EVENT 0x01
357#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
358#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
359#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8
360#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)
361#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_PAGE_FLIP_TARGET)
362struct drm_mode_crtc_page_flip {
363  __u32 crtc_id;
364  __u32 fb_id;
365  __u32 flags;
366  __u32 reserved;
367  __u64 user_data;
368};
369struct drm_mode_crtc_page_flip_target {
370  __u32 crtc_id;
371  __u32 fb_id;
372  __u32 flags;
373  __u32 sequence;
374  __u64 user_data;
375};
376struct drm_mode_create_dumb {
377  __u32 height;
378  __u32 width;
379  __u32 bpp;
380  __u32 flags;
381  __u32 handle;
382  __u32 pitch;
383  __u64 size;
384};
385struct drm_mode_map_dumb {
386  __u32 handle;
387  __u32 pad;
388  __u64 offset;
389};
390struct drm_mode_destroy_dumb {
391  __u32 handle;
392};
393#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
394#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
395#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
396#define DRM_MODE_ATOMIC_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_ATOMIC_TEST_ONLY | DRM_MODE_ATOMIC_NONBLOCK | DRM_MODE_ATOMIC_ALLOW_MODESET)
397struct drm_mode_atomic {
398  __u32 flags;
399  __u32 count_objs;
400  __u64 objs_ptr;
401  __u64 count_props_ptr;
402  __u64 props_ptr;
403  __u64 prop_values_ptr;
404  __u64 reserved;
405  __u64 user_data;
406};
407struct drm_format_modifier_blob {
408#define FORMAT_BLOB_CURRENT 1
409  __u32 version;
410  __u32 flags;
411  __u32 count_formats;
412  __u32 formats_offset;
413  __u32 count_modifiers;
414  __u32 modifiers_offset;
415};
416struct drm_format_modifier {
417  __u64 formats;
418  __u32 offset;
419  __u32 pad;
420  __u64 modifier;
421};
422struct drm_mode_create_blob {
423  __u64 data;
424  __u32 length;
425  __u32 blob_id;
426};
427struct drm_mode_destroy_blob {
428  __u32 blob_id;
429};
430struct drm_mode_create_lease {
431  __u64 object_ids;
432  __u32 object_count;
433  __u32 flags;
434  __u32 lessee_id;
435  __u32 fd;
436};
437struct drm_mode_list_lessees {
438  __u32 count_lessees;
439  __u32 pad;
440  __u64 lessees_ptr;
441};
442struct drm_mode_get_lease {
443  __u32 count_objects;
444  __u32 pad;
445  __u64 objects_ptr;
446};
447struct drm_mode_revoke_lease {
448  __u32 lessee_id;
449};
450#ifdef __cplusplus
451#endif
452#endif
453