1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef _UAPI_I915_DRM_H_ 20#define _UAPI_I915_DRM_H_ 21#include "drm.h" 22#ifdef __cplusplus 23#endif 24#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 25#define I915_ERROR_UEVENT "ERROR" 26#define I915_RESET_UEVENT "RESET" 27enum i915_mocs_table_index { 28 I915_MOCS_UNCACHED, 29 I915_MOCS_PTE, 30 I915_MOCS_CACHED, 31}; 32#define I915_NR_TEX_REGIONS 255 33#define I915_LOG_MIN_TEX_REGION_SIZE 14 34typedef struct _drm_i915_init { 35 enum { 36 I915_INIT_DMA = 0x01, 37 I915_CLEANUP_DMA = 0x02, 38 I915_RESUME_DMA = 0x03 39 } func; 40 unsigned int mmio_offset; 41 int sarea_priv_offset; 42 unsigned int ring_start; 43 unsigned int ring_end; 44 unsigned int ring_size; 45 unsigned int front_offset; 46 unsigned int back_offset; 47 unsigned int depth_offset; 48 unsigned int w; 49 unsigned int h; 50 unsigned int pitch; 51 unsigned int pitch_bits; 52 unsigned int back_pitch; 53 unsigned int depth_pitch; 54 unsigned int cpp; 55 unsigned int chipset; 56} drm_i915_init_t; 57typedef struct _drm_i915_sarea { 58 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 59 int last_upload; 60 int last_enqueue; 61 int last_dispatch; 62 int ctxOwner; 63 int texAge; 64 int pf_enabled; 65 int pf_active; 66 int pf_current_page; 67 int perf_boxes; 68 int width, height; 69 drm_handle_t front_handle; 70 int front_offset; 71 int front_size; 72 drm_handle_t back_handle; 73 int back_offset; 74 int back_size; 75 drm_handle_t depth_handle; 76 int depth_offset; 77 int depth_size; 78 drm_handle_t tex_handle; 79 int tex_offset; 80 int tex_size; 81 int log_tex_granularity; 82 int pitch; 83 int rotation; 84 int rotated_offset; 85 int rotated_size; 86 int rotated_pitch; 87 int virtualX, virtualY; 88 unsigned int front_tiled; 89 unsigned int back_tiled; 90 unsigned int depth_tiled; 91 unsigned int rotated_tiled; 92 unsigned int rotated2_tiled; 93 int pipeA_x; 94 int pipeA_y; 95 int pipeA_w; 96 int pipeA_h; 97 int pipeB_x; 98 int pipeB_y; 99 int pipeB_w; 100 int pipeB_h; 101 drm_handle_t unused_handle; 102 __u32 unused1, unused2, unused3; 103 __u32 front_bo_handle; 104 __u32 back_bo_handle; 105 __u32 unused_bo_handle; 106 __u32 depth_bo_handle; 107} drm_i915_sarea_t; 108#define planeA_x pipeA_x 109#define planeA_y pipeA_y 110#define planeA_w pipeA_w 111#define planeA_h pipeA_h 112#define planeB_x pipeB_x 113#define planeB_y pipeB_y 114#define planeB_w pipeB_w 115#define planeB_h pipeB_h 116#define I915_BOX_RING_EMPTY 0x1 117#define I915_BOX_FLIP 0x2 118#define I915_BOX_WAIT 0x4 119#define I915_BOX_TEXTURE_LOAD 0x8 120#define I915_BOX_LOST_CONTEXT 0x10 121#define DRM_I915_INIT 0x00 122#define DRM_I915_FLUSH 0x01 123#define DRM_I915_FLIP 0x02 124#define DRM_I915_BATCHBUFFER 0x03 125#define DRM_I915_IRQ_EMIT 0x04 126#define DRM_I915_IRQ_WAIT 0x05 127#define DRM_I915_GETPARAM 0x06 128#define DRM_I915_SETPARAM 0x07 129#define DRM_I915_ALLOC 0x08 130#define DRM_I915_FREE 0x09 131#define DRM_I915_INIT_HEAP 0x0a 132#define DRM_I915_CMDBUFFER 0x0b 133#define DRM_I915_DESTROY_HEAP 0x0c 134#define DRM_I915_SET_VBLANK_PIPE 0x0d 135#define DRM_I915_GET_VBLANK_PIPE 0x0e 136#define DRM_I915_VBLANK_SWAP 0x0f 137#define DRM_I915_HWS_ADDR 0x11 138#define DRM_I915_GEM_INIT 0x13 139#define DRM_I915_GEM_EXECBUFFER 0x14 140#define DRM_I915_GEM_PIN 0x15 141#define DRM_I915_GEM_UNPIN 0x16 142#define DRM_I915_GEM_BUSY 0x17 143#define DRM_I915_GEM_THROTTLE 0x18 144#define DRM_I915_GEM_ENTERVT 0x19 145#define DRM_I915_GEM_LEAVEVT 0x1a 146#define DRM_I915_GEM_CREATE 0x1b 147#define DRM_I915_GEM_PREAD 0x1c 148#define DRM_I915_GEM_PWRITE 0x1d 149#define DRM_I915_GEM_MMAP 0x1e 150#define DRM_I915_GEM_SET_DOMAIN 0x1f 151#define DRM_I915_GEM_SW_FINISH 0x20 152#define DRM_I915_GEM_SET_TILING 0x21 153#define DRM_I915_GEM_GET_TILING 0x22 154#define DRM_I915_GEM_GET_APERTURE 0x23 155#define DRM_I915_GEM_MMAP_GTT 0x24 156#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 157#define DRM_I915_GEM_MADVISE 0x26 158#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 159#define DRM_I915_OVERLAY_ATTRS 0x28 160#define DRM_I915_GEM_EXECBUFFER2 0x29 161#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 162#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 163#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 164#define DRM_I915_GEM_WAIT 0x2c 165#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 166#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 167#define DRM_I915_GEM_SET_CACHING 0x2f 168#define DRM_I915_GEM_GET_CACHING 0x30 169#define DRM_I915_REG_READ 0x31 170#define DRM_I915_GET_RESET_STATS 0x32 171#define DRM_I915_GEM_USERPTR 0x33 172#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 173#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 174#define DRM_I915_PERF_OPEN 0x36 175#define DRM_I915_PERF_ADD_CONFIG 0x37 176#define DRM_I915_PERF_REMOVE_CONFIG 0x38 177#define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 178#define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH) 179#define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP) 180#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 181#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 182#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 183#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 184#define DRM_IOCTL_I915_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 185#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 186#define DRM_IOCTL_I915_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 187#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 188#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 189#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 190#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 191#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 192#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 193#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 194#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 195#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 196#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 197#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 198#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 199#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 200#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 201#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 202#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 203#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 204#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 205#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 206#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 207#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 208#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 209#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 210#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 211#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 212#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 213#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 214#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 215#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 216#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 217#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 218#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 219#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 220#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 221#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 222#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 223#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 224#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 225#define DRM_IOCTL_I915_REG_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 226#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 227#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 228#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 229#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 230#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 231#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) 232#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) 233typedef struct drm_i915_batchbuffer { 234 int start; 235 int used; 236 int DR1; 237 int DR4; 238 int num_cliprects; 239 struct drm_clip_rect __user * cliprects; 240} drm_i915_batchbuffer_t; 241typedef struct _drm_i915_cmdbuffer { 242 char __user * buf; 243 int sz; 244 int DR1; 245 int DR4; 246 int num_cliprects; 247 struct drm_clip_rect __user * cliprects; 248} drm_i915_cmdbuffer_t; 249typedef struct drm_i915_irq_emit { 250 int __user * irq_seq; 251} drm_i915_irq_emit_t; 252typedef struct drm_i915_irq_wait { 253 int irq_seq; 254} drm_i915_irq_wait_t; 255#define I915_PARAM_IRQ_ACTIVE 1 256#define I915_PARAM_ALLOW_BATCHBUFFER 2 257#define I915_PARAM_LAST_DISPATCH 3 258#define I915_PARAM_CHIPSET_ID 4 259#define I915_PARAM_HAS_GEM 5 260#define I915_PARAM_NUM_FENCES_AVAIL 6 261#define I915_PARAM_HAS_OVERLAY 7 262#define I915_PARAM_HAS_PAGEFLIPPING 8 263#define I915_PARAM_HAS_EXECBUF2 9 264#define I915_PARAM_HAS_BSD 10 265#define I915_PARAM_HAS_BLT 11 266#define I915_PARAM_HAS_RELAXED_FENCING 12 267#define I915_PARAM_HAS_COHERENT_RINGS 13 268#define I915_PARAM_HAS_EXEC_CONSTANTS 14 269#define I915_PARAM_HAS_RELAXED_DELTA 15 270#define I915_PARAM_HAS_GEN7_SOL_RESET 16 271#define I915_PARAM_HAS_LLC 17 272#define I915_PARAM_HAS_ALIASING_PPGTT 18 273#define I915_PARAM_HAS_WAIT_TIMEOUT 19 274#define I915_PARAM_HAS_SEMAPHORES 20 275#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 276#define I915_PARAM_HAS_VEBOX 22 277#define I915_PARAM_HAS_SECURE_BATCHES 23 278#define I915_PARAM_HAS_PINNED_BATCHES 24 279#define I915_PARAM_HAS_EXEC_NO_RELOC 25 280#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 281#define I915_PARAM_HAS_WT 27 282#define I915_PARAM_CMD_PARSER_VERSION 28 283#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 284#define I915_PARAM_MMAP_VERSION 30 285#define I915_PARAM_HAS_BSD2 31 286#define I915_PARAM_REVISION 32 287#define I915_PARAM_SUBSLICE_TOTAL 33 288#define I915_PARAM_EU_TOTAL 34 289#define I915_PARAM_HAS_GPU_RESET 35 290#define I915_PARAM_HAS_RESOURCE_STREAMER 36 291#define I915_PARAM_HAS_EXEC_SOFTPIN 37 292#define I915_PARAM_HAS_POOLED_EU 38 293#define I915_PARAM_MIN_EU_IN_POOL 39 294#define I915_PARAM_MMAP_GTT_VERSION 40 295#define I915_PARAM_HAS_SCHEDULER 41 296#define I915_SCHEDULER_CAP_ENABLED (1ul << 0) 297#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) 298#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) 299#define I915_PARAM_HUC_STATUS 42 300#define I915_PARAM_HAS_EXEC_ASYNC 43 301#define I915_PARAM_HAS_EXEC_FENCE 44 302#define I915_PARAM_HAS_EXEC_CAPTURE 45 303#define I915_PARAM_SLICE_MASK 46 304#define I915_PARAM_SUBSLICE_MASK 47 305#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 306#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 307typedef struct drm_i915_getparam { 308 __s32 param; 309 int __user * value; 310} drm_i915_getparam_t; 311#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 312#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 313#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 314#define I915_SETPARAM_NUM_USED_FENCES 4 315typedef struct drm_i915_setparam { 316 int param; 317 int value; 318} drm_i915_setparam_t; 319#define I915_MEM_REGION_AGP 1 320typedef struct drm_i915_mem_alloc { 321 int region; 322 int alignment; 323 int size; 324 int __user * region_offset; 325} drm_i915_mem_alloc_t; 326typedef struct drm_i915_mem_free { 327 int region; 328 int region_offset; 329} drm_i915_mem_free_t; 330typedef struct drm_i915_mem_init_heap { 331 int region; 332 int size; 333 int start; 334} drm_i915_mem_init_heap_t; 335typedef struct drm_i915_mem_destroy_heap { 336 int region; 337} drm_i915_mem_destroy_heap_t; 338#define DRM_I915_VBLANK_PIPE_A 1 339#define DRM_I915_VBLANK_PIPE_B 2 340typedef struct drm_i915_vblank_pipe { 341 int pipe; 342} drm_i915_vblank_pipe_t; 343typedef struct drm_i915_vblank_swap { 344 drm_drawable_t drawable; 345 enum drm_vblank_seq_type seqtype; 346 unsigned int sequence; 347} drm_i915_vblank_swap_t; 348typedef struct drm_i915_hws_addr { 349 __u64 addr; 350} drm_i915_hws_addr_t; 351struct drm_i915_gem_init { 352 __u64 gtt_start; 353 __u64 gtt_end; 354}; 355struct drm_i915_gem_create { 356 __u64 size; 357 __u32 handle; 358 __u32 pad; 359}; 360struct drm_i915_gem_pread { 361 __u32 handle; 362 __u32 pad; 363 __u64 offset; 364 __u64 size; 365 __u64 data_ptr; 366}; 367struct drm_i915_gem_pwrite { 368 __u32 handle; 369 __u32 pad; 370 __u64 offset; 371 __u64 size; 372 __u64 data_ptr; 373}; 374struct drm_i915_gem_mmap { 375 __u32 handle; 376 __u32 pad; 377 __u64 offset; 378 __u64 size; 379 __u64 addr_ptr; 380 __u64 flags; 381#define I915_MMAP_WC 0x1 382}; 383struct drm_i915_gem_mmap_gtt { 384 __u32 handle; 385 __u32 pad; 386 __u64 offset; 387}; 388struct drm_i915_gem_set_domain { 389 __u32 handle; 390 __u32 read_domains; 391 __u32 write_domain; 392}; 393struct drm_i915_gem_sw_finish { 394 __u32 handle; 395}; 396struct drm_i915_gem_relocation_entry { 397 __u32 target_handle; 398 __u32 delta; 399 __u64 offset; 400 __u64 presumed_offset; 401 __u32 read_domains; 402 __u32 write_domain; 403}; 404#define I915_GEM_DOMAIN_CPU 0x00000001 405#define I915_GEM_DOMAIN_RENDER 0x00000002 406#define I915_GEM_DOMAIN_SAMPLER 0x00000004 407#define I915_GEM_DOMAIN_COMMAND 0x00000008 408#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 409#define I915_GEM_DOMAIN_VERTEX 0x00000020 410#define I915_GEM_DOMAIN_GTT 0x00000040 411#define I915_GEM_DOMAIN_WC 0x00000080 412struct drm_i915_gem_exec_object { 413 __u32 handle; 414 __u32 relocation_count; 415 __u64 relocs_ptr; 416 __u64 alignment; 417 __u64 offset; 418}; 419struct drm_i915_gem_execbuffer { 420 __u64 buffers_ptr; 421 __u32 buffer_count; 422 __u32 batch_start_offset; 423 __u32 batch_len; 424 __u32 DR1; 425 __u32 DR4; 426 __u32 num_cliprects; 427 __u64 cliprects_ptr; 428}; 429struct drm_i915_gem_exec_object2 { 430 __u32 handle; 431 __u32 relocation_count; 432 __u64 relocs_ptr; 433 __u64 alignment; 434 __u64 offset; 435#define EXEC_OBJECT_NEEDS_FENCE (1 << 0) 436#define EXEC_OBJECT_NEEDS_GTT (1 << 1) 437#define EXEC_OBJECT_WRITE (1 << 2) 438#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1 << 3) 439#define EXEC_OBJECT_PINNED (1 << 4) 440#define EXEC_OBJECT_PAD_TO_SIZE (1 << 5) 441#define EXEC_OBJECT_ASYNC (1 << 6) 442#define EXEC_OBJECT_CAPTURE (1 << 7) 443#define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_CAPTURE << 1) 444 __u64 flags; 445 union { 446 __u64 rsvd1; 447 __u64 pad_to_size; 448 }; 449 __u64 rsvd2; 450}; 451struct drm_i915_gem_exec_fence { 452 __u32 handle; 453#define I915_EXEC_FENCE_WAIT (1 << 0) 454#define I915_EXEC_FENCE_SIGNAL (1 << 1) 455#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (- (I915_EXEC_FENCE_SIGNAL << 1)) 456 __u32 flags; 457}; 458struct drm_i915_gem_execbuffer2 { 459 __u64 buffers_ptr; 460 __u32 buffer_count; 461 __u32 batch_start_offset; 462 __u32 batch_len; 463 __u32 DR1; 464 __u32 DR4; 465 __u32 num_cliprects; 466 __u64 cliprects_ptr; 467#define I915_EXEC_RING_MASK (7 << 0) 468#define I915_EXEC_DEFAULT (0 << 0) 469#define I915_EXEC_RENDER (1 << 0) 470#define I915_EXEC_BSD (2 << 0) 471#define I915_EXEC_BLT (3 << 0) 472#define I915_EXEC_VEBOX (4 << 0) 473#define I915_EXEC_CONSTANTS_MASK (3 << 6) 474#define I915_EXEC_CONSTANTS_REL_GENERAL (0 << 6) 475#define I915_EXEC_CONSTANTS_ABSOLUTE (1 << 6) 476#define I915_EXEC_CONSTANTS_REL_SURFACE (2 << 6) 477 __u64 flags; 478 __u64 rsvd1; 479 __u64 rsvd2; 480}; 481#define I915_EXEC_GEN7_SOL_RESET (1 << 8) 482#define I915_EXEC_SECURE (1 << 9) 483#define I915_EXEC_IS_PINNED (1 << 10) 484#define I915_EXEC_NO_RELOC (1 << 11) 485#define I915_EXEC_HANDLE_LUT (1 << 12) 486#define I915_EXEC_BSD_SHIFT (13) 487#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 488#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 489#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 490#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 491#define I915_EXEC_RESOURCE_STREAMER (1 << 15) 492#define I915_EXEC_FENCE_IN (1 << 16) 493#define I915_EXEC_FENCE_OUT (1 << 17) 494#define I915_EXEC_BATCH_FIRST (1 << 18) 495#define I915_EXEC_FENCE_ARRAY (1 << 19) 496#define __I915_EXEC_UNKNOWN_FLAGS (- (I915_EXEC_FENCE_ARRAY << 1)) 497#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 498#define i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 499#define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 500struct drm_i915_gem_pin { 501 __u32 handle; 502 __u32 pad; 503 __u64 alignment; 504 __u64 offset; 505}; 506struct drm_i915_gem_unpin { 507 __u32 handle; 508 __u32 pad; 509}; 510struct drm_i915_gem_busy { 511 __u32 handle; 512 __u32 busy; 513}; 514#define I915_CACHING_NONE 0 515#define I915_CACHING_CACHED 1 516#define I915_CACHING_DISPLAY 2 517struct drm_i915_gem_caching { 518 __u32 handle; 519 __u32 caching; 520}; 521#define I915_TILING_NONE 0 522#define I915_TILING_X 1 523#define I915_TILING_Y 2 524#define I915_TILING_LAST I915_TILING_Y 525#define I915_BIT_6_SWIZZLE_NONE 0 526#define I915_BIT_6_SWIZZLE_9 1 527#define I915_BIT_6_SWIZZLE_9_10 2 528#define I915_BIT_6_SWIZZLE_9_11 3 529#define I915_BIT_6_SWIZZLE_9_10_11 4 530#define I915_BIT_6_SWIZZLE_UNKNOWN 5 531#define I915_BIT_6_SWIZZLE_9_17 6 532#define I915_BIT_6_SWIZZLE_9_10_17 7 533struct drm_i915_gem_set_tiling { 534 __u32 handle; 535 __u32 tiling_mode; 536 __u32 stride; 537 __u32 swizzle_mode; 538}; 539struct drm_i915_gem_get_tiling { 540 __u32 handle; 541 __u32 tiling_mode; 542 __u32 swizzle_mode; 543 __u32 phys_swizzle_mode; 544}; 545struct drm_i915_gem_get_aperture { 546 __u64 aper_size; 547 __u64 aper_available_size; 548}; 549struct drm_i915_get_pipe_from_crtc_id { 550 __u32 crtc_id; 551 __u32 pipe; 552}; 553#define I915_MADV_WILLNEED 0 554#define I915_MADV_DONTNEED 1 555#define __I915_MADV_PURGED 2 556struct drm_i915_gem_madvise { 557 __u32 handle; 558 __u32 madv; 559 __u32 retained; 560}; 561#define I915_OVERLAY_TYPE_MASK 0xff 562#define I915_OVERLAY_YUV_PLANAR 0x01 563#define I915_OVERLAY_YUV_PACKED 0x02 564#define I915_OVERLAY_RGB 0x03 565#define I915_OVERLAY_DEPTH_MASK 0xff00 566#define I915_OVERLAY_RGB24 0x1000 567#define I915_OVERLAY_RGB16 0x2000 568#define I915_OVERLAY_RGB15 0x3000 569#define I915_OVERLAY_YUV422 0x0100 570#define I915_OVERLAY_YUV411 0x0200 571#define I915_OVERLAY_YUV420 0x0300 572#define I915_OVERLAY_YUV410 0x0400 573#define I915_OVERLAY_SWAP_MASK 0xff0000 574#define I915_OVERLAY_NO_SWAP 0x000000 575#define I915_OVERLAY_UV_SWAP 0x010000 576#define I915_OVERLAY_Y_SWAP 0x020000 577#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 578#define I915_OVERLAY_FLAGS_MASK 0xff000000 579#define I915_OVERLAY_ENABLE 0x01000000 580struct drm_intel_overlay_put_image { 581 __u32 flags; 582 __u32 bo_handle; 583 __u16 stride_Y; 584 __u16 stride_UV; 585 __u32 offset_Y; 586 __u32 offset_U; 587 __u32 offset_V; 588 __u16 src_width; 589 __u16 src_height; 590 __u16 src_scan_width; 591 __u16 src_scan_height; 592 __u32 crtc_id; 593 __u16 dst_x; 594 __u16 dst_y; 595 __u16 dst_width; 596 __u16 dst_height; 597}; 598#define I915_OVERLAY_UPDATE_ATTRS (1 << 0) 599#define I915_OVERLAY_UPDATE_GAMMA (1 << 1) 600#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1 << 2) 601struct drm_intel_overlay_attrs { 602 __u32 flags; 603 __u32 color_key; 604 __s32 brightness; 605 __u32 contrast; 606 __u32 saturation; 607 __u32 gamma0; 608 __u32 gamma1; 609 __u32 gamma2; 610 __u32 gamma3; 611 __u32 gamma4; 612 __u32 gamma5; 613}; 614#define I915_SET_COLORKEY_NONE (1 << 0) 615#define I915_SET_COLORKEY_DESTINATION (1 << 1) 616#define I915_SET_COLORKEY_SOURCE (1 << 2) 617struct drm_intel_sprite_colorkey { 618 __u32 plane_id; 619 __u32 min_value; 620 __u32 channel_mask; 621 __u32 max_value; 622 __u32 flags; 623}; 624struct drm_i915_gem_wait { 625 __u32 bo_handle; 626 __u32 flags; 627 __s64 timeout_ns; 628}; 629struct drm_i915_gem_context_create { 630 __u32 ctx_id; 631 __u32 pad; 632}; 633struct drm_i915_gem_context_destroy { 634 __u32 ctx_id; 635 __u32 pad; 636}; 637struct drm_i915_reg_read { 638 __u64 offset; 639#define I915_REG_READ_8B_WA (1ul << 0) 640 __u64 val; 641}; 642struct drm_i915_reset_stats { 643 __u32 ctx_id; 644 __u32 flags; 645 __u32 reset_count; 646 __u32 batch_active; 647 __u32 batch_pending; 648 __u32 pad; 649}; 650struct drm_i915_gem_userptr { 651 __u64 user_ptr; 652 __u64 user_size; 653 __u32 flags; 654#define I915_USERPTR_READ_ONLY 0x1 655#define I915_USERPTR_UNSYNCHRONIZED 0x80000000 656 __u32 handle; 657}; 658struct drm_i915_gem_context_param { 659 __u32 ctx_id; 660 __u32 size; 661 __u64 param; 662#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 663#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 664#define I915_CONTEXT_PARAM_GTT_SIZE 0x3 665#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 666#define I915_CONTEXT_PARAM_BANNABLE 0x5 667#define I915_CONTEXT_PARAM_PRIORITY 0x6 668#define I915_CONTEXT_MAX_USER_PRIORITY 1023 669#define I915_CONTEXT_DEFAULT_PRIORITY 0 670#define I915_CONTEXT_MIN_USER_PRIORITY - 1023 671 __u64 value; 672}; 673enum drm_i915_oa_format { 674 I915_OA_FORMAT_A13 = 1, 675 I915_OA_FORMAT_A29, 676 I915_OA_FORMAT_A13_B8_C8, 677 I915_OA_FORMAT_B4_C8, 678 I915_OA_FORMAT_A45_B8_C8, 679 I915_OA_FORMAT_B4_C8_A16, 680 I915_OA_FORMAT_C4_B8, 681 I915_OA_FORMAT_A12, 682 I915_OA_FORMAT_A12_B8_C8, 683 I915_OA_FORMAT_A32u40_A4u32_B8_C8, 684 I915_OA_FORMAT_MAX 685}; 686enum drm_i915_perf_property_id { 687 DRM_I915_PERF_PROP_CTX_HANDLE = 1, 688 DRM_I915_PERF_PROP_SAMPLE_OA, 689 DRM_I915_PERF_PROP_OA_METRICS_SET, 690 DRM_I915_PERF_PROP_OA_FORMAT, 691 DRM_I915_PERF_PROP_OA_EXPONENT, 692 DRM_I915_PERF_PROP_MAX 693}; 694struct drm_i915_perf_open_param { 695 __u32 flags; 696#define I915_PERF_FLAG_FD_CLOEXEC (1 << 0) 697#define I915_PERF_FLAG_FD_NONBLOCK (1 << 1) 698#define I915_PERF_FLAG_DISABLED (1 << 2) 699 __u32 num_properties; 700 __u64 properties_ptr; 701}; 702#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 703#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 704struct drm_i915_perf_record_header { 705 __u32 type; 706 __u16 pad; 707 __u16 size; 708}; 709enum drm_i915_perf_record_type { 710 DRM_I915_PERF_RECORD_SAMPLE = 1, 711 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 712 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 713 DRM_I915_PERF_RECORD_MAX 714}; 715struct drm_i915_perf_oa_config { 716 char uuid[36]; 717 __u32 n_mux_regs; 718 __u32 n_boolean_regs; 719 __u32 n_flex_regs; 720 __u64 mux_regs_ptr; 721 __u64 boolean_regs_ptr; 722 __u64 flex_regs_ptr; 723}; 724#ifdef __cplusplus 725#endif 726#endif 727