1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef KFD_IOCTL_H_INCLUDED 20#define KFD_IOCTL_H_INCLUDED 21#include <drm/drm.h> 22#include <linux/ioctl.h> 23#define KFD_IOCTL_MAJOR_VERSION 1 24#define KFD_IOCTL_MINOR_VERSION 1 25struct kfd_ioctl_get_version_args { 26 __u32 major_version; 27 __u32 minor_version; 28}; 29#define KFD_IOC_QUEUE_TYPE_COMPUTE 0 30#define KFD_IOC_QUEUE_TYPE_SDMA 1 31#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 2 32#define KFD_MAX_QUEUE_PERCENTAGE 100 33#define KFD_MAX_QUEUE_PRIORITY 15 34struct kfd_ioctl_create_queue_args { 35 __u64 ring_base_address; 36 __u64 write_pointer_address; 37 __u64 read_pointer_address; 38 __u64 doorbell_offset; 39 __u32 ring_size; 40 __u32 gpu_id; 41 __u32 queue_type; 42 __u32 queue_percentage; 43 __u32 queue_priority; 44 __u32 queue_id; 45 __u64 eop_buffer_address; 46 __u64 eop_buffer_size; 47 __u64 ctx_save_restore_address; 48 __u64 ctx_save_restore_size; 49}; 50struct kfd_ioctl_destroy_queue_args { 51 __u32 queue_id; 52 __u32 pad; 53}; 54struct kfd_ioctl_update_queue_args { 55 __u64 ring_base_address; 56 __u32 queue_id; 57 __u32 ring_size; 58 __u32 queue_percentage; 59 __u32 queue_priority; 60}; 61#define KFD_IOC_CACHE_POLICY_COHERENT 0 62#define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 63struct kfd_ioctl_set_memory_policy_args { 64 __u64 alternate_aperture_base; 65 __u64 alternate_aperture_size; 66 __u32 gpu_id; 67 __u32 default_policy; 68 __u32 alternate_policy; 69 __u32 pad; 70}; 71struct kfd_ioctl_get_clock_counters_args { 72 __u64 gpu_clock_counter; 73 __u64 cpu_clock_counter; 74 __u64 system_clock_counter; 75 __u64 system_clock_freq; 76 __u32 gpu_id; 77 __u32 pad; 78}; 79#define NUM_OF_SUPPORTED_GPUS 7 80struct kfd_process_device_apertures { 81 __u64 lds_base; 82 __u64 lds_limit; 83 __u64 scratch_base; 84 __u64 scratch_limit; 85 __u64 gpuvm_base; 86 __u64 gpuvm_limit; 87 __u32 gpu_id; 88 __u32 pad; 89}; 90struct kfd_ioctl_get_process_apertures_args { 91 struct kfd_process_device_apertures process_apertures[NUM_OF_SUPPORTED_GPUS]; 92 __u32 num_of_nodes; 93 __u32 pad; 94}; 95#define MAX_ALLOWED_NUM_POINTS 100 96#define MAX_ALLOWED_AW_BUFF_SIZE 4096 97#define MAX_ALLOWED_WAC_BUFF_SIZE 128 98struct kfd_ioctl_dbg_register_args { 99 __u32 gpu_id; 100 __u32 pad; 101}; 102struct kfd_ioctl_dbg_unregister_args { 103 __u32 gpu_id; 104 __u32 pad; 105}; 106struct kfd_ioctl_dbg_address_watch_args { 107 __u64 content_ptr; 108 __u32 gpu_id; 109 __u32 buf_size_in_bytes; 110}; 111struct kfd_ioctl_dbg_wave_control_args { 112 __u64 content_ptr; 113 __u32 gpu_id; 114 __u32 buf_size_in_bytes; 115}; 116#define KFD_IOC_EVENT_SIGNAL 0 117#define KFD_IOC_EVENT_NODECHANGE 1 118#define KFD_IOC_EVENT_DEVICESTATECHANGE 2 119#define KFD_IOC_EVENT_HW_EXCEPTION 3 120#define KFD_IOC_EVENT_SYSTEM_EVENT 4 121#define KFD_IOC_EVENT_DEBUG_EVENT 5 122#define KFD_IOC_EVENT_PROFILE_EVENT 6 123#define KFD_IOC_EVENT_QUEUE_EVENT 7 124#define KFD_IOC_EVENT_MEMORY 8 125#define KFD_IOC_WAIT_RESULT_COMPLETE 0 126#define KFD_IOC_WAIT_RESULT_TIMEOUT 1 127#define KFD_IOC_WAIT_RESULT_FAIL 2 128#define KFD_SIGNAL_EVENT_LIMIT 4096 129struct kfd_ioctl_create_event_args { 130 __u64 event_page_offset; 131 __u32 event_trigger_data; 132 __u32 event_type; 133 __u32 auto_reset; 134 __u32 node_id; 135 __u32 event_id; 136 __u32 event_slot_index; 137}; 138struct kfd_ioctl_destroy_event_args { 139 __u32 event_id; 140 __u32 pad; 141}; 142struct kfd_ioctl_set_event_args { 143 __u32 event_id; 144 __u32 pad; 145}; 146struct kfd_ioctl_reset_event_args { 147 __u32 event_id; 148 __u32 pad; 149}; 150struct kfd_memory_exception_failure { 151 __u32 NotPresent; 152 __u32 ReadOnly; 153 __u32 NoExecute; 154 __u32 pad; 155}; 156struct kfd_hsa_memory_exception_data { 157 struct kfd_memory_exception_failure failure; 158 __u64 va; 159 __u32 gpu_id; 160 __u32 pad; 161}; 162struct kfd_event_data { 163 union { 164 struct kfd_hsa_memory_exception_data memory_exception_data; 165 }; 166 __u64 kfd_event_data_ext; 167 __u32 event_id; 168 __u32 pad; 169}; 170struct kfd_ioctl_wait_events_args { 171 __u64 events_ptr; 172 __u32 num_events; 173 __u32 wait_for_all; 174 __u32 timeout; 175 __u32 wait_result; 176}; 177struct kfd_ioctl_set_scratch_backing_va_args { 178 __u64 va_addr; 179 __u32 gpu_id; 180 __u32 pad; 181}; 182struct kfd_ioctl_get_tile_config_args { 183 __u64 tile_config_ptr; 184 __u64 macro_tile_config_ptr; 185 __u32 num_tile_configs; 186 __u32 num_macro_tile_configs; 187 __u32 gpu_id; 188 __u32 gb_addr_config; 189 __u32 num_banks; 190 __u32 num_ranks; 191}; 192#define AMDKFD_IOCTL_BASE 'K' 193#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) 194#define AMDKFD_IOR(nr,type) _IOR(AMDKFD_IOCTL_BASE, nr, type) 195#define AMDKFD_IOW(nr,type) _IOW(AMDKFD_IOCTL_BASE, nr, type) 196#define AMDKFD_IOWR(nr,type) _IOWR(AMDKFD_IOCTL_BASE, nr, type) 197#define AMDKFD_IOC_GET_VERSION AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args) 198#define AMDKFD_IOC_CREATE_QUEUE AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args) 199#define AMDKFD_IOC_DESTROY_QUEUE AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args) 200#define AMDKFD_IOC_SET_MEMORY_POLICY AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args) 201#define AMDKFD_IOC_GET_CLOCK_COUNTERS AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args) 202#define AMDKFD_IOC_GET_PROCESS_APERTURES AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args) 203#define AMDKFD_IOC_UPDATE_QUEUE AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) 204#define AMDKFD_IOC_CREATE_EVENT AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args) 205#define AMDKFD_IOC_DESTROY_EVENT AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args) 206#define AMDKFD_IOC_SET_EVENT AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args) 207#define AMDKFD_IOC_RESET_EVENT AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args) 208#define AMDKFD_IOC_WAIT_EVENTS AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) 209#define AMDKFD_IOC_DBG_REGISTER AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args) 210#define AMDKFD_IOC_DBG_UNREGISTER AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args) 211#define AMDKFD_IOC_DBG_ADDRESS_WATCH AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args) 212#define AMDKFD_IOC_DBG_WAVE_CONTROL AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) 213#define AMDKFD_IOC_SET_SCRATCH_BACKING_VA AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args) 214#define AMDKFD_IOC_GET_TILE_CONFIG AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args) 215#define AMDKFD_COMMAND_START 0x01 216#define AMDKFD_COMMAND_END 0x13 217#endif 218