1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_SYNCLINK_H_
20#define _UAPI_SYNCLINK_H_
21#define SYNCLINK_H_VERSION 3.6
22#include <linux/types.h>
23#define BIT0 0x0001
24#define BIT1 0x0002
25#define BIT2 0x0004
26#define BIT3 0x0008
27#define BIT4 0x0010
28#define BIT5 0x0020
29#define BIT6 0x0040
30#define BIT7 0x0080
31#define BIT8 0x0100
32#define BIT9 0x0200
33#define BIT10 0x0400
34#define BIT11 0x0800
35#define BIT12 0x1000
36#define BIT13 0x2000
37#define BIT14 0x4000
38#define BIT15 0x8000
39#define BIT16 0x00010000
40#define BIT17 0x00020000
41#define BIT18 0x00040000
42#define BIT19 0x00080000
43#define BIT20 0x00100000
44#define BIT21 0x00200000
45#define BIT22 0x00400000
46#define BIT23 0x00800000
47#define BIT24 0x01000000
48#define BIT25 0x02000000
49#define BIT26 0x04000000
50#define BIT27 0x08000000
51#define BIT28 0x10000000
52#define BIT29 0x20000000
53#define BIT30 0x40000000
54#define BIT31 0x80000000
55#define HDLC_MAX_FRAME_SIZE 65535
56#define MAX_ASYNC_TRANSMIT 4096
57#define MAX_ASYNC_BUFFER_SIZE 4096
58#define ASYNC_PARITY_NONE 0
59#define ASYNC_PARITY_EVEN 1
60#define ASYNC_PARITY_ODD 2
61#define ASYNC_PARITY_SPACE 3
62#define HDLC_FLAG_UNDERRUN_ABORT7 0x0000
63#define HDLC_FLAG_UNDERRUN_ABORT15 0x0001
64#define HDLC_FLAG_UNDERRUN_FLAG 0x0002
65#define HDLC_FLAG_UNDERRUN_CRC 0x0004
66#define HDLC_FLAG_SHARE_ZERO 0x0010
67#define HDLC_FLAG_AUTO_CTS 0x0020
68#define HDLC_FLAG_AUTO_DCD 0x0040
69#define HDLC_FLAG_AUTO_RTS 0x0080
70#define HDLC_FLAG_RXC_DPLL 0x0100
71#define HDLC_FLAG_RXC_BRG 0x0200
72#define HDLC_FLAG_RXC_TXCPIN 0x8000
73#define HDLC_FLAG_RXC_RXCPIN 0x0000
74#define HDLC_FLAG_TXC_DPLL 0x0400
75#define HDLC_FLAG_TXC_BRG 0x0800
76#define HDLC_FLAG_TXC_TXCPIN 0x0000
77#define HDLC_FLAG_TXC_RXCPIN 0x0008
78#define HDLC_FLAG_DPLL_DIV8 0x1000
79#define HDLC_FLAG_DPLL_DIV16 0x2000
80#define HDLC_FLAG_DPLL_DIV32 0x0000
81#define HDLC_FLAG_HDLC_LOOPMODE 0x4000
82#define HDLC_CRC_NONE 0
83#define HDLC_CRC_16_CCITT 1
84#define HDLC_CRC_32_CCITT 2
85#define HDLC_CRC_MASK 0x00ff
86#define HDLC_CRC_RETURN_EX 0x8000
87#define RX_OK 0
88#define RX_CRC_ERROR 1
89#define HDLC_TXIDLE_FLAGS 0
90#define HDLC_TXIDLE_ALT_ZEROS_ONES 1
91#define HDLC_TXIDLE_ZEROS 2
92#define HDLC_TXIDLE_ONES 3
93#define HDLC_TXIDLE_ALT_MARK_SPACE 4
94#define HDLC_TXIDLE_SPACE 5
95#define HDLC_TXIDLE_MARK 6
96#define HDLC_TXIDLE_CUSTOM_8 0x10000000
97#define HDLC_TXIDLE_CUSTOM_16 0x20000000
98#define HDLC_ENCODING_NRZ 0
99#define HDLC_ENCODING_NRZB 1
100#define HDLC_ENCODING_NRZI_MARK 2
101#define HDLC_ENCODING_NRZI_SPACE 3
102#define HDLC_ENCODING_NRZI HDLC_ENCODING_NRZI_SPACE
103#define HDLC_ENCODING_BIPHASE_MARK 4
104#define HDLC_ENCODING_BIPHASE_SPACE 5
105#define HDLC_ENCODING_BIPHASE_LEVEL 6
106#define HDLC_ENCODING_DIFF_BIPHASE_LEVEL 7
107#define HDLC_PREAMBLE_LENGTH_8BITS 0
108#define HDLC_PREAMBLE_LENGTH_16BITS 1
109#define HDLC_PREAMBLE_LENGTH_32BITS 2
110#define HDLC_PREAMBLE_LENGTH_64BITS 3
111#define HDLC_PREAMBLE_PATTERN_NONE 0
112#define HDLC_PREAMBLE_PATTERN_ZEROS 1
113#define HDLC_PREAMBLE_PATTERN_FLAGS 2
114#define HDLC_PREAMBLE_PATTERN_10 3
115#define HDLC_PREAMBLE_PATTERN_01 4
116#define HDLC_PREAMBLE_PATTERN_ONES 5
117#define MGSL_MODE_ASYNC 1
118#define MGSL_MODE_HDLC 2
119#define MGSL_MODE_MONOSYNC 3
120#define MGSL_MODE_BISYNC 4
121#define MGSL_MODE_RAW 6
122#define MGSL_MODE_BASE_CLOCK 7
123#define MGSL_MODE_XSYNC 8
124#define MGSL_BUS_TYPE_ISA 1
125#define MGSL_BUS_TYPE_EISA 2
126#define MGSL_BUS_TYPE_PCI 5
127#define MGSL_INTERFACE_MASK 0xf
128#define MGSL_INTERFACE_DISABLE 0
129#define MGSL_INTERFACE_RS232 1
130#define MGSL_INTERFACE_V35 2
131#define MGSL_INTERFACE_RS422 3
132#define MGSL_INTERFACE_RTS_EN 0x10
133#define MGSL_INTERFACE_LL 0x20
134#define MGSL_INTERFACE_RL 0x40
135#define MGSL_INTERFACE_MSB_FIRST 0x80
136typedef struct _MGSL_PARAMS {
137  unsigned long mode;
138  unsigned char loopback;
139  unsigned short flags;
140  unsigned char encoding;
141  unsigned long clock_speed;
142  unsigned char addr_filter;
143  unsigned short crc_type;
144  unsigned char preamble_length;
145  unsigned char preamble;
146  unsigned long data_rate;
147  unsigned char data_bits;
148  unsigned char stop_bits;
149  unsigned char parity;
150} MGSL_PARAMS, * PMGSL_PARAMS;
151#define MICROGATE_VENDOR_ID 0x13c0
152#define SYNCLINK_DEVICE_ID 0x0010
153#define MGSCC_DEVICE_ID 0x0020
154#define SYNCLINK_SCA_DEVICE_ID 0x0030
155#define SYNCLINK_GT_DEVICE_ID 0x0070
156#define SYNCLINK_GT4_DEVICE_ID 0x0080
157#define SYNCLINK_AC_DEVICE_ID 0x0090
158#define SYNCLINK_GT2_DEVICE_ID 0x00A0
159#define MGSL_MAX_SERIAL_NUMBER 30
160#define DiagStatus_OK 0
161#define DiagStatus_AddressFailure 1
162#define DiagStatus_AddressConflict 2
163#define DiagStatus_IrqFailure 3
164#define DiagStatus_IrqConflict 4
165#define DiagStatus_DmaFailure 5
166#define DiagStatus_DmaConflict 6
167#define DiagStatus_PciAdapterNotFound 7
168#define DiagStatus_CantAssignPciResources 8
169#define DiagStatus_CantAssignPciMemAddr 9
170#define DiagStatus_CantAssignPciIoAddr 10
171#define DiagStatus_CantAssignPciIrq 11
172#define DiagStatus_MemoryError 12
173#define SerialSignal_DCD 0x01
174#define SerialSignal_TXD 0x02
175#define SerialSignal_RI 0x04
176#define SerialSignal_RXD 0x08
177#define SerialSignal_CTS 0x10
178#define SerialSignal_RTS 0x20
179#define SerialSignal_DSR 0x40
180#define SerialSignal_DTR 0x80
181struct mgsl_icount {
182  __u32 cts, dsr, rng, dcd, tx, rx;
183  __u32 frame, parity, overrun, brk;
184  __u32 buf_overrun;
185  __u32 txok;
186  __u32 txunder;
187  __u32 txabort;
188  __u32 txtimeout;
189  __u32 rxshort;
190  __u32 rxlong;
191  __u32 rxabort;
192  __u32 rxover;
193  __u32 rxcrc;
194  __u32 rxok;
195  __u32 exithunt;
196  __u32 rxidle;
197};
198struct gpio_desc {
199  __u32 state;
200  __u32 smask;
201  __u32 dir;
202  __u32 dmask;
203};
204#define DEBUG_LEVEL_DATA 1
205#define DEBUG_LEVEL_ERROR 2
206#define DEBUG_LEVEL_INFO 3
207#define DEBUG_LEVEL_BH 4
208#define DEBUG_LEVEL_ISR 5
209#define MgslEvent_DsrActive 0x0001
210#define MgslEvent_DsrInactive 0x0002
211#define MgslEvent_Dsr 0x0003
212#define MgslEvent_CtsActive 0x0004
213#define MgslEvent_CtsInactive 0x0008
214#define MgslEvent_Cts 0x000c
215#define MgslEvent_DcdActive 0x0010
216#define MgslEvent_DcdInactive 0x0020
217#define MgslEvent_Dcd 0x0030
218#define MgslEvent_RiActive 0x0040
219#define MgslEvent_RiInactive 0x0080
220#define MgslEvent_Ri 0x00c0
221#define MgslEvent_ExitHuntMode 0x0100
222#define MgslEvent_IdleReceived 0x0200
223#define MGSL_MAGIC_IOC 'm'
224#define MGSL_IOCSPARAMS _IOW(MGSL_MAGIC_IOC, 0, struct _MGSL_PARAMS)
225#define MGSL_IOCGPARAMS _IOR(MGSL_MAGIC_IOC, 1, struct _MGSL_PARAMS)
226#define MGSL_IOCSTXIDLE _IO(MGSL_MAGIC_IOC, 2)
227#define MGSL_IOCGTXIDLE _IO(MGSL_MAGIC_IOC, 3)
228#define MGSL_IOCTXENABLE _IO(MGSL_MAGIC_IOC, 4)
229#define MGSL_IOCRXENABLE _IO(MGSL_MAGIC_IOC, 5)
230#define MGSL_IOCTXABORT _IO(MGSL_MAGIC_IOC, 6)
231#define MGSL_IOCGSTATS _IO(MGSL_MAGIC_IOC, 7)
232#define MGSL_IOCWAITEVENT _IOWR(MGSL_MAGIC_IOC, 8, int)
233#define MGSL_IOCCLRMODCOUNT _IO(MGSL_MAGIC_IOC, 15)
234#define MGSL_IOCLOOPTXDONE _IO(MGSL_MAGIC_IOC, 9)
235#define MGSL_IOCSIF _IO(MGSL_MAGIC_IOC, 10)
236#define MGSL_IOCGIF _IO(MGSL_MAGIC_IOC, 11)
237#define MGSL_IOCSGPIO _IOW(MGSL_MAGIC_IOC, 16, struct gpio_desc)
238#define MGSL_IOCGGPIO _IOR(MGSL_MAGIC_IOC, 17, struct gpio_desc)
239#define MGSL_IOCWAITGPIO _IOWR(MGSL_MAGIC_IOC, 18, struct gpio_desc)
240#define MGSL_IOCSXSYNC _IO(MGSL_MAGIC_IOC, 19)
241#define MGSL_IOCGXSYNC _IO(MGSL_MAGIC_IOC, 20)
242#define MGSL_IOCSXCTRL _IO(MGSL_MAGIC_IOC, 21)
243#define MGSL_IOCGXCTRL _IO(MGSL_MAGIC_IOC, 22)
244#endif
245