1655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/**************************************************************************** 2655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng **************************************************************************** 3655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 4655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** This header was automatically generated from a Linux kernel header 5655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** of the same name, to make information necessary for userspace to 6655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** call into the kernel available to libc. It contains only constants, 7655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** structures, and macros generated from the original header, and thus, 8655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** contains no copyrightable information. 9655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 10655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** To edit the content of this header, modify the corresponding 11655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** source file (e.g. under external/kernel-headers/original/) then 12655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** run bionic/libc/kernel/tools/update_all.py 13655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 14655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** Any manual change here will be lost the next time this script will 15655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** be run. You've been warned! 16655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 17655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng **************************************************************************** 18655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ****************************************************************************/ 19655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#ifndef __RADEON_DRM_H__ 20655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define __RADEON_DRM_H__ 2105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#include "drm.h" 22106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#ifdef __cplusplus 23106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#endif 24106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#ifndef __RADEON_SAREA_DEFINES__ 25655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define __RADEON_SAREA_DEFINES__ 26655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_CONTEXT 0x00000001 27655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_VERTFMT 0x00000002 28655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_LINE 0x00000004 29655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_BUMPMAP 0x00000008 30655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_MASKS 0x00000010 31655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_VIEWPORT 0x00000020 32655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_SETUP 0x00000040 33655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_TCL 0x00000080 34655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_MISC 0x00000100 35655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_TEX0 0x00000200 36655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_TEX1 0x00000400 37655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_TEX2 0x00000800 38655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 39655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 40655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 41655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_CLIPRECTS 0x00008000 42655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_REQUIRE_QUIESCENCE 0x00010000 43655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_ZBIAS 0x00020000 44655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_ALL 0x003effff 45655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 46655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_MISC 0 47655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_CNTL 1 48655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_RB3D_COLORPITCH 2 49655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_RE_LINE_PATTERN 3 50655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_SE_LINE_WIDTH 4 51655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_LUM_MATRIX 5 52655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_ROT_MATRIX_0 6 53655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_RB3D_STENCILREFMASK 7 54655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_SE_VPORT_XSCALE 8 55655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_SE_CNTL 9 56655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_SE_CNTL_STATUS 10 57655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_RE_MISC 11 58655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_TXFILTER_0 12 59655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_BORDER_COLOR_0 13 60655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_TXFILTER_1 14 61655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_BORDER_COLOR_1 15 62655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_TXFILTER_2 16 63655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_BORDER_COLOR_2 17 64655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 65655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 66655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 67655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXCBLEND_0 21 68655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXCBLEND_1 22 69655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXCBLEND_2 23 70655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXCBLEND_3 24 71655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXCBLEND_4 25 72655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXCBLEND_5 26 73655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXCBLEND_6 27 74655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXCBLEND_7 28 75655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 76655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_TFACTOR_0 30 77655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_VTX_FMT_0 31 78655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_VAP_CTL 32 79655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_MATRIX_SELECT_0 33 80655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_TEX_PROC_CTL_2 34 81655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 82655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXFILTER_0 36 83655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXFILTER_1 37 84655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXFILTER_2 38 85655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXFILTER_3 39 86655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXFILTER_4 40 87655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXFILTER_5 41 88655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXOFFSET_0 42 89655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXOFFSET_1 43 90655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXOFFSET_2 44 91655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXOFFSET_3 45 92655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXOFFSET_4 46 93655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXOFFSET_5 47 94655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_VTE_CNTL 48 95655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 96655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TAM_DEBUG3 50 97655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_CNTL_X 51 98655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 99655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 100655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_RE_SCISSOR_TL_0 54 101655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_RE_SCISSOR_TL_1 55 102655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_RE_SCISSOR_TL_2 56 103655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_SE_VAP_CNTL_STATUS 57 104655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_SE_VTX_STATE_CNTL 58 105655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_RE_POINTSIZE 59 106655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 107655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_CUBIC_FACES_0 61 108655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 109655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_CUBIC_FACES_1 63 110655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_CUBIC_OFFSETS_1 64 111655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_CUBIC_FACES_2 65 112655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 113655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_CUBIC_FACES_3 67 114655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 115655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_CUBIC_FACES_4 69 116655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 117655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_CUBIC_FACES_5 71 118655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 119655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_TEX_SIZE_0 73 120655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_TEX_SIZE_1 74 121655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_TEX_SIZE_2 75 122655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_RB3D_BLENDCOLOR 76 123655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 124655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_CUBIC_FACES_0 78 125655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 126655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_CUBIC_FACES_1 80 127655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 128655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_CUBIC_FACES_2 82 129655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 130655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TRI_PERF_CNTL 84 131655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_AFS_0 85 132655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_AFS_1 86 133655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_ATF_TFACTOR 87 134655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXCTLALL_0 88 135655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXCTLALL_1 89 136655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXCTLALL_2 90 137655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXCTLALL_3 91 138655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXCTLALL_4 92 139655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_PP_TXCTLALL_5 93 140655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R200_EMIT_VAP_PVS_CNTL 94 141655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_MAX_STATE_PACKETS 95 142655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CMD_PACKET 1 143655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CMD_SCALARS 2 144655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CMD_VECTORS 3 145655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CMD_DMA_DISCARD 4 146655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CMD_PACKET3 5 147655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CMD_PACKET3_CLIP 6 148655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CMD_SCALARS2 7 149655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CMD_WAIT 8 150655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CMD_VECLINEAR 9 151655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef union { 152d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int i; 153d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 154d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, pad0, pad1, pad2; 155d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } header; 156d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 157d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, packet_id, pad0, pad1; 158d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } packet; 159d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 160d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, offset, stride, count; 161d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } scalars; 162d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 163d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, offset, stride, count; 164d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } vectors; 165d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 166d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, addr_lo, addr_hi, count; 167d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } veclinear; 168d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 169d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, buf_idx, pad0, pad1; 170d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } dma; 171d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 172d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, flags, pad0, pad1; 173d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } wait; 174655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_cmd_header_t; 175655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_WAIT_2D 0x1 176655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_WAIT_3D 0x2 177655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_CMD_PACKET3_CLEAR 0 178655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_CMD_PACKET3_RAW 1 179655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_CMD_PACKET0 1 180655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_CMD_VPU 2 181655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_CMD_PACKET3 3 182655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_CMD_END3D 4 183655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_CMD_CP_DELAY 5 184655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_CMD_DMA_DISCARD 6 185655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_CMD_WAIT 7 186655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_WAIT_2D 0x1 187655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_WAIT_3D 0x2 188655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_WAIT_2D_CLEAN 0x3 189655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_WAIT_3D_CLEAN 0x4 190655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_NEW_WAIT_2D_3D 0x3 191655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_NEW_WAIT_2D_2D_CLEAN 0x4 192655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_NEW_WAIT_3D_3D_CLEAN 0x6 193655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 194655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_CMD_SCRATCH 8 195655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R300_CMD_R500FP 9 196655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef union { 197d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int u; 198d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 199d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, pad0, pad1, pad2; 200d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } header; 201d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 202d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, count, reglo, reghi; 203d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } packet0; 204d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 205d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, count, adrlo, adrhi; 206d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } vpu; 207d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 208d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, packet, pad0, pad1; 209d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } packet3; 210d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 211d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, packet; 212d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned short count; 213d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } delay; 214d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 215d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, buf_idx, pad0, pad1; 216d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } dma; 217d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 218d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, flags, pad0, pad1; 219d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } wait; 220d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 221d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, reg, n_bufs, flags; 222d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } scratch; 223d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct { 224d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned char cmd_type, count, adrlo, adrhi_flags; 225d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } r500fp; 226655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_r300_cmd_header_t; 227655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_FRONT 0x1 228655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_BACK 0x2 229655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_DEPTH 0x4 230655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_STENCIL 0x8 231655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CLEAR_FASTZ 0x80000000 232655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_USE_HIERZ 0x40000000 233655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_USE_COMP_ZBUF 0x20000000 234655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R500FP_CONSTANT_TYPE (1 << 1) 235655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R500FP_CONSTANT_CLAMP (1 << 2) 236655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_POINTS 0x1 237655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_LINES 0x2 238655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_LINE_STRIP 0x3 239655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TRIANGLES 0x4 240655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TRIANGLE_FAN 0x5 241655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TRIANGLE_STRIP 0x6 242655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_BUFFER_SIZE 65536 243655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INDEX_PRIM_OFFSET 20 244655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_SCRATCH_REG_OFFSET 32 245655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define R600_SCRATCH_REG_OFFSET 256 246655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_NR_SAREA_CLIPRECTS 12 247655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_LOCAL_TEX_HEAP 0 248655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_GART_TEX_HEAP 1 249655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_NR_TEX_HEAPS 2 250655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_NR_TEX_REGIONS 64 251655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_LOG_TEX_GRANULARITY 16 252655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_MAX_TEXTURE_LEVELS 12 253655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_MAX_TEXTURE_UNITS 3 254655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_MAX_SURFACES 8 255655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_OFFSET_SHIFT 10 256655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 257655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 258655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#endif 259655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct { 260d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int red; 261d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int green; 262d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int blue; 263d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int alpha; 264655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} radeon_color_regs_t; 265655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct { 266d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int pp_misc; 267d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int pp_fog_color; 268d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int re_solid_color; 269d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int rb3d_blendcntl; 270d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int rb3d_depthoffset; 271d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int rb3d_depthpitch; 272d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int rb3d_zstencilcntl; 273d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int pp_cntl; 274d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int rb3d_cntl; 275d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int rb3d_coloroffset; 276d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int re_width_height; 277d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int rb3d_colorpitch; 278d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int se_cntl; 279d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int se_coord_fmt; 280d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int re_line_pattern; 281d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int re_line_state; 282d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int se_line_width; 283d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int pp_lum_matrix; 284d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int pp_rot_matrix_0; 285d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int pp_rot_matrix_1; 286d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int rb3d_stencilrefmask; 287d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int rb3d_ropcntl; 288d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int rb3d_planemask; 289d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int se_vport_xscale; 290d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int se_vport_xoffset; 291d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int se_vport_yscale; 292d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int se_vport_yoffset; 293d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int se_vport_zscale; 294d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int se_vport_zoffset; 295d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int se_cntl_status; 296d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int re_top_left; 297d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int re_misc; 298655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_context_regs_t; 299655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct { 300d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int se_zbias_factor; 301d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int se_zbias_constant; 302655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_context2_regs_t; 303655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct { 304d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int pp_txfilter; 305d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int pp_txformat; 306d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int pp_txoffset; 307d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int pp_txcblend; 308d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int pp_txablend; 309d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int pp_tfactor; 310d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int pp_border_color; 311655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_texture_regs_t; 312655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct { 313d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int start; 314d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int finish; 315d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int prim : 8; 316d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int stateidx : 8; 317d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int numverts : 16; 318d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int vc_format; 319655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_prim_t; 320655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct { 321d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao drm_radeon_context_regs_t context; 322d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 323d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao drm_radeon_context2_regs_t context2; 324d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int dirty; 325655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_state_t; 326655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct { 327d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao drm_radeon_context_regs_t context_state; 328d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 329d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int dirty; 330d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int vertsize; 331d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int vc_format; 332d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; 333d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int nbox; 334d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int last_frame; 335d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int last_dispatch; 336d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int last_clear; 337d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 1]; 338d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 339d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int ctx_owner; 340d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int pfState; 341d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int pfCurrentPage; 342d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int crtc2_base; 343d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int tiling_enabled; 344655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_sarea_t; 345655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_CP_INIT 0x00 346655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_CP_START 0x01 347655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_CP_STOP 0x02 348655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_CP_RESET 0x03 349655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_CP_IDLE 0x04 350655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_RESET 0x05 351655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_FULLSCREEN 0x06 352655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_SWAP 0x07 353655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_CLEAR 0x08 354655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_VERTEX 0x09 355655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_INDICES 0x0A 356655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_NOT_USED 357655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_STIPPLE 0x0C 358655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_INDIRECT 0x0D 359655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_TEXTURE 0x0E 360655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_VERTEX2 0x0F 361655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_CMDBUF 0x10 362655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_GETPARAM 0x11 363655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_FLIP 0x12 364655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_ALLOC 0x13 365655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_FREE 0x14 366655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_INIT_HEAP 0x15 367655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_IRQ_EMIT 0x16 368655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_IRQ_WAIT 0x17 369655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_CP_RESUME 0x18 370655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_SETPARAM 0x19 371655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_SURF_ALLOC 0x1a 372655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_SURF_FREE 0x1b 373655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_GEM_INFO 0x1c 374655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_GEM_CREATE 0x1d 375655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_GEM_MMAP 0x1e 376655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_GEM_PREAD 0x21 377655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_GEM_PWRITE 0x22 378655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_GEM_SET_DOMAIN 0x23 379655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_GEM_WAIT_IDLE 0x24 380655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_CS 0x26 381655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_INFO 0x27 382655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_GEM_SET_TILING 0x28 383655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_GEM_GET_TILING 0x29 384655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_GEM_BUSY 0x2a 385655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_GEM_VA 0x2b 386ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define DRM_RADEON_GEM_OP 0x2c 38782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define DRM_RADEON_GEM_USERPTR 0x2d 388d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 389d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_CP_START DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_START) 390d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 391d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_CP_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 392d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 393d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_RESET) 394d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 395d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_SWAP) 396d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) 397d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) 398d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) 399d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) 40082d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) 401d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) 402d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) 403d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) 40482d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) 405d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_FLIP) 406655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) 407d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 408d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 409ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 410d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 411d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 412d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 413d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 414d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) 415655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) 41682d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) 417ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) 418655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) 419655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) 42082d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) 421ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) 422655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) 423655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) 42482d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) 425ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) 426655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) 427655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) 42882d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op) 42982d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr) 430655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_init { 431d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao enum { 432d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao RADEON_INIT_CP = 0x01, 433d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao RADEON_CLEANUP_CP = 0x02, 434d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao RADEON_INIT_R200_CP = 0x03, 435d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao RADEON_INIT_R300_CP = 0x04, 436d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao RADEON_INIT_R600_CP = 0x05 437d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } func; 438d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned long sarea_priv_offset; 439d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int is_pci; 440d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int cp_mode; 441d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int gart_size; 442d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int ring_size; 443d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int usec_timeout; 444d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int fb_bpp; 445d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int front_offset, front_pitch; 446d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int back_offset, back_pitch; 447d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int depth_bpp; 448d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int depth_offset, depth_pitch; 449d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned long fb_offset; 450d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned long mmio_offset; 451d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned long ring_offset; 452d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned long ring_rptr_offset; 453d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned long buffers_offset; 454d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned long gart_textures_offset; 455655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_init_t; 456655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_cp_stop { 457d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int flush; 458d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int idle; 459d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao} drm_radeon_cp_stop_t; 460655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_fullscreen { 461d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao enum { 462d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao RADEON_INIT_FULLSCREEN = 0x01, 463d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao RADEON_CLEANUP_FULLSCREEN = 0x02 464d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao } func; 465655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_fullscreen_t; 466655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define CLEAR_X1 0 467655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define CLEAR_Y1 1 468655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define CLEAR_X2 2 469655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define CLEAR_Y2 3 470655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define CLEAR_DEPTH 4 471655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef union drm_radeon_clear_rect { 472d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao float f[5]; 473d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int ui[5]; 474655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_clear_rect_t; 475655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_clear { 476d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int flags; 477d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int clear_color; 478d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int clear_depth; 479d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int color_mask; 480d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int depth_mask; 481d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao drm_radeon_clear_rect_t __user * depth_boxes; 482655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_clear_t; 483655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_vertex { 484d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int prim; 485d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int idx; 486d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int count; 487d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int discard; 488655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_vertex_t; 489655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_indices { 490d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int prim; 491d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int idx; 492d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int start; 493d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int end; 494d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int discard; 495655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_indices_t; 496655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_vertex2 { 497d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int idx; 498d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int discard; 499d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int nr_states; 500d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao drm_radeon_state_t __user * state; 501d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int nr_prims; 502d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao drm_radeon_prim_t __user * prim; 503d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao} drm_radeon_vertex2_t; 504655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_cmd_buffer { 505d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int bufsz; 506d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao char __user * buf; 507d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int nbox; 508d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao struct drm_clip_rect __user * boxes; 509655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_cmd_buffer_t; 510655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_tex_image { 511d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int x, y; 512d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int width, height; 513d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao const void __user * data; 514655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_tex_image_t; 515655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_texture { 516d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int offset; 517d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int pitch; 518d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int format; 519d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int width; 520d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int height; 521d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao drm_radeon_tex_image_t __user * image; 522655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_texture_t; 523655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_stipple { 524d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int __user * mask; 525655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_stipple_t; 526655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_indirect { 527d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int idx; 528d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int start; 529d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int end; 530d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int discard; 531655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_indirect_t; 532655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CARD_PCI 0 533655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CARD_AGP 1 534655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CARD_PCIE 2 535655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_GART_BUFFER_OFFSET 1 536655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_LAST_FRAME 2 537655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_LAST_DISPATCH 3 538655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_LAST_CLEAR 4 539655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_IRQ_NR 5 540655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_GART_BASE 6 541655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_REGISTER_HANDLE 7 542655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_STATUS_HANDLE 8 543655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_SAREA_HANDLE 9 544655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_GART_TEX_HANDLE 10 545655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_SCRATCH_OFFSET 11 546655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_CARD_TYPE 12 547655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_VBLANK_CRTC 13 548655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_FB_LOCATION 14 549655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_NUM_GB_PIPES 15 550655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_DEVICE_ID 16 551655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_PARAM_NUM_Z_PIPES 17 552655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_getparam { 553d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int param; 554d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao void __user * value; 555d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao} drm_radeon_getparam_t; 556655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_MEM_REGION_GART 1 557655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_MEM_REGION_FB 2 558655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_mem_alloc { 559d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int region; 560d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int alignment; 561d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int size; 562d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int __user * region_offset; 563655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_mem_alloc_t; 564655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_mem_free { 565d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int region; 566d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int region_offset; 567d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao} drm_radeon_mem_free_t; 568655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_mem_init_heap { 569d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int region; 570d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int size; 571d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int start; 572655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_mem_init_heap_t; 573655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_irq_emit { 574d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int __user * irq_seq; 575655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_irq_emit_t; 576655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_irq_wait { 577d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao int irq_seq; 578655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_irq_wait_t; 579655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_setparam { 580d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int param; 581d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao __s64 value; 582655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_setparam_t; 583655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_SETPARAM_FB_LOCATION 1 584655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_SETPARAM_SWITCH_TILING 2 585655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_SETPARAM_PCIGART_LOCATION 3 586655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_SETPARAM_NEW_MEMMAP 4 587655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 588655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_SETPARAM_VBLANK_CRTC 6 589655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_surface_alloc { 590d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int address; 591d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int size; 592d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int flags; 593655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_surface_alloc_t; 594655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengtypedef struct drm_radeon_surface_free { 595d7db594b8d1dab36b711bd887a9dd21675c87243Tao Bao unsigned int address; 596655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng} drm_radeon_surface_free_t; 597655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_VBLANK_CRTC1 1 598655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define DRM_RADEON_VBLANK_CRTC2 2 599655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_GEM_DOMAIN_CPU 0x1 600655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_GEM_DOMAIN_GTT 0x2 601655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_GEM_DOMAIN_VRAM 0x4 602655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengstruct drm_radeon_gem_info { 603106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 gart_size; 604106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 vram_size; 605106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 vram_visible; 606655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng}; 60782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_GEM_NO_BACKING_STORE (1 << 0) 60882d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_GEM_GTT_UC (1 << 1) 60982d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_GEM_GTT_WC (1 << 2) 61082d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_GEM_CPU_ACCESS (1 << 3) 61182d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_GEM_NO_CPU_ACCESS (1 << 4) 612655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengstruct drm_radeon_gem_create { 613106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 size; 614106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 alignment; 615106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 handle; 616106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 initial_domain; 617106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 flags; 61882d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris}; 61982d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_GEM_USERPTR_READONLY (1 << 0) 62082d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_GEM_USERPTR_ANONONLY (1 << 1) 62182d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_GEM_USERPTR_VALIDATE (1 << 2) 62282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_GEM_USERPTR_REGISTER (1 << 3) 62382d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferrisstruct drm_radeon_gem_userptr { 624106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 addr; 625106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 size; 626106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 flags; 627106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 handle; 628655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng}; 629655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_MACRO 0x1 630655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_MICRO 0x2 631655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_SWAP_16BIT 0x4 632655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_SWAP_32BIT 0x8 633655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_SURFACE 0x10 634655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_MICRO_SQUARE 0x20 635655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_EG_BANKW_SHIFT 8 636655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_EG_BANKW_MASK 0xf 637655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_EG_BANKH_SHIFT 12 638655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_EG_BANKH_MASK 0xf 639655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 640655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf 641655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 642655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf 643655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 644655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf 645655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengstruct drm_radeon_gem_set_tiling { 646106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 handle; 647106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 tiling_flags; 648106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 pitch; 649655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng}; 650655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengstruct drm_radeon_gem_get_tiling { 651106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 handle; 652106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 tiling_flags; 653106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 pitch; 654655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng}; 655106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferrisstruct drm_radeon_gem_mmap { 656106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 handle; 657106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 pad; 658106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 offset; 659106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 size; 660106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 addr_ptr; 661655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng}; 662655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengstruct drm_radeon_gem_set_domain { 663106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 handle; 664106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 read_domains; 665106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 write_domain; 666655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng}; 667106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferrisstruct drm_radeon_gem_wait_idle { 668106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 handle; 669106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 pad; 670655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng}; 671106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferrisstruct drm_radeon_gem_busy { 672106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 handle; 673106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 domain; 674655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng}; 675106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferrisstruct drm_radeon_gem_pread { 676106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 handle; 677106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 pad; 678106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 offset; 679106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 size; 680106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 data_ptr; 681655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng}; 682655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengstruct drm_radeon_gem_pwrite { 683106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 handle; 684106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 pad; 685106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 offset; 686106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 size; 687106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 data_ptr; 688106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris}; 689ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferrisstruct drm_radeon_gem_op { 690106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 handle; 691106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 op; 692106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 value; 693ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris}; 694ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0 695ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1 696ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define RADEON_VA_MAP 1 697655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_VA_UNMAP 2 698655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_VA_RESULT_OK 0 699655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_VA_RESULT_ERROR 1 700ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define RADEON_VA_RESULT_VA_EXIST 2 701655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_VM_PAGE_VALID (1 << 0) 702655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_VM_PAGE_READABLE (1 << 1) 703655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_VM_PAGE_WRITEABLE (1 << 2) 704ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define RADEON_VM_PAGE_SYSTEM (1 << 3) 705655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_VM_PAGE_SNOOPED (1 << 4) 706655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengstruct drm_radeon_gem_va { 707106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 handle; 708106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 operation; 709106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 vm_id; 710106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 flags; 711106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 offset; 712106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris}; 713655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CHUNK_ID_RELOCS 0x01 714655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CHUNK_ID_IB 0x02 715655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CHUNK_ID_FLAGS 0x03 716ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define RADEON_CHUNK_ID_CONST_IB 0x04 717655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CS_KEEP_TILING_FLAGS 0x01 718655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CS_USE_VM 0x02 719655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CS_END_OF_FRAME 0x04 720ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define RADEON_CS_RING_GFX 0 721655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CS_RING_COMPUTE 1 722655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CS_RING_DMA 2 723655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_CS_RING_UVD 3 724ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define RADEON_CS_RING_VCE 4 725ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferrisstruct drm_radeon_cs_chunk { 726106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 chunk_id; 727106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 length_dw; 728106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 chunk_data; 729655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng}; 73082d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_RELOC_PRIO_MASK (0xf << 0) 731655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengstruct drm_radeon_cs_reloc { 732106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 handle; 733106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 read_domains; 734106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 write_domain; 735106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 flags; 73682d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris}; 737655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengstruct drm_radeon_cs { 738106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 num_chunks; 739106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 cs_id; 740106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 chunks; 741106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 gart_limit; 742106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 vram_limit; 743655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng}; 74482d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_INFO_DEVICE_ID 0x00 745655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_NUM_GB_PIPES 0x01 746655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_NUM_Z_PIPES 0x02 747655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_ACCEL_WORKING 0x03 74882d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_INFO_CRTC_FROM_ID 0x04 749655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_ACCEL_WORKING2 0x05 750655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_TILING_CONFIG 0x06 751655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_WANT_HYPERZ 0x07 75282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_INFO_WANT_CMASK 0x08 753655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 754655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_NUM_BACKENDS 0x0a 755655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_NUM_TILE_PIPES 0x0b 75682d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_INFO_FUSION_GART_WORKING 0x0c 757655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_BACKEND_MAP 0x0d 758655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_VA_START 0x0e 759655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f 76082d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_INFO_MAX_PIPES 0x10 761655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_TIMESTAMP 0x11 762655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_MAX_SE 0x12 763655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_MAX_SH_PER_SE 0x13 76482d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_INFO_FASTFB_WORKING 0x14 765655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_RING_WORKING 0x15 766655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 76738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 76882d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 76938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19 77038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define RADEON_INFO_MAX_SCLK 0x1a 771ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define RADEON_INFO_VCE_FW_VERSION 0x1b 77282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_INFO_VCE_FB_VERSION 0x1c 773ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define RADEON_INFO_NUM_BYTES_MOVED 0x1d 774ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define RADEON_INFO_VRAM_USAGE 0x1e 775ba8d4f460b51161eb82cf1006cb34a3cc1389f47Christopher Ferris#define RADEON_INFO_GTT_USAGE 0x1f 77682d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define RADEON_INFO_ACTIVE_CU_COUNT 0x20 77705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define RADEON_INFO_CURRENT_GPU_TEMP 0x21 77805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define RADEON_INFO_CURRENT_GPU_SCLK 0x22 77905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define RADEON_INFO_CURRENT_GPU_MCLK 0x23 78005d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define RADEON_INFO_READ_REG 0x24 781dda4fd4644b0ce06b78f1a612de98a73b6ca3d6bChristopher Ferris#define RADEON_INFO_VA_UNMAP_WORKING 0x25 78205d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define RADEON_INFO_GPU_RESET_COUNTER 0x26 783655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Chengstruct drm_radeon_info { 784106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 request; 785106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u32 pad; 786106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris __u64 value; 787655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng}; 788655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8 78905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define SI_TILE_MODE_COLOR_1D 13 790dda4fd4644b0ce06b78f1a612de98a73b6ca3d6bChristopher Ferris#define SI_TILE_MODE_COLOR_1D_SCANOUT 9 791655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define SI_TILE_MODE_COLOR_2D_8BPP 14 792655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define SI_TILE_MODE_COLOR_2D_16BPP 15 79305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define SI_TILE_MODE_COLOR_2D_32BPP 16 794dda4fd4644b0ce06b78f1a612de98a73b6ca3d6bChristopher Ferris#define SI_TILE_MODE_COLOR_2D_64BPP 17 795655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11 796655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12 79705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define SI_TILE_MODE_DEPTH_STENCIL_1D 4 798dda4fd4644b0ce06b78f1a612de98a73b6ca3d6bChristopher Ferris#define SI_TILE_MODE_DEPTH_STENCIL_2D 0 799655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3 800655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 80105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 802dda4fd4644b0ce06b78f1a612de98a73b6ca3d6bChristopher Ferris#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 803106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#ifdef __cplusplus 804106b3a8a7dc03c19a45e322de425ac56aafac358Christopher Ferris#endif 80538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#endif 806