1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __VMWGFX_DRM_H__
20#define __VMWGFX_DRM_H__
21#include "drm.h"
22#ifdef __cplusplus
23#endif
24#define DRM_VMW_MAX_SURFACE_FACES 6
25#define DRM_VMW_MAX_MIP_LEVELS 24
26#define DRM_VMW_GET_PARAM 0
27#define DRM_VMW_ALLOC_DMABUF 1
28#define DRM_VMW_UNREF_DMABUF 2
29#define DRM_VMW_HANDLE_CLOSE 2
30#define DRM_VMW_CURSOR_BYPASS 3
31#define DRM_VMW_CONTROL_STREAM 4
32#define DRM_VMW_CLAIM_STREAM 5
33#define DRM_VMW_UNREF_STREAM 6
34#define DRM_VMW_CREATE_CONTEXT 7
35#define DRM_VMW_UNREF_CONTEXT 8
36#define DRM_VMW_CREATE_SURFACE 9
37#define DRM_VMW_UNREF_SURFACE 10
38#define DRM_VMW_REF_SURFACE 11
39#define DRM_VMW_EXECBUF 12
40#define DRM_VMW_GET_3D_CAP 13
41#define DRM_VMW_FENCE_WAIT 14
42#define DRM_VMW_FENCE_SIGNALED 15
43#define DRM_VMW_FENCE_UNREF 16
44#define DRM_VMW_FENCE_EVENT 17
45#define DRM_VMW_PRESENT 18
46#define DRM_VMW_PRESENT_READBACK 19
47#define DRM_VMW_UPDATE_LAYOUT 20
48#define DRM_VMW_CREATE_SHADER 21
49#define DRM_VMW_UNREF_SHADER 22
50#define DRM_VMW_GB_SURFACE_CREATE 23
51#define DRM_VMW_GB_SURFACE_REF 24
52#define DRM_VMW_SYNCCPU 25
53#define DRM_VMW_CREATE_EXTENDED_CONTEXT 26
54#define DRM_VMW_PARAM_NUM_STREAMS 0
55#define DRM_VMW_PARAM_NUM_FREE_STREAMS 1
56#define DRM_VMW_PARAM_3D 2
57#define DRM_VMW_PARAM_HW_CAPS 3
58#define DRM_VMW_PARAM_FIFO_CAPS 4
59#define DRM_VMW_PARAM_MAX_FB_SIZE 5
60#define DRM_VMW_PARAM_FIFO_HW_VERSION 6
61#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7
62#define DRM_VMW_PARAM_3D_CAPS_SIZE 8
63#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9
64#define DRM_VMW_PARAM_MAX_MOB_SIZE 10
65#define DRM_VMW_PARAM_SCREEN_TARGET 11
66#define DRM_VMW_PARAM_DX 12
67enum drm_vmw_handle_type {
68  DRM_VMW_HANDLE_LEGACY = 0,
69  DRM_VMW_HANDLE_PRIME = 1
70};
71struct drm_vmw_getparam_arg {
72  __u64 value;
73  __u32 param;
74  __u32 pad64;
75};
76struct drm_vmw_context_arg {
77  __s32 cid;
78  __u32 pad64;
79};
80struct drm_vmw_surface_create_req {
81  __u32 flags;
82  __u32 format;
83  __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES];
84  __u64 size_addr;
85  __s32 shareable;
86  __s32 scanout;
87};
88struct drm_vmw_surface_arg {
89  __s32 sid;
90  enum drm_vmw_handle_type handle_type;
91};
92struct drm_vmw_size {
93  __u32 width;
94  __u32 height;
95  __u32 depth;
96  __u32 pad64;
97};
98union drm_vmw_surface_create_arg {
99  struct drm_vmw_surface_arg rep;
100  struct drm_vmw_surface_create_req req;
101};
102union drm_vmw_surface_reference_arg {
103  struct drm_vmw_surface_create_req rep;
104  struct drm_vmw_surface_arg req;
105};
106#define DRM_VMW_EXECBUF_VERSION 2
107#define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0)
108#define DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1)
109struct drm_vmw_execbuf_arg {
110  __u64 commands;
111  __u32 command_size;
112  __u32 throttle_us;
113  __u64 fence_rep;
114  __u32 version;
115  __u32 flags;
116  __u32 context_handle;
117  __s32 imported_fence_fd;
118};
119struct drm_vmw_fence_rep {
120  __u32 handle;
121  __u32 mask;
122  __u32 seqno;
123  __u32 passed_seqno;
124  __s32 fd;
125  __s32 error;
126};
127struct drm_vmw_alloc_dmabuf_req {
128  __u32 size;
129  __u32 pad64;
130};
131struct drm_vmw_dmabuf_rep {
132  __u64 map_handle;
133  __u32 handle;
134  __u32 cur_gmr_id;
135  __u32 cur_gmr_offset;
136  __u32 pad64;
137};
138union drm_vmw_alloc_dmabuf_arg {
139  struct drm_vmw_alloc_dmabuf_req req;
140  struct drm_vmw_dmabuf_rep rep;
141};
142struct drm_vmw_unref_dmabuf_arg {
143  __u32 handle;
144  __u32 pad64;
145};
146struct drm_vmw_rect {
147  __s32 x;
148  __s32 y;
149  __u32 w;
150  __u32 h;
151};
152struct drm_vmw_control_stream_arg {
153  __u32 stream_id;
154  __u32 enabled;
155  __u32 flags;
156  __u32 color_key;
157  __u32 handle;
158  __u32 offset;
159  __s32 format;
160  __u32 size;
161  __u32 width;
162  __u32 height;
163  __u32 pitch[3];
164  __u32 pad64;
165  struct drm_vmw_rect src;
166  struct drm_vmw_rect dst;
167};
168#define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0)
169#define DRM_VMW_CURSOR_BYPASS_FLAGS (1)
170struct drm_vmw_cursor_bypass_arg {
171  __u32 flags;
172  __u32 crtc_id;
173  __s32 xpos;
174  __s32 ypos;
175  __s32 xhot;
176  __s32 yhot;
177};
178struct drm_vmw_stream_arg {
179  __u32 stream_id;
180  __u32 pad64;
181};
182struct drm_vmw_get_3d_cap_arg {
183  __u64 buffer;
184  __u32 max_size;
185  __u32 pad64;
186};
187#define DRM_VMW_FENCE_FLAG_EXEC (1 << 0)
188#define DRM_VMW_FENCE_FLAG_QUERY (1 << 1)
189#define DRM_VMW_WAIT_OPTION_UNREF (1 << 0)
190struct drm_vmw_fence_wait_arg {
191  __u32 handle;
192  __s32 cookie_valid;
193  __u64 kernel_cookie;
194  __u64 timeout_us;
195  __s32 lazy;
196  __s32 flags;
197  __s32 wait_options;
198  __s32 pad64;
199};
200struct drm_vmw_fence_signaled_arg {
201  __u32 handle;
202  __u32 flags;
203  __s32 signaled;
204  __u32 passed_seqno;
205  __u32 signaled_flags;
206  __u32 pad64;
207};
208struct drm_vmw_fence_arg {
209  __u32 handle;
210  __u32 pad64;
211};
212#define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000
213struct drm_vmw_event_fence {
214  struct drm_event base;
215  __u64 user_data;
216  __u32 tv_sec;
217  __u32 tv_usec;
218};
219#define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0)
220struct drm_vmw_fence_event_arg {
221  __u64 fence_rep;
222  __u64 user_data;
223  __u32 handle;
224  __u32 flags;
225};
226struct drm_vmw_present_arg {
227  __u32 fb_id;
228  __u32 sid;
229  __s32 dest_x;
230  __s32 dest_y;
231  __u64 clips_ptr;
232  __u32 num_clips;
233  __u32 pad64;
234};
235struct drm_vmw_present_readback_arg {
236  __u32 fb_id;
237  __u32 num_clips;
238  __u64 clips_ptr;
239  __u64 fence_rep;
240};
241struct drm_vmw_update_layout_arg {
242  __u32 num_outputs;
243  __u32 pad64;
244  __u64 rects;
245};
246enum drm_vmw_shader_type {
247  drm_vmw_shader_type_vs = 0,
248  drm_vmw_shader_type_ps,
249};
250struct drm_vmw_shader_create_arg {
251  enum drm_vmw_shader_type shader_type;
252  __u32 size;
253  __u32 buffer_handle;
254  __u32 shader_handle;
255  __u64 offset;
256};
257struct drm_vmw_shader_arg {
258  __u32 handle;
259  __u32 pad64;
260};
261enum drm_vmw_surface_flags {
262  drm_vmw_surface_flag_shareable = (1 << 0),
263  drm_vmw_surface_flag_scanout = (1 << 1),
264  drm_vmw_surface_flag_create_buffer = (1 << 2)
265};
266struct drm_vmw_gb_surface_create_req {
267  __u32 svga3d_flags;
268  __u32 format;
269  __u32 mip_levels;
270  enum drm_vmw_surface_flags drm_surface_flags;
271  __u32 multisample_count;
272  __u32 autogen_filter;
273  __u32 buffer_handle;
274  __u32 array_size;
275  struct drm_vmw_size base_size;
276};
277struct drm_vmw_gb_surface_create_rep {
278  __u32 handle;
279  __u32 backup_size;
280  __u32 buffer_handle;
281  __u32 buffer_size;
282  __u64 buffer_map_handle;
283};
284union drm_vmw_gb_surface_create_arg {
285  struct drm_vmw_gb_surface_create_rep rep;
286  struct drm_vmw_gb_surface_create_req req;
287};
288struct drm_vmw_gb_surface_ref_rep {
289  struct drm_vmw_gb_surface_create_req creq;
290  struct drm_vmw_gb_surface_create_rep crep;
291};
292union drm_vmw_gb_surface_reference_arg {
293  struct drm_vmw_gb_surface_ref_rep rep;
294  struct drm_vmw_surface_arg req;
295};
296enum drm_vmw_synccpu_flags {
297  drm_vmw_synccpu_read = (1 << 0),
298  drm_vmw_synccpu_write = (1 << 1),
299  drm_vmw_synccpu_dontblock = (1 << 2),
300  drm_vmw_synccpu_allow_cs = (1 << 3)
301};
302enum drm_vmw_synccpu_op {
303  drm_vmw_synccpu_grab,
304  drm_vmw_synccpu_release
305};
306struct drm_vmw_synccpu_arg {
307  enum drm_vmw_synccpu_op op;
308  enum drm_vmw_synccpu_flags flags;
309  __u32 handle;
310  __u32 pad64;
311};
312enum drm_vmw_extended_context {
313  drm_vmw_context_legacy,
314  drm_vmw_context_dx
315};
316union drm_vmw_extended_context_arg {
317  enum drm_vmw_extended_context req;
318  struct drm_vmw_context_arg rep;
319};
320struct drm_vmw_handle_close_arg {
321  __u32 handle;
322  __u32 pad64;
323};
324#ifdef __cplusplus
325#endif
326#endif
327