1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef _UAPI_LINUX_PERF_EVENT_H 20#define _UAPI_LINUX_PERF_EVENT_H 21#include <linux/types.h> 22#include <linux/ioctl.h> 23#include <asm/byteorder.h> 24enum perf_type_id { 25 PERF_TYPE_HARDWARE = 0, 26 PERF_TYPE_SOFTWARE = 1, 27 PERF_TYPE_TRACEPOINT = 2, 28 PERF_TYPE_HW_CACHE = 3, 29 PERF_TYPE_RAW = 4, 30 PERF_TYPE_BREAKPOINT = 5, 31 PERF_TYPE_MAX, 32}; 33enum perf_hw_id { 34 PERF_COUNT_HW_CPU_CYCLES = 0, 35 PERF_COUNT_HW_INSTRUCTIONS = 1, 36 PERF_COUNT_HW_CACHE_REFERENCES = 2, 37 PERF_COUNT_HW_CACHE_MISSES = 3, 38 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 39 PERF_COUNT_HW_BRANCH_MISSES = 5, 40 PERF_COUNT_HW_BUS_CYCLES = 6, 41 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 42 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 43 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 44 PERF_COUNT_HW_MAX, 45}; 46enum perf_hw_cache_id { 47 PERF_COUNT_HW_CACHE_L1D = 0, 48 PERF_COUNT_HW_CACHE_L1I = 1, 49 PERF_COUNT_HW_CACHE_LL = 2, 50 PERF_COUNT_HW_CACHE_DTLB = 3, 51 PERF_COUNT_HW_CACHE_ITLB = 4, 52 PERF_COUNT_HW_CACHE_BPU = 5, 53 PERF_COUNT_HW_CACHE_NODE = 6, 54 PERF_COUNT_HW_CACHE_MAX, 55}; 56enum perf_hw_cache_op_id { 57 PERF_COUNT_HW_CACHE_OP_READ = 0, 58 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 59 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 60 PERF_COUNT_HW_CACHE_OP_MAX, 61}; 62enum perf_hw_cache_op_result_id { 63 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 64 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 65 PERF_COUNT_HW_CACHE_RESULT_MAX, 66}; 67enum perf_sw_ids { 68 PERF_COUNT_SW_CPU_CLOCK = 0, 69 PERF_COUNT_SW_TASK_CLOCK = 1, 70 PERF_COUNT_SW_PAGE_FAULTS = 2, 71 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 72 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 73 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 74 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 75 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 76 PERF_COUNT_SW_EMULATION_FAULTS = 8, 77 PERF_COUNT_SW_DUMMY = 9, 78 PERF_COUNT_SW_BPF_OUTPUT = 10, 79 PERF_COUNT_SW_MAX, 80}; 81enum perf_event_sample_format { 82 PERF_SAMPLE_IP = 1U << 0, 83 PERF_SAMPLE_TID = 1U << 1, 84 PERF_SAMPLE_TIME = 1U << 2, 85 PERF_SAMPLE_ADDR = 1U << 3, 86 PERF_SAMPLE_READ = 1U << 4, 87 PERF_SAMPLE_CALLCHAIN = 1U << 5, 88 PERF_SAMPLE_ID = 1U << 6, 89 PERF_SAMPLE_CPU = 1U << 7, 90 PERF_SAMPLE_PERIOD = 1U << 8, 91 PERF_SAMPLE_STREAM_ID = 1U << 9, 92 PERF_SAMPLE_RAW = 1U << 10, 93 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 94 PERF_SAMPLE_REGS_USER = 1U << 12, 95 PERF_SAMPLE_STACK_USER = 1U << 13, 96 PERF_SAMPLE_WEIGHT = 1U << 14, 97 PERF_SAMPLE_DATA_SRC = 1U << 15, 98 PERF_SAMPLE_IDENTIFIER = 1U << 16, 99 PERF_SAMPLE_TRANSACTION = 1U << 17, 100 PERF_SAMPLE_REGS_INTR = 1U << 18, 101 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 102 PERF_SAMPLE_MAX = 1U << 20, 103}; 104enum perf_branch_sample_type_shift { 105 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, 106 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, 107 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, 108 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, 109 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, 110 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, 111 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, 112 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, 113 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, 114 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, 115 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, 116 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, 117 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, 118 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, 119 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, 120 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, 121 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, 122 PERF_SAMPLE_BRANCH_MAX_SHIFT 123}; 124enum perf_branch_sample_type { 125 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 126 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 127 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 128 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 129 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 130 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 131 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 132 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 133 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 134 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 135 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 136 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 137 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 138 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 139 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 140 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 141 PERF_SAMPLE_BRANCH_TYPE_SAVE = 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 142 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 143}; 144enum { 145 PERF_BR_UNKNOWN = 0, 146 PERF_BR_COND = 1, 147 PERF_BR_UNCOND = 2, 148 PERF_BR_IND = 3, 149 PERF_BR_CALL = 4, 150 PERF_BR_IND_CALL = 5, 151 PERF_BR_RET = 6, 152 PERF_BR_SYSCALL = 7, 153 PERF_BR_SYSRET = 8, 154 PERF_BR_COND_CALL = 9, 155 PERF_BR_COND_RET = 10, 156 PERF_BR_MAX, 157}; 158#define PERF_SAMPLE_BRANCH_PLM_ALL (PERF_SAMPLE_BRANCH_USER | PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_HV) 159enum perf_sample_regs_abi { 160 PERF_SAMPLE_REGS_ABI_NONE = 0, 161 PERF_SAMPLE_REGS_ABI_32 = 1, 162 PERF_SAMPLE_REGS_ABI_64 = 2, 163}; 164enum { 165 PERF_TXN_ELISION = (1 << 0), 166 PERF_TXN_TRANSACTION = (1 << 1), 167 PERF_TXN_SYNC = (1 << 2), 168 PERF_TXN_ASYNC = (1 << 3), 169 PERF_TXN_RETRY = (1 << 4), 170 PERF_TXN_CONFLICT = (1 << 5), 171 PERF_TXN_CAPACITY_WRITE = (1 << 6), 172 PERF_TXN_CAPACITY_READ = (1 << 7), 173 PERF_TXN_MAX = (1 << 8), 174 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 175 PERF_TXN_ABORT_SHIFT = 32, 176}; 177enum perf_event_read_format { 178 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 179 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 180 PERF_FORMAT_ID = 1U << 2, 181 PERF_FORMAT_GROUP = 1U << 3, 182 PERF_FORMAT_MAX = 1U << 4, 183}; 184#define PERF_ATTR_SIZE_VER0 64 185#define PERF_ATTR_SIZE_VER1 72 186#define PERF_ATTR_SIZE_VER2 80 187#define PERF_ATTR_SIZE_VER3 96 188#define PERF_ATTR_SIZE_VER4 104 189#define PERF_ATTR_SIZE_VER5 112 190struct perf_event_attr { 191 __u32 type; 192 __u32 size; 193 __u64 config; 194 union { 195 __u64 sample_period; 196 __u64 sample_freq; 197 }; 198 __u64 sample_type; 199 __u64 read_format; 200 __u64 disabled : 1, inherit : 1, pinned : 1, exclusive : 1, exclude_user : 1, exclude_kernel : 1, exclude_hv : 1, exclude_idle : 1, mmap : 1, comm : 1, freq : 1, inherit_stat : 1, enable_on_exec : 1, task : 1, watermark : 1, precise_ip : 2, mmap_data : 1, sample_id_all : 1, exclude_host : 1, exclude_guest : 1, exclude_callchain_kernel : 1, exclude_callchain_user : 1, mmap2 : 1, comm_exec : 1, use_clockid : 1, context_switch : 1, write_backward : 1, namespaces : 1, __reserved_1 : 35; 201 union { 202 __u32 wakeup_events; 203 __u32 wakeup_watermark; 204 }; 205 __u32 bp_type; 206 union { 207 __u64 bp_addr; 208 __u64 config1; 209 }; 210 union { 211 __u64 bp_len; 212 __u64 config2; 213 }; 214 __u64 branch_sample_type; 215 __u64 sample_regs_user; 216 __u32 sample_stack_user; 217 __s32 clockid; 218 __u64 sample_regs_intr; 219 __u32 aux_watermark; 220 __u16 sample_max_stack; 221 __u16 __reserved_2; 222}; 223#define perf_flags(attr) (* (& (attr)->read_format + 1)) 224#define PERF_EVENT_IOC_ENABLE _IO('$', 0) 225#define PERF_EVENT_IOC_DISABLE _IO('$', 1) 226#define PERF_EVENT_IOC_REFRESH _IO('$', 2) 227#define PERF_EVENT_IOC_RESET _IO('$', 3) 228#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 229#define PERF_EVENT_IOC_SET_OUTPUT _IO('$', 5) 230#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 231#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 232#define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 233#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 234enum perf_event_ioc_flags { 235 PERF_IOC_FLAG_GROUP = 1U << 0, 236}; 237struct perf_event_mmap_page { 238 __u32 version; 239 __u32 compat_version; 240 __u32 lock; 241 __u32 index; 242 __s64 offset; 243 __u64 time_enabled; 244 __u64 time_running; 245 union { 246 __u64 capabilities; 247 struct { 248 __u64 cap_bit0 : 1, cap_bit0_is_deprecated : 1, cap_user_rdpmc : 1, cap_user_time : 1, cap_user_time_zero : 1, cap_____res : 59; 249 }; 250 }; 251 __u16 pmc_width; 252 __u16 time_shift; 253 __u32 time_mult; 254 __u64 time_offset; 255 __u64 time_zero; 256 __u32 size; 257 __u8 __reserved[118 * 8 + 4]; 258 __u64 data_head; 259 __u64 data_tail; 260 __u64 data_offset; 261 __u64 data_size; 262 __u64 aux_head; 263 __u64 aux_tail; 264 __u64 aux_offset; 265 __u64 aux_size; 266}; 267#define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 268#define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 269#define PERF_RECORD_MISC_KERNEL (1 << 0) 270#define PERF_RECORD_MISC_USER (2 << 0) 271#define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 272#define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 273#define PERF_RECORD_MISC_GUEST_USER (5 << 0) 274#define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 275#define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 276#define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 277#define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 278#define PERF_RECORD_MISC_EXACT_IP (1 << 14) 279#define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 280struct perf_event_header { 281 __u32 type; 282 __u16 misc; 283 __u16 size; 284}; 285struct perf_ns_link_info { 286 __u64 dev; 287 __u64 ino; 288}; 289enum { 290 NET_NS_INDEX = 0, 291 UTS_NS_INDEX = 1, 292 IPC_NS_INDEX = 2, 293 PID_NS_INDEX = 3, 294 USER_NS_INDEX = 4, 295 MNT_NS_INDEX = 5, 296 CGROUP_NS_INDEX = 6, 297 NR_NAMESPACES, 298}; 299enum perf_event_type { 300 PERF_RECORD_MMAP = 1, 301 PERF_RECORD_LOST = 2, 302 PERF_RECORD_COMM = 3, 303 PERF_RECORD_EXIT = 4, 304 PERF_RECORD_THROTTLE = 5, 305 PERF_RECORD_UNTHROTTLE = 6, 306 PERF_RECORD_FORK = 7, 307 PERF_RECORD_READ = 8, 308 PERF_RECORD_SAMPLE = 9, 309 PERF_RECORD_MMAP2 = 10, 310 PERF_RECORD_AUX = 11, 311 PERF_RECORD_ITRACE_START = 12, 312 PERF_RECORD_LOST_SAMPLES = 13, 313 PERF_RECORD_SWITCH = 14, 314 PERF_RECORD_SWITCH_CPU_WIDE = 15, 315 PERF_RECORD_NAMESPACES = 16, 316 PERF_RECORD_MAX, 317}; 318#define PERF_MAX_STACK_DEPTH 127 319#define PERF_MAX_CONTEXTS_PER_STACK 8 320enum perf_callchain_context { 321 PERF_CONTEXT_HV = (__u64) - 32, 322 PERF_CONTEXT_KERNEL = (__u64) - 128, 323 PERF_CONTEXT_USER = (__u64) - 512, 324 PERF_CONTEXT_GUEST = (__u64) - 2048, 325 PERF_CONTEXT_GUEST_KERNEL = (__u64) - 2176, 326 PERF_CONTEXT_GUEST_USER = (__u64) - 2560, 327 PERF_CONTEXT_MAX = (__u64) - 4095, 328}; 329#define PERF_AUX_FLAG_TRUNCATED 0x01 330#define PERF_AUX_FLAG_OVERWRITE 0x02 331#define PERF_AUX_FLAG_PARTIAL 0x04 332#define PERF_AUX_FLAG_COLLISION 0x08 333#define PERF_FLAG_FD_NO_GROUP (1UL << 0) 334#define PERF_FLAG_FD_OUTPUT (1UL << 1) 335#define PERF_FLAG_PID_CGROUP (1UL << 2) 336#define PERF_FLAG_FD_CLOEXEC (1UL << 3) 337#ifdef __LITTLE_ENDIAN_BITFIELD 338union perf_mem_data_src { 339 __u64 val; 340 struct { 341 __u64 mem_op : 5, mem_lvl : 14, mem_snoop : 5, mem_lock : 2, mem_dtlb : 7, mem_lvl_num : 4, mem_remote : 1, mem_snoopx : 2, mem_rsvd : 24; 342 }; 343}; 344#elif defined(__BIG_ENDIAN_BITFIELD) 345union perf_mem_data_src { 346 __u64 val; 347 struct { 348 __u64 mem_rsvd : 24, mem_snoopx : 2, mem_remote : 1, mem_lvl_num : 4, mem_dtlb : 7, mem_lock : 2, mem_snoop : 5, mem_lvl : 14, mem_op : 5; 349 }; 350}; 351#else 352#error "Unknown endianness" 353#endif 354#define PERF_MEM_OP_NA 0x01 355#define PERF_MEM_OP_LOAD 0x02 356#define PERF_MEM_OP_STORE 0x04 357#define PERF_MEM_OP_PFETCH 0x08 358#define PERF_MEM_OP_EXEC 0x10 359#define PERF_MEM_OP_SHIFT 0 360#define PERF_MEM_LVL_NA 0x01 361#define PERF_MEM_LVL_HIT 0x02 362#define PERF_MEM_LVL_MISS 0x04 363#define PERF_MEM_LVL_L1 0x08 364#define PERF_MEM_LVL_LFB 0x10 365#define PERF_MEM_LVL_L2 0x20 366#define PERF_MEM_LVL_L3 0x40 367#define PERF_MEM_LVL_LOC_RAM 0x80 368#define PERF_MEM_LVL_REM_RAM1 0x100 369#define PERF_MEM_LVL_REM_RAM2 0x200 370#define PERF_MEM_LVL_REM_CCE1 0x400 371#define PERF_MEM_LVL_REM_CCE2 0x800 372#define PERF_MEM_LVL_IO 0x1000 373#define PERF_MEM_LVL_UNC 0x2000 374#define PERF_MEM_LVL_SHIFT 5 375#define PERF_MEM_REMOTE_REMOTE 0x01 376#define PERF_MEM_REMOTE_SHIFT 37 377#define PERF_MEM_LVLNUM_L1 0x01 378#define PERF_MEM_LVLNUM_L2 0x02 379#define PERF_MEM_LVLNUM_L3 0x03 380#define PERF_MEM_LVLNUM_L4 0x04 381#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b 382#define PERF_MEM_LVLNUM_LFB 0x0c 383#define PERF_MEM_LVLNUM_RAM 0x0d 384#define PERF_MEM_LVLNUM_PMEM 0x0e 385#define PERF_MEM_LVLNUM_NA 0x0f 386#define PERF_MEM_LVLNUM_SHIFT 33 387#define PERF_MEM_SNOOP_NA 0x01 388#define PERF_MEM_SNOOP_NONE 0x02 389#define PERF_MEM_SNOOP_HIT 0x04 390#define PERF_MEM_SNOOP_MISS 0x08 391#define PERF_MEM_SNOOP_HITM 0x10 392#define PERF_MEM_SNOOP_SHIFT 19 393#define PERF_MEM_SNOOPX_FWD 0x01 394#define PERF_MEM_SNOOPX_SHIFT 37 395#define PERF_MEM_LOCK_NA 0x01 396#define PERF_MEM_LOCK_LOCKED 0x02 397#define PERF_MEM_LOCK_SHIFT 24 398#define PERF_MEM_TLB_NA 0x01 399#define PERF_MEM_TLB_HIT 0x02 400#define PERF_MEM_TLB_MISS 0x04 401#define PERF_MEM_TLB_L1 0x08 402#define PERF_MEM_TLB_L2 0x10 403#define PERF_MEM_TLB_WK 0x20 404#define PERF_MEM_TLB_OS 0x40 405#define PERF_MEM_TLB_SHIFT 26 406#define PERF_MEM_S(a,s) (((__u64) PERF_MEM_ ##a ##_ ##s) << PERF_MEM_ ##a ##_SHIFT) 407struct perf_branch_entry { 408 __u64 from; 409 __u64 to; 410 __u64 mispred : 1, predicted : 1, in_tx : 1, abort : 1, cycles : 16, type : 4, reserved : 40; 411}; 412#endif 413