1/*
2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __TSP_PRIVATE_H__
8#define __TSP_PRIVATE_H__
9
10/* Definitions to help the assembler access the SMC/ERET args structure */
11#define TSP_ARGS_SIZE		0x40
12#define TSP_ARG0		0x0
13#define TSP_ARG1		0x8
14#define TSP_ARG2		0x10
15#define TSP_ARG3		0x18
16#define TSP_ARG4		0x20
17#define TSP_ARG5		0x28
18#define TSP_ARG6		0x30
19#define TSP_ARG7		0x38
20#define TSP_ARGS_END		0x40
21
22
23#ifndef __ASSEMBLY__
24
25#include <cassert.h>
26#include <platform_def.h> /* For CACHE_WRITEBACK_GRANULE */
27#include <spinlock.h>
28#include <stdint.h>
29#include <tsp.h>
30
31
32typedef struct work_statistics {
33	/* Number of s-el1 interrupts on this cpu */
34	uint32_t sel1_intr_count;
35	/* Number of non s-el1 interrupts on this cpu which preempted TSP */
36	uint32_t preempt_intr_count;
37	/* Number of sync s-el1 interrupts on this cpu */
38	uint32_t sync_sel1_intr_count;
39	/* Number of s-el1 interrupts returns on this cpu */
40	uint32_t sync_sel1_intr_ret_count;
41	uint32_t smc_count;		/* Number of returns on this cpu */
42	uint32_t eret_count;		/* Number of entries on this cpu */
43	uint32_t cpu_on_count;		/* Number of cpu on requests */
44	uint32_t cpu_off_count;		/* Number of cpu off requests */
45	uint32_t cpu_suspend_count;	/* Number of cpu suspend requests */
46	uint32_t cpu_resume_count;	/* Number of cpu resume requests */
47} __aligned(CACHE_WRITEBACK_GRANULE) work_statistics_t;
48
49typedef struct tsp_args {
50	uint64_t _regs[TSP_ARGS_END >> 3];
51} __aligned(CACHE_WRITEBACK_GRANULE) tsp_args_t;
52
53/* Macros to access members of the above structure using their offsets */
54#define read_sp_arg(args, offset)	((args)->_regs[offset >> 3])
55#define write_sp_arg(args, offset, val) (((args)->_regs[offset >> 3])	\
56					 = val)
57/*
58 * Ensure that the assembler's view of the size of the tsp_args is the
59 * same as the compilers
60 */
61CASSERT(TSP_ARGS_SIZE == sizeof(tsp_args_t), assert_sp_args_size_mismatch);
62
63void tsp_get_magic(uint64_t args[4]);
64
65tsp_args_t *tsp_cpu_resume_main(uint64_t arg0,
66				uint64_t arg1,
67				uint64_t arg2,
68				uint64_t arg3,
69				uint64_t arg4,
70				uint64_t arg5,
71				uint64_t arg6,
72				uint64_t arg7);
73tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0,
74				 uint64_t arg1,
75				 uint64_t arg2,
76				 uint64_t arg3,
77				 uint64_t arg4,
78				 uint64_t arg5,
79				 uint64_t arg6,
80				 uint64_t arg7);
81tsp_args_t *tsp_cpu_on_main(void);
82tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
83			     uint64_t arg1,
84			     uint64_t arg2,
85			     uint64_t arg3,
86			     uint64_t arg4,
87			     uint64_t arg5,
88			     uint64_t arg6,
89			     uint64_t arg7);
90
91/* Generic Timer functions */
92void tsp_generic_timer_start(void);
93void tsp_generic_timer_handler(void);
94void tsp_generic_timer_stop(void);
95void tsp_generic_timer_save(void);
96void tsp_generic_timer_restore(void);
97
98/* S-EL1 interrupt management functions */
99void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3);
100
101
102/* Data structure to keep track of TSP statistics */
103extern spinlock_t console_lock;
104extern work_statistics_t tsp_stats[PLATFORM_CORE_COUNT];
105
106/* Vector table of jumps */
107extern tsp_vectors_t tsp_vector_table;
108
109
110#endif /* __ASSEMBLY__ */
111
112#endif /* __TSP_PRIVATE_H__ */
113
114