AArch64GenAsmWriter.inc revision 7925323569769659cb21e3b0d7a2f02ad02e87e3
1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|*Assembly Writer Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9/* Capstone Disassembly Engine, http://www.capstone-engine.org */ 10/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ 11 12/// printInstruction - This method is automatically generated by tablegen 13/// from the instruction set description. 14static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 15{ 16 static const uint32_t OpInfo[] = { 17 0U, // PHI 18 0U, // INLINEASM 19 0U, // CFI_INSTRUCTION 20 0U, // EH_LABEL 21 0U, // GC_LABEL 22 0U, // KILL 23 0U, // EXTRACT_SUBREG 24 0U, // INSERT_SUBREG 25 0U, // IMPLICIT_DEF 26 0U, // SUBREG_TO_REG 27 0U, // COPY_TO_REGCLASS 28 2694U, // DBG_VALUE 29 0U, // REG_SEQUENCE 30 0U, // COPY 31 2687U, // BUNDLE 32 2704U, // LIFETIME_START 33 2674U, // LIFETIME_END 34 0U, // STACKMAP 35 0U, // PATCHPOINT 36 0U, // LOAD_STACK_GUARD 37 6182U, // ABSv16i8 38 553920550U, // ABSv1i64 39 1074272294U, // ABSv2i32 40 1611405350U, // ABSv2i64 41 2148538406U, // ABSv4i16 42 2685671462U, // ABSv4i32 43 3222804518U, // ABSv8i16 44 3759937574U, // ABSv8i8 45 17049662U, // ADCSWr 46 17049662U, // ADCSXr 47 17048298U, // ADCWr 48 17048298U, // ADCXr 49 537400863U, // ADDHNv2i64_v2i32 50 571748634U, // ADDHNv2i64_v4i32 51 1074796063U, // ADDHNv4i32_v4i16 52 1108881690U, // ADDHNv4i32_v8i16 53 1644179738U, // ADDHNv8i16_v16i8 54 1612453407U, // ADDHNv8i16_v8i8 55 2147489464U, // ADDPv16i8 56 2684884664U, // ADDPv2i32 57 537663160U, // ADDPv2i64 58 1610884792U, // ADDPv2i64p 59 3222279864U, // ADDPv4i16 60 1075058360U, // ADDPv4i32 61 1612191416U, // ADDPv8i16 62 3759937208U, // ADDPv8i8 63 17049674U, // ADDSWri 64 0U, // ADDSWrr 65 17049674U, // ADDSWrs 66 17049674U, // ADDSWrx 67 17049674U, // ADDSXri 68 0U, // ADDSXrr 69 17049674U, // ADDSXrs 70 17049674U, // ADDSXrx 71 17049674U, // ADDSXrx64 72 272671U, // ADDVv16i8v 73 2147756319U, // ADDVv4i16v 74 2684627231U, // ADDVv4i32v 75 3221498143U, // ADDVv8i16v 76 3758369055U, // ADDVv8i8v 77 17048359U, // ADDWri 78 0U, // ADDWrr 79 17048359U, // ADDWrs 80 17048359U, // ADDWrx 81 17048359U, // ADDXri 82 0U, // ADDXrr 83 17048359U, // ADDXrs 84 17048359U, // ADDXrx 85 17048359U, // ADDXrx64 86 2147488551U, // ADDv16i8 87 17048359U, // ADDv1i64 88 2684883751U, // ADDv2i32 89 537662247U, // ADDv2i64 90 3222278951U, // ADDv4i16 91 1075057447U, // ADDv4i32 92 1612190503U, // ADDv8i16 93 3759936295U, // ADDv8i8 94 0U, // ADJCALLSTACKDOWN 95 0U, // ADJCALLSTACKUP 96 553920403U, // ADR 97 50603811U, // ADRP 98 33567598U, // AESDrr 99 33567656U, // AESErr 100 4852U, // AESIMCrr 101 4860U, // AESMCrr 102 17049680U, // ANDSWri 103 0U, // ANDSWrr 104 17049680U, // ANDSWrs 105 17049680U, // ANDSXri 106 0U, // ANDSXrr 107 17049680U, // ANDSXrs 108 17048425U, // ANDWri 109 0U, // ANDWrr 110 17048425U, // ANDWrs 111 17048425U, // ANDXri 112 0U, // ANDXrr 113 17048425U, // ANDXrs 114 2147488617U, // ANDv16i8 115 3759936361U, // ANDv8i8 116 17049553U, // ASRVWr 117 17049553U, // ASRVXr 118 16935U, // B 119 67380710U, // BFMWri 120 67380710U, // BFMXri 121 0U, // BICSWrr 122 17049668U, // BICSWrs 123 0U, // BICSXrr 124 17049668U, // BICSXrs 125 0U, // BICWrr 126 17048303U, // BICWrs 127 0U, // BICXrr 128 17048303U, // BICXrs 129 2147488495U, // BICv16i8 130 84423407U, // BICv2i32 131 84947695U, // BICv4i16 132 85209839U, // BICv4i32 133 85471983U, // BICv8i16 134 3759936239U, // BICv8i8 135 2147488704U, // BIFv16i8 136 3759936448U, // BIFv8i8 137 2181052603U, // BITv16i8 138 3793500347U, // BITv8i8 139 17641U, // BL 140 2107319U, // BLR 141 2107279U, // BR 142 21688U, // BRK 143 2181051810U, // BSLv16i8 144 3793499554U, // BSLv8i8 145 27247U, // Bcc 146 100936257U, // CBNZW 147 100936257U, // CBNZX 148 100936242U, // CBZW 149 100936242U, // CBZX 150 17049144U, // CCMNWi 151 17049144U, // CCMNWr 152 17049144U, // CCMNXi 153 17049144U, // CCMNXr 154 17049316U, // CCMPWi 155 17049316U, // CCMPWr 156 17049316U, // CCMPXi 157 17049316U, // CCMPXr 158 2107924U, // CLREX 159 553920604U, // CLSWr 160 553920604U, // CLSXr 161 6236U, // CLSv16i8 162 1074272348U, // CLSv2i32 163 2148538460U, // CLSv4i16 164 2685671516U, // CLSv4i32 165 3222804572U, // CLSv8i16 166 3759937628U, // CLSv8i8 167 553921084U, // CLZWr 168 553921084U, // CLZXr 169 6716U, // CLZv16i8 170 1074272828U, // CLZv2i32 171 2148538940U, // CLZv4i16 172 2685671996U, // CLZv4i32 173 3222805052U, // CLZv8i16 174 3759938108U, // CLZv8i8 175 2147489643U, // CMEQv16i8 176 5995U, // CMEQv16i8rz 177 17049451U, // CMEQv1i64 178 553920363U, // CMEQv1i64rz 179 2684884843U, // CMEQv2i32 180 1074272107U, // CMEQv2i32rz 181 537663339U, // CMEQv2i64 182 1611405163U, // CMEQv2i64rz 183 3222280043U, // CMEQv4i16 184 2148538219U, // CMEQv4i16rz 185 1075058539U, // CMEQv4i32 186 2685671275U, // CMEQv4i32rz 187 1612191595U, // CMEQv8i16 188 3222804331U, // CMEQv8i16rz 189 3759937387U, // CMEQv8i8 190 3759937387U, // CMEQv8i8rz 191 2147488636U, // CMGEv16i8 192 4988U, // CMGEv16i8rz 193 17048444U, // CMGEv1i64 194 553919356U, // CMGEv1i64rz 195 2684883836U, // CMGEv2i32 196 1074271100U, // CMGEv2i32rz 197 537662332U, // CMGEv2i64 198 1611404156U, // CMGEv2i64rz 199 3222279036U, // CMGEv4i16 200 2148537212U, // CMGEv4i16rz 201 1075057532U, // CMGEv4i32 202 2685670268U, // CMGEv4i32rz 203 1612190588U, // CMGEv8i16 204 3222803324U, // CMGEv8i16rz 205 3759936380U, // CMGEv8i8 206 3759936380U, // CMGEv8i8rz 207 2147489972U, // CMGTv16i8 208 6324U, // CMGTv16i8rz 209 17049780U, // CMGTv1i64 210 553920692U, // CMGTv1i64rz 211 2684885172U, // CMGTv2i32 212 1074272436U, // CMGTv2i32rz 213 537663668U, // CMGTv2i64 214 1611405492U, // CMGTv2i64rz 215 3222280372U, // CMGTv4i16 216 2148538548U, // CMGTv4i16rz 217 1075058868U, // CMGTv4i32 218 2685671604U, // CMGTv4i32rz 219 1612191924U, // CMGTv8i16 220 3222804660U, // CMGTv8i16rz 221 3759937716U, // CMGTv8i8 222 3759937716U, // CMGTv8i8rz 223 2147488916U, // CMHIv16i8 224 17048724U, // CMHIv1i64 225 2684884116U, // CMHIv2i32 226 537662612U, // CMHIv2i64 227 3222279316U, // CMHIv4i16 228 1075057812U, // CMHIv4i32 229 1612190868U, // CMHIv8i16 230 3759936660U, // CMHIv8i8 231 2147489878U, // CMHSv16i8 232 17049686U, // CMHSv1i64 233 2684885078U, // CMHSv2i32 234 537663574U, // CMHSv2i64 235 3222280278U, // CMHSv4i16 236 1075058774U, // CMHSv4i32 237 1612191830U, // CMHSv8i16 238 3759937622U, // CMHSv8i8 239 4995U, // CMLEv16i8rz 240 553919363U, // CMLEv1i64rz 241 1074271107U, // CMLEv2i32rz 242 1611404163U, // CMLEv2i64rz 243 2148537219U, // CMLEv4i16rz 244 2685670275U, // CMLEv4i32rz 245 3222803331U, // CMLEv8i16rz 246 3759936387U, // CMLEv8i8rz 247 6342U, // CMLTv16i8rz 248 553920710U, // CMLTv1i64rz 249 1074272454U, // CMLTv2i32rz 250 1611405510U, // CMLTv2i64rz 251 2148538566U, // CMLTv4i16rz 252 2685671622U, // CMLTv4i32rz 253 3222804678U, // CMLTv8i16rz 254 3759937734U, // CMLTv8i8rz 255 2147490013U, // CMTSTv16i8 256 17049821U, // CMTSTv1i64 257 2684885213U, // CMTSTv2i32 258 537663709U, // CMTSTv2i64 259 3222280413U, // CMTSTv4i16 260 1075058909U, // CMTSTv4i32 261 1612191965U, // CMTSTv8i16 262 3759937757U, // CMTSTv8i8 263 6348U, // CNTv16i8 264 3759937740U, // CNTv8i8 265 272763U, // CPYi16 266 537143675U, // CPYi32 267 1074014587U, // CPYi64 268 1610885499U, // CPYi8 269 17048098U, // CRC32Brr 270 17048106U, // CRC32CBrr 271 17048575U, // CRC32CHrr 272 17050039U, // CRC32CWrr 273 17050123U, // CRC32CXrr 274 17048558U, // CRC32Hrr 275 17050017U, // CRC32Wrr 276 17050092U, // CRC32Xrr 277 17048888U, // CSELWr 278 17048888U, // CSELXr 279 17048323U, // CSINCWr 280 17048323U, // CSINCXr 281 17049971U, // CSINVWr 282 17049971U, // CSINVXr 283 17048544U, // CSNEGWr 284 17048544U, // CSNEGXr 285 20524U, // DCPS1 286 20889U, // DCPS2 287 20938U, // DCPS3 288 29235U, // DMB 289 2719U, // DRPS 290 29324U, // DSB 291 553654070U, // DUPv16i8gpr 292 1610618678U, // DUPv16i8lane 293 554178358U, // DUPv2i32gpr 294 537401142U, // DUPv2i32lane 295 554440502U, // DUPv2i64gpr 296 1074534198U, // DUPv2i64lane 297 554702646U, // DUPv4i16gpr 298 1054518U, // DUPv4i16lane 299 554964790U, // DUPv4i32gpr 300 538187574U, // DUPv4i32lane 301 555226934U, // DUPv8i16gpr 302 1578806U, // DUPv8i16lane 303 555489078U, // DUPv8i8gpr 304 1612453686U, // DUPv8i8lane 305 0U, // EONWrr 306 17049150U, // EONWrs 307 0U, // EONXrr 308 17049150U, // EONXrs 309 17049538U, // EORWri 310 0U, // EORWrr 311 17049538U, // EORWrs 312 17049538U, // EORXri 313 0U, // EORXrr 314 17049538U, // EORXrs 315 2147489730U, // EORv16i8 316 3759937474U, // EORv8i8 317 2724U, // ERET 318 17049585U, // EXTRWrri 319 17049585U, // EXTRXrri 320 2147490026U, // EXTv16i8 321 3759937770U, // EXTv8i8 322 0U, // F128CSEL 323 17048340U, // FABD32 324 17048340U, // FABD64 325 2684883732U, // FABDv2f32 326 537662228U, // FABDv2f64 327 1075057428U, // FABDv4f32 328 553920549U, // FABSDr 329 553920549U, // FABSSr 330 1074272293U, // FABSv2f32 331 1611405349U, // FABSv2f64 332 2685671461U, // FABSv4f32 333 17048436U, // FACGE32 334 17048436U, // FACGE64 335 2684883828U, // FACGEv2f32 336 537662324U, // FACGEv2f64 337 1075057524U, // FACGEv4f32 338 17049772U, // FACGT32 339 17049772U, // FACGT64 340 2684885164U, // FACGTv2f32 341 537663660U, // FACGTv2f64 342 1075058860U, // FACGTv4f32 343 17048358U, // FADDDrr 344 2684884663U, // FADDPv2f32 345 537663159U, // FADDPv2f64 346 1074013879U, // FADDPv2i32p 347 1610884791U, // FADDPv2i64p 348 1075058359U, // FADDPv4f32 349 17048358U, // FADDSrr 350 2684883750U, // FADDv2f32 351 537662246U, // FADDv2f64 352 1075057446U, // FADDv4f32 353 17049315U, // FCCMPDrr 354 17048473U, // FCCMPEDrr 355 17048473U, // FCCMPESrr 356 17049315U, // FCCMPSrr 357 17049450U, // FCMEQ32 358 17049450U, // FCMEQ64 359 2164533098U, // FCMEQv1i32rz 360 2164533098U, // FCMEQv1i64rz 361 2684884842U, // FCMEQv2f32 362 537663338U, // FCMEQv2f64 363 2684884842U, // FCMEQv2i32rz 364 3222017898U, // FCMEQv2i64rz 365 1075058538U, // FCMEQv4f32 366 3759413098U, // FCMEQv4i32rz 367 17048443U, // FCMGE32 368 17048443U, // FCMGE64 369 2164532091U, // FCMGEv1i32rz 370 2164532091U, // FCMGEv1i64rz 371 2684883835U, // FCMGEv2f32 372 537662331U, // FCMGEv2f64 373 2684883835U, // FCMGEv2i32rz 374 3222016891U, // FCMGEv2i64rz 375 1075057531U, // FCMGEv4f32 376 3759412091U, // FCMGEv4i32rz 377 17049779U, // FCMGT32 378 17049779U, // FCMGT64 379 2164533427U, // FCMGTv1i32rz 380 2164533427U, // FCMGTv1i64rz 381 2684885171U, // FCMGTv2f32 382 537663667U, // FCMGTv2f64 383 2684885171U, // FCMGTv2i32rz 384 3222018227U, // FCMGTv2i64rz 385 1075058867U, // FCMGTv4f32 386 3759413427U, // FCMGTv4i32rz 387 2164532098U, // FCMLEv1i32rz 388 2164532098U, // FCMLEv1i64rz 389 2684883842U, // FCMLEv2i32rz 390 3222016898U, // FCMLEv2i64rz 391 3759412098U, // FCMLEv4i32rz 392 2164533445U, // FCMLTv1i32rz 393 2164533445U, // FCMLTv1i64rz 394 2684885189U, // FCMLTv2i32rz 395 3222018245U, // FCMLTv2i64rz 396 3759413445U, // FCMLTv4i32rz 397 2369258U, // FCMPDri 398 553920234U, // FCMPDrr 399 2368417U, // FCMPEDri 400 553919393U, // FCMPEDrr 401 2368417U, // FCMPESri 402 553919393U, // FCMPESrr 403 2369258U, // FCMPSri 404 553920234U, // FCMPSrr 405 17048887U, // FCSELDrrr 406 17048887U, // FCSELSrrr 407 553920541U, // FCVTASUWDr 408 553920541U, // FCVTASUWSr 409 553920541U, // FCVTASUXDr 410 553920541U, // FCVTASUXSr 411 553920541U, // FCVTASv1i32 412 553920541U, // FCVTASv1i64 413 1074272285U, // FCVTASv2f32 414 1611405341U, // FCVTASv2f64 415 2685671453U, // FCVTASv4f32 416 553920751U, // FCVTAUUWDr 417 553920751U, // FCVTAUUWSr 418 553920751U, // FCVTAUUXDr 419 553920751U, // FCVTAUUXSr 420 553920751U, // FCVTAUv1i32 421 553920751U, // FCVTAUv1i64 422 1074272495U, // FCVTAUv2f32 423 1611405551U, // FCVTAUv2f64 424 2685671663U, // FCVTAUv4f32 425 553920740U, // FCVTDHr 426 553920740U, // FCVTDSr 427 553920740U, // FCVTHDr 428 553920740U, // FCVTHSr 429 1074533828U, // FCVTLv2i32 430 2148799940U, // FCVTLv4i16 431 2685145352U, // FCVTLv4i32 432 3222540552U, // FCVTLv8i16 433 553920615U, // FCVTMSUWDr 434 553920615U, // FCVTMSUWSr 435 553920615U, // FCVTMSUXDr 436 553920615U, // FCVTMSUXSr 437 553920615U, // FCVTMSv1i32 438 553920615U, // FCVTMSv1i64 439 1074272359U, // FCVTMSv2f32 440 1611405415U, // FCVTMSv2f64 441 2685671527U, // FCVTMSv4f32 442 553920767U, // FCVTMUUWDr 443 553920767U, // FCVTMUUWSr 444 553920767U, // FCVTMUUXDr 445 553920767U, // FCVTMUUXSr 446 553920767U, // FCVTMUv1i32 447 553920767U, // FCVTMUv1i64 448 1074272511U, // FCVTMUv2f32 449 1611405567U, // FCVTMUv2f64 450 2685671679U, // FCVTMUv4f32 451 553920628U, // FCVTNSUWDr 452 553920628U, // FCVTNSUWSr 453 553920628U, // FCVTNSUXDr 454 553920628U, // FCVTNSUXSr 455 553920628U, // FCVTNSv1i32 456 553920628U, // FCVTNSv1i64 457 1074272372U, // FCVTNSv2f32 458 1611405428U, // FCVTNSv2f64 459 2685671540U, // FCVTNSv4f32 460 553920775U, // FCVTNUUWDr 461 553920775U, // FCVTNUUWSr 462 553920775U, // FCVTNUUXDr 463 553920775U, // FCVTNUUXSr 464 553920775U, // FCVTNUv1i32 465 553920775U, // FCVTNUv1i64 466 1074272519U, // FCVTNUv2f32 467 1611405575U, // FCVTNUv2f64 468 2685671687U, // FCVTNUv4f32 469 1611142770U, // FCVTNv2i32 470 2685408882U, // FCVTNv4i16 471 1645490510U, // FCVTNv4i32 472 2719494478U, // FCVTNv8i16 473 553920644U, // FCVTPSUWDr 474 553920644U, // FCVTPSUWSr 475 553920644U, // FCVTPSUXDr 476 553920644U, // FCVTPSUXSr 477 553920644U, // FCVTPSv1i32 478 553920644U, // FCVTPSv1i64 479 1074272388U, // FCVTPSv2f32 480 1611405444U, // FCVTPSv2f64 481 2685671556U, // FCVTPSv4f32 482 553920783U, // FCVTPUUWDr 483 553920783U, // FCVTPUUWSr 484 553920783U, // FCVTPUUXDr 485 553920783U, // FCVTPUUXSr 486 553920783U, // FCVTPUv1i32 487 553920783U, // FCVTPUv1i64 488 1074272527U, // FCVTPUv2f32 489 1611405583U, // FCVTPUv2f64 490 2685671695U, // FCVTPUv4f32 491 553920740U, // FCVTSDr 492 553920740U, // FCVTSHr 493 553920168U, // FCVTXNv1i64 494 1611142824U, // FCVTXNv2f32 495 1645490564U, // FCVTXNv4f32 496 17049759U, // FCVTZSSWDri 497 17049759U, // FCVTZSSWSri 498 17049759U, // FCVTZSSXDri 499 17049759U, // FCVTZSSXSri 500 553920671U, // FCVTZSUWDr 501 553920671U, // FCVTZSUWSr 502 553920671U, // FCVTZSUXDr 503 553920671U, // FCVTZSUXSr 504 17049759U, // FCVTZS_IntSWDri 505 17049759U, // FCVTZS_IntSWSri 506 17049759U, // FCVTZS_IntSXDri 507 17049759U, // FCVTZS_IntSXSri 508 553920671U, // FCVTZS_IntUWDr 509 553920671U, // FCVTZS_IntUWSr 510 553920671U, // FCVTZS_IntUXDr 511 553920671U, // FCVTZS_IntUXSr 512 1074272415U, // FCVTZS_Intv2f32 513 1611405471U, // FCVTZS_Intv2f64 514 2685671583U, // FCVTZS_Intv4f32 515 17049759U, // FCVTZSd 516 17049759U, // FCVTZSs 517 553920671U, // FCVTZSv1i32 518 553920671U, // FCVTZSv1i64 519 1074272415U, // FCVTZSv2f32 520 1611405471U, // FCVTZSv2f64 521 2684885151U, // FCVTZSv2i32_shift 522 537663647U, // FCVTZSv2i64_shift 523 2685671583U, // FCVTZSv4f32 524 1075058847U, // FCVTZSv4i32_shift 525 17049879U, // FCVTZUSWDri 526 17049879U, // FCVTZUSWSri 527 17049879U, // FCVTZUSXDri 528 17049879U, // FCVTZUSXSri 529 553920791U, // FCVTZUUWDr 530 553920791U, // FCVTZUUWSr 531 553920791U, // FCVTZUUXDr 532 553920791U, // FCVTZUUXSr 533 17049879U, // FCVTZU_IntSWDri 534 17049879U, // FCVTZU_IntSWSri 535 17049879U, // FCVTZU_IntSXDri 536 17049879U, // FCVTZU_IntSXSri 537 553920791U, // FCVTZU_IntUWDr 538 553920791U, // FCVTZU_IntUWSr 539 553920791U, // FCVTZU_IntUXDr 540 553920791U, // FCVTZU_IntUXSr 541 1074272535U, // FCVTZU_Intv2f32 542 1611405591U, // FCVTZU_Intv2f64 543 2685671703U, // FCVTZU_Intv4f32 544 17049879U, // FCVTZUd 545 17049879U, // FCVTZUs 546 553920791U, // FCVTZUv1i32 547 553920791U, // FCVTZUv1i64 548 1074272535U, // FCVTZUv2f32 549 1611405591U, // FCVTZUv2f64 550 2684885271U, // FCVTZUv2i32_shift 551 537663767U, // FCVTZUv2i64_shift 552 2685671703U, // FCVTZUv4f32 553 1075058967U, // FCVTZUv4i32_shift 554 17049898U, // FDIVDrr 555 17049898U, // FDIVSrr 556 2684885290U, // FDIVv2f32 557 537663786U, // FDIVv2f64 558 1075058986U, // FDIVv4f32 559 17048394U, // FMADDDrrr 560 17048394U, // FMADDSrrr 561 17050100U, // FMAXDrr 562 17049087U, // FMAXNMDrr 563 2684884729U, // FMAXNMPv2f32 564 537663225U, // FMAXNMPv2f64 565 1074013945U, // FMAXNMPv2i32p 566 1610884857U, // FMAXNMPv2i64p 567 1075058425U, // FMAXNMPv4f32 568 17049087U, // FMAXNMSrr 569 2684627285U, // FMAXNMVv4i32v 570 2684884479U, // FMAXNMv2f32 571 537662975U, // FMAXNMv2f64 572 1075058175U, // FMAXNMv4f32 573 2684884802U, // FMAXPv2f32 574 537663298U, // FMAXPv2f64 575 1074014018U, // FMAXPv2i32p 576 1610884930U, // FMAXPv2i64p 577 1075058498U, // FMAXPv4f32 578 17050100U, // FMAXSrr 579 2684627340U, // FMAXVv4i32v 580 2684885492U, // FMAXv2f32 581 537663988U, // FMAXv2f64 582 1075059188U, // FMAXv4f32 583 17049126U, // FMINDrr 584 17049079U, // FMINNMDrr 585 2684884720U, // FMINNMPv2f32 586 537663216U, // FMINNMPv2f64 587 1074013936U, // FMINNMPv2i32p 588 1610884848U, // FMINNMPv2i64p 589 1075058416U, // FMINNMPv4f32 590 17049079U, // FMINNMSrr 591 2684627276U, // FMINNMVv4i32v 592 2684884471U, // FMINNMv2f32 593 537662967U, // FMINNMv2f64 594 1075058167U, // FMINNMv4f32 595 2684884744U, // FMINPv2f32 596 537663240U, // FMINPv2f64 597 1074013960U, // FMINPv2i32p 598 1610884872U, // FMINPv2i64p 599 1075058440U, // FMINPv4f32 600 17049126U, // FMINSrr 601 2684627294U, // FMINVv4i32v 602 2684884518U, // FMINv2f32 603 537663014U, // FMINv2f64 604 1075058214U, // FMINv4f32 605 67404282U, // FMLAv1i32_indexed 606 67404282U, // FMLAv1i64_indexed 607 2718446074U, // FMLAv2f32 608 571224570U, // FMLAv2f64 609 2718446074U, // FMLAv2i32_indexed 610 571224570U, // FMLAv2i64_indexed 611 1108619770U, // FMLAv4f32 612 1108619770U, // FMLAv4i32_indexed 613 67405921U, // FMLSv1i32_indexed 614 67405921U, // FMLSv1i64_indexed 615 2718447713U, // FMLSv2f32 616 571226209U, // FMLSv2f64 617 2718447713U, // FMLSv2i32_indexed 618 571226209U, // FMLSv2i64_indexed 619 1108621409U, // FMLSv4f32 620 1108621409U, // FMLSv4i32_indexed 621 1074014586U, // FMOVDXHighr 622 553920890U, // FMOVDXr 623 117713274U, // FMOVDi 624 553920890U, // FMOVDr 625 553920890U, // FMOVSWr 626 117713274U, // FMOVSi 627 553920890U, // FMOVSr 628 553920890U, // FMOVWSr 629 556276090U, // FMOVXDHighr 630 553920890U, // FMOVXDr 631 117971322U, // FMOVv2f32_ns 632 118233466U, // FMOVv2f64_ns 633 118757754U, // FMOVv4f32_ns 634 17048257U, // FMSUBDrrr 635 17048257U, // FMSUBSrrr 636 17049035U, // FMULDrr 637 17049035U, // FMULSrr 638 17050139U, // FMULX32 639 17050139U, // FMULX64 640 17050139U, // FMULXv1i32_indexed 641 17050139U, // FMULXv1i64_indexed 642 2684885531U, // FMULXv2f32 643 537664027U, // FMULXv2f64 644 2684885531U, // FMULXv2i32_indexed 645 537664027U, // FMULXv2i64_indexed 646 1075059227U, // FMULXv4f32 647 1075059227U, // FMULXv4i32_indexed 648 17049035U, // FMULv1i32_indexed 649 17049035U, // FMULv1i64_indexed 650 2684884427U, // FMULv2f32 651 537662923U, // FMULv2f64 652 2684884427U, // FMULv2i32_indexed 653 537662923U, // FMULv2i64_indexed 654 1075058123U, // FMULv4f32 655 1075058123U, // FMULv4i32_indexed 656 553919443U, // FNEGDr 657 553919443U, // FNEGSr 658 1074271187U, // FNEGv2f32 659 1611404243U, // FNEGv2f64 660 2685670355U, // FNEGv4f32 661 17048401U, // FNMADDDrrr 662 17048401U, // FNMADDSrrr 663 17048264U, // FNMSUBDrrr 664 17048264U, // FNMSUBSrrr 665 17049041U, // FNMULDrr 666 17049041U, // FNMULSrr 667 553919369U, // FRECPEv1i32 668 553919369U, // FRECPEv1i64 669 1074271113U, // FRECPEv2f32 670 1611404169U, // FRECPEv2f64 671 2685670281U, // FRECPEv4f32 672 17049724U, // FRECPS32 673 17049724U, // FRECPS64 674 2684885116U, // FRECPSv2f32 675 537663612U, // FRECPSv2f64 676 1075058812U, // FRECPSv4f32 677 553921058U, // FRECPXv1i32 678 553921058U, // FRECPXv1i64 679 553919002U, // FRINTADr 680 553919002U, // FRINTASr 681 1074270746U, // FRINTAv2f32 682 1611403802U, // FRINTAv2f64 683 2685669914U, // FRINTAv4f32 684 553919658U, // FRINTIDr 685 553919658U, // FRINTISr 686 1074271402U, // FRINTIv2f32 687 1611404458U, // FRINTIv2f64 688 2685670570U, // FRINTIv4f32 689 553920007U, // FRINTMDr 690 553920007U, // FRINTMSr 691 1074271751U, // FRINTMv2f32 692 1611404807U, // FRINTMv2f64 693 2685670919U, // FRINTMv4f32 694 553920106U, // FRINTNDr 695 553920106U, // FRINTNSr 696 1074271850U, // FRINTNv2f32 697 1611404906U, // FRINTNv2f64 698 2685671018U, // FRINTNv4f32 699 553920297U, // FRINTPDr 700 553920297U, // FRINTPSr 701 1074272041U, // FRINTPv2f32 702 1611405097U, // FRINTPv2f64 703 2685671209U, // FRINTPv4f32 704 553921066U, // FRINTXDr 705 553921066U, // FRINTXSr 706 1074272810U, // FRINTXv2f32 707 1611405866U, // FRINTXv2f64 708 2685671978U, // FRINTXv4f32 709 553921101U, // FRINTZDr 710 553921101U, // FRINTZSr 711 1074272845U, // FRINTZv2f32 712 1611405901U, // FRINTZv2f64 713 2685672013U, // FRINTZv4f32 714 553919406U, // FRSQRTEv1i32 715 553919406U, // FRSQRTEv1i64 716 1074271150U, // FRSQRTEv2f32 717 1611404206U, // FRSQRTEv2f64 718 2685670318U, // FRSQRTEv4f32 719 17049745U, // FRSQRTS32 720 17049745U, // FRSQRTS64 721 2684885137U, // FRSQRTSv2f32 722 537663633U, // FRSQRTSv2f64 723 1075058833U, // FRSQRTSv4f32 724 553920726U, // FSQRTDr 725 553920726U, // FSQRTSr 726 1074272470U, // FSQRTv2f32 727 1611405526U, // FSQRTv2f64 728 2685671638U, // FSQRTv4f32 729 17048237U, // FSUBDrr 730 17048237U, // FSUBSrr 731 2684883629U, // FSUBv2f32 732 537662125U, // FSUBv2f64 733 1075057325U, // FSUBv4f32 734 23145U, // HINT 735 22720U, // HLT 736 21258U, // HVC 737 137115759U, // INSvi16gpr 738 153892975U, // INSvi16lane 739 137377903U, // INSvi32gpr 740 691026031U, // INSvi32lane 741 136853615U, // INSvi64gpr 742 1227372655U, // INSvi64lane 743 137640047U, // INSvi8gpr 744 1765029999U, // INSvi8lane 745 29329U, // ISB 746 36885U, // LD1Fourv16b 747 3710997U, // LD1Fourv16b_POST 748 45077U, // LD1Fourv1d 749 3981333U, // LD1Fourv1d_POST 750 53269U, // LD1Fourv2d 751 3727381U, // LD1Fourv2d_POST 752 61461U, // LD1Fourv2s 753 3997717U, // LD1Fourv2s_POST 754 69653U, // LD1Fourv4h 755 4005909U, // LD1Fourv4h_POST 756 77845U, // LD1Fourv4s 757 3751957U, // LD1Fourv4s_POST 758 86037U, // LD1Fourv8b 759 4022293U, // LD1Fourv8b_POST 760 94229U, // LD1Fourv8h 761 3768341U, // LD1Fourv8h_POST 762 36885U, // LD1Onev16b 763 4235285U, // LD1Onev16b_POST 764 45077U, // LD1Onev1d 765 4505621U, // LD1Onev1d_POST 766 53269U, // LD1Onev2d 767 4251669U, // LD1Onev2d_POST 768 61461U, // LD1Onev2s 769 4522005U, // LD1Onev2s_POST 770 69653U, // LD1Onev4h 771 4530197U, // LD1Onev4h_POST 772 77845U, // LD1Onev4s 773 4276245U, // LD1Onev4s_POST 774 86037U, // LD1Onev8b 775 4546581U, // LD1Onev8b_POST 776 94229U, // LD1Onev8h 777 4292629U, // LD1Onev8h_POST 778 38769U, // LD1Rv16b 779 4761457U, // LD1Rv16b_POST 780 46961U, // LD1Rv1d 781 4507505U, // LD1Rv1d_POST 782 55153U, // LD1Rv2d 783 4515697U, // LD1Rv2d_POST 784 63345U, // LD1Rv2s 785 5048177U, // LD1Rv2s_POST 786 71537U, // LD1Rv4h 787 5318513U, // LD1Rv4h_POST 788 79729U, // LD1Rv4s 789 5064561U, // LD1Rv4s_POST 790 87921U, // LD1Rv8b 791 4810609U, // LD1Rv8b_POST 792 96113U, // LD1Rv8h 793 5343089U, // LD1Rv8h_POST 794 36885U, // LD1Threev16b 795 5546005U, // LD1Threev16b_POST 796 45077U, // LD1Threev1d 797 5816341U, // LD1Threev1d_POST 798 53269U, // LD1Threev2d 799 5562389U, // LD1Threev2d_POST 800 61461U, // LD1Threev2s 801 5832725U, // LD1Threev2s_POST 802 69653U, // LD1Threev4h 803 5840917U, // LD1Threev4h_POST 804 77845U, // LD1Threev4s 805 5586965U, // LD1Threev4s_POST 806 86037U, // LD1Threev8b 807 5857301U, // LD1Threev8b_POST 808 94229U, // LD1Threev8h 809 5603349U, // LD1Threev8h_POST 810 36885U, // LD1Twov16b 811 3973141U, // LD1Twov16b_POST 812 45077U, // LD1Twov1d 813 4243477U, // LD1Twov1d_POST 814 53269U, // LD1Twov2d 815 3989525U, // LD1Twov2d_POST 816 61461U, // LD1Twov2s 817 4259861U, // LD1Twov2s_POST 818 69653U, // LD1Twov4h 819 4268053U, // LD1Twov4h_POST 820 77845U, // LD1Twov4s 821 4014101U, // LD1Twov4s_POST 822 86037U, // LD1Twov8b 823 4284437U, // LD1Twov8b_POST 824 94229U, // LD1Twov8h 825 4030485U, // LD1Twov8h_POST 826 6131733U, // LD1i16 827 6397973U, // LD1i16_POST 828 6139925U, // LD1i32 829 6668309U, // LD1i32_POST 830 6148117U, // LD1i64 831 6938645U, // LD1i64_POST 832 6156309U, // LD1i8 833 7208981U, // LD1i8_POST 834 38775U, // LD2Rv16b 835 5285751U, // LD2Rv16b_POST 836 46967U, // LD2Rv1d 837 4245367U, // LD2Rv1d_POST 838 55159U, // LD2Rv2d 839 4253559U, // LD2Rv2d_POST 840 63351U, // LD2Rv2s 841 4523895U, // LD2Rv2s_POST 842 71543U, // LD2Rv4h 843 5056375U, // LD2Rv4h_POST 844 79735U, // LD2Rv4s 845 4540279U, // LD2Rv4s_POST 846 87927U, // LD2Rv8b 847 5334903U, // LD2Rv8b_POST 848 96119U, // LD2Rv8h 849 5080951U, // LD2Rv8h_POST 850 36947U, // LD2Twov16b 851 3973203U, // LD2Twov16b_POST 852 53331U, // LD2Twov2d 853 3989587U, // LD2Twov2d_POST 854 61523U, // LD2Twov2s 855 4259923U, // LD2Twov2s_POST 856 69715U, // LD2Twov4h 857 4268115U, // LD2Twov4h_POST 858 77907U, // LD2Twov4s 859 4014163U, // LD2Twov4s_POST 860 86099U, // LD2Twov8b 861 4284499U, // LD2Twov8b_POST 862 94291U, // LD2Twov8h 863 4030547U, // LD2Twov8h_POST 864 6131795U, // LD2i16 865 6660179U, // LD2i16_POST 866 6139987U, // LD2i32 867 6930515U, // LD2i32_POST 868 6148179U, // LD2i64 869 7462995U, // LD2i64_POST 870 6156371U, // LD2i8 871 6422611U, // LD2i8_POST 872 38781U, // LD3Rv16b 873 7645053U, // LD3Rv16b_POST 874 46973U, // LD3Rv1d 875 5818237U, // LD3Rv1d_POST 876 55165U, // LD3Rv2d 877 5826429U, // LD3Rv2d_POST 878 63357U, // LD3Rv2s 879 7931773U, // LD3Rv2s_POST 880 71549U, // LD3Rv4h 881 8202109U, // LD3Rv4h_POST 882 79741U, // LD3Rv4s 883 7948157U, // LD3Rv4s_POST 884 87933U, // LD3Rv8b 885 7694205U, // LD3Rv8b_POST 886 96125U, // LD3Rv8h 887 8226685U, // LD3Rv8h_POST 888 37317U, // LD3Threev16b 889 5546437U, // LD3Threev16b_POST 890 53701U, // LD3Threev2d 891 5562821U, // LD3Threev2d_POST 892 61893U, // LD3Threev2s 893 5833157U, // LD3Threev2s_POST 894 70085U, // LD3Threev4h 895 5841349U, // LD3Threev4h_POST 896 78277U, // LD3Threev4s 897 5587397U, // LD3Threev4s_POST 898 86469U, // LD3Threev8b 899 5857733U, // LD3Threev8b_POST 900 94661U, // LD3Threev8h 901 5603781U, // LD3Threev8h_POST 902 6132165U, // LD3i16 903 8495557U, // LD3i16_POST 904 6140357U, // LD3i32 905 8765893U, // LD3i32_POST 906 6148549U, // LD3i64 907 9036229U, // LD3i64_POST 908 6156741U, // LD3i8 909 9306565U, // LD3i8_POST 910 37341U, // LD4Fourv16b 911 3711453U, // LD4Fourv16b_POST 912 53725U, // LD4Fourv2d 913 3727837U, // LD4Fourv2d_POST 914 61917U, // LD4Fourv2s 915 3998173U, // LD4Fourv2s_POST 916 70109U, // LD4Fourv4h 917 4006365U, // LD4Fourv4h_POST 918 78301U, // LD4Fourv4s 919 3752413U, // LD4Fourv4s_POST 920 86493U, // LD4Fourv8b 921 4022749U, // LD4Fourv8b_POST 922 94685U, // LD4Fourv8h 923 3768797U, // LD4Fourv8h_POST 924 38787U, // LD4Rv16b 925 5023619U, // LD4Rv16b_POST 926 46979U, // LD4Rv1d 927 3983235U, // LD4Rv1d_POST 928 55171U, // LD4Rv2d 929 3991427U, // LD4Rv2d_POST 930 63363U, // LD4Rv2s 931 4261763U, // LD4Rv2s_POST 932 71555U, // LD4Rv4h 933 4532099U, // LD4Rv4h_POST 934 79747U, // LD4Rv4s 935 4278147U, // LD4Rv4s_POST 936 87939U, // LD4Rv8b 937 5072771U, // LD4Rv8b_POST 938 96131U, // LD4Rv8h 939 4556675U, // LD4Rv8h_POST 940 6132189U, // LD4i16 941 6922717U, // LD4i16_POST 942 6140381U, // LD4i32 943 7455197U, // LD4i32_POST 944 6148573U, // LD4i64 945 9560541U, // LD4i64_POST 946 6156765U, // LD4i8 947 6685149U, // LD4i8_POST 948 26485304U, // LDARB 949 26485801U, // LDARH 950 26486665U, // LDARW 951 26486665U, // LDARX 952 553920315U, // LDAXPW 953 553920315U, // LDAXPX 954 26485358U, // LDAXRB 955 26485855U, // LDAXRH 956 26486787U, // LDAXRW 957 26486787U, // LDAXRX 958 553920258U, // LDNPDi 959 553920258U, // LDNPQi 960 553920258U, // LDNPSi 961 553920258U, // LDNPWi 962 553920258U, // LDNPXi 963 553920190U, // LDPDi 964 604276414U, // LDPDpost 965 604276414U, // LDPDpre 966 553920190U, // LDPQi 967 604276414U, // LDPQpost 968 604276414U, // LDPQpre 969 553920974U, // LDPSWi 970 604277198U, // LDPSWpost 971 604277198U, // LDPSWpre 972 553920190U, // LDPSi 973 604276414U, // LDPSpost 974 604276414U, // LDPSpre 975 553920190U, // LDPWi 976 604276414U, // LDPWpost 977 604276414U, // LDPWpre 978 553920190U, // LDPXi 979 604276414U, // LDPXpost 980 604276414U, // LDPXpre 981 1150583359U, // LDRBBpost 982 76841535U, // LDRBBpre 983 26485311U, // LDRBBroW 984 26485311U, // LDRBBroX 985 26485311U, // LDRBBui 986 1150584728U, // LDRBpost 987 76842904U, // LDRBpre 988 26486680U, // LDRBroW 989 26486680U, // LDRBroX 990 26486680U, // LDRBui 991 100935576U, // LDRDl 992 1150584728U, // LDRDpost 993 76842904U, // LDRDpre 994 26486680U, // LDRDroW 995 26486680U, // LDRDroX 996 26486680U, // LDRDui 997 1150583856U, // LDRHHpost 998 76842032U, // LDRHHpre 999 26485808U, // LDRHHroW 1000 26485808U, // LDRHHroX 1001 26485808U, // LDRHHui 1002 1150584728U, // LDRHpost 1003 76842904U, // LDRHpre 1004 26486680U, // LDRHroW 1005 26486680U, // LDRHroX 1006 26486680U, // LDRHui 1007 100935576U, // LDRQl 1008 1150584728U, // LDRQpost 1009 76842904U, // LDRQpre 1010 26486680U, // LDRQroW 1011 26486680U, // LDRQroX 1012 26486680U, // LDRQui 1013 1150583446U, // LDRSBWpost 1014 76841622U, // LDRSBWpre 1015 26485398U, // LDRSBWroW 1016 26485398U, // LDRSBWroX 1017 26485398U, // LDRSBWui 1018 1150583446U, // LDRSBXpost 1019 76841622U, // LDRSBXpre 1020 26485398U, // LDRSBXroW 1021 26485398U, // LDRSBXroX 1022 26485398U, // LDRSBXui 1023 1150583933U, // LDRSHWpost 1024 76842109U, // LDRSHWpre 1025 26485885U, // LDRSHWroW 1026 26485885U, // LDRSHWroX 1027 26485885U, // LDRSHWui 1028 1150583933U, // LDRSHXpost 1029 76842109U, // LDRSHXpre 1030 26485885U, // LDRSHXroW 1031 26485885U, // LDRSHXroX 1032 26485885U, // LDRSHXui 1033 100936149U, // LDRSWl 1034 1150585301U, // LDRSWpost 1035 76843477U, // LDRSWpre 1036 26487253U, // LDRSWroW 1037 26487253U, // LDRSWroX 1038 26487253U, // LDRSWui 1039 100935576U, // LDRSl 1040 1150584728U, // LDRSpost 1041 76842904U, // LDRSpre 1042 26486680U, // LDRSroW 1043 26486680U, // LDRSroX 1044 26486680U, // LDRSui 1045 100935576U, // LDRWl 1046 1150584728U, // LDRWpost 1047 76842904U, // LDRWpre 1048 26486680U, // LDRWroW 1049 26486680U, // LDRWroX 1050 26486680U, // LDRWui 1051 100935576U, // LDRXl 1052 1150584728U, // LDRXpost 1053 76842904U, // LDRXpre 1054 26486680U, // LDRXroW 1055 26486680U, // LDRXroX 1056 26486680U, // LDRXui 1057 26485324U, // LDTRBi 1058 26485821U, // LDTRHi 1059 26485405U, // LDTRSBWi 1060 26485405U, // LDTRSBXi 1061 26485892U, // LDTRSHWi 1062 26485892U, // LDTRSHXi 1063 26487260U, // LDTRSWi 1064 26486752U, // LDTRWi 1065 26486752U, // LDTRXi 1066 26485344U, // LDURBBi 1067 26486775U, // LDURBi 1068 26486775U, // LDURDi 1069 26485841U, // LDURHHi 1070 26486775U, // LDURHi 1071 26486775U, // LDURQi 1072 26485413U, // LDURSBWi 1073 26485413U, // LDURSBXi 1074 26485900U, // LDURSHWi 1075 26485900U, // LDURSHXi 1076 26487268U, // LDURSWi 1077 26486775U, // LDURSi 1078 26486775U, // LDURWi 1079 26486775U, // LDURXi 1080 553920343U, // LDXPW 1081 553920343U, // LDXPX 1082 26485366U, // LDXRB 1083 26485863U, // LDXRH 1084 26486794U, // LDXRW 1085 26486794U, // LDXRX 1086 0U, // LOADgot 1087 17049003U, // LSLVWr 1088 17049003U, // LSLVXr 1089 17049558U, // LSRVWr 1090 17049558U, // LSRVXr 1091 17048395U, // MADDWrrr 1092 17048395U, // MADDXrrr 1093 2181050875U, // MLAv16i8 1094 2718446075U, // MLAv2i32 1095 2718446075U, // MLAv2i32_indexed 1096 3255841275U, // MLAv4i16 1097 3255841275U, // MLAv4i16_indexed 1098 1108619771U, // MLAv4i32 1099 1108619771U, // MLAv4i32_indexed 1100 1645752827U, // MLAv8i16 1101 1645752827U, // MLAv8i16_indexed 1102 3793498619U, // MLAv8i8 1103 2181052514U, // MLSv16i8 1104 2718447714U, // MLSv2i32 1105 2718447714U, // MLSv2i32_indexed 1106 3255842914U, // MLSv4i16 1107 3255842914U, // MLSv4i16_indexed 1108 1108621410U, // MLSv4i32 1109 1108621410U, // MLSv4i32_indexed 1110 1645754466U, // MLSv8i16 1111 1645754466U, // MLSv8i16_indexed 1112 3793500258U, // MLSv8i8 1113 168043698U, // MOVID 1114 721425586U, // MOVIv16b_ns 1115 168563890U, // MOVIv2d_ns 1116 1795691698U, // MOVIv2i32 1117 1795691698U, // MOVIv2s_msl 1118 1796215986U, // MOVIv4i16 1119 1796478130U, // MOVIv4i32 1120 1796478130U, // MOVIv4s_msl 1121 723260594U, // MOVIv8b_ns 1122 1796740274U, // MOVIv8i16 1123 84157629U, // MOVKWi 1124 84157629U, // MOVKXi 1125 1795434146U, // MOVNWi 1126 1795434146U, // MOVNXi 1127 1795435093U, // MOVZWi 1128 1795435093U, // MOVZXi 1129 0U, // MOVaddr 1130 0U, // MOVaddrBA 1131 0U, // MOVaddrCP 1132 0U, // MOVaddrEXT 1133 0U, // MOVaddrJT 1134 0U, // MOVaddrTLS 1135 0U, // MOVi32imm 1136 0U, // MOVi64imm 1137 201599116U, // MRS 1138 137179U, // MSR 1139 141275U, // MSRpstate 1140 17048258U, // MSUBWrrr 1141 17048258U, // MSUBXrrr 1142 2147489228U, // MULv16i8 1143 2684884428U, // MULv2i32 1144 2684884428U, // MULv2i32_indexed 1145 3222279628U, // MULv4i16 1146 3222279628U, // MULv4i16_indexed 1147 1075058124U, // MULv4i32 1148 1075058124U, // MULv4i32_indexed 1149 1612191180U, // MULv8i16 1150 1612191180U, // MULv8i16_indexed 1151 3759936972U, // MULv8i8 1152 1795691679U, // MVNIv2i32 1153 1795691679U, // MVNIv2s_msl 1154 1796215967U, // MVNIv4i16 1155 1796478111U, // MVNIv4i32 1156 1796478111U, // MVNIv4s_msl 1157 1796740255U, // MVNIv8i16 1158 5076U, // NEGv16i8 1159 553919444U, // NEGv1i64 1160 1074271188U, // NEGv2i32 1161 1611404244U, // NEGv2i64 1162 2148537300U, // NEGv4i16 1163 2685670356U, // NEGv4i32 1164 3222803412U, // NEGv8i16 1165 3759936468U, // NEGv8i8 1166 6353U, // NOTv16i8 1167 3759937745U, // NOTv8i8 1168 0U, // ORNWrr 1169 17049189U, // ORNWrs 1170 0U, // ORNXrr 1171 17049189U, // ORNXrs 1172 2147489381U, // ORNv16i8 1173 3759937125U, // ORNv8i8 1174 17049548U, // ORRWri 1175 0U, // ORRWrr 1176 17049548U, // ORRWrs 1177 17049548U, // ORRXri 1178 0U, // ORRXrr 1179 17049548U, // ORRXrs 1180 2147489740U, // ORRv16i8 1181 84424652U, // ORRv2i32 1182 84948940U, // ORRv4i16 1183 85211084U, // ORRv4i32 1184 85473228U, // ORRv8i16 1185 3759937484U, // ORRv8i8 1186 2149060822U, // PMULLv16i8 1187 228070797U, // PMULLv1i64 1188 244846806U, // PMULLv2i64 1189 3759674765U, // PMULLv8i8 1190 2147489240U, // PMULv16i8 1191 3759936984U, // PMULv8i8 1192 101070321U, // PRFMl 1193 26621425U, // PRFMroW 1194 26621425U, // PRFMroX 1195 26621425U, // PRFMui 1196 26621455U, // PRFUMi 1197 537400862U, // RADDHNv2i64_v2i32 1198 571748633U, // RADDHNv2i64_v4i32 1199 1074796062U, // RADDHNv4i32_v4i16 1200 1108881689U, // RADDHNv4i32_v8i16 1201 1644179737U, // RADDHNv8i16_v16i8 1202 1612453406U, // RADDHNv8i16_v8i8 1203 553920698U, // RBITWr 1204 553920698U, // RBITXr 1205 6330U, // RBITv16i8 1206 3759937722U, // RBITv8i8 1207 2107559U, // RET 1208 0U, // RET_ReallyLR 1209 553918951U, // REV16Wr 1210 553918951U, // REV16Xr 1211 4583U, // REV16v16i8 1212 3759935975U, // REV16v8i8 1213 553918540U, // REV32Xr 1214 4172U, // REV32v16i8 1215 2148536396U, // REV32v4i16 1216 3222802508U, // REV32v8i16 1217 3759935564U, // REV32v8i8 1218 4566U, // REV64v16i8 1219 1074270678U, // REV64v2i32 1220 2148536790U, // REV64v4i16 1221 2685669846U, // REV64v4i32 1222 3222802902U, // REV64v8i16 1223 3759935958U, // REV64v8i8 1224 553920805U, // REVWr 1225 553920805U, // REVXr 1226 17049543U, // RORVWr 1227 17049543U, // RORVXr 1228 1644179766U, // RSHRNv16i8_shift 1229 537400917U, // RSHRNv2i32_shift 1230 1074796117U, // RSHRNv4i16_shift 1231 571748662U, // RSHRNv4i32_shift 1232 1108881718U, // RSHRNv8i16_shift 1233 1612453461U, // RSHRNv8i8_shift 1234 537400854U, // RSUBHNv2i64_v2i32 1235 571748624U, // RSUBHNv2i64_v4i32 1236 1074796054U, // RSUBHNv4i32_v4i16 1237 1108881680U, // RSUBHNv4i32_v8i16 1238 1644179728U, // RSUBHNv8i16_v16i8 1239 1612453398U, // RSUBHNv8i16_v8i8 1240 2182623330U, // SABALv16i8_v8i16 1241 2718708931U, // SABALv2i32_v2i64 1242 3256104131U, // SABALv4i16_v4i32 1243 1108095074U, // SABALv4i32_v2i64 1244 1645490274U, // SABALv8i16_v4i32 1245 3793237187U, // SABALv8i8_v8i16 1246 2181050862U, // SABAv16i8 1247 2718446062U, // SABAv2i32 1248 3255841262U, // SABAv4i16 1249 1108619758U, // SABAv4i32 1250 1645752814U, // SABAv8i16 1251 3793498606U, // SABAv8i8 1252 2149060764U, // SABDLv16i8_v8i16 1253 2685146379U, // SABDLv2i32_v2i64 1254 3222541579U, // SABDLv4i16_v4i32 1255 1074532508U, // SABDLv4i32_v2i64 1256 1611927708U, // SABDLv8i16_v4i32 1257 3759674635U, // SABDLv8i8_v8i16 1258 2147488538U, // SABDv16i8 1259 2684883738U, // SABDv2i32 1260 3222278938U, // SABDv4i16 1261 1075057434U, // SABDv4i32 1262 1612190490U, // SABDv8i16 1263 3759936282U, // SABDv8i8 1264 35141315U, // SADALPv16i8_v8i16 1265 1117533891U, // SADALPv2i32_v1i64 1266 2181576387U, // SADALPv4i16_v2i32 1267 2718709443U, // SADALPv4i32_v2i64 1268 3256104643U, // SADALPv8i16_v4i32 1269 3792713411U, // SADALPv8i8_v4i16 1270 1578707U, // SADDLPv16i8_v8i16 1271 1083971283U, // SADDLPv2i32_v1i64 1272 2148013779U, // SADDLPv4i16_v2i32 1273 2685146835U, // SADDLPv4i32_v2i64 1274 3222542035U, // SADDLPv8i16_v4i32 1275 3759150803U, // SADDLPv8i8_v4i16 1276 272700U, // SADDLVv16i8v 1277 2147756348U, // SADDLVv4i16v 1278 2684627260U, // SADDLVv4i32v 1279 3221498172U, // SADDLVv8i16v 1280 3758369084U, // SADDLVv8i8v 1281 2149060780U, // SADDLv16i8_v8i16 1282 2685146409U, // SADDLv2i32_v2i64 1283 3222541609U, // SADDLv4i16_v4i32 1284 1074532524U, // SADDLv4i32_v2i64 1285 1611927724U, // SADDLv8i16_v4i32 1286 3759674665U, // SADDLv8i8_v8i16 1287 1612190133U, // SADDWv16i8_v8i16 1288 537663936U, // SADDWv2i32_v2i64 1289 1075059136U, // SADDWv4i16_v4i32 1290 537661877U, // SADDWv4i32_v2i64 1291 1075057077U, // SADDWv8i16_v4i32 1292 1612192192U, // SADDWv8i8_v8i16 1293 17049656U, // SBCSWr 1294 17049656U, // SBCSXr 1295 17048293U, // SBCWr 1296 17048293U, // SBCXr 1297 17049061U, // SBFMWri 1298 17049061U, // SBFMXri 1299 17048517U, // SCVTFSWDri 1300 17048517U, // SCVTFSWSri 1301 17048517U, // SCVTFSXDri 1302 17048517U, // SCVTFSXSri 1303 553919429U, // SCVTFUWDri 1304 553919429U, // SCVTFUWSri 1305 553919429U, // SCVTFUXDri 1306 553919429U, // SCVTFUXSri 1307 17048517U, // SCVTFd 1308 17048517U, // SCVTFs 1309 553919429U, // SCVTFv1i32 1310 553919429U, // SCVTFv1i64 1311 1074271173U, // SCVTFv2f32 1312 1611404229U, // SCVTFv2f64 1313 2684883909U, // SCVTFv2i32_shift 1314 537662405U, // SCVTFv2i64_shift 1315 2685670341U, // SCVTFv4f32 1316 1075057605U, // SCVTFv4i32_shift 1317 17049904U, // SDIVWr 1318 17049904U, // SDIVXr 1319 17049904U, // SDIV_IntWr 1320 17049904U, // SDIV_IntXr 1321 67404510U, // SHA1Crrr 1322 553919463U, // SHA1Hrr 1323 67405278U, // SHA1Mrrr 1324 67405488U, // SHA1Prrr 1325 1108619265U, // SHA1SU0rrr 1326 2719232056U, // SHA1SU1rr 1327 67403864U, // SHA256H2rrr 1328 67404790U, // SHA256Hrrr 1329 2719232010U, // SHA256SU0rr 1330 1108619329U, // SHA256SU1rrr 1331 2147488572U, // SHADDv16i8 1332 2684883772U, // SHADDv2i32 1333 3222278972U, // SHADDv4i16 1334 1075057468U, // SHADDv4i32 1335 1612190524U, // SHADDv8i16 1336 3759936316U, // SHADDv8i8 1337 2149060797U, // SHLLv16i8 1338 2685146487U, // SHLLv2i32 1339 3222541687U, // SHLLv4i16 1340 3758887101U, // SHLLv4i32 1341 1315005U, // SHLLv8i16 1342 538449271U, // SHLLv8i8 1343 17048896U, // SHLd 1344 2147489088U, // SHLv16i8_shift 1345 2684884288U, // SHLv2i32_shift 1346 537662784U, // SHLv2i64_shift 1347 3222279488U, // SHLv4i16_shift 1348 1075057984U, // SHLv4i32_shift 1349 1612191040U, // SHLv8i16_shift 1350 3759936832U, // SHLv8i8_shift 1351 1644179748U, // SHRNv16i8_shift 1352 537400901U, // SHRNv2i32_shift 1353 1074796101U, // SHRNv4i16_shift 1354 571748644U, // SHRNv4i32_shift 1355 1108881700U, // SHRNv8i16_shift 1356 1612453445U, // SHRNv8i8_shift 1357 2147488435U, // SHSUBv16i8 1358 2684883635U, // SHSUBv2i32 1359 3222278835U, // SHSUBv4i16 1360 1075057331U, // SHSUBv4i32 1361 1612190387U, // SHSUBv8i16 1362 3759936179U, // SHSUBv8i8 1363 67404954U, // SLId 1364 2181051546U, // SLIv16i8_shift 1365 2718446746U, // SLIv2i32_shift 1366 571225242U, // SLIv2i64_shift 1367 3255841946U, // SLIv4i16_shift 1368 1108620442U, // SLIv4i32_shift 1369 1645753498U, // SLIv8i16_shift 1370 3793499290U, // SLIv8i8_shift 1371 17048857U, // SMADDLrrr 1372 2147489609U, // SMAXPv16i8 1373 2684884809U, // SMAXPv2i32 1374 3222280009U, // SMAXPv4i16 1375 1075058505U, // SMAXPv4i32 1376 1612191561U, // SMAXPv8i16 1377 3759937353U, // SMAXPv8i8 1378 272787U, // SMAXVv16i8v 1379 2147756435U, // SMAXVv4i16v 1380 2684627347U, // SMAXVv4i32v 1381 3221498259U, // SMAXVv8i16v 1382 3758369171U, // SMAXVv8i8v 1383 2147490298U, // SMAXv16i8 1384 2684885498U, // SMAXv2i32 1385 3222280698U, // SMAXv4i16 1386 1075059194U, // SMAXv4i32 1387 1612192250U, // SMAXv8i16 1388 3759938042U, // SMAXv8i8 1389 21246U, // SMC 1390 2147489551U, // SMINPv16i8 1391 2684884751U, // SMINPv2i32 1392 3222279951U, // SMINPv4i16 1393 1075058447U, // SMINPv4i32 1394 1612191503U, // SMINPv8i16 1395 3759937295U, // SMINPv8i8 1396 272741U, // SMINVv16i8v 1397 2147756389U, // SMINVv4i16v 1398 2684627301U, // SMINVv4i32v 1399 3221498213U, // SMINVv8i16v 1400 3758369125U, // SMINVv8i8v 1401 2147489324U, // SMINv16i8 1402 2684884524U, // SMINv2i32 1403 3222279724U, // SMINv4i16 1404 1075058220U, // SMINv4i32 1405 1612191276U, // SMINv8i16 1406 3759937068U, // SMINv8i8 1407 2182623356U, // SMLALv16i8_v8i16 1408 2718708954U, // SMLALv2i32_indexed 1409 2718708954U, // SMLALv2i32_v2i64 1410 3256104154U, // SMLALv4i16_indexed 1411 3256104154U, // SMLALv4i16_v4i32 1412 1108095100U, // SMLALv4i32_indexed 1413 1108095100U, // SMLALv4i32_v2i64 1414 1645490300U, // SMLALv8i16_indexed 1415 1645490300U, // SMLALv8i16_v4i32 1416 3793237210U, // SMLALv8i8_v8i16 1417 2182623480U, // SMLSLv16i8_v8i16 1418 2718709168U, // SMLSLv2i32_indexed 1419 2718709168U, // SMLSLv2i32_v2i64 1420 3256104368U, // SMLSLv4i16_indexed 1421 3256104368U, // SMLSLv4i16_v4i32 1422 1108095224U, // SMLSLv4i32_indexed 1423 1108095224U, // SMLSLv4i32_v2i64 1424 1645490424U, // SMLSLv8i16_indexed 1425 1645490424U, // SMLSLv8i16_v4i32 1426 3793237424U, // SMLSLv8i8_v8i16 1427 272768U, // SMOVvi16to32 1428 272768U, // SMOVvi16to64 1429 537143680U, // SMOVvi32to64 1430 1610885504U, // SMOVvi8to32 1431 1610885504U, // SMOVvi8to64 1432 17048813U, // SMSUBLrrr 1433 17048603U, // SMULHrr 1434 2149060830U, // SMULLv16i8_v8i16 1435 2685146516U, // SMULLv2i32_indexed 1436 2685146516U, // SMULLv2i32_v2i64 1437 3222541716U, // SMULLv4i16_indexed 1438 3222541716U, // SMULLv4i16_v4i32 1439 1074532574U, // SMULLv4i32_indexed 1440 1074532574U, // SMULLv4i32_v2i64 1441 1611927774U, // SMULLv8i16_indexed 1442 1611927774U, // SMULLv8i16_v4i32 1443 3759674772U, // SMULLv8i8_v8i16 1444 6187U, // SQABSv16i8 1445 553920555U, // SQABSv1i16 1446 553920555U, // SQABSv1i32 1447 553920555U, // SQABSv1i64 1448 553920555U, // SQABSv1i8 1449 1074272299U, // SQABSv2i32 1450 1611405355U, // SQABSv2i64 1451 2148538411U, // SQABSv4i16 1452 2685671467U, // SQABSv4i32 1453 3222804523U, // SQABSv8i16 1454 3759937579U, // SQABSv8i8 1455 2147488602U, // SQADDv16i8 1456 17048410U, // SQADDv1i16 1457 17048410U, // SQADDv1i32 1458 17048410U, // SQADDv1i64 1459 17048410U, // SQADDv1i8 1460 2684883802U, // SQADDv2i32 1461 537662298U, // SQADDv2i64 1462 3222279002U, // SQADDv4i16 1463 1075057498U, // SQADDv4i32 1464 1612190554U, // SQADDv8i16 1465 3759936346U, // SQADDv8i8 1466 67405009U, // SQDMLALi16 1467 67405009U, // SQDMLALi32 1468 67405009U, // SQDMLALv1i32_indexed 1469 67405009U, // SQDMLALv1i64_indexed 1470 2718708945U, // SQDMLALv2i32_indexed 1471 2718708945U, // SQDMLALv2i32_v2i64 1472 3256104145U, // SQDMLALv4i16_indexed 1473 3256104145U, // SQDMLALv4i16_v4i32 1474 1108095090U, // SQDMLALv4i32_indexed 1475 1108095090U, // SQDMLALv4i32_v2i64 1476 1645490290U, // SQDMLALv8i16_indexed 1477 1645490290U, // SQDMLALv8i16_v4i32 1478 67405223U, // SQDMLSLi16 1479 67405223U, // SQDMLSLi32 1480 67405223U, // SQDMLSLv1i32_indexed 1481 67405223U, // SQDMLSLv1i64_indexed 1482 2718709159U, // SQDMLSLv2i32_indexed 1483 2718709159U, // SQDMLSLv2i32_v2i64 1484 3256104359U, // SQDMLSLv4i16_indexed 1485 3256104359U, // SQDMLSLv4i16_v4i32 1486 1108095214U, // SQDMLSLv4i32_indexed 1487 1108095214U, // SQDMLSLv4i32_v2i64 1488 1645490414U, // SQDMLSLv8i16_indexed 1489 1645490414U, // SQDMLSLv8i16_v4i32 1490 17048584U, // SQDMULHv1i16 1491 17048584U, // SQDMULHv1i16_indexed 1492 17048584U, // SQDMULHv1i32 1493 17048584U, // SQDMULHv1i32_indexed 1494 2684883976U, // SQDMULHv2i32 1495 2684883976U, // SQDMULHv2i32_indexed 1496 3222279176U, // SQDMULHv4i16 1497 3222279176U, // SQDMULHv4i16_indexed 1498 1075057672U, // SQDMULHv4i32 1499 1075057672U, // SQDMULHv4i32_indexed 1500 1612190728U, // SQDMULHv8i16 1501 1612190728U, // SQDMULHv8i16_indexed 1502 17048964U, // SQDMULLi16 1503 17048964U, // SQDMULLi32 1504 17048964U, // SQDMULLv1i32_indexed 1505 17048964U, // SQDMULLv1i64_indexed 1506 2685146500U, // SQDMULLv2i32_indexed 1507 2685146500U, // SQDMULLv2i32_v2i64 1508 3222541700U, // SQDMULLv4i16_indexed 1509 3222541700U, // SQDMULLv4i16_v4i32 1510 1074532556U, // SQDMULLv4i32_indexed 1511 1074532556U, // SQDMULLv4i32_v2i64 1512 1611927756U, // SQDMULLv8i16_indexed 1513 1611927756U, // SQDMULLv8i16_v4i32 1514 5081U, // SQNEGv16i8 1515 553919449U, // SQNEGv1i16 1516 553919449U, // SQNEGv1i32 1517 553919449U, // SQNEGv1i64 1518 553919449U, // SQNEGv1i8 1519 1074271193U, // SQNEGv2i32 1520 1611404249U, // SQNEGv2i64 1521 2148537305U, // SQNEGv4i16 1522 2685670361U, // SQNEGv4i32 1523 3222803417U, // SQNEGv8i16 1524 3759936473U, // SQNEGv8i8 1525 17048593U, // SQRDMULHv1i16 1526 17048593U, // SQRDMULHv1i16_indexed 1527 17048593U, // SQRDMULHv1i32 1528 17048593U, // SQRDMULHv1i32_indexed 1529 2684883985U, // SQRDMULHv2i32 1530 2684883985U, // SQRDMULHv2i32_indexed 1531 3222279185U, // SQRDMULHv4i16 1532 3222279185U, // SQRDMULHv4i16_indexed 1533 1075057681U, // SQRDMULHv4i32 1534 1075057681U, // SQRDMULHv4i32_indexed 1535 1612190737U, // SQRDMULHv8i16 1536 1612190737U, // SQRDMULHv8i16_indexed 1537 2147489100U, // SQRSHLv16i8 1538 17048908U, // SQRSHLv1i16 1539 17048908U, // SQRSHLv1i32 1540 17048908U, // SQRSHLv1i64 1541 17048908U, // SQRSHLv1i8 1542 2684884300U, // SQRSHLv2i32 1543 537662796U, // SQRSHLv2i64 1544 3222279500U, // SQRSHLv4i16 1545 1075057996U, // SQRSHLv4i32 1546 1612191052U, // SQRSHLv8i16 1547 3759936844U, // SQRSHLv8i8 1548 17049171U, // SQRSHRNb 1549 17049171U, // SQRSHRNh 1550 17049171U, // SQRSHRNs 1551 1644179764U, // SQRSHRNv16i8_shift 1552 537400915U, // SQRSHRNv2i32_shift 1553 1074796115U, // SQRSHRNv4i16_shift 1554 571748660U, // SQRSHRNv4i32_shift 1555 1108881716U, // SQRSHRNv8i16_shift 1556 1612453459U, // SQRSHRNv8i8_shift 1557 17049232U, // SQRSHRUNb 1558 17049232U, // SQRSHRUNh 1559 17049232U, // SQRSHRUNs 1560 1644179824U, // SQRSHRUNv16i8_shift 1561 537400976U, // SQRSHRUNv2i32_shift 1562 1074796176U, // SQRSHRUNv4i16_shift 1563 571748720U, // SQRSHRUNv4i32_shift 1564 1108881776U, // SQRSHRUNv8i16_shift 1565 1612453520U, // SQRSHRUNv8i8_shift 1566 17049847U, // SQSHLUb 1567 17049847U, // SQSHLUd 1568 17049847U, // SQSHLUh 1569 17049847U, // SQSHLUs 1570 2147490039U, // SQSHLUv16i8_shift 1571 2684885239U, // SQSHLUv2i32_shift 1572 537663735U, // SQSHLUv2i64_shift 1573 3222280439U, // SQSHLUv4i16_shift 1574 1075058935U, // SQSHLUv4i32_shift 1575 1612191991U, // SQSHLUv8i16_shift 1576 3759937783U, // SQSHLUv8i8_shift 1577 17048894U, // SQSHLb 1578 17048894U, // SQSHLd 1579 17048894U, // SQSHLh 1580 17048894U, // SQSHLs 1581 2147489086U, // SQSHLv16i8 1582 2147489086U, // SQSHLv16i8_shift 1583 17048894U, // SQSHLv1i16 1584 17048894U, // SQSHLv1i32 1585 17048894U, // SQSHLv1i64 1586 17048894U, // SQSHLv1i8 1587 2684884286U, // SQSHLv2i32 1588 2684884286U, // SQSHLv2i32_shift 1589 537662782U, // SQSHLv2i64 1590 537662782U, // SQSHLv2i64_shift 1591 3222279486U, // SQSHLv4i16 1592 3222279486U, // SQSHLv4i16_shift 1593 1075057982U, // SQSHLv4i32 1594 1075057982U, // SQSHLv4i32_shift 1595 1612191038U, // SQSHLv8i16 1596 1612191038U, // SQSHLv8i16_shift 1597 3759936830U, // SQSHLv8i8 1598 3759936830U, // SQSHLv8i8_shift 1599 17049155U, // SQSHRNb 1600 17049155U, // SQSHRNh 1601 17049155U, // SQSHRNs 1602 1644179746U, // SQSHRNv16i8_shift 1603 537400899U, // SQSHRNv2i32_shift 1604 1074796099U, // SQSHRNv4i16_shift 1605 571748642U, // SQSHRNv4i32_shift 1606 1108881698U, // SQSHRNv8i16_shift 1607 1612453443U, // SQSHRNv8i8_shift 1608 17049223U, // SQSHRUNb 1609 17049223U, // SQSHRUNh 1610 17049223U, // SQSHRUNs 1611 1644179814U, // SQSHRUNv16i8_shift 1612 537400967U, // SQSHRUNv2i32_shift 1613 1074796167U, // SQSHRUNv4i16_shift 1614 571748710U, // SQSHRUNv4i32_shift 1615 1108881766U, // SQSHRUNv8i16_shift 1616 1612453511U, // SQSHRUNv8i8_shift 1617 2147488464U, // SQSUBv16i8 1618 17048272U, // SQSUBv1i16 1619 17048272U, // SQSUBv1i32 1620 17048272U, // SQSUBv1i64 1621 17048272U, // SQSUBv1i8 1622 2684883664U, // SQSUBv2i32 1623 537662160U, // SQSUBv2i64 1624 3222278864U, // SQSUBv4i16 1625 1075057360U, // SQSUBv4i32 1626 1612190416U, // SQSUBv8i16 1627 3759936208U, // SQSUBv8i8 1628 3254792534U, // SQXTNv16i8 1629 553920121U, // SQXTNv1i16 1630 553920121U, // SQXTNv1i32 1631 553920121U, // SQXTNv1i8 1632 1611142777U, // SQXTNv2i32 1633 2685408889U, // SQXTNv4i16 1634 1645490518U, // SQXTNv4i32 1635 2719494486U, // SQXTNv8i16 1636 3223066233U, // SQXTNv8i8 1637 3254792571U, // SQXTUNv16i8 1638 553920154U, // SQXTUNv1i16 1639 553920154U, // SQXTUNv1i32 1640 553920154U, // SQXTUNv1i8 1641 1611142810U, // SQXTUNv2i32 1642 2685408922U, // SQXTUNv4i16 1643 1645490555U, // SQXTUNv4i32 1644 2719494523U, // SQXTUNv8i16 1645 3223066266U, // SQXTUNv8i8 1646 2147488556U, // SRHADDv16i8 1647 2684883756U, // SRHADDv2i32 1648 3222278956U, // SRHADDv4i16 1649 1075057452U, // SRHADDv4i32 1650 1612190508U, // SRHADDv8i16 1651 3759936300U, // SRHADDv8i8 1652 67404965U, // SRId 1653 2181051557U, // SRIv16i8_shift 1654 2718446757U, // SRIv2i32_shift 1655 571225253U, // SRIv2i64_shift 1656 3255841957U, // SRIv4i16_shift 1657 1108620453U, // SRIv4i32_shift 1658 1645753509U, // SRIv8i16_shift 1659 3793499301U, // SRIv8i8_shift 1660 2147489116U, // SRSHLv16i8 1661 17048924U, // SRSHLv1i64 1662 2684884316U, // SRSHLv2i32 1663 537662812U, // SRSHLv2i64 1664 3222279516U, // SRSHLv4i16 1665 1075058012U, // SRSHLv4i32 1666 1612191068U, // SRSHLv8i16 1667 3759936860U, // SRSHLv8i8 1668 17049501U, // SRSHRd 1669 2147489693U, // SRSHRv16i8_shift 1670 2684884893U, // SRSHRv2i32_shift 1671 537663389U, // SRSHRv2i64_shift 1672 3222280093U, // SRSHRv4i16_shift 1673 1075058589U, // SRSHRv4i32_shift 1674 1612191645U, // SRSHRv8i16_shift 1675 3759937437U, // SRSHRv8i8_shift 1676 67404288U, // SRSRAd 1677 2181050880U, // SRSRAv16i8_shift 1678 2718446080U, // SRSRAv2i32_shift 1679 571224576U, // SRSRAv2i64_shift 1680 3255841280U, // SRSRAv4i16_shift 1681 1108619776U, // SRSRAv4i32_shift 1682 1645752832U, // SRSRAv8i16_shift 1683 3793498624U, // SRSRAv8i8_shift 1684 2149060796U, // SSHLLv16i8_shift 1685 2685146486U, // SSHLLv2i32_shift 1686 3222541686U, // SSHLLv4i16_shift 1687 1074532540U, // SSHLLv4i32_shift 1688 1611927740U, // SSHLLv8i16_shift 1689 3759674742U, // SSHLLv8i8_shift 1690 2147489130U, // SSHLv16i8 1691 17048938U, // SSHLv1i64 1692 2684884330U, // SSHLv2i32 1693 537662826U, // SSHLv2i64 1694 3222279530U, // SSHLv4i16 1695 1075058026U, // SSHLv4i32 1696 1612191082U, // SSHLv8i16 1697 3759936874U, // SSHLv8i8 1698 17049515U, // SSHRd 1699 2147489707U, // SSHRv16i8_shift 1700 2684884907U, // SSHRv2i32_shift 1701 537663403U, // SSHRv2i64_shift 1702 3222280107U, // SSHRv4i16_shift 1703 1075058603U, // SSHRv4i32_shift 1704 1612191659U, // SSHRv8i16_shift 1705 3759937451U, // SSHRv8i8_shift 1706 67404302U, // SSRAd 1707 2181050894U, // SSRAv16i8_shift 1708 2718446094U, // SSRAv2i32_shift 1709 571224590U, // SSRAv2i64_shift 1710 3255841294U, // SSRAv4i16_shift 1711 1108619790U, // SSRAv4i32_shift 1712 1645752846U, // SSRAv8i16_shift 1713 3793498638U, // SSRAv8i8_shift 1714 2149060748U, // SSUBLv16i8_v8i16 1715 2685146365U, // SSUBLv2i32_v2i64 1716 3222541565U, // SSUBLv4i16_v4i32 1717 1074532492U, // SSUBLv4i32_v2i64 1718 1611927692U, // SSUBLv8i16_v4i32 1719 3759674621U, // SSUBLv8i8_v8i16 1720 1612190117U, // SSUBWv16i8_v8i16 1721 537663913U, // SSUBWv2i32_v2i64 1722 1075059113U, // SSUBWv4i16_v4i32 1723 537661861U, // SSUBWv4i32_v2i64 1724 1075057061U, // SSUBWv8i16_v4i32 1725 1612192169U, // SSUBWv8i8_v8i16 1726 36915U, // ST1Fourv16b 1727 3711027U, // ST1Fourv16b_POST 1728 45107U, // ST1Fourv1d 1729 3981363U, // ST1Fourv1d_POST 1730 53299U, // ST1Fourv2d 1731 3727411U, // ST1Fourv2d_POST 1732 61491U, // ST1Fourv2s 1733 3997747U, // ST1Fourv2s_POST 1734 69683U, // ST1Fourv4h 1735 4005939U, // ST1Fourv4h_POST 1736 77875U, // ST1Fourv4s 1737 3751987U, // ST1Fourv4s_POST 1738 86067U, // ST1Fourv8b 1739 4022323U, // ST1Fourv8b_POST 1740 94259U, // ST1Fourv8h 1741 3768371U, // ST1Fourv8h_POST 1742 36915U, // ST1Onev16b 1743 4235315U, // ST1Onev16b_POST 1744 45107U, // ST1Onev1d 1745 4505651U, // ST1Onev1d_POST 1746 53299U, // ST1Onev2d 1747 4251699U, // ST1Onev2d_POST 1748 61491U, // ST1Onev2s 1749 4522035U, // ST1Onev2s_POST 1750 69683U, // ST1Onev4h 1751 4530227U, // ST1Onev4h_POST 1752 77875U, // ST1Onev4s 1753 4276275U, // ST1Onev4s_POST 1754 86067U, // ST1Onev8b 1755 4546611U, // ST1Onev8b_POST 1756 94259U, // ST1Onev8h 1757 4292659U, // ST1Onev8h_POST 1758 36915U, // ST1Threev16b 1759 5546035U, // ST1Threev16b_POST 1760 45107U, // ST1Threev1d 1761 5816371U, // ST1Threev1d_POST 1762 53299U, // ST1Threev2d 1763 5562419U, // ST1Threev2d_POST 1764 61491U, // ST1Threev2s 1765 5832755U, // ST1Threev2s_POST 1766 69683U, // ST1Threev4h 1767 5840947U, // ST1Threev4h_POST 1768 77875U, // ST1Threev4s 1769 5586995U, // ST1Threev4s_POST 1770 86067U, // ST1Threev8b 1771 5857331U, // ST1Threev8b_POST 1772 94259U, // ST1Threev8h 1773 5603379U, // ST1Threev8h_POST 1774 36915U, // ST1Twov16b 1775 3973171U, // ST1Twov16b_POST 1776 45107U, // ST1Twov1d 1777 4243507U, // ST1Twov1d_POST 1778 53299U, // ST1Twov2d 1779 3989555U, // ST1Twov2d_POST 1780 61491U, // ST1Twov2s 1781 4259891U, // ST1Twov2s_POST 1782 69683U, // ST1Twov4h 1783 4268083U, // ST1Twov4h_POST 1784 77875U, // ST1Twov4s 1785 4014131U, // ST1Twov4s_POST 1786 86067U, // ST1Twov8b 1787 4284467U, // ST1Twov8b_POST 1788 94259U, // ST1Twov8h 1789 4030515U, // ST1Twov8h_POST 1790 147507U, // ST1i16 1791 262246451U, // ST1i16_POST 1792 151603U, // ST1i32 1793 279031859U, // ST1i32_POST 1794 155699U, // ST1i64 1795 295817267U, // ST1i64_POST 1796 159795U, // ST1i8 1797 312602675U, // ST1i8_POST 1798 37280U, // ST2Twov16b 1799 3973536U, // ST2Twov16b_POST 1800 53664U, // ST2Twov2d 1801 3989920U, // ST2Twov2d_POST 1802 61856U, // ST2Twov2s 1803 4260256U, // ST2Twov2s_POST 1804 70048U, // ST2Twov4h 1805 4268448U, // ST2Twov4h_POST 1806 78240U, // ST2Twov4s 1807 4014496U, // ST2Twov4s_POST 1808 86432U, // ST2Twov8b 1809 4284832U, // ST2Twov8b_POST 1810 94624U, // ST2Twov8h 1811 4030880U, // ST2Twov8h_POST 1812 147872U, // ST2i16 1813 279024032U, // ST2i16_POST 1814 151968U, // ST2i32 1815 295809440U, // ST2i32_POST 1816 156064U, // ST2i64 1817 329372064U, // ST2i64_POST 1818 160160U, // ST2i8 1819 262271392U, // ST2i8_POST 1820 37329U, // ST3Threev16b 1821 5546449U, // ST3Threev16b_POST 1822 53713U, // ST3Threev2d 1823 5562833U, // ST3Threev2d_POST 1824 61905U, // ST3Threev2s 1825 5833169U, // ST3Threev2s_POST 1826 70097U, // ST3Threev4h 1827 5841361U, // ST3Threev4h_POST 1828 78289U, // ST3Threev4s 1829 5587409U, // ST3Threev4s_POST 1830 86481U, // ST3Threev8b 1831 5857745U, // ST3Threev8b_POST 1832 94673U, // ST3Threev8h 1833 5603793U, // ST3Threev8h_POST 1834 147921U, // ST3i16 1835 346132945U, // ST3i16_POST 1836 152017U, // ST3i32 1837 362918353U, // ST3i32_POST 1838 156113U, // ST3i64 1839 379703761U, // ST3i64_POST 1840 160209U, // ST3i8 1841 396489169U, // ST3i8_POST 1842 37346U, // ST4Fourv16b 1843 3711458U, // ST4Fourv16b_POST 1844 53730U, // ST4Fourv2d 1845 3727842U, // ST4Fourv2d_POST 1846 61922U, // ST4Fourv2s 1847 3998178U, // ST4Fourv2s_POST 1848 70114U, // ST4Fourv4h 1849 4006370U, // ST4Fourv4h_POST 1850 78306U, // ST4Fourv4s 1851 3752418U, // ST4Fourv4s_POST 1852 86498U, // ST4Fourv8b 1853 4022754U, // ST4Fourv8b_POST 1854 94690U, // ST4Fourv8h 1855 3768802U, // ST4Fourv8h_POST 1856 147938U, // ST4i16 1857 295801314U, // ST4i16_POST 1858 152034U, // ST4i32 1859 329363938U, // ST4i32_POST 1860 156130U, // ST4i64 1861 413258210U, // ST4i64_POST 1862 160226U, // ST4i8 1863 279048674U, // ST4i8_POST 1864 26485317U, // STLRB 1865 26485814U, // STLRH 1866 26486716U, // STLRW 1867 26486716U, // STLRX 1868 17049437U, // STLXPW 1869 17049437U, // STLXPX 1870 553919101U, // STLXRB 1871 553919598U, // STLXRH 1872 553920528U, // STLXRW 1873 553920528U, // STLXRX 1874 553920285U, // STNPDi 1875 553920285U, // STNPQi 1876 553920285U, // STNPSi 1877 553920285U, // STNPWi 1878 553920285U, // STNPXi 1879 553920305U, // STPDi 1880 604276529U, // STPDpost 1881 604276529U, // STPDpre 1882 553920305U, // STPQi 1883 604276529U, // STPQpost 1884 604276529U, // STPQpre 1885 553920305U, // STPSi 1886 604276529U, // STPSpost 1887 604276529U, // STPSpre 1888 553920305U, // STPWi 1889 604276529U, // STPWpost 1890 604276529U, // STPWpre 1891 553920305U, // STPXi 1892 604276529U, // STPXpost 1893 604276529U, // STPXpre 1894 1150583379U, // STRBBpost 1895 76841555U, // STRBBpre 1896 26485331U, // STRBBroW 1897 26485331U, // STRBBroX 1898 26485331U, // STRBBui 1899 1150584806U, // STRBpost 1900 76842982U, // STRBpre 1901 26486758U, // STRBroW 1902 26486758U, // STRBroX 1903 26486758U, // STRBui 1904 1150584806U, // STRDpost 1905 76842982U, // STRDpre 1906 26486758U, // STRDroW 1907 26486758U, // STRDroX 1908 26486758U, // STRDui 1909 1150583876U, // STRHHpost 1910 76842052U, // STRHHpre 1911 26485828U, // STRHHroW 1912 26485828U, // STRHHroX 1913 26485828U, // STRHHui 1914 1150584806U, // STRHpost 1915 76842982U, // STRHpre 1916 26486758U, // STRHroW 1917 26486758U, // STRHroX 1918 26486758U, // STRHui 1919 1150584806U, // STRQpost 1920 76842982U, // STRQpre 1921 26486758U, // STRQroW 1922 26486758U, // STRQroX 1923 26486758U, // STRQui 1924 1150584806U, // STRSpost 1925 76842982U, // STRSpre 1926 26486758U, // STRSroW 1927 26486758U, // STRSroX 1928 26486758U, // STRSui 1929 1150584806U, // STRWpost 1930 76842982U, // STRWpre 1931 26486758U, // STRWroW 1932 26486758U, // STRWroX 1933 26486758U, // STRWui 1934 1150584806U, // STRXpost 1935 76842982U, // STRXpre 1936 26486758U, // STRXroW 1937 26486758U, // STRXroX 1938 26486758U, // STRXui 1939 26485337U, // STTRBi 1940 26485834U, // STTRHi 1941 26486763U, // STTRWi 1942 26486763U, // STTRXi 1943 26485351U, // STURBBi 1944 26486781U, // STURBi 1945 26486781U, // STURDi 1946 26485848U, // STURHHi 1947 26486781U, // STURHi 1948 26486781U, // STURQi 1949 26486781U, // STURSi 1950 26486781U, // STURWi 1951 26486781U, // STURXi 1952 17049444U, // STXPW 1953 17049444U, // STXPX 1954 553919109U, // STXRB 1955 553919606U, // STXRH 1956 553920535U, // STXRW 1957 553920535U, // STXRX 1958 537400855U, // SUBHNv2i64_v2i32 1959 571748625U, // SUBHNv2i64_v4i32 1960 1074796055U, // SUBHNv4i32_v4i16 1961 1108881681U, // SUBHNv4i32_v8i16 1962 1644179729U, // SUBHNv8i16_v16i8 1963 1612453399U, // SUBHNv8i16_v8i8 1964 17049650U, // SUBSWri 1965 0U, // SUBSWrr 1966 17049650U, // SUBSWrs 1967 17049650U, // SUBSWrx 1968 17049650U, // SUBSXri 1969 0U, // SUBSXrr 1970 17049650U, // SUBSXrs 1971 17049650U, // SUBSXrx 1972 17049650U, // SUBSXrx64 1973 17048238U, // SUBWri 1974 0U, // SUBWrr 1975 17048238U, // SUBWrs 1976 17048238U, // SUBWrx 1977 17048238U, // SUBXri 1978 0U, // SUBXrr 1979 17048238U, // SUBXrs 1980 17048238U, // SUBXrx 1981 17048238U, // SUBXrx64 1982 2147488430U, // SUBv16i8 1983 17048238U, // SUBv1i64 1984 2684883630U, // SUBv2i32 1985 537662126U, // SUBv2i64 1986 3222278830U, // SUBv4i16 1987 1075057326U, // SUBv4i32 1988 1612190382U, // SUBv8i16 1989 3759936174U, // SUBv8i8 1990 33567585U, // SUQADDv16i8 1991 604275553U, // SUQADDv1i16 1992 604275553U, // SUQADDv1i32 1993 604275553U, // SUQADDv1i64 1994 604275553U, // SUQADDv1i8 1995 1107833697U, // SUQADDv2i32 1996 1644966753U, // SUQADDv2i64 1997 2182099809U, // SUQADDv4i16 1998 2719232865U, // SUQADDv4i32 1999 3256365921U, // SUQADDv8i16 2000 3793498977U, // SUQADDv8i8 2001 21263U, // SVC 2002 17049022U, // SYSLxt 2003 419702938U, // SYSxt 2004 436212968U, // TBLv16i8Four 2005 436212968U, // TBLv16i8One 2006 436212968U, // TBLv16i8Three 2007 436212968U, // TBLv16i8Two 2008 4196144360U, // TBLv8i8Four 2009 4196144360U, // TBLv8i8One 2010 4196144360U, // TBLv8i8Three 2011 4196144360U, // TBLv8i8Two 2012 17050183U, // TBNZW 2013 17050183U, // TBNZX 2014 452999686U, // TBXv16i8Four 2015 452999686U, // TBXv16i8One 2016 452999686U, // TBXv16i8Three 2017 452999686U, // TBXv16i8Two 2018 4212931078U, // TBXv8i8Four 2019 4212931078U, // TBXv8i8One 2020 4212931078U, // TBXv8i8Three 2021 4212931078U, // TBXv8i8Two 2022 17050167U, // TBZW 2023 17050167U, // TBZX 2024 0U, // TCRETURNdi 2025 0U, // TCRETURNri 2026 2107995U, // TLSDESCCALL 2027 0U, // TLSDESC_BLR 2028 2147487770U, // TRN1v16i8 2029 2684882970U, // TRN1v2i32 2030 537661466U, // TRN1v2i64 2031 3222278170U, // TRN1v4i16 2032 1075056666U, // TRN1v4i32 2033 1612189722U, // TRN1v8i16 2034 3759935514U, // TRN1v8i8 2035 2147488072U, // TRN2v16i8 2036 2684883272U, // TRN2v2i32 2037 537661768U, // TRN2v2i64 2038 3222278472U, // TRN2v4i16 2039 1075056968U, // TRN2v4i32 2040 1612190024U, // TRN2v8i16 2041 3759935816U, // TRN2v8i8 2042 2182623338U, // UABALv16i8_v8i16 2043 2718708938U, // UABALv2i32_v2i64 2044 3256104138U, // UABALv4i16_v4i32 2045 1108095082U, // UABALv4i32_v2i64 2046 1645490282U, // UABALv8i16_v4i32 2047 3793237194U, // UABALv8i8_v8i16 2048 2181050868U, // UABAv16i8 2049 2718446068U, // UABAv2i32 2050 3255841268U, // UABAv4i16 2051 1108619764U, // UABAv4i32 2052 1645752820U, // UABAv8i16 2053 3793498612U, // UABAv8i8 2054 2149060772U, // UABDLv16i8_v8i16 2055 2685146386U, // UABDLv2i32_v2i64 2056 3222541586U, // UABDLv4i16_v4i32 2057 1074532516U, // UABDLv4i32_v2i64 2058 1611927716U, // UABDLv8i16_v4i32 2059 3759674642U, // UABDLv8i8_v8i16 2060 2147488544U, // UABDv16i8 2061 2684883744U, // UABDv2i32 2062 3222278944U, // UABDv4i16 2063 1075057440U, // UABDv4i32 2064 1612190496U, // UABDv8i16 2065 3759936288U, // UABDv8i8 2066 35141323U, // UADALPv16i8_v8i16 2067 1117533899U, // UADALPv2i32_v1i64 2068 2181576395U, // UADALPv4i16_v2i32 2069 2718709451U, // UADALPv4i32_v2i64 2070 3256104651U, // UADALPv8i16_v4i32 2071 3792713419U, // UADALPv8i8_v4i16 2072 1578715U, // UADDLPv16i8_v8i16 2073 1083971291U, // UADDLPv2i32_v1i64 2074 2148013787U, // UADDLPv4i16_v2i32 2075 2685146843U, // UADDLPv4i32_v2i64 2076 3222542043U, // UADDLPv8i16_v4i32 2077 3759150811U, // UADDLPv8i8_v4i16 2078 272708U, // UADDLVv16i8v 2079 2147756356U, // UADDLVv4i16v 2080 2684627268U, // UADDLVv4i32v 2081 3221498180U, // UADDLVv8i16v 2082 3758369092U, // UADDLVv8i8v 2083 2149060788U, // UADDLv16i8_v8i16 2084 2685146416U, // UADDLv2i32_v2i64 2085 3222541616U, // UADDLv4i16_v4i32 2086 1074532532U, // UADDLv4i32_v2i64 2087 1611927732U, // UADDLv8i16_v4i32 2088 3759674672U, // UADDLv8i8_v8i16 2089 1612190141U, // UADDWv16i8_v8i16 2090 537663943U, // UADDWv2i32_v2i64 2091 1075059143U, // UADDWv4i16_v4i32 2092 537661885U, // UADDWv4i32_v2i64 2093 1075057085U, // UADDWv8i16_v4i32 2094 1612192199U, // UADDWv8i8_v8i16 2095 17049067U, // UBFMWri 2096 17049067U, // UBFMXri 2097 17048524U, // UCVTFSWDri 2098 17048524U, // UCVTFSWSri 2099 17048524U, // UCVTFSXDri 2100 17048524U, // UCVTFSXSri 2101 553919436U, // UCVTFUWDri 2102 553919436U, // UCVTFUWSri 2103 553919436U, // UCVTFUXDri 2104 553919436U, // UCVTFUXSri 2105 17048524U, // UCVTFd 2106 17048524U, // UCVTFs 2107 553919436U, // UCVTFv1i32 2108 553919436U, // UCVTFv1i64 2109 1074271180U, // UCVTFv2f32 2110 1611404236U, // UCVTFv2f64 2111 2684883916U, // UCVTFv2i32_shift 2112 537662412U, // UCVTFv2i64_shift 2113 2685670348U, // UCVTFv4f32 2114 1075057612U, // UCVTFv4i32_shift 2115 17049910U, // UDIVWr 2116 17049910U, // UDIVXr 2117 17049910U, // UDIV_IntWr 2118 17049910U, // UDIV_IntXr 2119 2147488579U, // UHADDv16i8 2120 2684883779U, // UHADDv2i32 2121 3222278979U, // UHADDv4i16 2122 1075057475U, // UHADDv4i32 2123 1612190531U, // UHADDv8i16 2124 3759936323U, // UHADDv8i8 2125 2147488442U, // UHSUBv16i8 2126 2684883642U, // UHSUBv2i32 2127 3222278842U, // UHSUBv4i16 2128 1075057338U, // UHSUBv4i32 2129 1612190394U, // UHSUBv8i16 2130 3759936186U, // UHSUBv8i8 2131 17048865U, // UMADDLrrr 2132 2147489616U, // UMAXPv16i8 2133 2684884816U, // UMAXPv2i32 2134 3222280016U, // UMAXPv4i16 2135 1075058512U, // UMAXPv4i32 2136 1612191568U, // UMAXPv8i16 2137 3759937360U, // UMAXPv8i8 2138 272794U, // UMAXVv16i8v 2139 2147756442U, // UMAXVv4i16v 2140 2684627354U, // UMAXVv4i32v 2141 3221498266U, // UMAXVv8i16v 2142 3758369178U, // UMAXVv8i8v 2143 2147490304U, // UMAXv16i8 2144 2684885504U, // UMAXv2i32 2145 3222280704U, // UMAXv4i16 2146 1075059200U, // UMAXv4i32 2147 1612192256U, // UMAXv8i16 2148 3759938048U, // UMAXv8i8 2149 2147489558U, // UMINPv16i8 2150 2684884758U, // UMINPv2i32 2151 3222279958U, // UMINPv4i16 2152 1075058454U, // UMINPv4i32 2153 1612191510U, // UMINPv8i16 2154 3759937302U, // UMINPv8i8 2155 272748U, // UMINVv16i8v 2156 2147756396U, // UMINVv4i16v 2157 2684627308U, // UMINVv4i32v 2158 3221498220U, // UMINVv8i16v 2159 3758369132U, // UMINVv8i8v 2160 2147489330U, // UMINv16i8 2161 2684884530U, // UMINv2i32 2162 3222279730U, // UMINv4i16 2163 1075058226U, // UMINv4i32 2164 1612191282U, // UMINv8i16 2165 3759937074U, // UMINv8i8 2166 2182623364U, // UMLALv16i8_v8i16 2167 2718708961U, // UMLALv2i32_indexed 2168 2718708961U, // UMLALv2i32_v2i64 2169 3256104161U, // UMLALv4i16_indexed 2170 3256104161U, // UMLALv4i16_v4i32 2171 1108095108U, // UMLALv4i32_indexed 2172 1108095108U, // UMLALv4i32_v2i64 2173 1645490308U, // UMLALv8i16_indexed 2174 1645490308U, // UMLALv8i16_v4i32 2175 3793237217U, // UMLALv8i8_v8i16 2176 2182623488U, // UMLSLv16i8_v8i16 2177 2718709175U, // UMLSLv2i32_indexed 2178 2718709175U, // UMLSLv2i32_v2i64 2179 3256104375U, // UMLSLv4i16_indexed 2180 3256104375U, // UMLSLv4i16_v4i32 2181 1108095232U, // UMLSLv4i32_indexed 2182 1108095232U, // UMLSLv4i32_v2i64 2183 1645490432U, // UMLSLv8i16_indexed 2184 1645490432U, // UMLSLv8i16_v4i32 2185 3793237431U, // UMLSLv8i8_v8i16 2186 272774U, // UMOVvi16 2187 537143686U, // UMOVvi32 2188 1074014598U, // UMOVvi64 2189 1610885510U, // UMOVvi8 2190 17048821U, // UMSUBLrrr 2191 17048610U, // UMULHrr 2192 2149060838U, // UMULLv16i8_v8i16 2193 2685146523U, // UMULLv2i32_indexed 2194 2685146523U, // UMULLv2i32_v2i64 2195 3222541723U, // UMULLv4i16_indexed 2196 3222541723U, // UMULLv4i16_v4i32 2197 1074532582U, // UMULLv4i32_indexed 2198 1074532582U, // UMULLv4i32_v2i64 2199 1611927782U, // UMULLv8i16_indexed 2200 1611927782U, // UMULLv8i16_v4i32 2201 3759674779U, // UMULLv8i8_v8i16 2202 2147488610U, // UQADDv16i8 2203 17048418U, // UQADDv1i16 2204 17048418U, // UQADDv1i32 2205 17048418U, // UQADDv1i64 2206 17048418U, // UQADDv1i8 2207 2684883810U, // UQADDv2i32 2208 537662306U, // UQADDv2i64 2209 3222279010U, // UQADDv4i16 2210 1075057506U, // UQADDv4i32 2211 1612190562U, // UQADDv8i16 2212 3759936354U, // UQADDv8i8 2213 2147489108U, // UQRSHLv16i8 2214 17048916U, // UQRSHLv1i16 2215 17048916U, // UQRSHLv1i32 2216 17048916U, // UQRSHLv1i64 2217 17048916U, // UQRSHLv1i8 2218 2684884308U, // UQRSHLv2i32 2219 537662804U, // UQRSHLv2i64 2220 3222279508U, // UQRSHLv4i16 2221 1075058004U, // UQRSHLv4i32 2222 1612191060U, // UQRSHLv8i16 2223 3759936852U, // UQRSHLv8i8 2224 17049180U, // UQRSHRNb 2225 17049180U, // UQRSHRNh 2226 17049180U, // UQRSHRNs 2227 1644179774U, // UQRSHRNv16i8_shift 2228 537400924U, // UQRSHRNv2i32_shift 2229 1074796124U, // UQRSHRNv4i16_shift 2230 571748670U, // UQRSHRNv4i32_shift 2231 1108881726U, // UQRSHRNv8i16_shift 2232 1612453468U, // UQRSHRNv8i8_shift 2233 17048901U, // UQSHLb 2234 17048901U, // UQSHLd 2235 17048901U, // UQSHLh 2236 17048901U, // UQSHLs 2237 2147489093U, // UQSHLv16i8 2238 2147489093U, // UQSHLv16i8_shift 2239 17048901U, // UQSHLv1i16 2240 17048901U, // UQSHLv1i32 2241 17048901U, // UQSHLv1i64 2242 17048901U, // UQSHLv1i8 2243 2684884293U, // UQSHLv2i32 2244 2684884293U, // UQSHLv2i32_shift 2245 537662789U, // UQSHLv2i64 2246 537662789U, // UQSHLv2i64_shift 2247 3222279493U, // UQSHLv4i16 2248 3222279493U, // UQSHLv4i16_shift 2249 1075057989U, // UQSHLv4i32 2250 1075057989U, // UQSHLv4i32_shift 2251 1612191045U, // UQSHLv8i16 2252 1612191045U, // UQSHLv8i16_shift 2253 3759936837U, // UQSHLv8i8 2254 3759936837U, // UQSHLv8i8_shift 2255 17049163U, // UQSHRNb 2256 17049163U, // UQSHRNh 2257 17049163U, // UQSHRNs 2258 1644179755U, // UQSHRNv16i8_shift 2259 537400907U, // UQSHRNv2i32_shift 2260 1074796107U, // UQSHRNv4i16_shift 2261 571748651U, // UQSHRNv4i32_shift 2262 1108881707U, // UQSHRNv8i16_shift 2263 1612453451U, // UQSHRNv8i8_shift 2264 2147488471U, // UQSUBv16i8 2265 17048279U, // UQSUBv1i16 2266 17048279U, // UQSUBv1i32 2267 17048279U, // UQSUBv1i64 2268 17048279U, // UQSUBv1i8 2269 2684883671U, // UQSUBv2i32 2270 537662167U, // UQSUBv2i64 2271 3222278871U, // UQSUBv4i16 2272 1075057367U, // UQSUBv4i32 2273 1612190423U, // UQSUBv8i16 2274 3759936215U, // UQSUBv8i8 2275 3254792542U, // UQXTNv16i8 2276 553920128U, // UQXTNv1i16 2277 553920128U, // UQXTNv1i32 2278 553920128U, // UQXTNv1i8 2279 1611142784U, // UQXTNv2i32 2280 2685408896U, // UQXTNv4i16 2281 1645490526U, // UQXTNv4i32 2282 2719494494U, // UQXTNv8i16 2283 3223066240U, // UQXTNv8i8 2284 1074271121U, // URECPEv2i32 2285 2685670289U, // URECPEv4i32 2286 2147488564U, // URHADDv16i8 2287 2684883764U, // URHADDv2i32 2288 3222278964U, // URHADDv4i16 2289 1075057460U, // URHADDv4i32 2290 1612190516U, // URHADDv8i16 2291 3759936308U, // URHADDv8i8 2292 2147489123U, // URSHLv16i8 2293 17048931U, // URSHLv1i64 2294 2684884323U, // URSHLv2i32 2295 537662819U, // URSHLv2i64 2296 3222279523U, // URSHLv4i16 2297 1075058019U, // URSHLv4i32 2298 1612191075U, // URSHLv8i16 2299 3759936867U, // URSHLv8i8 2300 17049508U, // URSHRd 2301 2147489700U, // URSHRv16i8_shift 2302 2684884900U, // URSHRv2i32_shift 2303 537663396U, // URSHRv2i64_shift 2304 3222280100U, // URSHRv4i16_shift 2305 1075058596U, // URSHRv4i32_shift 2306 1612191652U, // URSHRv8i16_shift 2307 3759937444U, // URSHRv8i8_shift 2308 1074271159U, // URSQRTEv2i32 2309 2685670327U, // URSQRTEv4i32 2310 67404295U, // URSRAd 2311 2181050887U, // URSRAv16i8_shift 2312 2718446087U, // URSRAv2i32_shift 2313 571224583U, // URSRAv2i64_shift 2314 3255841287U, // URSRAv4i16_shift 2315 1108619783U, // URSRAv4i32_shift 2316 1645752839U, // URSRAv8i16_shift 2317 3793498631U, // URSRAv8i8_shift 2318 2149060804U, // USHLLv16i8_shift 2319 2685146493U, // USHLLv2i32_shift 2320 3222541693U, // USHLLv4i16_shift 2321 1074532548U, // USHLLv4i32_shift 2322 1611927748U, // USHLLv8i16_shift 2323 3759674749U, // USHLLv8i8_shift 2324 2147489136U, // USHLv16i8 2325 17048944U, // USHLv1i64 2326 2684884336U, // USHLv2i32 2327 537662832U, // USHLv2i64 2328 3222279536U, // USHLv4i16 2329 1075058032U, // USHLv4i32 2330 1612191088U, // USHLv8i16 2331 3759936880U, // USHLv8i8 2332 17049521U, // USHRd 2333 2147489713U, // USHRv16i8_shift 2334 2684884913U, // USHRv2i32_shift 2335 537663409U, // USHRv2i64_shift 2336 3222280113U, // USHRv4i16_shift 2337 1075058609U, // USHRv4i32_shift 2338 1612191665U, // USHRv8i16_shift 2339 3759937457U, // USHRv8i8_shift 2340 33567577U, // USQADDv16i8 2341 604275545U, // USQADDv1i16 2342 604275545U, // USQADDv1i32 2343 604275545U, // USQADDv1i64 2344 604275545U, // USQADDv1i8 2345 1107833689U, // USQADDv2i32 2346 1644966745U, // USQADDv2i64 2347 2182099801U, // USQADDv4i16 2348 2719232857U, // USQADDv4i32 2349 3256365913U, // USQADDv8i16 2350 3793498969U, // USQADDv8i8 2351 67404308U, // USRAd 2352 2181050900U, // USRAv16i8_shift 2353 2718446100U, // USRAv2i32_shift 2354 571224596U, // USRAv2i64_shift 2355 3255841300U, // USRAv4i16_shift 2356 1108619796U, // USRAv4i32_shift 2357 1645752852U, // USRAv8i16_shift 2358 3793498644U, // USRAv8i8_shift 2359 2149060756U, // USUBLv16i8_v8i16 2360 2685146372U, // USUBLv2i32_v2i64 2361 3222541572U, // USUBLv4i16_v4i32 2362 1074532500U, // USUBLv4i32_v2i64 2363 1611927700U, // USUBLv8i16_v4i32 2364 3759674628U, // USUBLv8i8_v8i16 2365 1612190125U, // USUBWv16i8_v8i16 2366 537663920U, // USUBWv2i32_v2i64 2367 1075059120U, // USUBWv4i16_v4i32 2368 537661869U, // USUBWv4i32_v2i64 2369 1075057069U, // USUBWv8i16_v4i32 2370 1612192176U, // USUBWv8i8_v8i16 2371 2147487782U, // UZP1v16i8 2372 2684882982U, // UZP1v2i32 2373 537661478U, // UZP1v2i64 2374 3222278182U, // UZP1v4i16 2375 1075056678U, // UZP1v4i32 2376 1612189734U, // UZP1v8i16 2377 3759935526U, // UZP1v8i8 2378 2147488147U, // UZP2v16i8 2379 2684883347U, // UZP2v2i32 2380 537661843U, // UZP2v2i64 2381 3222278547U, // UZP2v4i16 2382 1075057043U, // UZP2v4i32 2383 1612190099U, // UZP2v8i16 2384 3759935891U, // UZP2v8i8 2385 3254792536U, // XTNv16i8 2386 1611142779U, // XTNv2i32 2387 2685408891U, // XTNv4i16 2388 1645490520U, // XTNv4i32 2389 2719494488U, // XTNv8i16 2390 3223066235U, // XTNv8i8 2391 2147487776U, // ZIP1v16i8 2392 2684882976U, // ZIP1v2i32 2393 537661472U, // ZIP1v2i64 2394 3222278176U, // ZIP1v4i16 2395 1075056672U, // ZIP1v4i32 2396 1612189728U, // ZIP1v8i16 2397 3759935520U, // ZIP1v8i8 2398 2147488141U, // ZIP2v16i8 2399 2684883341U, // ZIP2v2i32 2400 537661837U, // ZIP2v2i64 2401 3222278541U, // ZIP2v4i16 2402 1075057037U, // ZIP2v4i32 2403 1612190093U, // ZIP2v8i16 2404 3759935885U, // ZIP2v8i8 2405 0U 2406 }; 2407 2408 static const uint32_t OpInfo2[] = { 2409 0U, // PHI 2410 0U, // INLINEASM 2411 0U, // CFI_INSTRUCTION 2412 0U, // EH_LABEL 2413 0U, // GC_LABEL 2414 0U, // KILL 2415 0U, // EXTRACT_SUBREG 2416 0U, // INSERT_SUBREG 2417 0U, // IMPLICIT_DEF 2418 0U, // SUBREG_TO_REG 2419 0U, // COPY_TO_REGCLASS 2420 0U, // DBG_VALUE 2421 0U, // REG_SEQUENCE 2422 0U, // COPY 2423 0U, // BUNDLE 2424 0U, // LIFETIME_START 2425 0U, // LIFETIME_END 2426 0U, // STACKMAP 2427 0U, // PATCHPOINT 2428 0U, // LOAD_STACK_GUARD 2429 0U, // ABSv16i8 2430 0U, // ABSv1i64 2431 0U, // ABSv2i32 2432 0U, // ABSv2i64 2433 0U, // ABSv4i16 2434 0U, // ABSv4i32 2435 0U, // ABSv8i16 2436 0U, // ABSv8i8 2437 1U, // ADCSWr 2438 1U, // ADCSXr 2439 1U, // ADCWr 2440 1U, // ADCXr 2441 265U, // ADDHNv2i64_v2i32 2442 273U, // ADDHNv2i64_v4i32 2443 521U, // ADDHNv4i32_v4i16 2444 529U, // ADDHNv4i32_v8i16 2445 785U, // ADDHNv8i16_v16i8 2446 777U, // ADDHNv8i16_v8i8 2447 1033U, // ADDPv16i8 2448 1289U, // ADDPv2i32 2449 265U, // ADDPv2i64 2450 0U, // ADDPv2i64p 2451 1545U, // ADDPv4i16 2452 521U, // ADDPv4i32 2453 777U, // ADDPv8i16 2454 1801U, // ADDPv8i8 2455 25U, // ADDSWri 2456 0U, // ADDSWrr 2457 33U, // ADDSWrs 2458 41U, // ADDSWrx 2459 25U, // ADDSXri 2460 0U, // ADDSXrr 2461 33U, // ADDSXrs 2462 41U, // ADDSXrx 2463 2049U, // ADDSXrx64 2464 0U, // ADDVv16i8v 2465 0U, // ADDVv4i16v 2466 0U, // ADDVv4i32v 2467 0U, // ADDVv8i16v 2468 0U, // ADDVv8i8v 2469 25U, // ADDWri 2470 0U, // ADDWrr 2471 33U, // ADDWrs 2472 41U, // ADDWrx 2473 25U, // ADDXri 2474 0U, // ADDXrr 2475 33U, // ADDXrs 2476 41U, // ADDXrx 2477 2049U, // ADDXrx64 2478 1033U, // ADDv16i8 2479 1U, // ADDv1i64 2480 1289U, // ADDv2i32 2481 265U, // ADDv2i64 2482 1545U, // ADDv4i16 2483 521U, // ADDv4i32 2484 777U, // ADDv8i16 2485 1801U, // ADDv8i8 2486 0U, // ADJCALLSTACKDOWN 2487 0U, // ADJCALLSTACKUP 2488 0U, // ADR 2489 0U, // ADRP 2490 0U, // AESDrr 2491 0U, // AESErr 2492 0U, // AESIMCrr 2493 0U, // AESMCrr 2494 49U, // ANDSWri 2495 0U, // ANDSWrr 2496 33U, // ANDSWrs 2497 57U, // ANDSXri 2498 0U, // ANDSXrr 2499 33U, // ANDSXrs 2500 49U, // ANDWri 2501 0U, // ANDWrr 2502 33U, // ANDWrs 2503 57U, // ANDXri 2504 0U, // ANDXrr 2505 33U, // ANDXrs 2506 1033U, // ANDv16i8 2507 1801U, // ANDv8i8 2508 1U, // ASRVWr 2509 1U, // ASRVXr 2510 0U, // B 2511 2369U, // BFMWri 2512 2369U, // BFMXri 2513 0U, // BICSWrr 2514 33U, // BICSWrs 2515 0U, // BICSXrr 2516 33U, // BICSXrs 2517 0U, // BICWrr 2518 33U, // BICWrs 2519 0U, // BICXrr 2520 33U, // BICXrs 2521 1033U, // BICv16i8 2522 0U, // BICv2i32 2523 0U, // BICv4i16 2524 0U, // BICv4i32 2525 0U, // BICv8i16 2526 1801U, // BICv8i8 2527 1033U, // BIFv16i8 2528 1801U, // BIFv8i8 2529 1041U, // BITv16i8 2530 1809U, // BITv8i8 2531 0U, // BL 2532 0U, // BLR 2533 0U, // BR 2534 0U, // BRK 2535 1041U, // BSLv16i8 2536 1809U, // BSLv8i8 2537 0U, // Bcc 2538 0U, // CBNZW 2539 0U, // CBNZX 2540 0U, // CBZW 2541 0U, // CBZX 2542 10497U, // CCMNWi 2543 10497U, // CCMNWr 2544 10497U, // CCMNXi 2545 10497U, // CCMNXr 2546 10497U, // CCMPWi 2547 10497U, // CCMPWr 2548 10497U, // CCMPXi 2549 10497U, // CCMPXr 2550 0U, // CLREX 2551 0U, // CLSWr 2552 0U, // CLSXr 2553 0U, // CLSv16i8 2554 0U, // CLSv2i32 2555 0U, // CLSv4i16 2556 0U, // CLSv4i32 2557 0U, // CLSv8i16 2558 0U, // CLSv8i8 2559 0U, // CLZWr 2560 0U, // CLZXr 2561 0U, // CLZv16i8 2562 0U, // CLZv2i32 2563 0U, // CLZv4i16 2564 0U, // CLZv4i32 2565 0U, // CLZv8i16 2566 0U, // CLZv8i8 2567 1033U, // CMEQv16i8 2568 2U, // CMEQv16i8rz 2569 1U, // CMEQv1i64 2570 2U, // CMEQv1i64rz 2571 1289U, // CMEQv2i32 2572 2U, // CMEQv2i32rz 2573 265U, // CMEQv2i64 2574 2U, // CMEQv2i64rz 2575 1545U, // CMEQv4i16 2576 2U, // CMEQv4i16rz 2577 521U, // CMEQv4i32 2578 2U, // CMEQv4i32rz 2579 777U, // CMEQv8i16 2580 2U, // CMEQv8i16rz 2581 1801U, // CMEQv8i8 2582 2U, // CMEQv8i8rz 2583 1033U, // CMGEv16i8 2584 2U, // CMGEv16i8rz 2585 1U, // CMGEv1i64 2586 2U, // CMGEv1i64rz 2587 1289U, // CMGEv2i32 2588 2U, // CMGEv2i32rz 2589 265U, // CMGEv2i64 2590 2U, // CMGEv2i64rz 2591 1545U, // CMGEv4i16 2592 2U, // CMGEv4i16rz 2593 521U, // CMGEv4i32 2594 2U, // CMGEv4i32rz 2595 777U, // CMGEv8i16 2596 2U, // CMGEv8i16rz 2597 1801U, // CMGEv8i8 2598 2U, // CMGEv8i8rz 2599 1033U, // CMGTv16i8 2600 2U, // CMGTv16i8rz 2601 1U, // CMGTv1i64 2602 2U, // CMGTv1i64rz 2603 1289U, // CMGTv2i32 2604 2U, // CMGTv2i32rz 2605 265U, // CMGTv2i64 2606 2U, // CMGTv2i64rz 2607 1545U, // CMGTv4i16 2608 2U, // CMGTv4i16rz 2609 521U, // CMGTv4i32 2610 2U, // CMGTv4i32rz 2611 777U, // CMGTv8i16 2612 2U, // CMGTv8i16rz 2613 1801U, // CMGTv8i8 2614 2U, // CMGTv8i8rz 2615 1033U, // CMHIv16i8 2616 1U, // CMHIv1i64 2617 1289U, // CMHIv2i32 2618 265U, // CMHIv2i64 2619 1545U, // CMHIv4i16 2620 521U, // CMHIv4i32 2621 777U, // CMHIv8i16 2622 1801U, // CMHIv8i8 2623 1033U, // CMHSv16i8 2624 1U, // CMHSv1i64 2625 1289U, // CMHSv2i32 2626 265U, // CMHSv2i64 2627 1545U, // CMHSv4i16 2628 521U, // CMHSv4i32 2629 777U, // CMHSv8i16 2630 1801U, // CMHSv8i8 2631 2U, // CMLEv16i8rz 2632 2U, // CMLEv1i64rz 2633 2U, // CMLEv2i32rz 2634 2U, // CMLEv2i64rz 2635 2U, // CMLEv4i16rz 2636 2U, // CMLEv4i32rz 2637 2U, // CMLEv8i16rz 2638 2U, // CMLEv8i8rz 2639 2U, // CMLTv16i8rz 2640 2U, // CMLTv1i64rz 2641 2U, // CMLTv2i32rz 2642 2U, // CMLTv2i64rz 2643 2U, // CMLTv4i16rz 2644 2U, // CMLTv4i32rz 2645 2U, // CMLTv8i16rz 2646 2U, // CMLTv8i8rz 2647 1033U, // CMTSTv16i8 2648 1U, // CMTSTv1i64 2649 1289U, // CMTSTv2i32 2650 265U, // CMTSTv2i64 2651 1545U, // CMTSTv4i16 2652 521U, // CMTSTv4i32 2653 777U, // CMTSTv8i16 2654 1801U, // CMTSTv8i8 2655 0U, // CNTv16i8 2656 0U, // CNTv8i8 2657 75U, // CPYi16 2658 75U, // CPYi32 2659 75U, // CPYi64 2660 75U, // CPYi8 2661 1U, // CRC32Brr 2662 1U, // CRC32CBrr 2663 1U, // CRC32CHrr 2664 1U, // CRC32CWrr 2665 1U, // CRC32CXrr 2666 1U, // CRC32Hrr 2667 1U, // CRC32Wrr 2668 1U, // CRC32Xrr 2669 10497U, // CSELWr 2670 10497U, // CSELXr 2671 10497U, // CSINCWr 2672 10497U, // CSINCXr 2673 10497U, // CSINVWr 2674 10497U, // CSINVXr 2675 10497U, // CSNEGWr 2676 10497U, // CSNEGXr 2677 0U, // DCPS1 2678 0U, // DCPS2 2679 0U, // DCPS3 2680 0U, // DMB 2681 0U, // DRPS 2682 0U, // DSB 2683 0U, // DUPv16i8gpr 2684 75U, // DUPv16i8lane 2685 0U, // DUPv2i32gpr 2686 75U, // DUPv2i32lane 2687 0U, // DUPv2i64gpr 2688 75U, // DUPv2i64lane 2689 0U, // DUPv4i16gpr 2690 75U, // DUPv4i16lane 2691 0U, // DUPv4i32gpr 2692 75U, // DUPv4i32lane 2693 0U, // DUPv8i16gpr 2694 75U, // DUPv8i16lane 2695 0U, // DUPv8i8gpr 2696 75U, // DUPv8i8lane 2697 0U, // EONWrr 2698 33U, // EONWrs 2699 0U, // EONXrr 2700 33U, // EONXrs 2701 49U, // EORWri 2702 0U, // EORWrr 2703 33U, // EORWrs 2704 57U, // EORXri 2705 0U, // EORXrr 2706 33U, // EORXrs 2707 1033U, // EORv16i8 2708 1801U, // EORv8i8 2709 0U, // ERET 2710 18689U, // EXTRWrri 2711 18689U, // EXTRXrri 2712 2569U, // EXTv16i8 2713 2825U, // EXTv8i8 2714 0U, // F128CSEL 2715 1U, // FABD32 2716 1U, // FABD64 2717 1289U, // FABDv2f32 2718 265U, // FABDv2f64 2719 521U, // FABDv4f32 2720 0U, // FABSDr 2721 0U, // FABSSr 2722 0U, // FABSv2f32 2723 0U, // FABSv2f64 2724 0U, // FABSv4f32 2725 1U, // FACGE32 2726 1U, // FACGE64 2727 1289U, // FACGEv2f32 2728 265U, // FACGEv2f64 2729 521U, // FACGEv4f32 2730 1U, // FACGT32 2731 1U, // FACGT64 2732 1289U, // FACGTv2f32 2733 265U, // FACGTv2f64 2734 521U, // FACGTv4f32 2735 1U, // FADDDrr 2736 1289U, // FADDPv2f32 2737 265U, // FADDPv2f64 2738 0U, // FADDPv2i32p 2739 0U, // FADDPv2i64p 2740 521U, // FADDPv4f32 2741 1U, // FADDSrr 2742 1289U, // FADDv2f32 2743 265U, // FADDv2f64 2744 521U, // FADDv4f32 2745 10497U, // FCCMPDrr 2746 10497U, // FCCMPEDrr 2747 10497U, // FCCMPESrr 2748 10497U, // FCCMPSrr 2749 1U, // FCMEQ32 2750 1U, // FCMEQ64 2751 3U, // FCMEQv1i32rz 2752 3U, // FCMEQv1i64rz 2753 1289U, // FCMEQv2f32 2754 265U, // FCMEQv2f64 2755 3U, // FCMEQv2i32rz 2756 3U, // FCMEQv2i64rz 2757 521U, // FCMEQv4f32 2758 3U, // FCMEQv4i32rz 2759 1U, // FCMGE32 2760 1U, // FCMGE64 2761 3U, // FCMGEv1i32rz 2762 3U, // FCMGEv1i64rz 2763 1289U, // FCMGEv2f32 2764 265U, // FCMGEv2f64 2765 3U, // FCMGEv2i32rz 2766 3U, // FCMGEv2i64rz 2767 521U, // FCMGEv4f32 2768 3U, // FCMGEv4i32rz 2769 1U, // FCMGT32 2770 1U, // FCMGT64 2771 3U, // FCMGTv1i32rz 2772 3U, // FCMGTv1i64rz 2773 1289U, // FCMGTv2f32 2774 265U, // FCMGTv2f64 2775 3U, // FCMGTv2i32rz 2776 3U, // FCMGTv2i64rz 2777 521U, // FCMGTv4f32 2778 3U, // FCMGTv4i32rz 2779 3U, // FCMLEv1i32rz 2780 3U, // FCMLEv1i64rz 2781 3U, // FCMLEv2i32rz 2782 3U, // FCMLEv2i64rz 2783 3U, // FCMLEv4i32rz 2784 3U, // FCMLTv1i32rz 2785 3U, // FCMLTv1i64rz 2786 3U, // FCMLTv2i32rz 2787 3U, // FCMLTv2i64rz 2788 3U, // FCMLTv4i32rz 2789 0U, // FCMPDri 2790 0U, // FCMPDrr 2791 0U, // FCMPEDri 2792 0U, // FCMPEDrr 2793 0U, // FCMPESri 2794 0U, // FCMPESrr 2795 0U, // FCMPSri 2796 0U, // FCMPSrr 2797 10497U, // FCSELDrrr 2798 10497U, // FCSELSrrr 2799 0U, // FCVTASUWDr 2800 0U, // FCVTASUWSr 2801 0U, // FCVTASUXDr 2802 0U, // FCVTASUXSr 2803 0U, // FCVTASv1i32 2804 0U, // FCVTASv1i64 2805 0U, // FCVTASv2f32 2806 0U, // FCVTASv2f64 2807 0U, // FCVTASv4f32 2808 0U, // FCVTAUUWDr 2809 0U, // FCVTAUUWSr 2810 0U, // FCVTAUUXDr 2811 0U, // FCVTAUUXSr 2812 0U, // FCVTAUv1i32 2813 0U, // FCVTAUv1i64 2814 0U, // FCVTAUv2f32 2815 0U, // FCVTAUv2f64 2816 0U, // FCVTAUv4f32 2817 0U, // FCVTDHr 2818 0U, // FCVTDSr 2819 0U, // FCVTHDr 2820 0U, // FCVTHSr 2821 0U, // FCVTLv2i32 2822 0U, // FCVTLv4i16 2823 0U, // FCVTLv4i32 2824 0U, // FCVTLv8i16 2825 0U, // FCVTMSUWDr 2826 0U, // FCVTMSUWSr 2827 0U, // FCVTMSUXDr 2828 0U, // FCVTMSUXSr 2829 0U, // FCVTMSv1i32 2830 0U, // FCVTMSv1i64 2831 0U, // FCVTMSv2f32 2832 0U, // FCVTMSv2f64 2833 0U, // FCVTMSv4f32 2834 0U, // FCVTMUUWDr 2835 0U, // FCVTMUUWSr 2836 0U, // FCVTMUUXDr 2837 0U, // FCVTMUUXSr 2838 0U, // FCVTMUv1i32 2839 0U, // FCVTMUv1i64 2840 0U, // FCVTMUv2f32 2841 0U, // FCVTMUv2f64 2842 0U, // FCVTMUv4f32 2843 0U, // FCVTNSUWDr 2844 0U, // FCVTNSUWSr 2845 0U, // FCVTNSUXDr 2846 0U, // FCVTNSUXSr 2847 0U, // FCVTNSv1i32 2848 0U, // FCVTNSv1i64 2849 0U, // FCVTNSv2f32 2850 0U, // FCVTNSv2f64 2851 0U, // FCVTNSv4f32 2852 0U, // FCVTNUUWDr 2853 0U, // FCVTNUUWSr 2854 0U, // FCVTNUUXDr 2855 0U, // FCVTNUUXSr 2856 0U, // FCVTNUv1i32 2857 0U, // FCVTNUv1i64 2858 0U, // FCVTNUv2f32 2859 0U, // FCVTNUv2f64 2860 0U, // FCVTNUv4f32 2861 0U, // FCVTNv2i32 2862 0U, // FCVTNv4i16 2863 0U, // FCVTNv4i32 2864 0U, // FCVTNv8i16 2865 0U, // FCVTPSUWDr 2866 0U, // FCVTPSUWSr 2867 0U, // FCVTPSUXDr 2868 0U, // FCVTPSUXSr 2869 0U, // FCVTPSv1i32 2870 0U, // FCVTPSv1i64 2871 0U, // FCVTPSv2f32 2872 0U, // FCVTPSv2f64 2873 0U, // FCVTPSv4f32 2874 0U, // FCVTPUUWDr 2875 0U, // FCVTPUUWSr 2876 0U, // FCVTPUUXDr 2877 0U, // FCVTPUUXSr 2878 0U, // FCVTPUv1i32 2879 0U, // FCVTPUv1i64 2880 0U, // FCVTPUv2f32 2881 0U, // FCVTPUv2f64 2882 0U, // FCVTPUv4f32 2883 0U, // FCVTSDr 2884 0U, // FCVTSHr 2885 0U, // FCVTXNv1i64 2886 0U, // FCVTXNv2f32 2887 0U, // FCVTXNv4f32 2888 1U, // FCVTZSSWDri 2889 1U, // FCVTZSSWSri 2890 1U, // FCVTZSSXDri 2891 1U, // FCVTZSSXSri 2892 0U, // FCVTZSUWDr 2893 0U, // FCVTZSUWSr 2894 0U, // FCVTZSUXDr 2895 0U, // FCVTZSUXSr 2896 1U, // FCVTZS_IntSWDri 2897 1U, // FCVTZS_IntSWSri 2898 1U, // FCVTZS_IntSXDri 2899 1U, // FCVTZS_IntSXSri 2900 0U, // FCVTZS_IntUWDr 2901 0U, // FCVTZS_IntUWSr 2902 0U, // FCVTZS_IntUXDr 2903 0U, // FCVTZS_IntUXSr 2904 0U, // FCVTZS_Intv2f32 2905 0U, // FCVTZS_Intv2f64 2906 0U, // FCVTZS_Intv4f32 2907 1U, // FCVTZSd 2908 1U, // FCVTZSs 2909 0U, // FCVTZSv1i32 2910 0U, // FCVTZSv1i64 2911 0U, // FCVTZSv2f32 2912 0U, // FCVTZSv2f64 2913 1U, // FCVTZSv2i32_shift 2914 1U, // FCVTZSv2i64_shift 2915 0U, // FCVTZSv4f32 2916 1U, // FCVTZSv4i32_shift 2917 1U, // FCVTZUSWDri 2918 1U, // FCVTZUSWSri 2919 1U, // FCVTZUSXDri 2920 1U, // FCVTZUSXSri 2921 0U, // FCVTZUUWDr 2922 0U, // FCVTZUUWSr 2923 0U, // FCVTZUUXDr 2924 0U, // FCVTZUUXSr 2925 1U, // FCVTZU_IntSWDri 2926 1U, // FCVTZU_IntSWSri 2927 1U, // FCVTZU_IntSXDri 2928 1U, // FCVTZU_IntSXSri 2929 0U, // FCVTZU_IntUWDr 2930 0U, // FCVTZU_IntUWSr 2931 0U, // FCVTZU_IntUXDr 2932 0U, // FCVTZU_IntUXSr 2933 0U, // FCVTZU_Intv2f32 2934 0U, // FCVTZU_Intv2f64 2935 0U, // FCVTZU_Intv4f32 2936 1U, // FCVTZUd 2937 1U, // FCVTZUs 2938 0U, // FCVTZUv1i32 2939 0U, // FCVTZUv1i64 2940 0U, // FCVTZUv2f32 2941 0U, // FCVTZUv2f64 2942 1U, // FCVTZUv2i32_shift 2943 1U, // FCVTZUv2i64_shift 2944 0U, // FCVTZUv4f32 2945 1U, // FCVTZUv4i32_shift 2946 1U, // FDIVDrr 2947 1U, // FDIVSrr 2948 1289U, // FDIVv2f32 2949 265U, // FDIVv2f64 2950 521U, // FDIVv4f32 2951 18689U, // FMADDDrrr 2952 18689U, // FMADDSrrr 2953 1U, // FMAXDrr 2954 1U, // FMAXNMDrr 2955 1289U, // FMAXNMPv2f32 2956 265U, // FMAXNMPv2f64 2957 0U, // FMAXNMPv2i32p 2958 0U, // FMAXNMPv2i64p 2959 521U, // FMAXNMPv4f32 2960 1U, // FMAXNMSrr 2961 0U, // FMAXNMVv4i32v 2962 1289U, // FMAXNMv2f32 2963 265U, // FMAXNMv2f64 2964 521U, // FMAXNMv4f32 2965 1289U, // FMAXPv2f32 2966 265U, // FMAXPv2f64 2967 0U, // FMAXPv2i32p 2968 0U, // FMAXPv2i64p 2969 521U, // FMAXPv4f32 2970 1U, // FMAXSrr 2971 0U, // FMAXVv4i32v 2972 1289U, // FMAXv2f32 2973 265U, // FMAXv2f64 2974 521U, // FMAXv4f32 2975 1U, // FMINDrr 2976 1U, // FMINNMDrr 2977 1289U, // FMINNMPv2f32 2978 265U, // FMINNMPv2f64 2979 0U, // FMINNMPv2i32p 2980 0U, // FMINNMPv2i64p 2981 521U, // FMINNMPv4f32 2982 1U, // FMINNMSrr 2983 0U, // FMINNMVv4i32v 2984 1289U, // FMINNMv2f32 2985 265U, // FMINNMv2f64 2986 521U, // FMINNMv4f32 2987 1289U, // FMINPv2f32 2988 265U, // FMINPv2f64 2989 0U, // FMINPv2i32p 2990 0U, // FMINPv2i64p 2991 521U, // FMINPv4f32 2992 1U, // FMINSrr 2993 0U, // FMINVv4i32v 2994 1289U, // FMINv2f32 2995 265U, // FMINv2f64 2996 521U, // FMINv4f32 2997 27665U, // FMLAv1i32_indexed 2998 27921U, // FMLAv1i64_indexed 2999 1297U, // FMLAv2f32 3000 273U, // FMLAv2f64 3001 27665U, // FMLAv2i32_indexed 3002 27921U, // FMLAv2i64_indexed 3003 529U, // FMLAv4f32 3004 27665U, // FMLAv4i32_indexed 3005 27665U, // FMLSv1i32_indexed 3006 27921U, // FMLSv1i64_indexed 3007 1297U, // FMLSv2f32 3008 273U, // FMLSv2f64 3009 27665U, // FMLSv2i32_indexed 3010 27921U, // FMLSv2i64_indexed 3011 529U, // FMLSv4f32 3012 27665U, // FMLSv4i32_indexed 3013 75U, // FMOVDXHighr 3014 0U, // FMOVDXr 3015 0U, // FMOVDi 3016 0U, // FMOVDr 3017 0U, // FMOVSWr 3018 0U, // FMOVSi 3019 0U, // FMOVSr 3020 0U, // FMOVWSr 3021 0U, // FMOVXDHighr 3022 0U, // FMOVXDr 3023 0U, // FMOVv2f32_ns 3024 0U, // FMOVv2f64_ns 3025 0U, // FMOVv4f32_ns 3026 18689U, // FMSUBDrrr 3027 18689U, // FMSUBSrrr 3028 1U, // FMULDrr 3029 1U, // FMULSrr 3030 1U, // FMULX32 3031 1U, // FMULX64 3032 35849U, // FMULXv1i32_indexed 3033 36105U, // FMULXv1i64_indexed 3034 1289U, // FMULXv2f32 3035 265U, // FMULXv2f64 3036 35849U, // FMULXv2i32_indexed 3037 36105U, // FMULXv2i64_indexed 3038 521U, // FMULXv4f32 3039 35849U, // FMULXv4i32_indexed 3040 35849U, // FMULv1i32_indexed 3041 36105U, // FMULv1i64_indexed 3042 1289U, // FMULv2f32 3043 265U, // FMULv2f64 3044 35849U, // FMULv2i32_indexed 3045 36105U, // FMULv2i64_indexed 3046 521U, // FMULv4f32 3047 35849U, // FMULv4i32_indexed 3048 0U, // FNEGDr 3049 0U, // FNEGSr 3050 0U, // FNEGv2f32 3051 0U, // FNEGv2f64 3052 0U, // FNEGv4f32 3053 18689U, // FNMADDDrrr 3054 18689U, // FNMADDSrrr 3055 18689U, // FNMSUBDrrr 3056 18689U, // FNMSUBSrrr 3057 1U, // FNMULDrr 3058 1U, // FNMULSrr 3059 0U, // FRECPEv1i32 3060 0U, // FRECPEv1i64 3061 0U, // FRECPEv2f32 3062 0U, // FRECPEv2f64 3063 0U, // FRECPEv4f32 3064 1U, // FRECPS32 3065 1U, // FRECPS64 3066 1289U, // FRECPSv2f32 3067 265U, // FRECPSv2f64 3068 521U, // FRECPSv4f32 3069 0U, // FRECPXv1i32 3070 0U, // FRECPXv1i64 3071 0U, // FRINTADr 3072 0U, // FRINTASr 3073 0U, // FRINTAv2f32 3074 0U, // FRINTAv2f64 3075 0U, // FRINTAv4f32 3076 0U, // FRINTIDr 3077 0U, // FRINTISr 3078 0U, // FRINTIv2f32 3079 0U, // FRINTIv2f64 3080 0U, // FRINTIv4f32 3081 0U, // FRINTMDr 3082 0U, // FRINTMSr 3083 0U, // FRINTMv2f32 3084 0U, // FRINTMv2f64 3085 0U, // FRINTMv4f32 3086 0U, // FRINTNDr 3087 0U, // FRINTNSr 3088 0U, // FRINTNv2f32 3089 0U, // FRINTNv2f64 3090 0U, // FRINTNv4f32 3091 0U, // FRINTPDr 3092 0U, // FRINTPSr 3093 0U, // FRINTPv2f32 3094 0U, // FRINTPv2f64 3095 0U, // FRINTPv4f32 3096 0U, // FRINTXDr 3097 0U, // FRINTXSr 3098 0U, // FRINTXv2f32 3099 0U, // FRINTXv2f64 3100 0U, // FRINTXv4f32 3101 0U, // FRINTZDr 3102 0U, // FRINTZSr 3103 0U, // FRINTZv2f32 3104 0U, // FRINTZv2f64 3105 0U, // FRINTZv4f32 3106 0U, // FRSQRTEv1i32 3107 0U, // FRSQRTEv1i64 3108 0U, // FRSQRTEv2f32 3109 0U, // FRSQRTEv2f64 3110 0U, // FRSQRTEv4f32 3111 1U, // FRSQRTS32 3112 1U, // FRSQRTS64 3113 1289U, // FRSQRTSv2f32 3114 265U, // FRSQRTSv2f64 3115 521U, // FRSQRTSv4f32 3116 0U, // FSQRTDr 3117 0U, // FSQRTSr 3118 0U, // FSQRTv2f32 3119 0U, // FSQRTv2f64 3120 0U, // FSQRTv4f32 3121 1U, // FSUBDrr 3122 1U, // FSUBSrr 3123 1289U, // FSUBv2f32 3124 265U, // FSUBv2f64 3125 521U, // FSUBv4f32 3126 0U, // HINT 3127 0U, // HLT 3128 0U, // HVC 3129 0U, // INSvi16gpr 3130 83U, // INSvi16lane 3131 0U, // INSvi32gpr 3132 83U, // INSvi32lane 3133 0U, // INSvi64gpr 3134 83U, // INSvi64lane 3135 0U, // INSvi8gpr 3136 83U, // INSvi8lane 3137 0U, // ISB 3138 0U, // LD1Fourv16b 3139 0U, // LD1Fourv16b_POST 3140 0U, // LD1Fourv1d 3141 0U, // LD1Fourv1d_POST 3142 0U, // LD1Fourv2d 3143 0U, // LD1Fourv2d_POST 3144 0U, // LD1Fourv2s 3145 0U, // LD1Fourv2s_POST 3146 0U, // LD1Fourv4h 3147 0U, // LD1Fourv4h_POST 3148 0U, // LD1Fourv4s 3149 0U, // LD1Fourv4s_POST 3150 0U, // LD1Fourv8b 3151 0U, // LD1Fourv8b_POST 3152 0U, // LD1Fourv8h 3153 0U, // LD1Fourv8h_POST 3154 0U, // LD1Onev16b 3155 0U, // LD1Onev16b_POST 3156 0U, // LD1Onev1d 3157 0U, // LD1Onev1d_POST 3158 0U, // LD1Onev2d 3159 0U, // LD1Onev2d_POST 3160 0U, // LD1Onev2s 3161 0U, // LD1Onev2s_POST 3162 0U, // LD1Onev4h 3163 0U, // LD1Onev4h_POST 3164 0U, // LD1Onev4s 3165 0U, // LD1Onev4s_POST 3166 0U, // LD1Onev8b 3167 0U, // LD1Onev8b_POST 3168 0U, // LD1Onev8h 3169 0U, // LD1Onev8h_POST 3170 0U, // LD1Rv16b 3171 0U, // LD1Rv16b_POST 3172 0U, // LD1Rv1d 3173 0U, // LD1Rv1d_POST 3174 0U, // LD1Rv2d 3175 0U, // LD1Rv2d_POST 3176 0U, // LD1Rv2s 3177 0U, // LD1Rv2s_POST 3178 0U, // LD1Rv4h 3179 0U, // LD1Rv4h_POST 3180 0U, // LD1Rv4s 3181 0U, // LD1Rv4s_POST 3182 0U, // LD1Rv8b 3183 0U, // LD1Rv8b_POST 3184 0U, // LD1Rv8h 3185 0U, // LD1Rv8h_POST 3186 0U, // LD1Threev16b 3187 0U, // LD1Threev16b_POST 3188 0U, // LD1Threev1d 3189 0U, // LD1Threev1d_POST 3190 0U, // LD1Threev2d 3191 0U, // LD1Threev2d_POST 3192 0U, // LD1Threev2s 3193 0U, // LD1Threev2s_POST 3194 0U, // LD1Threev4h 3195 0U, // LD1Threev4h_POST 3196 0U, // LD1Threev4s 3197 0U, // LD1Threev4s_POST 3198 0U, // LD1Threev8b 3199 0U, // LD1Threev8b_POST 3200 0U, // LD1Threev8h 3201 0U, // LD1Threev8h_POST 3202 0U, // LD1Twov16b 3203 0U, // LD1Twov16b_POST 3204 0U, // LD1Twov1d 3205 0U, // LD1Twov1d_POST 3206 0U, // LD1Twov2d 3207 0U, // LD1Twov2d_POST 3208 0U, // LD1Twov2s 3209 0U, // LD1Twov2s_POST 3210 0U, // LD1Twov4h 3211 0U, // LD1Twov4h_POST 3212 0U, // LD1Twov4s 3213 0U, // LD1Twov4s_POST 3214 0U, // LD1Twov8b 3215 0U, // LD1Twov8b_POST 3216 0U, // LD1Twov8h 3217 0U, // LD1Twov8h_POST 3218 0U, // LD1i16 3219 0U, // LD1i16_POST 3220 0U, // LD1i32 3221 0U, // LD1i32_POST 3222 0U, // LD1i64 3223 0U, // LD1i64_POST 3224 0U, // LD1i8 3225 0U, // LD1i8_POST 3226 0U, // LD2Rv16b 3227 0U, // LD2Rv16b_POST 3228 0U, // LD2Rv1d 3229 0U, // LD2Rv1d_POST 3230 0U, // LD2Rv2d 3231 0U, // LD2Rv2d_POST 3232 0U, // LD2Rv2s 3233 0U, // LD2Rv2s_POST 3234 0U, // LD2Rv4h 3235 0U, // LD2Rv4h_POST 3236 0U, // LD2Rv4s 3237 0U, // LD2Rv4s_POST 3238 0U, // LD2Rv8b 3239 0U, // LD2Rv8b_POST 3240 0U, // LD2Rv8h 3241 0U, // LD2Rv8h_POST 3242 0U, // LD2Twov16b 3243 0U, // LD2Twov16b_POST 3244 0U, // LD2Twov2d 3245 0U, // LD2Twov2d_POST 3246 0U, // LD2Twov2s 3247 0U, // LD2Twov2s_POST 3248 0U, // LD2Twov4h 3249 0U, // LD2Twov4h_POST 3250 0U, // LD2Twov4s 3251 0U, // LD2Twov4s_POST 3252 0U, // LD2Twov8b 3253 0U, // LD2Twov8b_POST 3254 0U, // LD2Twov8h 3255 0U, // LD2Twov8h_POST 3256 0U, // LD2i16 3257 0U, // LD2i16_POST 3258 0U, // LD2i32 3259 0U, // LD2i32_POST 3260 0U, // LD2i64 3261 0U, // LD2i64_POST 3262 0U, // LD2i8 3263 0U, // LD2i8_POST 3264 0U, // LD3Rv16b 3265 0U, // LD3Rv16b_POST 3266 0U, // LD3Rv1d 3267 0U, // LD3Rv1d_POST 3268 0U, // LD3Rv2d 3269 0U, // LD3Rv2d_POST 3270 0U, // LD3Rv2s 3271 0U, // LD3Rv2s_POST 3272 0U, // LD3Rv4h 3273 0U, // LD3Rv4h_POST 3274 0U, // LD3Rv4s 3275 0U, // LD3Rv4s_POST 3276 0U, // LD3Rv8b 3277 0U, // LD3Rv8b_POST 3278 0U, // LD3Rv8h 3279 0U, // LD3Rv8h_POST 3280 0U, // LD3Threev16b 3281 0U, // LD3Threev16b_POST 3282 0U, // LD3Threev2d 3283 0U, // LD3Threev2d_POST 3284 0U, // LD3Threev2s 3285 0U, // LD3Threev2s_POST 3286 0U, // LD3Threev4h 3287 0U, // LD3Threev4h_POST 3288 0U, // LD3Threev4s 3289 0U, // LD3Threev4s_POST 3290 0U, // LD3Threev8b 3291 0U, // LD3Threev8b_POST 3292 0U, // LD3Threev8h 3293 0U, // LD3Threev8h_POST 3294 0U, // LD3i16 3295 0U, // LD3i16_POST 3296 0U, // LD3i32 3297 0U, // LD3i32_POST 3298 0U, // LD3i64 3299 0U, // LD3i64_POST 3300 0U, // LD3i8 3301 0U, // LD3i8_POST 3302 0U, // LD4Fourv16b 3303 0U, // LD4Fourv16b_POST 3304 0U, // LD4Fourv2d 3305 0U, // LD4Fourv2d_POST 3306 0U, // LD4Fourv2s 3307 0U, // LD4Fourv2s_POST 3308 0U, // LD4Fourv4h 3309 0U, // LD4Fourv4h_POST 3310 0U, // LD4Fourv4s 3311 0U, // LD4Fourv4s_POST 3312 0U, // LD4Fourv8b 3313 0U, // LD4Fourv8b_POST 3314 0U, // LD4Fourv8h 3315 0U, // LD4Fourv8h_POST 3316 0U, // LD4Rv16b 3317 0U, // LD4Rv16b_POST 3318 0U, // LD4Rv1d 3319 0U, // LD4Rv1d_POST 3320 0U, // LD4Rv2d 3321 0U, // LD4Rv2d_POST 3322 0U, // LD4Rv2s 3323 0U, // LD4Rv2s_POST 3324 0U, // LD4Rv4h 3325 0U, // LD4Rv4h_POST 3326 0U, // LD4Rv4s 3327 0U, // LD4Rv4s_POST 3328 0U, // LD4Rv8b 3329 0U, // LD4Rv8b_POST 3330 0U, // LD4Rv8h 3331 0U, // LD4Rv8h_POST 3332 0U, // LD4i16 3333 0U, // LD4i16_POST 3334 0U, // LD4i32 3335 0U, // LD4i32_POST 3336 0U, // LD4i64 3337 0U, // LD4i64_POST 3338 0U, // LD4i8 3339 0U, // LD4i8_POST 3340 4U, // LDARB 3341 4U, // LDARH 3342 4U, // LDARW 3343 4U, // LDARX 3344 3588U, // LDAXPW 3345 3588U, // LDAXPX 3346 4U, // LDAXRB 3347 4U, // LDAXRH 3348 4U, // LDAXRW 3349 4U, // LDAXRX 3350 43268U, // LDNPDi 3351 51460U, // LDNPQi 3352 59652U, // LDNPSi 3353 59652U, // LDNPWi 3354 43268U, // LDNPXi 3355 43268U, // LDPDi 3356 69444U, // LDPDpost 3357 330052U, // LDPDpre 3358 51460U, // LDPQi 3359 77636U, // LDPQpost 3360 338244U, // LDPQpre 3361 59652U, // LDPSWi 3362 85828U, // LDPSWpost 3363 346436U, // LDPSWpre 3364 59652U, // LDPSi 3365 85828U, // LDPSpost 3366 346436U, // LDPSpre 3367 59652U, // LDPWi 3368 85828U, // LDPWpost 3369 346436U, // LDPWpre 3370 43268U, // LDPXi 3371 69444U, // LDPXpost 3372 330052U, // LDPXpre 3373 4U, // LDRBBpost 3374 4161U, // LDRBBpre 3375 92417U, // LDRBBroW 3376 100609U, // LDRBBroX 3377 89U, // LDRBBui 3378 4U, // LDRBpost 3379 4161U, // LDRBpre 3380 92417U, // LDRBroW 3381 100609U, // LDRBroX 3382 89U, // LDRBui 3383 0U, // LDRDl 3384 4U, // LDRDpost 3385 4161U, // LDRDpre 3386 108801U, // LDRDroW 3387 116993U, // LDRDroX 3388 97U, // LDRDui 3389 4U, // LDRHHpost 3390 4161U, // LDRHHpre 3391 125185U, // LDRHHroW 3392 133377U, // LDRHHroX 3393 105U, // LDRHHui 3394 4U, // LDRHpost 3395 4161U, // LDRHpre 3396 125185U, // LDRHroW 3397 133377U, // LDRHroX 3398 105U, // LDRHui 3399 0U, // LDRQl 3400 4U, // LDRQpost 3401 4161U, // LDRQpre 3402 141569U, // LDRQroW 3403 149761U, // LDRQroX 3404 113U, // LDRQui 3405 4U, // LDRSBWpost 3406 4161U, // LDRSBWpre 3407 92417U, // LDRSBWroW 3408 100609U, // LDRSBWroX 3409 89U, // LDRSBWui 3410 4U, // LDRSBXpost 3411 4161U, // LDRSBXpre 3412 92417U, // LDRSBXroW 3413 100609U, // LDRSBXroX 3414 89U, // LDRSBXui 3415 4U, // LDRSHWpost 3416 4161U, // LDRSHWpre 3417 125185U, // LDRSHWroW 3418 133377U, // LDRSHWroX 3419 105U, // LDRSHWui 3420 4U, // LDRSHXpost 3421 4161U, // LDRSHXpre 3422 125185U, // LDRSHXroW 3423 133377U, // LDRSHXroX 3424 105U, // LDRSHXui 3425 0U, // LDRSWl 3426 4U, // LDRSWpost 3427 4161U, // LDRSWpre 3428 157953U, // LDRSWroW 3429 166145U, // LDRSWroX 3430 121U, // LDRSWui 3431 0U, // LDRSl 3432 4U, // LDRSpost 3433 4161U, // LDRSpre 3434 157953U, // LDRSroW 3435 166145U, // LDRSroX 3436 121U, // LDRSui 3437 0U, // LDRWl 3438 4U, // LDRWpost 3439 4161U, // LDRWpre 3440 157953U, // LDRWroW 3441 166145U, // LDRWroX 3442 121U, // LDRWui 3443 0U, // LDRXl 3444 4U, // LDRXpost 3445 4161U, // LDRXpre 3446 108801U, // LDRXroW 3447 116993U, // LDRXroX 3448 97U, // LDRXui 3449 3585U, // LDTRBi 3450 3585U, // LDTRHi 3451 3585U, // LDTRSBWi 3452 3585U, // LDTRSBXi 3453 3585U, // LDTRSHWi 3454 3585U, // LDTRSHXi 3455 3585U, // LDTRSWi 3456 3585U, // LDTRWi 3457 3585U, // LDTRXi 3458 3585U, // LDURBBi 3459 3585U, // LDURBi 3460 3585U, // LDURDi 3461 3585U, // LDURHHi 3462 3585U, // LDURHi 3463 3585U, // LDURQi 3464 3585U, // LDURSBWi 3465 3585U, // LDURSBXi 3466 3585U, // LDURSHWi 3467 3585U, // LDURSHXi 3468 3585U, // LDURSWi 3469 3585U, // LDURSi 3470 3585U, // LDURWi 3471 3585U, // LDURXi 3472 3588U, // LDXPW 3473 3588U, // LDXPX 3474 4U, // LDXRB 3475 4U, // LDXRH 3476 4U, // LDXRW 3477 4U, // LDXRX 3478 0U, // LOADgot 3479 1U, // LSLVWr 3480 1U, // LSLVXr 3481 1U, // LSRVWr 3482 1U, // LSRVXr 3483 18689U, // MADDWrrr 3484 18689U, // MADDXrrr 3485 1041U, // MLAv16i8 3486 1297U, // MLAv2i32 3487 27665U, // MLAv2i32_indexed 3488 1553U, // MLAv4i16 3489 28945U, // MLAv4i16_indexed 3490 529U, // MLAv4i32 3491 27665U, // MLAv4i32_indexed 3492 785U, // MLAv8i16 3493 28945U, // MLAv8i16_indexed 3494 1809U, // MLAv8i8 3495 1041U, // MLSv16i8 3496 1297U, // MLSv2i32 3497 27665U, // MLSv2i32_indexed 3498 1553U, // MLSv4i16 3499 28945U, // MLSv4i16_indexed 3500 529U, // MLSv4i32 3501 27665U, // MLSv4i32_indexed 3502 785U, // MLSv8i16 3503 28945U, // MLSv8i16_indexed 3504 1809U, // MLSv8i8 3505 0U, // MOVID 3506 0U, // MOVIv16b_ns 3507 0U, // MOVIv2d_ns 3508 4U, // MOVIv2i32 3509 4U, // MOVIv2s_msl 3510 4U, // MOVIv4i16 3511 4U, // MOVIv4i32 3512 4U, // MOVIv4s_msl 3513 0U, // MOVIv8b_ns 3514 4U, // MOVIv8i16 3515 0U, // MOVKWi 3516 0U, // MOVKXi 3517 4U, // MOVNWi 3518 4U, // MOVNXi 3519 4U, // MOVZWi 3520 4U, // MOVZXi 3521 0U, // MOVaddr 3522 0U, // MOVaddrBA 3523 0U, // MOVaddrCP 3524 0U, // MOVaddrEXT 3525 0U, // MOVaddrJT 3526 0U, // MOVaddrTLS 3527 0U, // MOVi32imm 3528 0U, // MOVi64imm 3529 0U, // MRS 3530 0U, // MSR 3531 0U, // MSRpstate 3532 18689U, // MSUBWrrr 3533 18689U, // MSUBXrrr 3534 1033U, // MULv16i8 3535 1289U, // MULv2i32 3536 35849U, // MULv2i32_indexed 3537 1545U, // MULv4i16 3538 37129U, // MULv4i16_indexed 3539 521U, // MULv4i32 3540 35849U, // MULv4i32_indexed 3541 777U, // MULv8i16 3542 37129U, // MULv8i16_indexed 3543 1801U, // MULv8i8 3544 4U, // MVNIv2i32 3545 4U, // MVNIv2s_msl 3546 4U, // MVNIv4i16 3547 4U, // MVNIv4i32 3548 4U, // MVNIv4s_msl 3549 4U, // MVNIv8i16 3550 0U, // NEGv16i8 3551 0U, // NEGv1i64 3552 0U, // NEGv2i32 3553 0U, // NEGv2i64 3554 0U, // NEGv4i16 3555 0U, // NEGv4i32 3556 0U, // NEGv8i16 3557 0U, // NEGv8i8 3558 0U, // NOTv16i8 3559 0U, // NOTv8i8 3560 0U, // ORNWrr 3561 33U, // ORNWrs 3562 0U, // ORNXrr 3563 33U, // ORNXrs 3564 1033U, // ORNv16i8 3565 1801U, // ORNv8i8 3566 49U, // ORRWri 3567 0U, // ORRWrr 3568 33U, // ORRWrs 3569 57U, // ORRXri 3570 0U, // ORRXrr 3571 33U, // ORRXrs 3572 1033U, // ORRv16i8 3573 0U, // ORRv2i32 3574 0U, // ORRv4i16 3575 0U, // ORRv4i32 3576 0U, // ORRv8i16 3577 1801U, // ORRv8i8 3578 1033U, // PMULLv16i8 3579 0U, // PMULLv1i64 3580 0U, // PMULLv2i64 3581 1801U, // PMULLv8i8 3582 1033U, // PMULv16i8 3583 1801U, // PMULv8i8 3584 0U, // PRFMl 3585 108801U, // PRFMroW 3586 116993U, // PRFMroX 3587 97U, // PRFMui 3588 3585U, // PRFUMi 3589 265U, // RADDHNv2i64_v2i32 3590 273U, // RADDHNv2i64_v4i32 3591 521U, // RADDHNv4i32_v4i16 3592 529U, // RADDHNv4i32_v8i16 3593 785U, // RADDHNv8i16_v16i8 3594 777U, // RADDHNv8i16_v8i8 3595 0U, // RBITWr 3596 0U, // RBITXr 3597 0U, // RBITv16i8 3598 0U, // RBITv8i8 3599 0U, // RET 3600 0U, // RET_ReallyLR 3601 0U, // REV16Wr 3602 0U, // REV16Xr 3603 0U, // REV16v16i8 3604 0U, // REV16v8i8 3605 0U, // REV32Xr 3606 0U, // REV32v16i8 3607 0U, // REV32v4i16 3608 0U, // REV32v8i16 3609 0U, // REV32v8i8 3610 0U, // REV64v16i8 3611 0U, // REV64v2i32 3612 0U, // REV64v4i16 3613 0U, // REV64v4i32 3614 0U, // REV64v8i16 3615 0U, // REV64v8i8 3616 0U, // REVWr 3617 0U, // REVXr 3618 1U, // RORVWr 3619 1U, // RORVXr 3620 65U, // RSHRNv16i8_shift 3621 1U, // RSHRNv2i32_shift 3622 1U, // RSHRNv4i16_shift 3623 65U, // RSHRNv4i32_shift 3624 65U, // RSHRNv8i16_shift 3625 1U, // RSHRNv8i8_shift 3626 265U, // RSUBHNv2i64_v2i32 3627 273U, // RSUBHNv2i64_v4i32 3628 521U, // RSUBHNv4i32_v4i16 3629 529U, // RSUBHNv4i32_v8i16 3630 785U, // RSUBHNv8i16_v16i8 3631 777U, // RSUBHNv8i16_v8i8 3632 1041U, // SABALv16i8_v8i16 3633 1297U, // SABALv2i32_v2i64 3634 1553U, // SABALv4i16_v4i32 3635 529U, // SABALv4i32_v2i64 3636 785U, // SABALv8i16_v4i32 3637 1809U, // SABALv8i8_v8i16 3638 1041U, // SABAv16i8 3639 1297U, // SABAv2i32 3640 1553U, // SABAv4i16 3641 529U, // SABAv4i32 3642 785U, // SABAv8i16 3643 1809U, // SABAv8i8 3644 1033U, // SABDLv16i8_v8i16 3645 1289U, // SABDLv2i32_v2i64 3646 1545U, // SABDLv4i16_v4i32 3647 521U, // SABDLv4i32_v2i64 3648 777U, // SABDLv8i16_v4i32 3649 1801U, // SABDLv8i8_v8i16 3650 1033U, // SABDv16i8 3651 1289U, // SABDv2i32 3652 1545U, // SABDv4i16 3653 521U, // SABDv4i32 3654 777U, // SABDv8i16 3655 1801U, // SABDv8i8 3656 0U, // SADALPv16i8_v8i16 3657 0U, // SADALPv2i32_v1i64 3658 0U, // SADALPv4i16_v2i32 3659 0U, // SADALPv4i32_v2i64 3660 0U, // SADALPv8i16_v4i32 3661 0U, // SADALPv8i8_v4i16 3662 0U, // SADDLPv16i8_v8i16 3663 0U, // SADDLPv2i32_v1i64 3664 0U, // SADDLPv4i16_v2i32 3665 0U, // SADDLPv4i32_v2i64 3666 0U, // SADDLPv8i16_v4i32 3667 0U, // SADDLPv8i8_v4i16 3668 0U, // SADDLVv16i8v 3669 0U, // SADDLVv4i16v 3670 0U, // SADDLVv4i32v 3671 0U, // SADDLVv8i16v 3672 0U, // SADDLVv8i8v 3673 1033U, // SADDLv16i8_v8i16 3674 1289U, // SADDLv2i32_v2i64 3675 1545U, // SADDLv4i16_v4i32 3676 521U, // SADDLv4i32_v2i64 3677 777U, // SADDLv8i16_v4i32 3678 1801U, // SADDLv8i8_v8i16 3679 1033U, // SADDWv16i8_v8i16 3680 1289U, // SADDWv2i32_v2i64 3681 1545U, // SADDWv4i16_v4i32 3682 521U, // SADDWv4i32_v2i64 3683 777U, // SADDWv8i16_v4i32 3684 1801U, // SADDWv8i8_v8i16 3685 1U, // SBCSWr 3686 1U, // SBCSXr 3687 1U, // SBCWr 3688 1U, // SBCXr 3689 18689U, // SBFMWri 3690 18689U, // SBFMXri 3691 1U, // SCVTFSWDri 3692 1U, // SCVTFSWSri 3693 1U, // SCVTFSXDri 3694 1U, // SCVTFSXSri 3695 0U, // SCVTFUWDri 3696 0U, // SCVTFUWSri 3697 0U, // SCVTFUXDri 3698 0U, // SCVTFUXSri 3699 1U, // SCVTFd 3700 1U, // SCVTFs 3701 0U, // SCVTFv1i32 3702 0U, // SCVTFv1i64 3703 0U, // SCVTFv2f32 3704 0U, // SCVTFv2f64 3705 1U, // SCVTFv2i32_shift 3706 1U, // SCVTFv2i64_shift 3707 0U, // SCVTFv4f32 3708 1U, // SCVTFv4i32_shift 3709 1U, // SDIVWr 3710 1U, // SDIVXr 3711 1U, // SDIV_IntWr 3712 1U, // SDIV_IntXr 3713 529U, // SHA1Crrr 3714 0U, // SHA1Hrr 3715 529U, // SHA1Mrrr 3716 529U, // SHA1Prrr 3717 529U, // SHA1SU0rrr 3718 0U, // SHA1SU1rr 3719 529U, // SHA256H2rrr 3720 529U, // SHA256Hrrr 3721 0U, // SHA256SU0rr 3722 529U, // SHA256SU1rrr 3723 1033U, // SHADDv16i8 3724 1289U, // SHADDv2i32 3725 1545U, // SHADDv4i16 3726 521U, // SHADDv4i32 3727 777U, // SHADDv8i16 3728 1801U, // SHADDv8i8 3729 4U, // SHLLv16i8 3730 4U, // SHLLv2i32 3731 4U, // SHLLv4i16 3732 4U, // SHLLv4i32 3733 5U, // SHLLv8i16 3734 5U, // SHLLv8i8 3735 1U, // SHLd 3736 1U, // SHLv16i8_shift 3737 1U, // SHLv2i32_shift 3738 1U, // SHLv2i64_shift 3739 1U, // SHLv4i16_shift 3740 1U, // SHLv4i32_shift 3741 1U, // SHLv8i16_shift 3742 1U, // SHLv8i8_shift 3743 65U, // SHRNv16i8_shift 3744 1U, // SHRNv2i32_shift 3745 1U, // SHRNv4i16_shift 3746 65U, // SHRNv4i32_shift 3747 65U, // SHRNv8i16_shift 3748 1U, // SHRNv8i8_shift 3749 1033U, // SHSUBv16i8 3750 1289U, // SHSUBv2i32 3751 1545U, // SHSUBv4i16 3752 521U, // SHSUBv4i32 3753 777U, // SHSUBv8i16 3754 1801U, // SHSUBv8i8 3755 65U, // SLId 3756 65U, // SLIv16i8_shift 3757 65U, // SLIv2i32_shift 3758 65U, // SLIv2i64_shift 3759 65U, // SLIv4i16_shift 3760 65U, // SLIv4i32_shift 3761 65U, // SLIv8i16_shift 3762 65U, // SLIv8i8_shift 3763 18689U, // SMADDLrrr 3764 1033U, // SMAXPv16i8 3765 1289U, // SMAXPv2i32 3766 1545U, // SMAXPv4i16 3767 521U, // SMAXPv4i32 3768 777U, // SMAXPv8i16 3769 1801U, // SMAXPv8i8 3770 0U, // SMAXVv16i8v 3771 0U, // SMAXVv4i16v 3772 0U, // SMAXVv4i32v 3773 0U, // SMAXVv8i16v 3774 0U, // SMAXVv8i8v 3775 1033U, // SMAXv16i8 3776 1289U, // SMAXv2i32 3777 1545U, // SMAXv4i16 3778 521U, // SMAXv4i32 3779 777U, // SMAXv8i16 3780 1801U, // SMAXv8i8 3781 0U, // SMC 3782 1033U, // SMINPv16i8 3783 1289U, // SMINPv2i32 3784 1545U, // SMINPv4i16 3785 521U, // SMINPv4i32 3786 777U, // SMINPv8i16 3787 1801U, // SMINPv8i8 3788 0U, // SMINVv16i8v 3789 0U, // SMINVv4i16v 3790 0U, // SMINVv4i32v 3791 0U, // SMINVv8i16v 3792 0U, // SMINVv8i8v 3793 1033U, // SMINv16i8 3794 1289U, // SMINv2i32 3795 1545U, // SMINv4i16 3796 521U, // SMINv4i32 3797 777U, // SMINv8i16 3798 1801U, // SMINv8i8 3799 1041U, // SMLALv16i8_v8i16 3800 27665U, // SMLALv2i32_indexed 3801 1297U, // SMLALv2i32_v2i64 3802 28945U, // SMLALv4i16_indexed 3803 1553U, // SMLALv4i16_v4i32 3804 27665U, // SMLALv4i32_indexed 3805 529U, // SMLALv4i32_v2i64 3806 28945U, // SMLALv8i16_indexed 3807 785U, // SMLALv8i16_v4i32 3808 1809U, // SMLALv8i8_v8i16 3809 1041U, // SMLSLv16i8_v8i16 3810 27665U, // SMLSLv2i32_indexed 3811 1297U, // SMLSLv2i32_v2i64 3812 28945U, // SMLSLv4i16_indexed 3813 1553U, // SMLSLv4i16_v4i32 3814 27665U, // SMLSLv4i32_indexed 3815 529U, // SMLSLv4i32_v2i64 3816 28945U, // SMLSLv8i16_indexed 3817 785U, // SMLSLv8i16_v4i32 3818 1809U, // SMLSLv8i8_v8i16 3819 75U, // SMOVvi16to32 3820 75U, // SMOVvi16to64 3821 75U, // SMOVvi32to64 3822 75U, // SMOVvi8to32 3823 75U, // SMOVvi8to64 3824 18689U, // SMSUBLrrr 3825 1U, // SMULHrr 3826 1033U, // SMULLv16i8_v8i16 3827 35849U, // SMULLv2i32_indexed 3828 1289U, // SMULLv2i32_v2i64 3829 37129U, // SMULLv4i16_indexed 3830 1545U, // SMULLv4i16_v4i32 3831 35849U, // SMULLv4i32_indexed 3832 521U, // SMULLv4i32_v2i64 3833 37129U, // SMULLv8i16_indexed 3834 777U, // SMULLv8i16_v4i32 3835 1801U, // SMULLv8i8_v8i16 3836 0U, // SQABSv16i8 3837 0U, // SQABSv1i16 3838 0U, // SQABSv1i32 3839 0U, // SQABSv1i64 3840 0U, // SQABSv1i8 3841 0U, // SQABSv2i32 3842 0U, // SQABSv2i64 3843 0U, // SQABSv4i16 3844 0U, // SQABSv4i32 3845 0U, // SQABSv8i16 3846 0U, // SQABSv8i8 3847 1033U, // SQADDv16i8 3848 1U, // SQADDv1i16 3849 1U, // SQADDv1i32 3850 1U, // SQADDv1i64 3851 1U, // SQADDv1i8 3852 1289U, // SQADDv2i32 3853 265U, // SQADDv2i64 3854 1545U, // SQADDv4i16 3855 521U, // SQADDv4i32 3856 777U, // SQADDv8i16 3857 1801U, // SQADDv8i8 3858 65U, // SQDMLALi16 3859 65U, // SQDMLALi32 3860 28945U, // SQDMLALv1i32_indexed 3861 27665U, // SQDMLALv1i64_indexed 3862 27665U, // SQDMLALv2i32_indexed 3863 1297U, // SQDMLALv2i32_v2i64 3864 28945U, // SQDMLALv4i16_indexed 3865 1553U, // SQDMLALv4i16_v4i32 3866 27665U, // SQDMLALv4i32_indexed 3867 529U, // SQDMLALv4i32_v2i64 3868 28945U, // SQDMLALv8i16_indexed 3869 785U, // SQDMLALv8i16_v4i32 3870 65U, // SQDMLSLi16 3871 65U, // SQDMLSLi32 3872 28945U, // SQDMLSLv1i32_indexed 3873 27665U, // SQDMLSLv1i64_indexed 3874 27665U, // SQDMLSLv2i32_indexed 3875 1297U, // SQDMLSLv2i32_v2i64 3876 28945U, // SQDMLSLv4i16_indexed 3877 1553U, // SQDMLSLv4i16_v4i32 3878 27665U, // SQDMLSLv4i32_indexed 3879 529U, // SQDMLSLv4i32_v2i64 3880 28945U, // SQDMLSLv8i16_indexed 3881 785U, // SQDMLSLv8i16_v4i32 3882 1U, // SQDMULHv1i16 3883 37129U, // SQDMULHv1i16_indexed 3884 1U, // SQDMULHv1i32 3885 35849U, // SQDMULHv1i32_indexed 3886 1289U, // SQDMULHv2i32 3887 35849U, // SQDMULHv2i32_indexed 3888 1545U, // SQDMULHv4i16 3889 37129U, // SQDMULHv4i16_indexed 3890 521U, // SQDMULHv4i32 3891 35849U, // SQDMULHv4i32_indexed 3892 777U, // SQDMULHv8i16 3893 37129U, // SQDMULHv8i16_indexed 3894 1U, // SQDMULLi16 3895 1U, // SQDMULLi32 3896 37129U, // SQDMULLv1i32_indexed 3897 35849U, // SQDMULLv1i64_indexed 3898 35849U, // SQDMULLv2i32_indexed 3899 1289U, // SQDMULLv2i32_v2i64 3900 37129U, // SQDMULLv4i16_indexed 3901 1545U, // SQDMULLv4i16_v4i32 3902 35849U, // SQDMULLv4i32_indexed 3903 521U, // SQDMULLv4i32_v2i64 3904 37129U, // SQDMULLv8i16_indexed 3905 777U, // SQDMULLv8i16_v4i32 3906 0U, // SQNEGv16i8 3907 0U, // SQNEGv1i16 3908 0U, // SQNEGv1i32 3909 0U, // SQNEGv1i64 3910 0U, // SQNEGv1i8 3911 0U, // SQNEGv2i32 3912 0U, // SQNEGv2i64 3913 0U, // SQNEGv4i16 3914 0U, // SQNEGv4i32 3915 0U, // SQNEGv8i16 3916 0U, // SQNEGv8i8 3917 1U, // SQRDMULHv1i16 3918 37129U, // SQRDMULHv1i16_indexed 3919 1U, // SQRDMULHv1i32 3920 35849U, // SQRDMULHv1i32_indexed 3921 1289U, // SQRDMULHv2i32 3922 35849U, // SQRDMULHv2i32_indexed 3923 1545U, // SQRDMULHv4i16 3924 37129U, // SQRDMULHv4i16_indexed 3925 521U, // SQRDMULHv4i32 3926 35849U, // SQRDMULHv4i32_indexed 3927 777U, // SQRDMULHv8i16 3928 37129U, // SQRDMULHv8i16_indexed 3929 1033U, // SQRSHLv16i8 3930 1U, // SQRSHLv1i16 3931 1U, // SQRSHLv1i32 3932 1U, // SQRSHLv1i64 3933 1U, // SQRSHLv1i8 3934 1289U, // SQRSHLv2i32 3935 265U, // SQRSHLv2i64 3936 1545U, // SQRSHLv4i16 3937 521U, // SQRSHLv4i32 3938 777U, // SQRSHLv8i16 3939 1801U, // SQRSHLv8i8 3940 1U, // SQRSHRNb 3941 1U, // SQRSHRNh 3942 1U, // SQRSHRNs 3943 65U, // SQRSHRNv16i8_shift 3944 1U, // SQRSHRNv2i32_shift 3945 1U, // SQRSHRNv4i16_shift 3946 65U, // SQRSHRNv4i32_shift 3947 65U, // SQRSHRNv8i16_shift 3948 1U, // SQRSHRNv8i8_shift 3949 1U, // SQRSHRUNb 3950 1U, // SQRSHRUNh 3951 1U, // SQRSHRUNs 3952 65U, // SQRSHRUNv16i8_shift 3953 1U, // SQRSHRUNv2i32_shift 3954 1U, // SQRSHRUNv4i16_shift 3955 65U, // SQRSHRUNv4i32_shift 3956 65U, // SQRSHRUNv8i16_shift 3957 1U, // SQRSHRUNv8i8_shift 3958 1U, // SQSHLUb 3959 1U, // SQSHLUd 3960 1U, // SQSHLUh 3961 1U, // SQSHLUs 3962 1U, // SQSHLUv16i8_shift 3963 1U, // SQSHLUv2i32_shift 3964 1U, // SQSHLUv2i64_shift 3965 1U, // SQSHLUv4i16_shift 3966 1U, // SQSHLUv4i32_shift 3967 1U, // SQSHLUv8i16_shift 3968 1U, // SQSHLUv8i8_shift 3969 1U, // SQSHLb 3970 1U, // SQSHLd 3971 1U, // SQSHLh 3972 1U, // SQSHLs 3973 1033U, // SQSHLv16i8 3974 1U, // SQSHLv16i8_shift 3975 1U, // SQSHLv1i16 3976 1U, // SQSHLv1i32 3977 1U, // SQSHLv1i64 3978 1U, // SQSHLv1i8 3979 1289U, // SQSHLv2i32 3980 1U, // SQSHLv2i32_shift 3981 265U, // SQSHLv2i64 3982 1U, // SQSHLv2i64_shift 3983 1545U, // SQSHLv4i16 3984 1U, // SQSHLv4i16_shift 3985 521U, // SQSHLv4i32 3986 1U, // SQSHLv4i32_shift 3987 777U, // SQSHLv8i16 3988 1U, // SQSHLv8i16_shift 3989 1801U, // SQSHLv8i8 3990 1U, // SQSHLv8i8_shift 3991 1U, // SQSHRNb 3992 1U, // SQSHRNh 3993 1U, // SQSHRNs 3994 65U, // SQSHRNv16i8_shift 3995 1U, // SQSHRNv2i32_shift 3996 1U, // SQSHRNv4i16_shift 3997 65U, // SQSHRNv4i32_shift 3998 65U, // SQSHRNv8i16_shift 3999 1U, // SQSHRNv8i8_shift 4000 1U, // SQSHRUNb 4001 1U, // SQSHRUNh 4002 1U, // SQSHRUNs 4003 65U, // SQSHRUNv16i8_shift 4004 1U, // SQSHRUNv2i32_shift 4005 1U, // SQSHRUNv4i16_shift 4006 65U, // SQSHRUNv4i32_shift 4007 65U, // SQSHRUNv8i16_shift 4008 1U, // SQSHRUNv8i8_shift 4009 1033U, // SQSUBv16i8 4010 1U, // SQSUBv1i16 4011 1U, // SQSUBv1i32 4012 1U, // SQSUBv1i64 4013 1U, // SQSUBv1i8 4014 1289U, // SQSUBv2i32 4015 265U, // SQSUBv2i64 4016 1545U, // SQSUBv4i16 4017 521U, // SQSUBv4i32 4018 777U, // SQSUBv8i16 4019 1801U, // SQSUBv8i8 4020 0U, // SQXTNv16i8 4021 0U, // SQXTNv1i16 4022 0U, // SQXTNv1i32 4023 0U, // SQXTNv1i8 4024 0U, // SQXTNv2i32 4025 0U, // SQXTNv4i16 4026 0U, // SQXTNv4i32 4027 0U, // SQXTNv8i16 4028 0U, // SQXTNv8i8 4029 0U, // SQXTUNv16i8 4030 0U, // SQXTUNv1i16 4031 0U, // SQXTUNv1i32 4032 0U, // SQXTUNv1i8 4033 0U, // SQXTUNv2i32 4034 0U, // SQXTUNv4i16 4035 0U, // SQXTUNv4i32 4036 0U, // SQXTUNv8i16 4037 0U, // SQXTUNv8i8 4038 1033U, // SRHADDv16i8 4039 1289U, // SRHADDv2i32 4040 1545U, // SRHADDv4i16 4041 521U, // SRHADDv4i32 4042 777U, // SRHADDv8i16 4043 1801U, // SRHADDv8i8 4044 65U, // SRId 4045 65U, // SRIv16i8_shift 4046 65U, // SRIv2i32_shift 4047 65U, // SRIv2i64_shift 4048 65U, // SRIv4i16_shift 4049 65U, // SRIv4i32_shift 4050 65U, // SRIv8i16_shift 4051 65U, // SRIv8i8_shift 4052 1033U, // SRSHLv16i8 4053 1U, // SRSHLv1i64 4054 1289U, // SRSHLv2i32 4055 265U, // SRSHLv2i64 4056 1545U, // SRSHLv4i16 4057 521U, // SRSHLv4i32 4058 777U, // SRSHLv8i16 4059 1801U, // SRSHLv8i8 4060 1U, // SRSHRd 4061 1U, // SRSHRv16i8_shift 4062 1U, // SRSHRv2i32_shift 4063 1U, // SRSHRv2i64_shift 4064 1U, // SRSHRv4i16_shift 4065 1U, // SRSHRv4i32_shift 4066 1U, // SRSHRv8i16_shift 4067 1U, // SRSHRv8i8_shift 4068 65U, // SRSRAd 4069 65U, // SRSRAv16i8_shift 4070 65U, // SRSRAv2i32_shift 4071 65U, // SRSRAv2i64_shift 4072 65U, // SRSRAv4i16_shift 4073 65U, // SRSRAv4i32_shift 4074 65U, // SRSRAv8i16_shift 4075 65U, // SRSRAv8i8_shift 4076 1U, // SSHLLv16i8_shift 4077 1U, // SSHLLv2i32_shift 4078 1U, // SSHLLv4i16_shift 4079 1U, // SSHLLv4i32_shift 4080 1U, // SSHLLv8i16_shift 4081 1U, // SSHLLv8i8_shift 4082 1033U, // SSHLv16i8 4083 1U, // SSHLv1i64 4084 1289U, // SSHLv2i32 4085 265U, // SSHLv2i64 4086 1545U, // SSHLv4i16 4087 521U, // SSHLv4i32 4088 777U, // SSHLv8i16 4089 1801U, // SSHLv8i8 4090 1U, // SSHRd 4091 1U, // SSHRv16i8_shift 4092 1U, // SSHRv2i32_shift 4093 1U, // SSHRv2i64_shift 4094 1U, // SSHRv4i16_shift 4095 1U, // SSHRv4i32_shift 4096 1U, // SSHRv8i16_shift 4097 1U, // SSHRv8i8_shift 4098 65U, // SSRAd 4099 65U, // SSRAv16i8_shift 4100 65U, // SSRAv2i32_shift 4101 65U, // SSRAv2i64_shift 4102 65U, // SSRAv4i16_shift 4103 65U, // SSRAv4i32_shift 4104 65U, // SSRAv8i16_shift 4105 65U, // SSRAv8i8_shift 4106 1033U, // SSUBLv16i8_v8i16 4107 1289U, // SSUBLv2i32_v2i64 4108 1545U, // SSUBLv4i16_v4i32 4109 521U, // SSUBLv4i32_v2i64 4110 777U, // SSUBLv8i16_v4i32 4111 1801U, // SSUBLv8i8_v8i16 4112 1033U, // SSUBWv16i8_v8i16 4113 1289U, // SSUBWv2i32_v2i64 4114 1545U, // SSUBWv4i16_v4i32 4115 521U, // SSUBWv4i32_v2i64 4116 777U, // SSUBWv8i16_v4i32 4117 1801U, // SSUBWv8i8_v8i16 4118 0U, // ST1Fourv16b 4119 0U, // ST1Fourv16b_POST 4120 0U, // ST1Fourv1d 4121 0U, // ST1Fourv1d_POST 4122 0U, // ST1Fourv2d 4123 0U, // ST1Fourv2d_POST 4124 0U, // ST1Fourv2s 4125 0U, // ST1Fourv2s_POST 4126 0U, // ST1Fourv4h 4127 0U, // ST1Fourv4h_POST 4128 0U, // ST1Fourv4s 4129 0U, // ST1Fourv4s_POST 4130 0U, // ST1Fourv8b 4131 0U, // ST1Fourv8b_POST 4132 0U, // ST1Fourv8h 4133 0U, // ST1Fourv8h_POST 4134 0U, // ST1Onev16b 4135 0U, // ST1Onev16b_POST 4136 0U, // ST1Onev1d 4137 0U, // ST1Onev1d_POST 4138 0U, // ST1Onev2d 4139 0U, // ST1Onev2d_POST 4140 0U, // ST1Onev2s 4141 0U, // ST1Onev2s_POST 4142 0U, // ST1Onev4h 4143 0U, // ST1Onev4h_POST 4144 0U, // ST1Onev4s 4145 0U, // ST1Onev4s_POST 4146 0U, // ST1Onev8b 4147 0U, // ST1Onev8b_POST 4148 0U, // ST1Onev8h 4149 0U, // ST1Onev8h_POST 4150 0U, // ST1Threev16b 4151 0U, // ST1Threev16b_POST 4152 0U, // ST1Threev1d 4153 0U, // ST1Threev1d_POST 4154 0U, // ST1Threev2d 4155 0U, // ST1Threev2d_POST 4156 0U, // ST1Threev2s 4157 0U, // ST1Threev2s_POST 4158 0U, // ST1Threev4h 4159 0U, // ST1Threev4h_POST 4160 0U, // ST1Threev4s 4161 0U, // ST1Threev4s_POST 4162 0U, // ST1Threev8b 4163 0U, // ST1Threev8b_POST 4164 0U, // ST1Threev8h 4165 0U, // ST1Threev8h_POST 4166 0U, // ST1Twov16b 4167 0U, // ST1Twov16b_POST 4168 0U, // ST1Twov1d 4169 0U, // ST1Twov1d_POST 4170 0U, // ST1Twov2d 4171 0U, // ST1Twov2d_POST 4172 0U, // ST1Twov2s 4173 0U, // ST1Twov2s_POST 4174 0U, // ST1Twov4h 4175 0U, // ST1Twov4h_POST 4176 0U, // ST1Twov4s 4177 0U, // ST1Twov4s_POST 4178 0U, // ST1Twov8b 4179 0U, // ST1Twov8b_POST 4180 0U, // ST1Twov8h 4181 0U, // ST1Twov8h_POST 4182 0U, // ST1i16 4183 0U, // ST1i16_POST 4184 0U, // ST1i32 4185 0U, // ST1i32_POST 4186 0U, // ST1i64 4187 0U, // ST1i64_POST 4188 0U, // ST1i8 4189 0U, // ST1i8_POST 4190 0U, // ST2Twov16b 4191 0U, // ST2Twov16b_POST 4192 0U, // ST2Twov2d 4193 0U, // ST2Twov2d_POST 4194 0U, // ST2Twov2s 4195 0U, // ST2Twov2s_POST 4196 0U, // ST2Twov4h 4197 0U, // ST2Twov4h_POST 4198 0U, // ST2Twov4s 4199 0U, // ST2Twov4s_POST 4200 0U, // ST2Twov8b 4201 0U, // ST2Twov8b_POST 4202 0U, // ST2Twov8h 4203 0U, // ST2Twov8h_POST 4204 0U, // ST2i16 4205 0U, // ST2i16_POST 4206 0U, // ST2i32 4207 0U, // ST2i32_POST 4208 0U, // ST2i64 4209 0U, // ST2i64_POST 4210 0U, // ST2i8 4211 0U, // ST2i8_POST 4212 0U, // ST3Threev16b 4213 0U, // ST3Threev16b_POST 4214 0U, // ST3Threev2d 4215 0U, // ST3Threev2d_POST 4216 0U, // ST3Threev2s 4217 0U, // ST3Threev2s_POST 4218 0U, // ST3Threev4h 4219 0U, // ST3Threev4h_POST 4220 0U, // ST3Threev4s 4221 0U, // ST3Threev4s_POST 4222 0U, // ST3Threev8b 4223 0U, // ST3Threev8b_POST 4224 0U, // ST3Threev8h 4225 0U, // ST3Threev8h_POST 4226 0U, // ST3i16 4227 0U, // ST3i16_POST 4228 0U, // ST3i32 4229 0U, // ST3i32_POST 4230 0U, // ST3i64 4231 0U, // ST3i64_POST 4232 0U, // ST3i8 4233 0U, // ST3i8_POST 4234 0U, // ST4Fourv16b 4235 0U, // ST4Fourv16b_POST 4236 0U, // ST4Fourv2d 4237 0U, // ST4Fourv2d_POST 4238 0U, // ST4Fourv2s 4239 0U, // ST4Fourv2s_POST 4240 0U, // ST4Fourv4h 4241 0U, // ST4Fourv4h_POST 4242 0U, // ST4Fourv4s 4243 0U, // ST4Fourv4s_POST 4244 0U, // ST4Fourv8b 4245 0U, // ST4Fourv8b_POST 4246 0U, // ST4Fourv8h 4247 0U, // ST4Fourv8h_POST 4248 0U, // ST4i16 4249 0U, // ST4i16_POST 4250 0U, // ST4i32 4251 0U, // ST4i32_POST 4252 0U, // ST4i64 4253 0U, // ST4i64_POST 4254 0U, // ST4i8 4255 0U, // ST4i8_POST 4256 4U, // STLRB 4257 4U, // STLRH 4258 4U, // STLRW 4259 4U, // STLRX 4260 4609U, // STLXPW 4261 4609U, // STLXPX 4262 3588U, // STLXRB 4263 3588U, // STLXRH 4264 3588U, // STLXRW 4265 3588U, // STLXRX 4266 43268U, // STNPDi 4267 51460U, // STNPQi 4268 59652U, // STNPSi 4269 59652U, // STNPWi 4270 43268U, // STNPXi 4271 43268U, // STPDi 4272 69444U, // STPDpost 4273 330052U, // STPDpre 4274 51460U, // STPQi 4275 77636U, // STPQpost 4276 338244U, // STPQpre 4277 59652U, // STPSi 4278 85828U, // STPSpost 4279 346436U, // STPSpre 4280 59652U, // STPWi 4281 85828U, // STPWpost 4282 346436U, // STPWpre 4283 43268U, // STPXi 4284 69444U, // STPXpost 4285 330052U, // STPXpre 4286 4U, // STRBBpost 4287 4161U, // STRBBpre 4288 92417U, // STRBBroW 4289 100609U, // STRBBroX 4290 89U, // STRBBui 4291 4U, // STRBpost 4292 4161U, // STRBpre 4293 92417U, // STRBroW 4294 100609U, // STRBroX 4295 89U, // STRBui 4296 4U, // STRDpost 4297 4161U, // STRDpre 4298 108801U, // STRDroW 4299 116993U, // STRDroX 4300 97U, // STRDui 4301 4U, // STRHHpost 4302 4161U, // STRHHpre 4303 125185U, // STRHHroW 4304 133377U, // STRHHroX 4305 105U, // STRHHui 4306 4U, // STRHpost 4307 4161U, // STRHpre 4308 125185U, // STRHroW 4309 133377U, // STRHroX 4310 105U, // STRHui 4311 4U, // STRQpost 4312 4161U, // STRQpre 4313 141569U, // STRQroW 4314 149761U, // STRQroX 4315 113U, // STRQui 4316 4U, // STRSpost 4317 4161U, // STRSpre 4318 157953U, // STRSroW 4319 166145U, // STRSroX 4320 121U, // STRSui 4321 4U, // STRWpost 4322 4161U, // STRWpre 4323 157953U, // STRWroW 4324 166145U, // STRWroX 4325 121U, // STRWui 4326 4U, // STRXpost 4327 4161U, // STRXpre 4328 108801U, // STRXroW 4329 116993U, // STRXroX 4330 97U, // STRXui 4331 3585U, // STTRBi 4332 3585U, // STTRHi 4333 3585U, // STTRWi 4334 3585U, // STTRXi 4335 3585U, // STURBBi 4336 3585U, // STURBi 4337 3585U, // STURDi 4338 3585U, // STURHHi 4339 3585U, // STURHi 4340 3585U, // STURQi 4341 3585U, // STURSi 4342 3585U, // STURWi 4343 3585U, // STURXi 4344 4609U, // STXPW 4345 4609U, // STXPX 4346 3588U, // STXRB 4347 3588U, // STXRH 4348 3588U, // STXRW 4349 3588U, // STXRX 4350 265U, // SUBHNv2i64_v2i32 4351 273U, // SUBHNv2i64_v4i32 4352 521U, // SUBHNv4i32_v4i16 4353 529U, // SUBHNv4i32_v8i16 4354 785U, // SUBHNv8i16_v16i8 4355 777U, // SUBHNv8i16_v8i8 4356 25U, // SUBSWri 4357 0U, // SUBSWrr 4358 33U, // SUBSWrs 4359 41U, // SUBSWrx 4360 25U, // SUBSXri 4361 0U, // SUBSXrr 4362 33U, // SUBSXrs 4363 41U, // SUBSXrx 4364 2049U, // SUBSXrx64 4365 25U, // SUBWri 4366 0U, // SUBWrr 4367 33U, // SUBWrs 4368 41U, // SUBWrx 4369 25U, // SUBXri 4370 0U, // SUBXrr 4371 33U, // SUBXrs 4372 41U, // SUBXrx 4373 2049U, // SUBXrx64 4374 1033U, // SUBv16i8 4375 1U, // SUBv1i64 4376 1289U, // SUBv2i32 4377 265U, // SUBv2i64 4378 1545U, // SUBv4i16 4379 521U, // SUBv4i32 4380 777U, // SUBv8i16 4381 1801U, // SUBv8i8 4382 0U, // SUQADDv16i8 4383 0U, // SUQADDv1i16 4384 0U, // SUQADDv1i32 4385 0U, // SUQADDv1i64 4386 0U, // SUQADDv1i8 4387 0U, // SUQADDv2i32 4388 0U, // SUQADDv2i64 4389 0U, // SUQADDv4i16 4390 0U, // SUQADDv4i32 4391 0U, // SUQADDv8i16 4392 0U, // SUQADDv8i8 4393 0U, // SVC 4394 129U, // SYSLxt 4395 0U, // SYSxt 4396 0U, // TBLv16i8Four 4397 0U, // TBLv16i8One 4398 0U, // TBLv16i8Three 4399 0U, // TBLv16i8Two 4400 0U, // TBLv8i8Four 4401 0U, // TBLv8i8One 4402 0U, // TBLv8i8Three 4403 0U, // TBLv8i8Two 4404 137U, // TBNZW 4405 137U, // TBNZX 4406 0U, // TBXv16i8Four 4407 0U, // TBXv16i8One 4408 0U, // TBXv16i8Three 4409 0U, // TBXv16i8Two 4410 0U, // TBXv8i8Four 4411 0U, // TBXv8i8One 4412 0U, // TBXv8i8Three 4413 0U, // TBXv8i8Two 4414 137U, // TBZW 4415 137U, // TBZX 4416 0U, // TCRETURNdi 4417 0U, // TCRETURNri 4418 0U, // TLSDESCCALL 4419 0U, // TLSDESC_BLR 4420 1033U, // TRN1v16i8 4421 1289U, // TRN1v2i32 4422 265U, // TRN1v2i64 4423 1545U, // TRN1v4i16 4424 521U, // TRN1v4i32 4425 777U, // TRN1v8i16 4426 1801U, // TRN1v8i8 4427 1033U, // TRN2v16i8 4428 1289U, // TRN2v2i32 4429 265U, // TRN2v2i64 4430 1545U, // TRN2v4i16 4431 521U, // TRN2v4i32 4432 777U, // TRN2v8i16 4433 1801U, // TRN2v8i8 4434 1041U, // UABALv16i8_v8i16 4435 1297U, // UABALv2i32_v2i64 4436 1553U, // UABALv4i16_v4i32 4437 529U, // UABALv4i32_v2i64 4438 785U, // UABALv8i16_v4i32 4439 1809U, // UABALv8i8_v8i16 4440 1041U, // UABAv16i8 4441 1297U, // UABAv2i32 4442 1553U, // UABAv4i16 4443 529U, // UABAv4i32 4444 785U, // UABAv8i16 4445 1809U, // UABAv8i8 4446 1033U, // UABDLv16i8_v8i16 4447 1289U, // UABDLv2i32_v2i64 4448 1545U, // UABDLv4i16_v4i32 4449 521U, // UABDLv4i32_v2i64 4450 777U, // UABDLv8i16_v4i32 4451 1801U, // UABDLv8i8_v8i16 4452 1033U, // UABDv16i8 4453 1289U, // UABDv2i32 4454 1545U, // UABDv4i16 4455 521U, // UABDv4i32 4456 777U, // UABDv8i16 4457 1801U, // UABDv8i8 4458 0U, // UADALPv16i8_v8i16 4459 0U, // UADALPv2i32_v1i64 4460 0U, // UADALPv4i16_v2i32 4461 0U, // UADALPv4i32_v2i64 4462 0U, // UADALPv8i16_v4i32 4463 0U, // UADALPv8i8_v4i16 4464 0U, // UADDLPv16i8_v8i16 4465 0U, // UADDLPv2i32_v1i64 4466 0U, // UADDLPv4i16_v2i32 4467 0U, // UADDLPv4i32_v2i64 4468 0U, // UADDLPv8i16_v4i32 4469 0U, // UADDLPv8i8_v4i16 4470 0U, // UADDLVv16i8v 4471 0U, // UADDLVv4i16v 4472 0U, // UADDLVv4i32v 4473 0U, // UADDLVv8i16v 4474 0U, // UADDLVv8i8v 4475 1033U, // UADDLv16i8_v8i16 4476 1289U, // UADDLv2i32_v2i64 4477 1545U, // UADDLv4i16_v4i32 4478 521U, // UADDLv4i32_v2i64 4479 777U, // UADDLv8i16_v4i32 4480 1801U, // UADDLv8i8_v8i16 4481 1033U, // UADDWv16i8_v8i16 4482 1289U, // UADDWv2i32_v2i64 4483 1545U, // UADDWv4i16_v4i32 4484 521U, // UADDWv4i32_v2i64 4485 777U, // UADDWv8i16_v4i32 4486 1801U, // UADDWv8i8_v8i16 4487 18689U, // UBFMWri 4488 18689U, // UBFMXri 4489 1U, // UCVTFSWDri 4490 1U, // UCVTFSWSri 4491 1U, // UCVTFSXDri 4492 1U, // UCVTFSXSri 4493 0U, // UCVTFUWDri 4494 0U, // UCVTFUWSri 4495 0U, // UCVTFUXDri 4496 0U, // UCVTFUXSri 4497 1U, // UCVTFd 4498 1U, // UCVTFs 4499 0U, // UCVTFv1i32 4500 0U, // UCVTFv1i64 4501 0U, // UCVTFv2f32 4502 0U, // UCVTFv2f64 4503 1U, // UCVTFv2i32_shift 4504 1U, // UCVTFv2i64_shift 4505 0U, // UCVTFv4f32 4506 1U, // UCVTFv4i32_shift 4507 1U, // UDIVWr 4508 1U, // UDIVXr 4509 1U, // UDIV_IntWr 4510 1U, // UDIV_IntXr 4511 1033U, // UHADDv16i8 4512 1289U, // UHADDv2i32 4513 1545U, // UHADDv4i16 4514 521U, // UHADDv4i32 4515 777U, // UHADDv8i16 4516 1801U, // UHADDv8i8 4517 1033U, // UHSUBv16i8 4518 1289U, // UHSUBv2i32 4519 1545U, // UHSUBv4i16 4520 521U, // UHSUBv4i32 4521 777U, // UHSUBv8i16 4522 1801U, // UHSUBv8i8 4523 18689U, // UMADDLrrr 4524 1033U, // UMAXPv16i8 4525 1289U, // UMAXPv2i32 4526 1545U, // UMAXPv4i16 4527 521U, // UMAXPv4i32 4528 777U, // UMAXPv8i16 4529 1801U, // UMAXPv8i8 4530 0U, // UMAXVv16i8v 4531 0U, // UMAXVv4i16v 4532 0U, // UMAXVv4i32v 4533 0U, // UMAXVv8i16v 4534 0U, // UMAXVv8i8v 4535 1033U, // UMAXv16i8 4536 1289U, // UMAXv2i32 4537 1545U, // UMAXv4i16 4538 521U, // UMAXv4i32 4539 777U, // UMAXv8i16 4540 1801U, // UMAXv8i8 4541 1033U, // UMINPv16i8 4542 1289U, // UMINPv2i32 4543 1545U, // UMINPv4i16 4544 521U, // UMINPv4i32 4545 777U, // UMINPv8i16 4546 1801U, // UMINPv8i8 4547 0U, // UMINVv16i8v 4548 0U, // UMINVv4i16v 4549 0U, // UMINVv4i32v 4550 0U, // UMINVv8i16v 4551 0U, // UMINVv8i8v 4552 1033U, // UMINv16i8 4553 1289U, // UMINv2i32 4554 1545U, // UMINv4i16 4555 521U, // UMINv4i32 4556 777U, // UMINv8i16 4557 1801U, // UMINv8i8 4558 1041U, // UMLALv16i8_v8i16 4559 27665U, // UMLALv2i32_indexed 4560 1297U, // UMLALv2i32_v2i64 4561 28945U, // UMLALv4i16_indexed 4562 1553U, // UMLALv4i16_v4i32 4563 27665U, // UMLALv4i32_indexed 4564 529U, // UMLALv4i32_v2i64 4565 28945U, // UMLALv8i16_indexed 4566 785U, // UMLALv8i16_v4i32 4567 1809U, // UMLALv8i8_v8i16 4568 1041U, // UMLSLv16i8_v8i16 4569 27665U, // UMLSLv2i32_indexed 4570 1297U, // UMLSLv2i32_v2i64 4571 28945U, // UMLSLv4i16_indexed 4572 1553U, // UMLSLv4i16_v4i32 4573 27665U, // UMLSLv4i32_indexed 4574 529U, // UMLSLv4i32_v2i64 4575 28945U, // UMLSLv8i16_indexed 4576 785U, // UMLSLv8i16_v4i32 4577 1809U, // UMLSLv8i8_v8i16 4578 75U, // UMOVvi16 4579 75U, // UMOVvi32 4580 75U, // UMOVvi64 4581 75U, // UMOVvi8 4582 18689U, // UMSUBLrrr 4583 1U, // UMULHrr 4584 1033U, // UMULLv16i8_v8i16 4585 35849U, // UMULLv2i32_indexed 4586 1289U, // UMULLv2i32_v2i64 4587 37129U, // UMULLv4i16_indexed 4588 1545U, // UMULLv4i16_v4i32 4589 35849U, // UMULLv4i32_indexed 4590 521U, // UMULLv4i32_v2i64 4591 37129U, // UMULLv8i16_indexed 4592 777U, // UMULLv8i16_v4i32 4593 1801U, // UMULLv8i8_v8i16 4594 1033U, // UQADDv16i8 4595 1U, // UQADDv1i16 4596 1U, // UQADDv1i32 4597 1U, // UQADDv1i64 4598 1U, // UQADDv1i8 4599 1289U, // UQADDv2i32 4600 265U, // UQADDv2i64 4601 1545U, // UQADDv4i16 4602 521U, // UQADDv4i32 4603 777U, // UQADDv8i16 4604 1801U, // UQADDv8i8 4605 1033U, // UQRSHLv16i8 4606 1U, // UQRSHLv1i16 4607 1U, // UQRSHLv1i32 4608 1U, // UQRSHLv1i64 4609 1U, // UQRSHLv1i8 4610 1289U, // UQRSHLv2i32 4611 265U, // UQRSHLv2i64 4612 1545U, // UQRSHLv4i16 4613 521U, // UQRSHLv4i32 4614 777U, // UQRSHLv8i16 4615 1801U, // UQRSHLv8i8 4616 1U, // UQRSHRNb 4617 1U, // UQRSHRNh 4618 1U, // UQRSHRNs 4619 65U, // UQRSHRNv16i8_shift 4620 1U, // UQRSHRNv2i32_shift 4621 1U, // UQRSHRNv4i16_shift 4622 65U, // UQRSHRNv4i32_shift 4623 65U, // UQRSHRNv8i16_shift 4624 1U, // UQRSHRNv8i8_shift 4625 1U, // UQSHLb 4626 1U, // UQSHLd 4627 1U, // UQSHLh 4628 1U, // UQSHLs 4629 1033U, // UQSHLv16i8 4630 1U, // UQSHLv16i8_shift 4631 1U, // UQSHLv1i16 4632 1U, // UQSHLv1i32 4633 1U, // UQSHLv1i64 4634 1U, // UQSHLv1i8 4635 1289U, // UQSHLv2i32 4636 1U, // UQSHLv2i32_shift 4637 265U, // UQSHLv2i64 4638 1U, // UQSHLv2i64_shift 4639 1545U, // UQSHLv4i16 4640 1U, // UQSHLv4i16_shift 4641 521U, // UQSHLv4i32 4642 1U, // UQSHLv4i32_shift 4643 777U, // UQSHLv8i16 4644 1U, // UQSHLv8i16_shift 4645 1801U, // UQSHLv8i8 4646 1U, // UQSHLv8i8_shift 4647 1U, // UQSHRNb 4648 1U, // UQSHRNh 4649 1U, // UQSHRNs 4650 65U, // UQSHRNv16i8_shift 4651 1U, // UQSHRNv2i32_shift 4652 1U, // UQSHRNv4i16_shift 4653 65U, // UQSHRNv4i32_shift 4654 65U, // UQSHRNv8i16_shift 4655 1U, // UQSHRNv8i8_shift 4656 1033U, // UQSUBv16i8 4657 1U, // UQSUBv1i16 4658 1U, // UQSUBv1i32 4659 1U, // UQSUBv1i64 4660 1U, // UQSUBv1i8 4661 1289U, // UQSUBv2i32 4662 265U, // UQSUBv2i64 4663 1545U, // UQSUBv4i16 4664 521U, // UQSUBv4i32 4665 777U, // UQSUBv8i16 4666 1801U, // UQSUBv8i8 4667 0U, // UQXTNv16i8 4668 0U, // UQXTNv1i16 4669 0U, // UQXTNv1i32 4670 0U, // UQXTNv1i8 4671 0U, // UQXTNv2i32 4672 0U, // UQXTNv4i16 4673 0U, // UQXTNv4i32 4674 0U, // UQXTNv8i16 4675 0U, // UQXTNv8i8 4676 0U, // URECPEv2i32 4677 0U, // URECPEv4i32 4678 1033U, // URHADDv16i8 4679 1289U, // URHADDv2i32 4680 1545U, // URHADDv4i16 4681 521U, // URHADDv4i32 4682 777U, // URHADDv8i16 4683 1801U, // URHADDv8i8 4684 1033U, // URSHLv16i8 4685 1U, // URSHLv1i64 4686 1289U, // URSHLv2i32 4687 265U, // URSHLv2i64 4688 1545U, // URSHLv4i16 4689 521U, // URSHLv4i32 4690 777U, // URSHLv8i16 4691 1801U, // URSHLv8i8 4692 1U, // URSHRd 4693 1U, // URSHRv16i8_shift 4694 1U, // URSHRv2i32_shift 4695 1U, // URSHRv2i64_shift 4696 1U, // URSHRv4i16_shift 4697 1U, // URSHRv4i32_shift 4698 1U, // URSHRv8i16_shift 4699 1U, // URSHRv8i8_shift 4700 0U, // URSQRTEv2i32 4701 0U, // URSQRTEv4i32 4702 65U, // URSRAd 4703 65U, // URSRAv16i8_shift 4704 65U, // URSRAv2i32_shift 4705 65U, // URSRAv2i64_shift 4706 65U, // URSRAv4i16_shift 4707 65U, // URSRAv4i32_shift 4708 65U, // URSRAv8i16_shift 4709 65U, // URSRAv8i8_shift 4710 1U, // USHLLv16i8_shift 4711 1U, // USHLLv2i32_shift 4712 1U, // USHLLv4i16_shift 4713 1U, // USHLLv4i32_shift 4714 1U, // USHLLv8i16_shift 4715 1U, // USHLLv8i8_shift 4716 1033U, // USHLv16i8 4717 1U, // USHLv1i64 4718 1289U, // USHLv2i32 4719 265U, // USHLv2i64 4720 1545U, // USHLv4i16 4721 521U, // USHLv4i32 4722 777U, // USHLv8i16 4723 1801U, // USHLv8i8 4724 1U, // USHRd 4725 1U, // USHRv16i8_shift 4726 1U, // USHRv2i32_shift 4727 1U, // USHRv2i64_shift 4728 1U, // USHRv4i16_shift 4729 1U, // USHRv4i32_shift 4730 1U, // USHRv8i16_shift 4731 1U, // USHRv8i8_shift 4732 0U, // USQADDv16i8 4733 0U, // USQADDv1i16 4734 0U, // USQADDv1i32 4735 0U, // USQADDv1i64 4736 0U, // USQADDv1i8 4737 0U, // USQADDv2i32 4738 0U, // USQADDv2i64 4739 0U, // USQADDv4i16 4740 0U, // USQADDv4i32 4741 0U, // USQADDv8i16 4742 0U, // USQADDv8i8 4743 65U, // USRAd 4744 65U, // USRAv16i8_shift 4745 65U, // USRAv2i32_shift 4746 65U, // USRAv2i64_shift 4747 65U, // USRAv4i16_shift 4748 65U, // USRAv4i32_shift 4749 65U, // USRAv8i16_shift 4750 65U, // USRAv8i8_shift 4751 1033U, // USUBLv16i8_v8i16 4752 1289U, // USUBLv2i32_v2i64 4753 1545U, // USUBLv4i16_v4i32 4754 521U, // USUBLv4i32_v2i64 4755 777U, // USUBLv8i16_v4i32 4756 1801U, // USUBLv8i8_v8i16 4757 1033U, // USUBWv16i8_v8i16 4758 1289U, // USUBWv2i32_v2i64 4759 1545U, // USUBWv4i16_v4i32 4760 521U, // USUBWv4i32_v2i64 4761 777U, // USUBWv8i16_v4i32 4762 1801U, // USUBWv8i8_v8i16 4763 1033U, // UZP1v16i8 4764 1289U, // UZP1v2i32 4765 265U, // UZP1v2i64 4766 1545U, // UZP1v4i16 4767 521U, // UZP1v4i32 4768 777U, // UZP1v8i16 4769 1801U, // UZP1v8i8 4770 1033U, // UZP2v16i8 4771 1289U, // UZP2v2i32 4772 265U, // UZP2v2i64 4773 1545U, // UZP2v4i16 4774 521U, // UZP2v4i32 4775 777U, // UZP2v8i16 4776 1801U, // UZP2v8i8 4777 0U, // XTNv16i8 4778 0U, // XTNv2i32 4779 0U, // XTNv4i16 4780 0U, // XTNv4i32 4781 0U, // XTNv8i16 4782 0U, // XTNv8i8 4783 1033U, // ZIP1v16i8 4784 1289U, // ZIP1v2i32 4785 265U, // ZIP1v2i64 4786 1545U, // ZIP1v4i16 4787 521U, // ZIP1v4i32 4788 777U, // ZIP1v8i16 4789 1801U, // ZIP1v8i8 4790 1033U, // ZIP2v16i8 4791 1289U, // ZIP2v2i32 4792 265U, // ZIP2v2i64 4793 1545U, // ZIP2v4i16 4794 521U, // ZIP2v4i32 4795 777U, // ZIP2v8i16 4796 1801U, // ZIP2v8i8 4797 0U 4798 }; 4799 4800#ifndef CAPSTONE_DIET 4801 static char AsmStrs[] = { 4802 /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', 9, 0, 4803 /* 9 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', 9, 0, 4804 /* 20 */ 'l', 'd', '1', 9, 0, 4805 /* 25 */ 't', 'r', 'n', '1', 9, 0, 4806 /* 31 */ 'z', 'i', 'p', '1', 9, 0, 4807 /* 37 */ 'u', 'z', 'p', '1', 9, 0, 4808 /* 43 */ 'd', 'c', 'p', 's', '1', 9, 0, 4809 /* 50 */ 's', 't', '1', 9, 0, 4810 /* 55 */ 's', 'h', 'a', '1', 's', 'u', '1', 9, 0, 4811 /* 64 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', 9, 0, 4812 /* 75 */ 'r', 'e', 'v', '3', '2', 9, 0, 4813 /* 82 */ 'l', 'd', '2', 9, 0, 4814 /* 87 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', 9, 0, 4815 /* 97 */ 's', 'a', 'b', 'a', 'l', '2', 9, 0, 4816 /* 105 */ 'u', 'a', 'b', 'a', 'l', '2', 9, 0, 4817 /* 113 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '2', 9, 0, 4818 /* 123 */ 's', 'm', 'l', 'a', 'l', '2', 9, 0, 4819 /* 131 */ 'u', 'm', 'l', 'a', 'l', '2', 9, 0, 4820 /* 139 */ 's', 's', 'u', 'b', 'l', '2', 9, 0, 4821 /* 147 */ 'u', 's', 'u', 'b', 'l', '2', 9, 0, 4822 /* 155 */ 's', 'a', 'b', 'd', 'l', '2', 9, 0, 4823 /* 163 */ 'u', 'a', 'b', 'd', 'l', '2', 9, 0, 4824 /* 171 */ 's', 'a', 'd', 'd', 'l', '2', 9, 0, 4825 /* 179 */ 'u', 'a', 'd', 'd', 'l', '2', 9, 0, 4826 /* 187 */ 's', 's', 'h', 'l', 'l', '2', 9, 0, 4827 /* 195 */ 'u', 's', 'h', 'l', 'l', '2', 9, 0, 4828 /* 203 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '2', 9, 0, 4829 /* 213 */ 'p', 'm', 'u', 'l', 'l', '2', 9, 0, 4830 /* 221 */ 's', 'm', 'u', 'l', 'l', '2', 9, 0, 4831 /* 229 */ 'u', 'm', 'u', 'l', 'l', '2', 9, 0, 4832 /* 237 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '2', 9, 0, 4833 /* 247 */ 's', 'm', 'l', 's', 'l', '2', 9, 0, 4834 /* 255 */ 'u', 'm', 'l', 's', 'l', '2', 9, 0, 4835 /* 263 */ 'f', 'c', 'v', 't', 'l', '2', 9, 0, 4836 /* 271 */ 'r', 's', 'u', 'b', 'h', 'n', '2', 9, 0, 4837 /* 280 */ 'r', 'a', 'd', 'd', 'h', 'n', '2', 9, 0, 4838 /* 289 */ 's', 'q', 's', 'h', 'r', 'n', '2', 9, 0, 4839 /* 298 */ 'u', 'q', 's', 'h', 'r', 'n', '2', 9, 0, 4840 /* 307 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, 4841 /* 317 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, 4842 /* 327 */ 't', 'r', 'n', '2', 9, 0, 4843 /* 333 */ 'f', 'c', 'v', 't', 'n', '2', 9, 0, 4844 /* 341 */ 's', 'q', 'x', 't', 'n', '2', 9, 0, 4845 /* 349 */ 'u', 'q', 'x', 't', 'n', '2', 9, 0, 4846 /* 357 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '2', 9, 0, 4847 /* 367 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '2', 9, 0, 4848 /* 378 */ 's', 'q', 'x', 't', 'u', 'n', '2', 9, 0, 4849 /* 387 */ 'f', 'c', 'v', 't', 'x', 'n', '2', 9, 0, 4850 /* 396 */ 'z', 'i', 'p', '2', 9, 0, 4851 /* 402 */ 'u', 'z', 'p', '2', 9, 0, 4852 /* 408 */ 'd', 'c', 'p', 's', '2', 9, 0, 4853 /* 415 */ 's', 't', '2', 9, 0, 4854 /* 420 */ 's', 's', 'u', 'b', 'w', '2', 9, 0, 4855 /* 428 */ 'u', 's', 'u', 'b', 'w', '2', 9, 0, 4856 /* 436 */ 's', 'a', 'd', 'd', 'w', '2', 9, 0, 4857 /* 444 */ 'u', 'a', 'd', 'd', 'w', '2', 9, 0, 4858 /* 452 */ 'l', 'd', '3', 9, 0, 4859 /* 457 */ 'd', 'c', 'p', 's', '3', 9, 0, 4860 /* 464 */ 's', 't', '3', 9, 0, 4861 /* 469 */ 'r', 'e', 'v', '6', '4', 9, 0, 4862 /* 476 */ 'l', 'd', '4', 9, 0, 4863 /* 481 */ 's', 't', '4', 9, 0, 4864 /* 486 */ 'r', 'e', 'v', '1', '6', 9, 0, 4865 /* 493 */ 's', 'a', 'b', 'a', 9, 0, 4866 /* 499 */ 'u', 'a', 'b', 'a', 9, 0, 4867 /* 505 */ 'f', 'm', 'l', 'a', 9, 0, 4868 /* 511 */ 's', 'r', 's', 'r', 'a', 9, 0, 4869 /* 518 */ 'u', 'r', 's', 'r', 'a', 9, 0, 4870 /* 525 */ 's', 's', 'r', 'a', 9, 0, 4871 /* 531 */ 'u', 's', 'r', 'a', 9, 0, 4872 /* 537 */ 'f', 'r', 'i', 'n', 't', 'a', 9, 0, 4873 /* 545 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, 4874 /* 553 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, 4875 /* 562 */ 'd', 'm', 'b', 9, 0, 4876 /* 567 */ 'l', 'd', 'a', 'r', 'b', 9, 0, 4877 /* 574 */ 'l', 'd', 'r', 'b', 9, 0, 4878 /* 580 */ 's', 't', 'l', 'r', 'b', 9, 0, 4879 /* 587 */ 'l', 'd', 't', 'r', 'b', 9, 0, 4880 /* 594 */ 's', 't', 'r', 'b', 9, 0, 4881 /* 600 */ 's', 't', 't', 'r', 'b', 9, 0, 4882 /* 607 */ 'l', 'd', 'u', 'r', 'b', 9, 0, 4883 /* 614 */ 's', 't', 'u', 'r', 'b', 9, 0, 4884 /* 621 */ 'l', 'd', 'a', 'x', 'r', 'b', 9, 0, 4885 /* 629 */ 'l', 'd', 'x', 'r', 'b', 9, 0, 4886 /* 636 */ 's', 't', 'l', 'x', 'r', 'b', 9, 0, 4887 /* 644 */ 's', 't', 'x', 'r', 'b', 9, 0, 4888 /* 651 */ 'd', 's', 'b', 9, 0, 4889 /* 656 */ 'i', 's', 'b', 9, 0, 4890 /* 661 */ 'l', 'd', 'r', 's', 'b', 9, 0, 4891 /* 668 */ 'l', 'd', 't', 'r', 's', 'b', 9, 0, 4892 /* 676 */ 'l', 'd', 'u', 'r', 's', 'b', 9, 0, 4893 /* 684 */ 'f', 's', 'u', 'b', 9, 0, 4894 /* 690 */ 's', 'h', 's', 'u', 'b', 9, 0, 4895 /* 697 */ 'u', 'h', 's', 'u', 'b', 9, 0, 4896 /* 704 */ 'f', 'm', 's', 'u', 'b', 9, 0, 4897 /* 711 */ 'f', 'n', 'm', 's', 'u', 'b', 9, 0, 4898 /* 719 */ 's', 'q', 's', 'u', 'b', 9, 0, 4899 /* 726 */ 'u', 'q', 's', 'u', 'b', 9, 0, 4900 /* 733 */ 's', 'h', 'a', '1', 'c', 9, 0, 4901 /* 740 */ 's', 'b', 'c', 9, 0, 4902 /* 745 */ 'a', 'd', 'c', 9, 0, 4903 /* 750 */ 'b', 'i', 'c', 9, 0, 4904 /* 755 */ 'a', 'e', 's', 'i', 'm', 'c', 9, 0, 4905 /* 763 */ 'a', 'e', 's', 'm', 'c', 9, 0, 4906 /* 770 */ 'c', 's', 'i', 'n', 'c', 9, 0, 4907 /* 777 */ 'h', 'v', 'c', 9, 0, 4908 /* 782 */ 's', 'v', 'c', 9, 0, 4909 /* 787 */ 'f', 'a', 'b', 'd', 9, 0, 4910 /* 793 */ 's', 'a', 'b', 'd', 9, 0, 4911 /* 799 */ 'u', 'a', 'b', 'd', 9, 0, 4912 /* 805 */ 'f', 'a', 'd', 'd', 9, 0, 4913 /* 811 */ 's', 'r', 'h', 'a', 'd', 'd', 9, 0, 4914 /* 819 */ 'u', 'r', 'h', 'a', 'd', 'd', 9, 0, 4915 /* 827 */ 's', 'h', 'a', 'd', 'd', 9, 0, 4916 /* 834 */ 'u', 'h', 'a', 'd', 'd', 9, 0, 4917 /* 841 */ 'f', 'm', 'a', 'd', 'd', 9, 0, 4918 /* 848 */ 'f', 'n', 'm', 'a', 'd', 'd', 9, 0, 4919 /* 856 */ 'u', 's', 'q', 'a', 'd', 'd', 9, 0, 4920 /* 864 */ 's', 'u', 'q', 'a', 'd', 'd', 9, 0, 4921 /* 872 */ 'a', 'n', 'd', 9, 0, 4922 /* 877 */ 'a', 'e', 's', 'd', 9, 0, 4923 /* 883 */ 'f', 'a', 'c', 'g', 'e', 9, 0, 4924 /* 890 */ 'f', 'c', 'm', 'g', 'e', 9, 0, 4925 /* 897 */ 'f', 'c', 'm', 'l', 'e', 9, 0, 4926 /* 904 */ 'f', 'r', 'e', 'c', 'p', 'e', 9, 0, 4927 /* 912 */ 'u', 'r', 'e', 'c', 'p', 'e', 9, 0, 4928 /* 920 */ 'f', 'c', 'c', 'm', 'p', 'e', 9, 0, 4929 /* 928 */ 'f', 'c', 'm', 'p', 'e', 9, 0, 4930 /* 935 */ 'a', 'e', 's', 'e', 9, 0, 4931 /* 941 */ 'f', 'r', 's', 'q', 'r', 't', 'e', 9, 0, 4932 /* 950 */ 'u', 'r', 's', 'q', 'r', 't', 'e', 9, 0, 4933 /* 959 */ 'b', 'i', 'f', 9, 0, 4934 /* 964 */ 's', 'c', 'v', 't', 'f', 9, 0, 4935 /* 971 */ 'u', 'c', 'v', 't', 'f', 9, 0, 4936 /* 978 */ 'f', 'n', 'e', 'g', 9, 0, 4937 /* 984 */ 's', 'q', 'n', 'e', 'g', 9, 0, 4938 /* 991 */ 'c', 's', 'n', 'e', 'g', 9, 0, 4939 /* 998 */ 's', 'h', 'a', '1', 'h', 9, 0, 4940 /* 1005 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, 4941 /* 1013 */ 's', 'h', 'a', '2', '5', '6', 'h', 9, 0, 4942 /* 1022 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, 4943 /* 1031 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', 9, 0, 4944 /* 1040 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 9, 0, 4945 /* 1050 */ 's', 'm', 'u', 'l', 'h', 9, 0, 4946 /* 1057 */ 'u', 'm', 'u', 'l', 'h', 9, 0, 4947 /* 1064 */ 'l', 'd', 'a', 'r', 'h', 9, 0, 4948 /* 1071 */ 'l', 'd', 'r', 'h', 9, 0, 4949 /* 1077 */ 's', 't', 'l', 'r', 'h', 9, 0, 4950 /* 1084 */ 'l', 'd', 't', 'r', 'h', 9, 0, 4951 /* 1091 */ 's', 't', 'r', 'h', 9, 0, 4952 /* 1097 */ 's', 't', 't', 'r', 'h', 9, 0, 4953 /* 1104 */ 'l', 'd', 'u', 'r', 'h', 9, 0, 4954 /* 1111 */ 's', 't', 'u', 'r', 'h', 9, 0, 4955 /* 1118 */ 'l', 'd', 'a', 'x', 'r', 'h', 9, 0, 4956 /* 1126 */ 'l', 'd', 'x', 'r', 'h', 9, 0, 4957 /* 1133 */ 's', 't', 'l', 'x', 'r', 'h', 9, 0, 4958 /* 1141 */ 's', 't', 'x', 'r', 'h', 9, 0, 4959 /* 1148 */ 'l', 'd', 'r', 's', 'h', 9, 0, 4960 /* 1155 */ 'l', 'd', 't', 'r', 's', 'h', 9, 0, 4961 /* 1163 */ 'l', 'd', 'u', 'r', 's', 'h', 9, 0, 4962 /* 1171 */ 'c', 'm', 'h', 'i', 9, 0, 4963 /* 1177 */ 's', 'l', 'i', 9, 0, 4964 /* 1182 */ 'm', 'v', 'n', 'i', 9, 0, 4965 /* 1188 */ 's', 'r', 'i', 9, 0, 4966 /* 1193 */ 'f', 'r', 'i', 'n', 't', 'i', 9, 0, 4967 /* 1201 */ 'm', 'o', 'v', 'i', 9, 0, 4968 /* 1207 */ 'b', 'r', 'k', 9, 0, 4969 /* 1212 */ 'm', 'o', 'v', 'k', 9, 0, 4970 /* 1218 */ 's', 'a', 'b', 'a', 'l', 9, 0, 4971 /* 1225 */ 'u', 'a', 'b', 'a', 'l', 9, 0, 4972 /* 1232 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 9, 0, 4973 /* 1241 */ 's', 'm', 'l', 'a', 'l', 9, 0, 4974 /* 1248 */ 'u', 'm', 'l', 'a', 'l', 9, 0, 4975 /* 1255 */ 't', 'b', 'l', 9, 0, 4976 /* 1260 */ 's', 'm', 's', 'u', 'b', 'l', 9, 0, 4977 /* 1268 */ 'u', 'm', 's', 'u', 'b', 'l', 9, 0, 4978 /* 1276 */ 's', 's', 'u', 'b', 'l', 9, 0, 4979 /* 1283 */ 'u', 's', 'u', 'b', 'l', 9, 0, 4980 /* 1290 */ 's', 'a', 'b', 'd', 'l', 9, 0, 4981 /* 1297 */ 'u', 'a', 'b', 'd', 'l', 9, 0, 4982 /* 1304 */ 's', 'm', 'a', 'd', 'd', 'l', 9, 0, 4983 /* 1312 */ 'u', 'm', 'a', 'd', 'd', 'l', 9, 0, 4984 /* 1320 */ 's', 'a', 'd', 'd', 'l', 9, 0, 4985 /* 1327 */ 'u', 'a', 'd', 'd', 'l', 9, 0, 4986 /* 1334 */ 'f', 'c', 's', 'e', 'l', 9, 0, 4987 /* 1341 */ 's', 'q', 's', 'h', 'l', 9, 0, 4988 /* 1348 */ 'u', 'q', 's', 'h', 'l', 9, 0, 4989 /* 1355 */ 's', 'q', 'r', 's', 'h', 'l', 9, 0, 4990 /* 1363 */ 'u', 'q', 'r', 's', 'h', 'l', 9, 0, 4991 /* 1371 */ 's', 'r', 's', 'h', 'l', 9, 0, 4992 /* 1378 */ 'u', 'r', 's', 'h', 'l', 9, 0, 4993 /* 1385 */ 's', 's', 'h', 'l', 9, 0, 4994 /* 1391 */ 'u', 's', 'h', 'l', 9, 0, 4995 /* 1397 */ 's', 's', 'h', 'l', 'l', 9, 0, 4996 /* 1404 */ 'u', 's', 'h', 'l', 'l', 9, 0, 4997 /* 1411 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 9, 0, 4998 /* 1420 */ 'p', 'm', 'u', 'l', 'l', 9, 0, 4999 /* 1427 */ 's', 'm', 'u', 'l', 'l', 9, 0, 5000 /* 1434 */ 'u', 'm', 'u', 'l', 'l', 9, 0, 5001 /* 1441 */ 'b', 's', 'l', 9, 0, 5002 /* 1446 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 9, 0, 5003 /* 1455 */ 's', 'm', 'l', 's', 'l', 9, 0, 5004 /* 1462 */ 'u', 'm', 'l', 's', 'l', 9, 0, 5005 /* 1469 */ 's', 'y', 's', 'l', 9, 0, 5006 /* 1475 */ 'f', 'c', 'v', 't', 'l', 9, 0, 5007 /* 1482 */ 'f', 'm', 'u', 'l', 9, 0, 5008 /* 1488 */ 'f', 'n', 'm', 'u', 'l', 9, 0, 5009 /* 1495 */ 'p', 'm', 'u', 'l', 9, 0, 5010 /* 1501 */ 's', 'h', 'a', '1', 'm', 9, 0, 5011 /* 1508 */ 's', 'b', 'f', 'm', 9, 0, 5012 /* 1514 */ 'u', 'b', 'f', 'm', 9, 0, 5013 /* 1520 */ 'p', 'r', 'f', 'm', 9, 0, 5014 /* 1526 */ 'f', 'm', 'i', 'n', 'n', 'm', 9, 0, 5015 /* 1534 */ 'f', 'm', 'a', 'x', 'n', 'm', 9, 0, 5016 /* 1542 */ 'f', 'r', 'i', 'n', 't', 'm', 9, 0, 5017 /* 1550 */ 'p', 'r', 'f', 'u', 'm', 9, 0, 5018 /* 1557 */ 'r', 's', 'u', 'b', 'h', 'n', 9, 0, 5019 /* 1565 */ 'r', 'a', 'd', 'd', 'h', 'n', 9, 0, 5020 /* 1573 */ 'f', 'm', 'i', 'n', 9, 0, 5021 /* 1579 */ 's', 'm', 'i', 'n', 9, 0, 5022 /* 1585 */ 'u', 'm', 'i', 'n', 9, 0, 5023 /* 1591 */ 'c', 'c', 'm', 'n', 9, 0, 5024 /* 1597 */ 'e', 'o', 'n', 9, 0, 5025 /* 1602 */ 's', 'q', 's', 'h', 'r', 'n', 9, 0, 5026 /* 1610 */ 'u', 'q', 's', 'h', 'r', 'n', 9, 0, 5027 /* 1618 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, 5028 /* 1627 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, 5029 /* 1636 */ 'o', 'r', 'n', 9, 0, 5030 /* 1641 */ 'f', 'r', 'i', 'n', 't', 'n', 9, 0, 5031 /* 1649 */ 'f', 'c', 'v', 't', 'n', 9, 0, 5032 /* 1656 */ 's', 'q', 'x', 't', 'n', 9, 0, 5033 /* 1663 */ 'u', 'q', 'x', 't', 'n', 9, 0, 5034 /* 1670 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 9, 0, 5035 /* 1679 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 9, 0, 5036 /* 1689 */ 's', 'q', 'x', 't', 'u', 'n', 9, 0, 5037 /* 1697 */ 'm', 'o', 'v', 'n', 9, 0, 5038 /* 1703 */ 'f', 'c', 'v', 't', 'x', 'n', 9, 0, 5039 /* 1711 */ 's', 'h', 'a', '1', 'p', 9, 0, 5040 /* 1718 */ 'f', 'a', 'd', 'd', 'p', 9, 0, 5041 /* 1725 */ 'l', 'd', 'p', 9, 0, 5042 /* 1730 */ 's', 'a', 'd', 'a', 'l', 'p', 9, 0, 5043 /* 1738 */ 'u', 'a', 'd', 'a', 'l', 'p', 9, 0, 5044 /* 1746 */ 's', 'a', 'd', 'd', 'l', 'p', 9, 0, 5045 /* 1754 */ 'u', 'a', 'd', 'd', 'l', 'p', 9, 0, 5046 /* 1762 */ 'f', 'c', 'c', 'm', 'p', 9, 0, 5047 /* 1769 */ 'f', 'c', 'm', 'p', 9, 0, 5048 /* 1775 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 9, 0, 5049 /* 1784 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 9, 0, 5050 /* 1793 */ 'l', 'd', 'n', 'p', 9, 0, 5051 /* 1799 */ 'f', 'm', 'i', 'n', 'p', 9, 0, 5052 /* 1806 */ 's', 'm', 'i', 'n', 'p', 9, 0, 5053 /* 1813 */ 'u', 'm', 'i', 'n', 'p', 9, 0, 5054 /* 1820 */ 's', 't', 'n', 'p', 9, 0, 5055 /* 1826 */ 'a', 'd', 'r', 'p', 9, 0, 5056 /* 1832 */ 'f', 'r', 'i', 'n', 't', 'p', 9, 0, 5057 /* 1840 */ 's', 't', 'p', 9, 0, 5058 /* 1845 */ 'd', 'u', 'p', 9, 0, 5059 /* 1850 */ 'l', 'd', 'a', 'x', 'p', 9, 0, 5060 /* 1857 */ 'f', 'm', 'a', 'x', 'p', 9, 0, 5061 /* 1864 */ 's', 'm', 'a', 'x', 'p', 9, 0, 5062 /* 1871 */ 'u', 'm', 'a', 'x', 'p', 9, 0, 5063 /* 1878 */ 'l', 'd', 'x', 'p', 9, 0, 5064 /* 1884 */ 's', 't', 'l', 'x', 'p', 9, 0, 5065 /* 1891 */ 's', 't', 'x', 'p', 9, 0, 5066 /* 1897 */ 'f', 'c', 'm', 'e', 'q', 9, 0, 5067 /* 1904 */ 'l', 'd', '1', 'r', 9, 0, 5068 /* 1910 */ 'l', 'd', '2', 'r', 9, 0, 5069 /* 1916 */ 'l', 'd', '3', 'r', 9, 0, 5070 /* 1922 */ 'l', 'd', '4', 'r', 9, 0, 5071 /* 1928 */ 'l', 'd', 'a', 'r', 9, 0, 5072 /* 1934 */ 'b', 'r', 9, 0, 5073 /* 1938 */ 'a', 'd', 'r', 9, 0, 5074 /* 1943 */ 'l', 'd', 'r', 9, 0, 5075 /* 1948 */ 's', 'r', 's', 'h', 'r', 9, 0, 5076 /* 1955 */ 'u', 'r', 's', 'h', 'r', 9, 0, 5077 /* 1962 */ 's', 's', 'h', 'r', 9, 0, 5078 /* 1968 */ 'u', 's', 'h', 'r', 9, 0, 5079 /* 1974 */ 'b', 'l', 'r', 9, 0, 5080 /* 1979 */ 's', 't', 'l', 'r', 9, 0, 5081 /* 1985 */ 'e', 'o', 'r', 9, 0, 5082 /* 1990 */ 'r', 'o', 'r', 9, 0, 5083 /* 1995 */ 'o', 'r', 'r', 9, 0, 5084 /* 2000 */ 'a', 's', 'r', 9, 0, 5085 /* 2005 */ 'l', 's', 'r', 9, 0, 5086 /* 2010 */ 'm', 's', 'r', 9, 0, 5087 /* 2015 */ 'l', 'd', 't', 'r', 9, 0, 5088 /* 2021 */ 's', 't', 'r', 9, 0, 5089 /* 2026 */ 's', 't', 't', 'r', 9, 0, 5090 /* 2032 */ 'e', 'x', 't', 'r', 9, 0, 5091 /* 2038 */ 'l', 'd', 'u', 'r', 9, 0, 5092 /* 2044 */ 's', 't', 'u', 'r', 9, 0, 5093 /* 2050 */ 'l', 'd', 'a', 'x', 'r', 9, 0, 5094 /* 2057 */ 'l', 'd', 'x', 'r', 9, 0, 5095 /* 2063 */ 's', 't', 'l', 'x', 'r', 9, 0, 5096 /* 2070 */ 's', 't', 'x', 'r', 9, 0, 5097 /* 2076 */ 'f', 'c', 'v', 't', 'a', 's', 9, 0, 5098 /* 2084 */ 'f', 'a', 'b', 's', 9, 0, 5099 /* 2090 */ 's', 'q', 'a', 'b', 's', 9, 0, 5100 /* 2097 */ 's', 'u', 'b', 's', 9, 0, 5101 /* 2103 */ 's', 'b', 'c', 's', 9, 0, 5102 /* 2109 */ 'a', 'd', 'c', 's', 9, 0, 5103 /* 2115 */ 'b', 'i', 'c', 's', 9, 0, 5104 /* 2121 */ 'a', 'd', 'd', 's', 9, 0, 5105 /* 2127 */ 'a', 'n', 'd', 's', 9, 0, 5106 /* 2133 */ 'c', 'm', 'h', 's', 9, 0, 5107 /* 2139 */ 'c', 'l', 's', 9, 0, 5108 /* 2144 */ 'f', 'm', 'l', 's', 9, 0, 5109 /* 2150 */ 'f', 'c', 'v', 't', 'm', 's', 9, 0, 5110 /* 2158 */ 'i', 'n', 's', 9, 0, 5111 /* 2163 */ 'f', 'c', 'v', 't', 'n', 's', 9, 0, 5112 /* 2171 */ 'f', 'r', 'e', 'c', 'p', 's', 9, 0, 5113 /* 2179 */ 'f', 'c', 'v', 't', 'p', 's', 9, 0, 5114 /* 2187 */ 'm', 'r', 's', 9, 0, 5115 /* 2192 */ 'f', 'r', 's', 'q', 'r', 't', 's', 9, 0, 5116 /* 2201 */ 's', 'y', 's', 9, 0, 5117 /* 2206 */ 'f', 'c', 'v', 't', 'z', 's', 9, 0, 5118 /* 2214 */ 'r', 'e', 't', 9, 0, 5119 /* 2219 */ 'f', 'a', 'c', 'g', 't', 9, 0, 5120 /* 2226 */ 'f', 'c', 'm', 'g', 't', 9, 0, 5121 /* 2233 */ 'r', 'b', 'i', 't', 9, 0, 5122 /* 2239 */ 'h', 'l', 't', 9, 0, 5123 /* 2244 */ 'f', 'c', 'm', 'l', 't', 9, 0, 5124 /* 2251 */ 'c', 'n', 't', 9, 0, 5125 /* 2256 */ 'n', 'o', 't', 9, 0, 5126 /* 2261 */ 'f', 's', 'q', 'r', 't', 9, 0, 5127 /* 2268 */ 'c', 'm', 't', 's', 't', 9, 0, 5128 /* 2275 */ 'f', 'c', 'v', 't', 9, 0, 5129 /* 2281 */ 'e', 'x', 't', 9, 0, 5130 /* 2286 */ 'f', 'c', 'v', 't', 'a', 'u', 9, 0, 5131 /* 2294 */ 's', 'q', 's', 'h', 'l', 'u', 9, 0, 5132 /* 2302 */ 'f', 'c', 'v', 't', 'm', 'u', 9, 0, 5133 /* 2310 */ 'f', 'c', 'v', 't', 'n', 'u', 9, 0, 5134 /* 2318 */ 'f', 'c', 'v', 't', 'p', 'u', 9, 0, 5135 /* 2326 */ 'f', 'c', 'v', 't', 'z', 'u', 9, 0, 5136 /* 2334 */ 'a', 'd', 'd', 'v', 9, 0, 5137 /* 2340 */ 'r', 'e', 'v', 9, 0, 5138 /* 2345 */ 'f', 'd', 'i', 'v', 9, 0, 5139 /* 2351 */ 's', 'd', 'i', 'v', 9, 0, 5140 /* 2357 */ 'u', 'd', 'i', 'v', 9, 0, 5141 /* 2363 */ 's', 'a', 'd', 'd', 'l', 'v', 9, 0, 5142 /* 2371 */ 'u', 'a', 'd', 'd', 'l', 'v', 9, 0, 5143 /* 2379 */ 'f', 'm', 'i', 'n', 'n', 'm', 'v', 9, 0, 5144 /* 2388 */ 'f', 'm', 'a', 'x', 'n', 'm', 'v', 9, 0, 5145 /* 2397 */ 'f', 'm', 'i', 'n', 'v', 9, 0, 5146 /* 2404 */ 's', 'm', 'i', 'n', 'v', 9, 0, 5147 /* 2411 */ 'u', 'm', 'i', 'n', 'v', 9, 0, 5148 /* 2418 */ 'c', 's', 'i', 'n', 'v', 9, 0, 5149 /* 2425 */ 'f', 'm', 'o', 'v', 9, 0, 5150 /* 2431 */ 's', 'm', 'o', 'v', 9, 0, 5151 /* 2437 */ 'u', 'm', 'o', 'v', 9, 0, 5152 /* 2443 */ 'f', 'm', 'a', 'x', 'v', 9, 0, 5153 /* 2450 */ 's', 'm', 'a', 'x', 'v', 9, 0, 5154 /* 2457 */ 'u', 'm', 'a', 'x', 'v', 9, 0, 5155 /* 2464 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, 5156 /* 2472 */ 's', 's', 'u', 'b', 'w', 9, 0, 5157 /* 2479 */ 'u', 's', 'u', 'b', 'w', 9, 0, 5158 /* 2486 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, 5159 /* 2495 */ 's', 'a', 'd', 'd', 'w', 9, 0, 5160 /* 2502 */ 'u', 'a', 'd', 'd', 'w', 9, 0, 5161 /* 2509 */ 'l', 'd', 'p', 's', 'w', 9, 0, 5162 /* 2516 */ 'l', 'd', 'r', 's', 'w', 9, 0, 5163 /* 2523 */ 'l', 'd', 't', 'r', 's', 'w', 9, 0, 5164 /* 2531 */ 'l', 'd', 'u', 'r', 's', 'w', 9, 0, 5165 /* 2539 */ 'c', 'r', 'c', '3', '2', 'x', 9, 0, 5166 /* 2547 */ 'f', 'm', 'a', 'x', 9, 0, 5167 /* 2553 */ 's', 'm', 'a', 'x', 9, 0, 5168 /* 2559 */ 'u', 'm', 'a', 'x', 9, 0, 5169 /* 2565 */ 't', 'b', 'x', 9, 0, 5170 /* 2570 */ 'c', 'r', 'c', '3', '2', 'c', 'x', 9, 0, 5171 /* 2579 */ 'c', 'l', 'r', 'e', 'x', 9, 0, 5172 /* 2586 */ 'f', 'm', 'u', 'l', 'x', 9, 0, 5173 /* 2593 */ 'f', 'r', 'e', 'c', 'p', 'x', 9, 0, 5174 /* 2601 */ 'f', 'r', 'i', 'n', 't', 'x', 9, 0, 5175 /* 2609 */ 'c', 'b', 'z', 9, 0, 5176 /* 2614 */ 't', 'b', 'z', 9, 0, 5177 /* 2619 */ 'c', 'l', 'z', 9, 0, 5178 /* 2624 */ 'c', 'b', 'n', 'z', 9, 0, 5179 /* 2630 */ 't', 'b', 'n', 'z', 9, 0, 5180 /* 2636 */ 'f', 'r', 'i', 'n', 't', 'z', 9, 0, 5181 /* 2644 */ 'm', 'o', 'v', 'z', 9, 0, 5182 /* 2650 */ '.', 't', 'l', 's', 'd', 'e', 's', 'c', 'c', 'a', 'l', 'l', 32, 0, 5183 /* 2664 */ 'h', 'i', 'n', 't', 32, 0, 5184 /* 2670 */ 'b', '.', 0, 5185 /* 2673 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, 5186 /* 2686 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, 5187 /* 2693 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, 5188 /* 2703 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, 5189 /* 2718 */ 'd', 'r', 'p', 's', 0, 5190 /* 2723 */ 'e', 'r', 'e', 't', 0, 5191 }; 5192#endif 5193 5194 // Emit the opcode for the instruction. 5195 uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)]; 5196 uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)]; 5197 uint64_t Bits = (Bits2 << 32) | Bits1; 5198 // assert(Bits != 0 && "Cannot print this instruction."); 5199#ifndef CAPSTONE_DIET 5200 SStream_concat0(O, AsmStrs+(Bits & 4095)-1); 5201#endif 5202 5203 5204 // Fragment 0 encoded into 6 bits for 40 unique commands. 5205 //printf("Frag-0: %"PRIu64"\n", (Bits >> 12) & 63); 5206 switch ((Bits >> 12) & 63) { 5207 default: // unreachable. 5208 case 0: 5209 // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, DRPS, ERET 5210 return; 5211 break; 5212 case 1: 5213 // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... 5214 printVRegOperand(MI, 0, O); 5215 break; 5216 case 2: 5217 // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPv2i64p, ADDSWri, ADDSWrs, ... 5218 printOperand(MI, 0, O); 5219 break; 5220 case 3: 5221 // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... 5222 printVRegOperand(MI, 1, O); 5223 break; 5224 case 4: 5225 // B, BL 5226 printAlignedLabel(MI, 0, O); 5227 return; 5228 break; 5229 case 5: 5230 // BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, SMC, SVC 5231 printHexImm(MI, 0, O); 5232 return; 5233 break; 5234 case 6: 5235 // Bcc 5236 printCondCode(MI, 0, O); 5237 SStream_concat0(O, "\t"); 5238 printAlignedLabel(MI, 1, O); 5239 return; 5240 break; 5241 case 7: 5242 // DMB, DSB, ISB 5243 printBarrierOption(MI, 0, O); 5244 return; 5245 break; 5246 case 8: 5247 // FMLAv1i32_indexed, FMLAv1i64_indexed, FMLSv1i32_indexed, FMLSv1i64_ind... 5248 printOperand(MI, 1, O); 5249 break; 5250 case 9: 5251 // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,... 5252 printTypedVectorList(MI, 0, O, 16, 'b', MRI); 5253 SStream_concat0(O, ", ["); 5254 set_mem_access(MI, true); 5255 printOperand(MI, 1, O); 5256 SStream_concat0(O, "]"); 5257 set_mem_access(MI, false); 5258 return; 5259 break; 5260 case 10: 5261 // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L... 5262 printTypedVectorList(MI, 1, O, 16, 'b', MRI); 5263 SStream_concat0(O, ", ["); 5264 set_mem_access(MI, true); 5265 printOperand(MI, 2, O); 5266 SStream_concat0(O, "], "); 5267 set_mem_access(MI, false); 5268 break; 5269 case 11: 5270 // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv... 5271 printTypedVectorList(MI, 0, O, 1, 'd', MRI); 5272 SStream_concat0(O, ", ["); 5273 set_mem_access(MI, true); 5274 printOperand(MI, 1, O); 5275 SStream_concat0(O, "]"); 5276 set_mem_access(MI, false); 5277 return; 5278 break; 5279 case 12: 5280 // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw... 5281 printTypedVectorList(MI, 1, O, 1, 'd', MRI); 5282 SStream_concat0(O, ", ["); 5283 set_mem_access(MI, true); 5284 printOperand(MI, 2, O); 5285 SStream_concat0(O, "], "); 5286 set_mem_access(MI, false); 5287 break; 5288 case 13: 5289 // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw... 5290 printTypedVectorList(MI, 0, O, 2, 'd', MRI); 5291 SStream_concat0(O, ", ["); 5292 set_mem_access(MI, true); 5293 printOperand(MI, 1, O); 5294 SStream_concat0(O, "]"); 5295 set_mem_access(MI, false); 5296 return; 5297 break; 5298 case 14: 5299 // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw... 5300 printTypedVectorList(MI, 1, O, 2, 'd', MRI); 5301 SStream_concat0(O, ", ["); 5302 set_mem_access(MI, true); 5303 printOperand(MI, 2, O); 5304 SStream_concat0(O, "], "); 5305 set_mem_access(MI, false); 5306 break; 5307 case 15: 5308 // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw... 5309 printTypedVectorList(MI, 0, O, 2, 's', MRI); 5310 SStream_concat0(O, ", ["); 5311 set_mem_access(MI, true); 5312 printOperand(MI, 1, O); 5313 SStream_concat0(O, "]"); 5314 set_mem_access(MI, false); 5315 return; 5316 break; 5317 case 16: 5318 // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw... 5319 printTypedVectorList(MI, 1, O, 2, 's', MRI); 5320 SStream_concat0(O, ", ["); 5321 set_mem_access(MI, true); 5322 printOperand(MI, 2, O); 5323 SStream_concat0(O, "], "); 5324 set_mem_access(MI, false); 5325 break; 5326 case 17: 5327 // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw... 5328 printTypedVectorList(MI, 0, O, 4, 'h', MRI); 5329 SStream_concat0(O, ", ["); 5330 set_mem_access(MI, true); 5331 printOperand(MI, 1, O); 5332 SStream_concat0(O, "]"); 5333 set_mem_access(MI, false); 5334 return; 5335 break; 5336 case 18: 5337 // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw... 5338 printTypedVectorList(MI, 1, O, 4, 'h', MRI); 5339 SStream_concat0(O, ", ["); 5340 set_mem_access(MI, true); 5341 printOperand(MI, 2, O); 5342 SStream_concat0(O, "], "); 5343 set_mem_access(MI, false); 5344 break; 5345 case 19: 5346 // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw... 5347 printTypedVectorList(MI, 0, O, 4, 's', MRI); 5348 SStream_concat0(O, ", ["); 5349 set_mem_access(MI, true); 5350 printOperand(MI, 1, O); 5351 SStream_concat0(O, "]"); 5352 set_mem_access(MI, false); 5353 return; 5354 break; 5355 case 20: 5356 // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw... 5357 printTypedVectorList(MI, 1, O, 4, 's', MRI); 5358 SStream_concat0(O, ", ["); 5359 set_mem_access(MI, true); 5360 printOperand(MI, 2, O); 5361 SStream_concat0(O, "], "); 5362 set_mem_access(MI, false); 5363 break; 5364 case 21: 5365 // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw... 5366 printTypedVectorList(MI, 0, O, 8, 'b', MRI); 5367 SStream_concat0(O, ", ["); 5368 set_mem_access(MI, true); 5369 printOperand(MI, 1, O); 5370 SStream_concat0(O, "]"); 5371 set_mem_access(MI, false); 5372 return; 5373 break; 5374 case 22: 5375 // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw... 5376 printTypedVectorList(MI, 1, O, 8, 'b', MRI); 5377 SStream_concat0(O, ", ["); 5378 set_mem_access(MI, true); 5379 printOperand(MI, 2, O); 5380 SStream_concat0(O, "], "); 5381 set_mem_access(MI, false); 5382 break; 5383 case 23: 5384 // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw... 5385 printTypedVectorList(MI, 0, O, 8, 'h', MRI); 5386 SStream_concat0(O, ", ["); 5387 set_mem_access(MI, true); 5388 printOperand(MI, 1, O); 5389 SStream_concat0(O, "]"); 5390 set_mem_access(MI, false); 5391 return; 5392 break; 5393 case 24: 5394 // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw... 5395 printTypedVectorList(MI, 1, O, 8, 'h', MRI); 5396 SStream_concat0(O, ", ["); 5397 set_mem_access(MI, true); 5398 printOperand(MI, 2, O); 5399 SStream_concat0(O, "], "); 5400 set_mem_access(MI, false); 5401 break; 5402 case 25: 5403 // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,... 5404 printTypedVectorList(MI, 1, O, 0, 'h', MRI); 5405 printVectorIndex(MI, 2, O); 5406 SStream_concat0(O, ", ["); 5407 set_mem_access(MI, true); 5408 printOperand(MI, 3, O); 5409 break; 5410 case 26: 5411 // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST 5412 printTypedVectorList(MI, 2, O, 0, 'h', MRI); 5413 printVectorIndex(MI, 3, O); 5414 SStream_concat0(O, ", ["); 5415 set_mem_access(MI, true); 5416 printOperand(MI, 4, O); 5417 SStream_concat0(O, "], "); 5418 set_mem_access(MI, false); 5419 break; 5420 case 27: 5421 // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,... 5422 printTypedVectorList(MI, 1, O, 0, 's', MRI); 5423 printVectorIndex(MI, 2, O); 5424 SStream_concat0(O, ", ["); 5425 set_mem_access(MI, true); 5426 printOperand(MI, 3, O); 5427 break; 5428 case 28: 5429 // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST 5430 printTypedVectorList(MI, 2, O, 0, 's', MRI); 5431 printVectorIndex(MI, 3, O); 5432 SStream_concat0(O, ", ["); 5433 set_mem_access(MI, true); 5434 printOperand(MI, 4, O); 5435 SStream_concat0(O, "], "); 5436 set_mem_access(MI, false); 5437 break; 5438 case 29: 5439 // LD1i64, LD2i64, LD3i64, LD4i64, ST1i64_POST, ST2i64_POST, ST3i64_POST,... 5440 printTypedVectorList(MI, 1, O, 0, 'd', MRI); 5441 printVectorIndex(MI, 2, O); 5442 SStream_concat0(O, ", ["); 5443 set_mem_access(MI, true); 5444 printOperand(MI, 3, O); 5445 break; 5446 case 30: 5447 // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST 5448 printTypedVectorList(MI, 2, O, 0, 'd', MRI); 5449 printVectorIndex(MI, 3, O); 5450 SStream_concat0(O, ", ["); 5451 set_mem_access(MI, true); 5452 printOperand(MI, 4, O); 5453 SStream_concat0(O, "], "); 5454 set_mem_access(MI, false); 5455 break; 5456 case 31: 5457 // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_... 5458 printTypedVectorList(MI, 1, O, 0, 'b', MRI); 5459 printVectorIndex(MI, 2, O); 5460 SStream_concat0(O, ", ["); 5461 set_mem_access(MI, true); 5462 printOperand(MI, 3, O); 5463 break; 5464 case 32: 5465 // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST 5466 printTypedVectorList(MI, 2, O, 0, 'b', MRI); 5467 printVectorIndex(MI, 3, O); 5468 SStream_concat0(O, ", ["); 5469 set_mem_access(MI, true); 5470 printOperand(MI, 4, O); 5471 SStream_concat0(O, "], "); 5472 set_mem_access(MI, false); 5473 break; 5474 case 33: 5475 // MSR 5476 printMSRSystemRegister(MI, 0, O); 5477 SStream_concat0(O, ", "); 5478 printOperand(MI, 1, O); 5479 return; 5480 break; 5481 case 34: 5482 // MSRpstate 5483 printSystemPStateField(MI, 0, O); 5484 SStream_concat0(O, ", "); 5485 printOperand(MI, 1, O); 5486 return; 5487 break; 5488 case 35: 5489 // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi 5490 printPrefetchOp(MI, 0, O); 5491 break; 5492 case 36: 5493 // ST1i16, ST2i16, ST3i16, ST4i16 5494 printTypedVectorList(MI, 0, O, 0, 'h', MRI); 5495 printVectorIndex(MI, 1, O); 5496 SStream_concat0(O, ", ["); 5497 set_mem_access(MI, true); 5498 printOperand(MI, 2, O); 5499 SStream_concat0(O, "]"); 5500 set_mem_access(MI, false); 5501 return; 5502 break; 5503 case 37: 5504 // ST1i32, ST2i32, ST3i32, ST4i32 5505 printTypedVectorList(MI, 0, O, 0, 's', MRI); 5506 printVectorIndex(MI, 1, O); 5507 SStream_concat0(O, ", ["); 5508 set_mem_access(MI, true); 5509 printOperand(MI, 2, O); 5510 SStream_concat0(O, "]"); 5511 set_mem_access(MI, false); 5512 return; 5513 break; 5514 case 38: 5515 // ST1i64, ST2i64, ST3i64, ST4i64 5516 printTypedVectorList(MI, 0, O, 0, 'd', MRI); 5517 printVectorIndex(MI, 1, O); 5518 SStream_concat0(O, ", ["); 5519 set_mem_access(MI, true); 5520 printOperand(MI, 2, O); 5521 SStream_concat0(O, "]"); 5522 set_mem_access(MI, false); 5523 return; 5524 break; 5525 case 39: 5526 // ST1i8, ST2i8, ST3i8, ST4i8 5527 printTypedVectorList(MI, 0, O, 0, 'b', MRI); 5528 printVectorIndex(MI, 1, O); 5529 SStream_concat0(O, ", ["); 5530 set_mem_access(MI, true); 5531 printOperand(MI, 2, O); 5532 SStream_concat0(O, "]"); 5533 set_mem_access(MI, false); 5534 return; 5535 break; 5536 } 5537 5538 5539 // Fragment 1 encoded into 6 bits for 41 unique commands. 5540 //printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 63); 5541 switch ((Bits >> 18) & 63) { 5542 default: // unreachable. 5543 case 0: 5544 // ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDv16i8, AESDrr, AESErr, AESIM... 5545 SStream_concat0(O, ".16b, "); 5546 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); 5547 break; 5548 case 1: 5549 // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPv2i64p, ADDSWri, ADDSWrs, ... 5550 SStream_concat0(O, ", "); 5551 break; 5552 case 2: 5553 // ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BICv2i32, CLSv2i32, C... 5554 SStream_concat0(O, ".2s, "); 5555 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); 5556 break; 5557 case 3: 5558 // ABSv2i64, ADDPv2i64, ADDv2i64, CMEQv2i64, CMEQv2i64rz, CMGEv2i64, CMGE... 5559 SStream_concat0(O, ".2d, "); 5560 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 5561 break; 5562 case 4: 5563 // ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BICv4i16, CLSv4i16, C... 5564 SStream_concat0(O, ".4h, "); 5565 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); 5566 break; 5567 case 5: 5568 // ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDv4i32, BICv4i32, CLSv4i32, C... 5569 SStream_concat0(O, ".4s, "); 5570 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); 5571 break; 5572 case 6: 5573 // ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDv8i16, BICv8i16, CLSv8i16, C... 5574 SStream_concat0(O, ".8h, "); 5575 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); 5576 break; 5577 case 7: 5578 // ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8... 5579 SStream_concat0(O, ".8b, "); 5580 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); 5581 break; 5582 case 8: 5583 // BLR, BR, CLREX, RET, TLSDESCCALL 5584 return; 5585 break; 5586 case 9: 5587 // FCMPDri, FCMPEDri, FCMPESri, FCMPSri 5588 SStream_concat0(O, ", #0.0"); 5589 arm64_op_addFP(MI, 0.0); 5590 return; 5591 break; 5592 case 10: 5593 // FMOVXDHighr, INSvi64gpr, INSvi64lane 5594 SStream_concat0(O, ".d"); 5595 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D); 5596 printVectorIndex(MI, 2, O); 5597 SStream_concat0(O, ", "); 5598 break; 5599 case 11: 5600 // INSvi16gpr, INSvi16lane 5601 SStream_concat0(O, ".h"); 5602 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H); 5603 printVectorIndex(MI, 2, O); 5604 SStream_concat0(O, ", "); 5605 break; 5606 case 12: 5607 // INSvi32gpr, INSvi32lane 5608 SStream_concat0(O, ".s"); 5609 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S); 5610 printVectorIndex(MI, 2, O); 5611 SStream_concat0(O, ", "); 5612 break; 5613 case 13: 5614 // INSvi8gpr, INSvi8lane 5615 SStream_concat0(O, ".b"); 5616 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_B); 5617 printVectorIndex(MI, 2, O); 5618 SStream_concat0(O, ", "); 5619 break; 5620 case 14: 5621 // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L... 5622 printPostIncOperand2(MI, 3, O, 64); 5623 return; 5624 break; 5625 case 15: 5626 // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD... 5627 printPostIncOperand2(MI, 3, O, 32); 5628 return; 5629 break; 5630 case 16: 5631 // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw... 5632 printPostIncOperand2(MI, 3, O, 16); 5633 return; 5634 break; 5635 case 17: 5636 // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1... 5637 printPostIncOperand2(MI, 3, O, 8); 5638 return; 5639 break; 5640 case 18: 5641 // LD1Rv16b_POST, LD1Rv8b_POST 5642 printPostIncOperand2(MI, 3, O, 1); 5643 return; 5644 break; 5645 case 19: 5646 // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,... 5647 printPostIncOperand2(MI, 3, O, 4); 5648 return; 5649 break; 5650 case 20: 5651 // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST 5652 printPostIncOperand2(MI, 3, O, 2); 5653 return; 5654 break; 5655 case 21: 5656 // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS... 5657 printPostIncOperand2(MI, 3, O, 48); 5658 return; 5659 break; 5660 case 22: 5661 // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST... 5662 printPostIncOperand2(MI, 3, O, 24); 5663 return; 5664 break; 5665 case 23: 5666 // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ... 5667 SStream_concat0(O, "]"); 5668 set_mem_access(MI, false); 5669 return; 5670 break; 5671 case 24: 5672 // LD1i16_POST, LD2i8_POST 5673 printPostIncOperand2(MI, 5, O, 2); 5674 return; 5675 break; 5676 case 25: 5677 // LD1i32_POST, LD2i16_POST, LD4i8_POST 5678 printPostIncOperand2(MI, 5, O, 4); 5679 return; 5680 break; 5681 case 26: 5682 // LD1i64_POST, LD2i32_POST, LD4i16_POST 5683 printPostIncOperand2(MI, 5, O, 8); 5684 return; 5685 break; 5686 case 27: 5687 // LD1i8_POST 5688 printPostIncOperand2(MI, 5, O, 1); 5689 return; 5690 break; 5691 case 28: 5692 // LD2i64_POST, LD4i32_POST 5693 printPostIncOperand2(MI, 5, O, 16); 5694 return; 5695 break; 5696 case 29: 5697 // LD3Rv16b_POST, LD3Rv8b_POST 5698 printPostIncOperand2(MI, 3, O, 3); 5699 return; 5700 break; 5701 case 30: 5702 // LD3Rv2s_POST, LD3Rv4s_POST 5703 printPostIncOperand2(MI, 3, O, 12); 5704 return; 5705 break; 5706 case 31: 5707 // LD3Rv4h_POST, LD3Rv8h_POST 5708 printPostIncOperand2(MI, 3, O, 6); 5709 return; 5710 break; 5711 case 32: 5712 // LD3i16_POST 5713 printPostIncOperand2(MI, 5, O, 6); 5714 return; 5715 break; 5716 case 33: 5717 // LD3i32_POST 5718 printPostIncOperand2(MI, 5, O, 12); 5719 return; 5720 break; 5721 case 34: 5722 // LD3i64_POST 5723 printPostIncOperand2(MI, 5, O, 24); 5724 return; 5725 break; 5726 case 35: 5727 // LD3i8_POST 5728 printPostIncOperand2(MI, 5, O, 3); 5729 return; 5730 break; 5731 case 36: 5732 // LD4i64_POST 5733 printPostIncOperand2(MI, 5, O, 32); 5734 return; 5735 break; 5736 case 37: 5737 // LDARB, LDARH, LDARW, LDARX, LDAXRB, LDAXRH, LDAXRW, LDAXRX, LDRBBpost,... 5738 SStream_concat0(O, ", ["); 5739 set_mem_access(MI, true); 5740 break; 5741 case 38: 5742 // PMULLv1i64, PMULLv2i64 5743 SStream_concat0(O, ".1q, "); 5744 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1Q); 5745 printVRegOperand(MI, 1, O); 5746 break; 5747 case 39: 5748 // SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v... 5749 SStream_concat0(O, ".1d, "); 5750 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); 5751 break; 5752 case 40: 5753 // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32... 5754 SStream_concat0(O, "], "); 5755 set_mem_access(MI, false); 5756 break; 5757 } 5758 5759 5760 // Fragment 2 encoded into 5 bits for 28 unique commands. 5761 //printf("Frag-2: %"PRIu64"\n", (Bits >> 24) & 31); 5762 switch ((Bits >> 24) & 31) { 5763 default: // unreachable. 5764 case 0: 5765 // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... 5766 printVRegOperand(MI, 1, O); 5767 break; 5768 case 1: 5769 // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSWri, ADDSWrs, ADDSWrx, ADD... 5770 printOperand(MI, 1, O); 5771 break; 5772 case 2: 5773 // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... 5774 printVRegOperand(MI, 2, O); 5775 break; 5776 case 3: 5777 // ADRP 5778 printAdrpLabel(MI, 1, O); 5779 return; 5780 break; 5781 case 4: 5782 // BFMWri, BFMXri, FMLAv1i32_indexed, FMLAv1i64_indexed, FMLSv1i32_indexe... 5783 printOperand(MI, 2, O); 5784 break; 5785 case 5: 5786 // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv... 5787 printHexImm(MI, 2, O); 5788 printShifter(MI, 3, O); 5789 return; 5790 break; 5791 case 6: 5792 // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P... 5793 printAlignedLabel(MI, 1, O); 5794 return; 5795 break; 5796 case 7: 5797 // FMOVDi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_ns, FMOVv4f32_ns 5798 printFPImmOperand(MI, 1, O); 5799 return; 5800 break; 5801 case 8: 5802 // INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr 5803 printOperand(MI, 3, O); 5804 return; 5805 break; 5806 case 9: 5807 // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane 5808 printVRegOperand(MI, 3, O); 5809 break; 5810 case 10: 5811 // MOVID, MOVIv2d_ns 5812 printSIMDType10Operand(MI, 1, O); 5813 return; 5814 break; 5815 case 11: 5816 // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl... 5817 printHexImm(MI, 1, O); 5818 break; 5819 case 12: 5820 // MRS 5821 printMRSSystemRegister(MI, 1, O); 5822 return; 5823 break; 5824 case 13: 5825 // PMULLv1i64 5826 SStream_concat0(O, ".1d, "); 5827 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); 5828 printVRegOperand(MI, 2, O); 5829 SStream_concat0(O, ".1d"); 5830 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); 5831 return; 5832 break; 5833 case 14: 5834 // PMULLv2i64 5835 SStream_concat0(O, ".2d, "); 5836 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 5837 printVRegOperand(MI, 2, O); 5838 SStream_concat0(O, ".2d"); 5839 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 5840 return; 5841 break; 5842 case 15: 5843 // ST1i16_POST, ST2i8_POST 5844 printPostIncOperand2(MI, 4, O, 2); 5845 return; 5846 break; 5847 case 16: 5848 // ST1i32_POST, ST2i16_POST, ST4i8_POST 5849 printPostIncOperand2(MI, 4, O, 4); 5850 return; 5851 break; 5852 case 17: 5853 // ST1i64_POST, ST2i32_POST, ST4i16_POST 5854 printPostIncOperand2(MI, 4, O, 8); 5855 return; 5856 break; 5857 case 18: 5858 // ST1i8_POST 5859 printPostIncOperand2(MI, 4, O, 1); 5860 return; 5861 break; 5862 case 19: 5863 // ST2i64_POST, ST4i32_POST 5864 printPostIncOperand2(MI, 4, O, 16); 5865 return; 5866 break; 5867 case 20: 5868 // ST3i16_POST 5869 printPostIncOperand2(MI, 4, O, 6); 5870 return; 5871 break; 5872 case 21: 5873 // ST3i32_POST 5874 printPostIncOperand2(MI, 4, O, 12); 5875 return; 5876 break; 5877 case 22: 5878 // ST3i64_POST 5879 printPostIncOperand2(MI, 4, O, 24); 5880 return; 5881 break; 5882 case 23: 5883 // ST3i8_POST 5884 printPostIncOperand2(MI, 4, O, 3); 5885 return; 5886 break; 5887 case 24: 5888 // ST4i64_POST 5889 printPostIncOperand2(MI, 4, O, 32); 5890 return; 5891 break; 5892 case 25: 5893 // SYSxt 5894 printSysCROperand(MI, 1, O); 5895 SStream_concat0(O, ", "); 5896 printSysCROperand(MI, 2, O); 5897 SStream_concat0(O, ", "); 5898 printOperand(MI, 3, O); 5899 SStream_concat0(O, ", "); 5900 printOperand(MI, 4, O); 5901 return; 5902 break; 5903 case 26: 5904 // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB... 5905 printTypedVectorList(MI, 1, O, 16, 'b', MRI); 5906 SStream_concat0(O, ", "); 5907 printVRegOperand(MI, 2, O); 5908 break; 5909 case 27: 5910 // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB... 5911 printTypedVectorList(MI, 2, O, 16, 'b', MRI); 5912 SStream_concat0(O, ", "); 5913 printVRegOperand(MI, 3, O); 5914 break; 5915 } 5916 5917 5918 // Fragment 3 encoded into 6 bits for 42 unique commands. 5919 //printf("Frag-3: %"PRIu64"\n", (Bits >> 29) & 63); 5920 switch ((Bits >> 29) & 63) { 5921 default: // unreachable. 5922 case 0: 5923 // ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, CLSv16i8, CLZ... 5924 SStream_concat0(O, ".16b"); 5925 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); 5926 return; 5927 break; 5928 case 1: 5929 // ABSv1i64, ADR, CLSWr, CLSXr, CLZWr, CLZXr, DUPv16i8gpr, DUPv2i32gpr, D... 5930 return; 5931 break; 5932 case 2: 5933 // ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV... 5934 SStream_concat0(O, ".2s"); 5935 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); 5936 return; 5937 break; 5938 case 3: 5939 // ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64... 5940 SStream_concat0(O, ".2d"); 5941 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 5942 return; 5943 break; 5944 case 4: 5945 // ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FCVTLv4i16, NEGv4i16, REV32v... 5946 SStream_concat0(O, ".4h"); 5947 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); 5948 return; 5949 break; 5950 case 5: 5951 // ABSv4i32, ADDVv4i32v, CLSv4i32, CLZv4i32, FABSv4f32, FCVTASv4f32, FCVT... 5952 SStream_concat0(O, ".4s"); 5953 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); 5954 return; 5955 break; 5956 case 6: 5957 // ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FCVTLv8i16, NEGv8i16, REV32v... 5958 SStream_concat0(O, ".8h"); 5959 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); 5960 return; 5961 break; 5962 case 7: 5963 // ABSv8i8, ADDVv8i8v, CLSv8i8, CLZv8i8, CNTv8i8, NEGv8i8, NOTv8i8, RBITv... 5964 SStream_concat0(O, ".8b"); 5965 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); 5966 return; 5967 break; 5968 case 8: 5969 // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSWri, ADDSWrs, ADDSWrx, ADDSXri, ADDS... 5970 SStream_concat0(O, ", "); 5971 break; 5972 case 9: 5973 // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... 5974 SStream_concat0(O, ".2d, "); 5975 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 5976 break; 5977 case 10: 5978 // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... 5979 SStream_concat0(O, ".4s, "); 5980 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); 5981 break; 5982 case 11: 5983 // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... 5984 SStream_concat0(O, ".8h, "); 5985 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); 5986 break; 5987 case 12: 5988 // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... 5989 SStream_concat0(O, ".16b, "); 5990 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); 5991 break; 5992 case 13: 5993 // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... 5994 SStream_concat0(O, ".2s, "); 5995 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); 5996 break; 5997 case 14: 5998 // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... 5999 SStream_concat0(O, ".4h, "); 6000 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); 6001 break; 6002 case 15: 6003 // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... 6004 SStream_concat0(O, ".8b, "); 6005 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); 6006 break; 6007 case 16: 6008 // CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz 6009 SStream_concat0(O, ".16b, #0"); 6010 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); 6011 arm64_op_addFP(MI, 0.0); 6012 return; 6013 break; 6014 case 17: 6015 // CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz 6016 SStream_concat0(O, ", #0"); 6017 arm64_op_addImm(MI, 0); 6018 return; 6019 break; 6020 case 18: 6021 // CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz 6022 SStream_concat0(O, ".2s, #0"); 6023 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); 6024 arm64_op_addImm(MI, 0); 6025 return; 6026 break; 6027 case 19: 6028 // CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz 6029 SStream_concat0(O, ".2d, #0"); 6030 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 6031 arm64_op_addImm(MI, 0); 6032 return; 6033 break; 6034 case 20: 6035 // CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz 6036 SStream_concat0(O, ".4h, #0"); 6037 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); 6038 arm64_op_addImm(MI, 0); 6039 return; 6040 break; 6041 case 21: 6042 // CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz 6043 SStream_concat0(O, ".4s, #0"); 6044 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); 6045 arm64_op_addImm(MI, 0); 6046 return; 6047 break; 6048 case 22: 6049 // CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz 6050 SStream_concat0(O, ".8h, #0"); 6051 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); 6052 arm64_op_addImm(MI, 0); 6053 return; 6054 break; 6055 case 23: 6056 // CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz 6057 SStream_concat0(O, ".8b, #0"); 6058 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); 6059 arm64_op_addImm(MI, 0); 6060 return; 6061 break; 6062 case 24: 6063 // CPYi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1... 6064 SStream_concat0(O, ".h"); 6065 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H); 6066 break; 6067 case 25: 6068 // CPYi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, UMOVvi3... 6069 SStream_concat0(O, ".s"); 6070 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S); 6071 break; 6072 case 26: 6073 // CPYi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64 6074 SStream_concat0(O, ".d"); 6075 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D); 6076 break; 6077 case 27: 6078 // CPYi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to64... 6079 SStream_concat0(O, ".b"); 6080 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_B); 6081 break; 6082 case 28: 6083 // FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i32rz, FCMGEv1i64rz, FCMGTv1i32rz, ... 6084 SStream_concat0(O, ", #0.0"); 6085 arm64_op_addFP(MI, 0.0); 6086 return; 6087 break; 6088 case 29: 6089 // FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz 6090 SStream_concat0(O, ".2s, #0.0"); 6091 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); 6092 arm64_op_addFP(MI, 0.0); 6093 return; 6094 break; 6095 case 30: 6096 // FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz 6097 SStream_concat0(O, ".2d, #0.0"); 6098 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 6099 arm64_op_addFP(MI, 0.0); 6100 return; 6101 break; 6102 case 31: 6103 // FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz 6104 SStream_concat0(O, ".4s, #0.0"); 6105 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); 6106 arm64_op_addFP(MI, 0.0); 6107 return; 6108 break; 6109 case 32: 6110 // LDARB, LDARH, LDARW, LDARX, LDAXRB, LDAXRH, LDAXRW, LDAXRX, LDXRB, LDX... 6111 SStream_concat0(O, "]"); 6112 set_mem_access(MI, false); 6113 return; 6114 break; 6115 case 33: 6116 // LDAXPW, LDAXPX, LDNPDi, LDNPQi, LDNPSi, LDNPWi, LDNPXi, LDPDi, LDPDpos... 6117 SStream_concat0(O, ", ["); 6118 set_mem_access(MI, true); 6119 break; 6120 case 34: 6121 // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo... 6122 SStream_concat0(O, "], "); 6123 set_mem_access(MI, false); 6124 printOperand(MI, 3, O); 6125 return; 6126 break; 6127 case 35: 6128 // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ... 6129 printShifter(MI, 2, O); 6130 return; 6131 break; 6132 case 36: 6133 // SHLLv16i8 6134 SStream_concat0(O, ".16b, #8"); 6135 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); 6136 arm64_op_addImm(MI, 8); 6137 return; 6138 break; 6139 case 37: 6140 // SHLLv2i32 6141 SStream_concat0(O, ".2s, #32"); 6142 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); 6143 arm64_op_addImm(MI, 32); 6144 return; 6145 break; 6146 case 38: 6147 // SHLLv4i16 6148 SStream_concat0(O, ".4h, #16"); 6149 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); 6150 arm64_op_addImm(MI, 16); 6151 return; 6152 break; 6153 case 39: 6154 // SHLLv4i32 6155 SStream_concat0(O, ".4s, #32"); 6156 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); 6157 arm64_op_addImm(MI, 32); 6158 return; 6159 break; 6160 case 40: 6161 // SHLLv8i16 6162 SStream_concat0(O, ".8h, #16"); 6163 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); 6164 arm64_op_addImm(MI, 16); 6165 return; 6166 break; 6167 case 41: 6168 // SHLLv8i8 6169 SStream_concat0(O, ".8b, #8"); 6170 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); 6171 arm64_op_addImm(MI, 8); 6172 return; 6173 break; 6174 } 6175 6176 6177 // Fragment 4 encoded into 5 bits for 18 unique commands. 6178 //printf("Frag-4: %"PRIu64"\n", (Bits >> 35) & 31); 6179 switch ((Bits >> 35) & 31) { 6180 default: // unreachable. 6181 case 0: 6182 // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSXrx64, ADDXrx64, ADDv1i64, ASRVWr, A... 6183 printOperand(MI, 2, O); 6184 break; 6185 case 1: 6186 // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2... 6187 printVRegOperand(MI, 2, O); 6188 break; 6189 case 2: 6190 // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BITv16i8, BITv8i... 6191 printVRegOperand(MI, 3, O); 6192 break; 6193 case 3: 6194 // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri 6195 printAddSubImm(MI, 2, O); 6196 return; 6197 break; 6198 case 4: 6199 // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI... 6200 printShiftedRegister(MI, 2, O); 6201 return; 6202 break; 6203 case 5: 6204 // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx 6205 printExtendedRegister(MI, 2, O); 6206 return; 6207 break; 6208 case 6: 6209 // ANDSWri, ANDWri, EORWri, ORRWri 6210 printLogicalImm32(MI, 2, O); 6211 return; 6212 break; 6213 case 7: 6214 // ANDSXri, ANDXri, EORXri, ORRXri 6215 printLogicalImm64(MI, 2, O); 6216 return; 6217 break; 6218 case 8: 6219 // BFMWri, BFMXri, LDPDpost, LDPDpre, LDPQpost, LDPQpre, LDPSWpost, LDPSW... 6220 printOperand(MI, 3, O); 6221 break; 6222 case 9: 6223 // CPYi16, CPYi32, CPYi64, CPYi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan... 6224 printVectorIndex(MI, 2, O); 6225 return; 6226 break; 6227 case 10: 6228 // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane 6229 printVectorIndex(MI, 4, O); 6230 return; 6231 break; 6232 case 11: 6233 // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui 6234 printUImm12Offset2(MI, 2, O, 1); 6235 SStream_concat0(O, "]"); 6236 set_mem_access(MI, false); 6237 return; 6238 break; 6239 case 12: 6240 // LDRDui, LDRXui, PRFMui, STRDui, STRXui 6241 printUImm12Offset2(MI, 2, O, 8); 6242 SStream_concat0(O, "]"); 6243 set_mem_access(MI, false); 6244 return; 6245 break; 6246 case 13: 6247 // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui 6248 printUImm12Offset2(MI, 2, O, 2); 6249 SStream_concat0(O, "]"); 6250 set_mem_access(MI, false); 6251 return; 6252 break; 6253 case 14: 6254 // LDRQui, STRQui 6255 printUImm12Offset2(MI, 2, O, 16); 6256 SStream_concat0(O, "]"); 6257 set_mem_access(MI, false); 6258 return; 6259 break; 6260 case 15: 6261 // LDRSWui, LDRSui, LDRWui, STRSui, STRWui 6262 printUImm12Offset2(MI, 2, O, 4); 6263 SStream_concat0(O, "]"); 6264 set_mem_access(MI, false); 6265 return; 6266 break; 6267 case 16: 6268 // SYSLxt 6269 printSysCROperand(MI, 2, O); 6270 SStream_concat0(O, ", "); 6271 printSysCROperand(MI, 3, O); 6272 SStream_concat0(O, ", "); 6273 printOperand(MI, 4, O); 6274 return; 6275 break; 6276 case 17: 6277 // TBNZW, TBNZX, TBZW, TBZX 6278 printAlignedLabel(MI, 2, O); 6279 return; 6280 break; 6281 } 6282 6283 6284 // Fragment 5 encoded into 5 bits for 19 unique commands. 6285 //printf("Frag-5: %"PRIu64"\n", (Bits >> 40) & 31); 6286 switch ((Bits >> 40) & 31) { 6287 default: // unreachable. 6288 case 0: 6289 // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDv1i64, ASRVWr, ASRVXr, CMEQv1i64, CMG... 6290 return; 6291 break; 6292 case 1: 6293 // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... 6294 SStream_concat0(O, ".2d"); 6295 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); 6296 return; 6297 break; 6298 case 2: 6299 // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... 6300 SStream_concat0(O, ".4s"); 6301 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); 6302 return; 6303 break; 6304 case 3: 6305 // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... 6306 SStream_concat0(O, ".8h"); 6307 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); 6308 return; 6309 break; 6310 case 4: 6311 // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... 6312 SStream_concat0(O, ".16b"); 6313 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); 6314 return; 6315 break; 6316 case 5: 6317 // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... 6318 SStream_concat0(O, ".2s"); 6319 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); 6320 return; 6321 break; 6322 case 6: 6323 // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... 6324 SStream_concat0(O, ".4h"); 6325 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); 6326 return; 6327 break; 6328 case 7: 6329 // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... 6330 SStream_concat0(O, ".8b"); 6331 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); 6332 return; 6333 break; 6334 case 8: 6335 // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64 6336 printArithExtend(MI, 3, O); 6337 return; 6338 break; 6339 case 9: 6340 // BFMWri, BFMXri, CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi... 6341 SStream_concat0(O, ", "); 6342 break; 6343 case 10: 6344 // EXTv16i8 6345 SStream_concat0(O, ".16b, "); 6346 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); 6347 printOperand(MI, 3, O); 6348 return; 6349 break; 6350 case 11: 6351 // EXTv8i8 6352 SStream_concat0(O, ".8b, "); 6353 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); 6354 printOperand(MI, 3, O); 6355 return; 6356 break; 6357 case 12: 6358 // FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_indexed, FMLSv1i32_ind... 6359 SStream_concat0(O, ".s"); 6360 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S); 6361 break; 6362 case 13: 6363 // FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind... 6364 SStream_concat0(O, ".d"); 6365 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D); 6366 break; 6367 case 14: 6368 // LDAXPW, LDAXPX, LDTRBi, LDTRHi, LDTRSBWi, LDTRSBXi, LDTRSHWi, LDTRSHXi... 6369 SStream_concat0(O, "]"); 6370 set_mem_access(MI, false); 6371 return; 6372 break; 6373 case 15: 6374 // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,... 6375 SStream_concat0(O, "], "); 6376 set_mem_access(MI, false); 6377 break; 6378 case 16: 6379 // LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, LDRHpre, LDRQpre, LDRSBWpre, LDR... 6380 SStream_concat0(O, "]!"); 6381 set_mem_access(MI, false); 6382 return; 6383 break; 6384 case 17: 6385 // MLAv4i16_indexed, MLAv8i16_indexed, MLSv4i16_indexed, MLSv8i16_indexed... 6386 SStream_concat0(O, ".h"); 6387 arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H); 6388 break; 6389 case 18: 6390 // STLXPW, STLXPX, STXPW, STXPX 6391 SStream_concat0(O, ", ["); 6392 set_mem_access(MI, true); 6393 printOperand(MI, 3, O); 6394 SStream_concat0(O, "]"); 6395 set_mem_access(MI, false); 6396 return; 6397 break; 6398 } 6399 6400 6401 // Fragment 6 encoded into 5 bits for 21 unique commands. 6402 //printf("Frag-6: %"PRIu64"\n", (Bits >> 45) & 31); 6403 switch ((Bits >> 45) & 31) { 6404 default: // unreachable. 6405 case 0: 6406 // BFMWri, BFMXri 6407 printOperand(MI, 4, O); 6408 return; 6409 break; 6410 case 1: 6411 // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr... 6412 printCondCode(MI, 3, O); 6413 return; 6414 break; 6415 case 2: 6416 // EXTRWrri, EXTRXrri, FMADDDrrr, FMADDSrrr, FMSUBDrrr, FMSUBSrrr, FNMADD... 6417 printOperand(MI, 3, O); 6418 return; 6419 break; 6420 case 3: 6421 // FMLAv1i32_indexed, FMLAv1i64_indexed, FMLAv2i32_indexed, FMLAv2i64_ind... 6422 printVectorIndex(MI, 4, O); 6423 return; 6424 break; 6425 case 4: 6426 // FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32_indexed, FMULXv2i64... 6427 printVectorIndex(MI, 3, O); 6428 return; 6429 break; 6430 case 5: 6431 // LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi 6432 printImmScale(MI, 3, O, 8); 6433 SStream_concat0(O, "]"); 6434 set_mem_access(MI, false); 6435 return; 6436 break; 6437 case 6: 6438 // LDNPQi, LDPQi, STNPQi, STPQi 6439 printImmScale(MI, 3, O, 16); 6440 SStream_concat0(O, "]"); 6441 set_mem_access(MI, false); 6442 return; 6443 break; 6444 case 7: 6445 // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi 6446 printImmScale(MI, 3, O, 4); 6447 SStream_concat0(O, "]"); 6448 set_mem_access(MI, false); 6449 return; 6450 break; 6451 case 8: 6452 // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP... 6453 printImmScale(MI, 4, O, 8); 6454 break; 6455 case 9: 6456 // LDPQpost, LDPQpre, STPQpost, STPQpre 6457 printImmScale(MI, 4, O, 16); 6458 break; 6459 case 10: 6460 // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S... 6461 printImmScale(MI, 4, O, 4); 6462 break; 6463 case 11: 6464 // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW 6465 printMemExtend(MI, 3, O, 'w', 8); 6466 SStream_concat0(O, "]"); 6467 set_mem_access(MI, false); 6468 return; 6469 break; 6470 case 12: 6471 // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX 6472 printMemExtend(MI, 3, O, 'x', 8); 6473 SStream_concat0(O, "]"); 6474 set_mem_access(MI, false); 6475 return; 6476 break; 6477 case 13: 6478 // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW 6479 printMemExtend(MI, 3, O, 'w', 64); 6480 SStream_concat0(O, "]"); 6481 set_mem_access(MI, false); 6482 return; 6483 break; 6484 case 14: 6485 // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX 6486 printMemExtend(MI, 3, O, 'x', 64); 6487 SStream_concat0(O, "]"); 6488 set_mem_access(MI, false); 6489 return; 6490 break; 6491 case 15: 6492 // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW 6493 printMemExtend(MI, 3, O, 'w', 16); 6494 SStream_concat0(O, "]"); 6495 set_mem_access(MI, false); 6496 return; 6497 break; 6498 case 16: 6499 // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX 6500 printMemExtend(MI, 3, O, 'x', 16); 6501 SStream_concat0(O, "]"); 6502 set_mem_access(MI, false); 6503 return; 6504 break; 6505 case 17: 6506 // LDRQroW, STRQroW 6507 printMemExtend(MI, 3, O, 'w', 128); 6508 SStream_concat0(O, "]"); 6509 set_mem_access(MI, false); 6510 return; 6511 break; 6512 case 18: 6513 // LDRQroX, STRQroX 6514 printMemExtend(MI, 3, O, 'x', 128); 6515 SStream_concat0(O, "]"); 6516 set_mem_access(MI, false); 6517 return; 6518 break; 6519 case 19: 6520 // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW 6521 printMemExtend(MI, 3, O, 'w', 32); 6522 SStream_concat0(O, "]"); 6523 set_mem_access(MI, false); 6524 return; 6525 break; 6526 case 20: 6527 // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX 6528 printMemExtend(MI, 3, O, 'x', 32); 6529 SStream_concat0(O, "]"); 6530 set_mem_access(MI, false); 6531 return; 6532 break; 6533 } 6534 6535 6536 // Fragment 7 encoded into 1 bits for 2 unique commands. 6537 //printf("Frag-7: %"PRIu64"\n", (Bits >> 50) & 1); 6538 if ((Bits >> 50) & 1) { 6539 // LDPDpre, LDPQpre, LDPSWpre, LDPSpre, LDPWpre, LDPXpre, STPDpre, STPQpr... 6540 SStream_concat0(O, "]!"); 6541 set_mem_access(MI, false); 6542 return; 6543 } else { 6544 // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,... 6545 return; 6546 } 6547} 6548 6549 6550/// getRegisterName - This method is automatically generated by tblgen 6551/// from the register set description. This returns the assembler name 6552/// for the specified register. 6553static char *getRegisterName(unsigned RegNo, int AltIdx) 6554{ 6555 // assert(RegNo && RegNo < 420 && "Invalid register number!"); 6556 6557#ifndef CAPSTONE_DIET 6558 static char AsmStrsNoRegAltName[] = { 6559 /* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, 6560 /* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, 6561 /* 26 */ 'b', '1', '0', 0, 6562 /* 30 */ 'd', '1', '0', 0, 6563 /* 34 */ 'h', '1', '0', 0, 6564 /* 38 */ 'q', '1', '0', 0, 6565 /* 42 */ 's', '1', '0', 0, 6566 /* 46 */ 'w', '1', '0', 0, 6567 /* 50 */ 'x', '1', '0', 0, 6568 /* 54 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, 6569 /* 70 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0, 6570 /* 86 */ 'b', '2', '0', 0, 6571 /* 90 */ 'd', '2', '0', 0, 6572 /* 94 */ 'h', '2', '0', 0, 6573 /* 98 */ 'q', '2', '0', 0, 6574 /* 102 */ 's', '2', '0', 0, 6575 /* 106 */ 'w', '2', '0', 0, 6576 /* 110 */ 'x', '2', '0', 0, 6577 /* 114 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, 6578 /* 130 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0, 6579 /* 146 */ 'b', '3', '0', 0, 6580 /* 150 */ 'd', '3', '0', 0, 6581 /* 154 */ 'h', '3', '0', 0, 6582 /* 158 */ 'q', '3', '0', 0, 6583 /* 162 */ 's', '3', '0', 0, 6584 /* 166 */ 'w', '3', '0', 0, 6585 /* 170 */ 'x', '3', '0', 0, 6586 /* 174 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0, 6587 /* 189 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0, 6588 /* 204 */ 'b', '0', 0, 6589 /* 207 */ 'd', '0', 0, 6590 /* 210 */ 'h', '0', 0, 6591 /* 213 */ 'q', '0', 0, 6592 /* 216 */ 's', '0', 0, 6593 /* 219 */ 'w', '0', 0, 6594 /* 222 */ 'x', '0', 0, 6595 /* 225 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, 6596 /* 239 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, 6597 /* 253 */ 'b', '1', '1', 0, 6598 /* 257 */ 'd', '1', '1', 0, 6599 /* 261 */ 'h', '1', '1', 0, 6600 /* 265 */ 'q', '1', '1', 0, 6601 /* 269 */ 's', '1', '1', 0, 6602 /* 273 */ 'w', '1', '1', 0, 6603 /* 277 */ 'x', '1', '1', 0, 6604 /* 281 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, 6605 /* 297 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0, 6606 /* 313 */ 'b', '2', '1', 0, 6607 /* 317 */ 'd', '2', '1', 0, 6608 /* 321 */ 'h', '2', '1', 0, 6609 /* 325 */ 'q', '2', '1', 0, 6610 /* 329 */ 's', '2', '1', 0, 6611 /* 333 */ 'w', '2', '1', 0, 6612 /* 337 */ 'x', '2', '1', 0, 6613 /* 341 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, 6614 /* 357 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0, 6615 /* 373 */ 'b', '3', '1', 0, 6616 /* 377 */ 'd', '3', '1', 0, 6617 /* 381 */ 'h', '3', '1', 0, 6618 /* 385 */ 'q', '3', '1', 0, 6619 /* 389 */ 's', '3', '1', 0, 6620 /* 393 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0, 6621 /* 407 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0, 6622 /* 421 */ 'b', '1', 0, 6623 /* 424 */ 'd', '1', 0, 6624 /* 427 */ 'h', '1', 0, 6625 /* 430 */ 'q', '1', 0, 6626 /* 433 */ 's', '1', 0, 6627 /* 436 */ 'w', '1', 0, 6628 /* 439 */ 'x', '1', 0, 6629 /* 442 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, 6630 /* 457 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, 6631 /* 472 */ 'b', '1', '2', 0, 6632 /* 476 */ 'd', '1', '2', 0, 6633 /* 480 */ 'h', '1', '2', 0, 6634 /* 484 */ 'q', '1', '2', 0, 6635 /* 488 */ 's', '1', '2', 0, 6636 /* 492 */ 'w', '1', '2', 0, 6637 /* 496 */ 'x', '1', '2', 0, 6638 /* 500 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, 6639 /* 516 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0, 6640 /* 532 */ 'b', '2', '2', 0, 6641 /* 536 */ 'd', '2', '2', 0, 6642 /* 540 */ 'h', '2', '2', 0, 6643 /* 544 */ 'q', '2', '2', 0, 6644 /* 548 */ 's', '2', '2', 0, 6645 /* 552 */ 'w', '2', '2', 0, 6646 /* 556 */ 'x', '2', '2', 0, 6647 /* 560 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, 6648 /* 573 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0, 6649 /* 586 */ 'b', '2', 0, 6650 /* 589 */ 'd', '2', 0, 6651 /* 592 */ 'h', '2', 0, 6652 /* 595 */ 'q', '2', 0, 6653 /* 598 */ 's', '2', 0, 6654 /* 601 */ 'w', '2', 0, 6655 /* 604 */ 'x', '2', 0, 6656 /* 607 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, 6657 /* 623 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, 6658 /* 639 */ 'b', '1', '3', 0, 6659 /* 643 */ 'd', '1', '3', 0, 6660 /* 647 */ 'h', '1', '3', 0, 6661 /* 651 */ 'q', '1', '3', 0, 6662 /* 655 */ 's', '1', '3', 0, 6663 /* 659 */ 'w', '1', '3', 0, 6664 /* 663 */ 'x', '1', '3', 0, 6665 /* 667 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, 6666 /* 683 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0, 6667 /* 699 */ 'b', '2', '3', 0, 6668 /* 703 */ 'd', '2', '3', 0, 6669 /* 707 */ 'h', '2', '3', 0, 6670 /* 711 */ 'q', '2', '3', 0, 6671 /* 715 */ 's', '2', '3', 0, 6672 /* 719 */ 'w', '2', '3', 0, 6673 /* 723 */ 'x', '2', '3', 0, 6674 /* 727 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, 6675 /* 739 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, 6676 /* 751 */ 'b', '3', 0, 6677 /* 754 */ 'd', '3', 0, 6678 /* 757 */ 'h', '3', 0, 6679 /* 760 */ 'q', '3', 0, 6680 /* 763 */ 's', '3', 0, 6681 /* 766 */ 'w', '3', 0, 6682 /* 769 */ 'x', '3', 0, 6683 /* 772 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, 6684 /* 788 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, 6685 /* 804 */ 'b', '1', '4', 0, 6686 /* 808 */ 'd', '1', '4', 0, 6687 /* 812 */ 'h', '1', '4', 0, 6688 /* 816 */ 'q', '1', '4', 0, 6689 /* 820 */ 's', '1', '4', 0, 6690 /* 824 */ 'w', '1', '4', 0, 6691 /* 828 */ 'x', '1', '4', 0, 6692 /* 832 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, 6693 /* 848 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0, 6694 /* 864 */ 'b', '2', '4', 0, 6695 /* 868 */ 'd', '2', '4', 0, 6696 /* 872 */ 'h', '2', '4', 0, 6697 /* 876 */ 'q', '2', '4', 0, 6698 /* 880 */ 's', '2', '4', 0, 6699 /* 884 */ 'w', '2', '4', 0, 6700 /* 888 */ 'x', '2', '4', 0, 6701 /* 892 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, 6702 /* 904 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, 6703 /* 916 */ 'b', '4', 0, 6704 /* 919 */ 'd', '4', 0, 6705 /* 922 */ 'h', '4', 0, 6706 /* 925 */ 'q', '4', 0, 6707 /* 928 */ 's', '4', 0, 6708 /* 931 */ 'w', '4', 0, 6709 /* 934 */ 'x', '4', 0, 6710 /* 937 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, 6711 /* 953 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, 6712 /* 969 */ 'b', '1', '5', 0, 6713 /* 973 */ 'd', '1', '5', 0, 6714 /* 977 */ 'h', '1', '5', 0, 6715 /* 981 */ 'q', '1', '5', 0, 6716 /* 985 */ 's', '1', '5', 0, 6717 /* 989 */ 'w', '1', '5', 0, 6718 /* 993 */ 'x', '1', '5', 0, 6719 /* 997 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, 6720 /* 1013 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0, 6721 /* 1029 */ 'b', '2', '5', 0, 6722 /* 1033 */ 'd', '2', '5', 0, 6723 /* 1037 */ 'h', '2', '5', 0, 6724 /* 1041 */ 'q', '2', '5', 0, 6725 /* 1045 */ 's', '2', '5', 0, 6726 /* 1049 */ 'w', '2', '5', 0, 6727 /* 1053 */ 'x', '2', '5', 0, 6728 /* 1057 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, 6729 /* 1069 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, 6730 /* 1081 */ 'b', '5', 0, 6731 /* 1084 */ 'd', '5', 0, 6732 /* 1087 */ 'h', '5', 0, 6733 /* 1090 */ 'q', '5', 0, 6734 /* 1093 */ 's', '5', 0, 6735 /* 1096 */ 'w', '5', 0, 6736 /* 1099 */ 'x', '5', 0, 6737 /* 1102 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, 6738 /* 1118 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0, 6739 /* 1134 */ 'b', '1', '6', 0, 6740 /* 1138 */ 'd', '1', '6', 0, 6741 /* 1142 */ 'h', '1', '6', 0, 6742 /* 1146 */ 'q', '1', '6', 0, 6743 /* 1150 */ 's', '1', '6', 0, 6744 /* 1154 */ 'w', '1', '6', 0, 6745 /* 1158 */ 'x', '1', '6', 0, 6746 /* 1162 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, 6747 /* 1178 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0, 6748 /* 1194 */ 'b', '2', '6', 0, 6749 /* 1198 */ 'd', '2', '6', 0, 6750 /* 1202 */ 'h', '2', '6', 0, 6751 /* 1206 */ 'q', '2', '6', 0, 6752 /* 1210 */ 's', '2', '6', 0, 6753 /* 1214 */ 'w', '2', '6', 0, 6754 /* 1218 */ 'x', '2', '6', 0, 6755 /* 1222 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, 6756 /* 1234 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, 6757 /* 1246 */ 'b', '6', 0, 6758 /* 1249 */ 'd', '6', 0, 6759 /* 1252 */ 'h', '6', 0, 6760 /* 1255 */ 'q', '6', 0, 6761 /* 1258 */ 's', '6', 0, 6762 /* 1261 */ 'w', '6', 0, 6763 /* 1264 */ 'x', '6', 0, 6764 /* 1267 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, 6765 /* 1283 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0, 6766 /* 1299 */ 'b', '1', '7', 0, 6767 /* 1303 */ 'd', '1', '7', 0, 6768 /* 1307 */ 'h', '1', '7', 0, 6769 /* 1311 */ 'q', '1', '7', 0, 6770 /* 1315 */ 's', '1', '7', 0, 6771 /* 1319 */ 'w', '1', '7', 0, 6772 /* 1323 */ 'x', '1', '7', 0, 6773 /* 1327 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, 6774 /* 1343 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0, 6775 /* 1359 */ 'b', '2', '7', 0, 6776 /* 1363 */ 'd', '2', '7', 0, 6777 /* 1367 */ 'h', '2', '7', 0, 6778 /* 1371 */ 'q', '2', '7', 0, 6779 /* 1375 */ 's', '2', '7', 0, 6780 /* 1379 */ 'w', '2', '7', 0, 6781 /* 1383 */ 'x', '2', '7', 0, 6782 /* 1387 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, 6783 /* 1399 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, 6784 /* 1411 */ 'b', '7', 0, 6785 /* 1414 */ 'd', '7', 0, 6786 /* 1417 */ 'h', '7', 0, 6787 /* 1420 */ 'q', '7', 0, 6788 /* 1423 */ 's', '7', 0, 6789 /* 1426 */ 'w', '7', 0, 6790 /* 1429 */ 'x', '7', 0, 6791 /* 1432 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, 6792 /* 1448 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0, 6793 /* 1464 */ 'b', '1', '8', 0, 6794 /* 1468 */ 'd', '1', '8', 0, 6795 /* 1472 */ 'h', '1', '8', 0, 6796 /* 1476 */ 'q', '1', '8', 0, 6797 /* 1480 */ 's', '1', '8', 0, 6798 /* 1484 */ 'w', '1', '8', 0, 6799 /* 1488 */ 'x', '1', '8', 0, 6800 /* 1492 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, 6801 /* 1508 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0, 6802 /* 1524 */ 'b', '2', '8', 0, 6803 /* 1528 */ 'd', '2', '8', 0, 6804 /* 1532 */ 'h', '2', '8', 0, 6805 /* 1536 */ 'q', '2', '8', 0, 6806 /* 1540 */ 's', '2', '8', 0, 6807 /* 1544 */ 'w', '2', '8', 0, 6808 /* 1548 */ 'x', '2', '8', 0, 6809 /* 1552 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, 6810 /* 1564 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, 6811 /* 1576 */ 'b', '8', 0, 6812 /* 1579 */ 'd', '8', 0, 6813 /* 1582 */ 'h', '8', 0, 6814 /* 1585 */ 'q', '8', 0, 6815 /* 1588 */ 's', '8', 0, 6816 /* 1591 */ 'w', '8', 0, 6817 /* 1594 */ 'x', '8', 0, 6818 /* 1597 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, 6819 /* 1613 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0, 6820 /* 1629 */ 'b', '1', '9', 0, 6821 /* 1633 */ 'd', '1', '9', 0, 6822 /* 1637 */ 'h', '1', '9', 0, 6823 /* 1641 */ 'q', '1', '9', 0, 6824 /* 1645 */ 's', '1', '9', 0, 6825 /* 1649 */ 'w', '1', '9', 0, 6826 /* 1653 */ 'x', '1', '9', 0, 6827 /* 1657 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, 6828 /* 1673 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0, 6829 /* 1689 */ 'b', '2', '9', 0, 6830 /* 1693 */ 'd', '2', '9', 0, 6831 /* 1697 */ 'h', '2', '9', 0, 6832 /* 1701 */ 'q', '2', '9', 0, 6833 /* 1705 */ 's', '2', '9', 0, 6834 /* 1709 */ 'w', '2', '9', 0, 6835 /* 1713 */ 'x', '2', '9', 0, 6836 /* 1717 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, 6837 /* 1729 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, 6838 /* 1741 */ 'b', '9', 0, 6839 /* 1744 */ 'd', '9', 0, 6840 /* 1747 */ 'h', '9', 0, 6841 /* 1750 */ 'q', '9', 0, 6842 /* 1753 */ 's', '9', 0, 6843 /* 1756 */ 'w', '9', 0, 6844 /* 1759 */ 'x', '9', 0, 6845 /* 1762 */ 'w', 's', 'p', 0, 6846 /* 1766 */ 'w', 'z', 'r', 0, 6847 /* 1770 */ 'x', 'z', 'r', 0, 6848 /* 1774 */ 'n', 'z', 'c', 'v', 0, 6849 }; 6850 6851 static const uint32_t RegAsmOffsetNoRegAltName[] = { 6852 1713, 170, 1774, 1763, 1762, 1766, 1770, 204, 421, 586, 751, 916, 1081, 1246, 6853 1411, 1576, 1741, 26, 253, 472, 639, 804, 969, 1134, 1299, 1464, 1629, 86, 6854 313, 532, 699, 864, 1029, 1194, 1359, 1524, 1689, 146, 373, 207, 424, 589, 6855 754, 919, 1084, 1249, 1414, 1579, 1744, 30, 257, 476, 643, 808, 973, 1138, 6856 1303, 1468, 1633, 90, 317, 536, 703, 868, 1033, 1198, 1363, 1528, 1693, 150, 6857 377, 210, 427, 592, 757, 922, 1087, 1252, 1417, 1582, 1747, 34, 261, 480, 6858 647, 812, 977, 1142, 1307, 1472, 1637, 94, 321, 540, 707, 872, 1037, 1202, 6859 1367, 1532, 1697, 154, 381, 213, 430, 595, 760, 925, 1090, 1255, 1420, 1585, 6860 1750, 38, 265, 484, 651, 816, 981, 1146, 1311, 1476, 1641, 98, 325, 544, 6861 711, 876, 1041, 1206, 1371, 1536, 1701, 158, 385, 216, 433, 598, 763, 928, 6862 1093, 1258, 1423, 1588, 1753, 42, 269, 488, 655, 820, 985, 1150, 1315, 1480, 6863 1645, 102, 329, 548, 715, 880, 1045, 1210, 1375, 1540, 1705, 162, 389, 219, 6864 436, 601, 766, 931, 1096, 1261, 1426, 1591, 1756, 46, 273, 492, 659, 824, 6865 989, 1154, 1319, 1484, 1649, 106, 333, 552, 719, 884, 1049, 1214, 1379, 1544, 6866 1709, 166, 222, 439, 604, 769, 934, 1099, 1264, 1429, 1594, 1759, 50, 277, 6867 496, 663, 828, 993, 1158, 1323, 1488, 1653, 110, 337, 556, 723, 888, 1053, 6868 1218, 1383, 1548, 401, 567, 733, 898, 1063, 1228, 1393, 1558, 1723, 6, 231, 6869 449, 615, 780, 945, 1110, 1275, 1440, 1605, 62, 289, 508, 675, 840, 1005, 6870 1170, 1335, 1500, 1665, 122, 349, 182, 727, 892, 1057, 1222, 1387, 1552, 1717, 6871 0, 225, 442, 607, 772, 937, 1102, 1267, 1432, 1597, 54, 281, 500, 667, 6872 832, 997, 1162, 1327, 1492, 1657, 114, 341, 174, 393, 560, 564, 730, 895, 6873 1060, 1225, 1390, 1555, 1720, 3, 228, 445, 611, 776, 941, 1106, 1271, 1436, 6874 1601, 58, 285, 504, 671, 836, 1001, 1166, 1331, 1496, 1661, 118, 345, 178, 6875 397, 415, 580, 745, 910, 1075, 1240, 1405, 1570, 1735, 19, 245, 464, 631, 6876 796, 961, 1126, 1291, 1456, 1621, 78, 305, 524, 691, 856, 1021, 1186, 1351, 6877 1516, 1681, 138, 365, 197, 739, 904, 1069, 1234, 1399, 1564, 1729, 13, 239, 6878 457, 623, 788, 953, 1118, 1283, 1448, 1613, 70, 297, 516, 683, 848, 1013, 6879 1178, 1343, 1508, 1673, 130, 357, 189, 407, 573, 577, 742, 907, 1072, 1237, 6880 1402, 1567, 1732, 16, 242, 460, 627, 792, 957, 1122, 1287, 1452, 1617, 74, 6881 301, 520, 687, 852, 1017, 1182, 1347, 1512, 1677, 134, 361, 193, 411, 6882 }; 6883 6884 static char AsmStrsvreg[] = { 6885 /* 0 */ 'v', '1', '0', 0, 6886 /* 4 */ 'v', '2', '0', 0, 6887 /* 8 */ 'v', '3', '0', 0, 6888 /* 12 */ 'v', '0', 0, 6889 /* 15 */ 'v', '1', '1', 0, 6890 /* 19 */ 'v', '2', '1', 0, 6891 /* 23 */ 'v', '3', '1', 0, 6892 /* 27 */ 'v', '1', 0, 6893 /* 30 */ 'v', '1', '2', 0, 6894 /* 34 */ 'v', '2', '2', 0, 6895 /* 38 */ 'v', '2', 0, 6896 /* 41 */ 'v', '1', '3', 0, 6897 /* 45 */ 'v', '2', '3', 0, 6898 /* 49 */ 'v', '3', 0, 6899 /* 52 */ 'v', '1', '4', 0, 6900 /* 56 */ 'v', '2', '4', 0, 6901 /* 60 */ 'v', '4', 0, 6902 /* 63 */ 'v', '1', '5', 0, 6903 /* 67 */ 'v', '2', '5', 0, 6904 /* 71 */ 'v', '5', 0, 6905 /* 74 */ 'v', '1', '6', 0, 6906 /* 78 */ 'v', '2', '6', 0, 6907 /* 82 */ 'v', '6', 0, 6908 /* 85 */ 'v', '1', '7', 0, 6909 /* 89 */ 'v', '2', '7', 0, 6910 /* 93 */ 'v', '7', 0, 6911 /* 96 */ 'v', '1', '8', 0, 6912 /* 100 */ 'v', '2', '8', 0, 6913 /* 104 */ 'v', '8', 0, 6914 /* 107 */ 'v', '1', '9', 0, 6915 /* 111 */ 'v', '2', '9', 0, 6916 /* 115 */ 'v', '9', 0, 6917 }; 6918 6919 static const uint32_t RegAsmOffsetvreg[] = { 6920 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6921 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6922 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 6923 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 6924 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 6925 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6926 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6927 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 6928 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 6929 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 6930 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6931 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6932 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6933 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6934 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6935 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6936 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 6937 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 6938 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 6939 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 6940 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 6941 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 6942 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 6943 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 6944 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 6945 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 6946 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 6947 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 6948 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 6949 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 6950 }; 6951 6952 const uint32_t *RegAsmOffset; 6953 char *AsmStrs; 6954 6955 switch(AltIdx) { 6956 default: // llvm_unreachable("Invalid register alt name index!"); 6957 case AArch64_NoRegAltName: 6958 AsmStrs = AsmStrsNoRegAltName; 6959 RegAsmOffset = RegAsmOffsetNoRegAltName; 6960 break; 6961 case AArch64_vreg: 6962 AsmStrs = AsmStrsvreg; 6963 RegAsmOffset = RegAsmOffsetvreg; 6964 break; 6965 } 6966 //int i; 6967 //for (i = 0; i < sizeof(RegAsmOffsetNoRegAltName)/4; i++) 6968 // printf("%s = %u\n", AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[i], i + 1); 6969 //printf("*************************\n"); 6970 //for (i = 0; i < sizeof(RegAsmOffsetvreg)/4; i++) 6971 // printf("%s = %u\n", AsmStrsvreg+RegAsmOffsetvreg[i], i + 1); 6972 //printf("-------------------------\n"); 6973 return AsmStrs+RegAsmOffset[RegNo-1]; 6974#else 6975 return NULL; 6976#endif 6977} 6978 6979#ifdef PRINT_ALIAS_INSTR 6980#undef PRINT_ALIAS_INSTR 6981 6982static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, 6983 unsigned PrintMethodIdx, SStream *OS, MCRegisterInfo *MRI) 6984{ 6985 // printf(">>>> Method: %u, opIdx: %x\n", PrintMethodIdx, OpIdx); 6986 switch (PrintMethodIdx) { 6987 default: 6988 // llvm_unreachable("Unknown PrintMethod kind"); 6989 break; 6990 case 0: 6991 printAddSubImm(MI, OpIdx, OS); 6992 break; 6993 case 1: 6994 printShifter(MI, OpIdx, OS); 6995 break; 6996 case 2: 6997 printArithExtend(MI, OpIdx, OS); 6998 break; 6999 case 3: 7000 printLogicalImm32(MI, OpIdx, OS); 7001 break; 7002 case 4: 7003 printLogicalImm64(MI, OpIdx, OS); 7004 break; 7005 case 5: 7006 printVRegOperand(MI, OpIdx, OS); 7007 break; 7008 case 6: 7009 printHexImm(MI, OpIdx, OS); 7010 break; 7011 case 7: 7012 printInverseCondCode(MI, OpIdx, OS); 7013 break; 7014 case 8: 7015 printVectorIndex(MI, OpIdx, OS); 7016 break; 7017 case 9: 7018 printTypedVectorList(MI, OpIdx, OS, 16, 'b', MRI); 7019 break; 7020 case 10: 7021 printTypedVectorList(MI, OpIdx, OS, 1, 'd', MRI); 7022 break; 7023 case 11: 7024 printTypedVectorList(MI, OpIdx, OS, 2, 'd', MRI); 7025 break; 7026 case 12: 7027 printTypedVectorList(MI, OpIdx, OS, 2, 's', MRI); 7028 break; 7029 case 13: 7030 printTypedVectorList(MI, OpIdx, OS, 4, 'h', MRI); 7031 break; 7032 case 14: 7033 printTypedVectorList(MI, OpIdx, OS, 4, 's', MRI); 7034 break; 7035 case 15: 7036 printTypedVectorList(MI, OpIdx, OS, 8, 'b', MRI); 7037 break; 7038 case 16: 7039 printTypedVectorList(MI, OpIdx, OS, 8, 'h', MRI); 7040 break; 7041 case 17: 7042 printTypedVectorList(MI, OpIdx, OS, 0, 'h', MRI); 7043 break; 7044 case 18: 7045 printTypedVectorList(MI, OpIdx, OS, 0, 's', MRI); 7046 break; 7047 case 19: 7048 printTypedVectorList(MI, OpIdx, OS, 0, 'd', MRI); 7049 break; 7050 case 20: 7051 printTypedVectorList(MI, OpIdx, OS, 0, 'b', MRI); 7052 break; 7053 case 21: 7054 printPrefetchOp(MI, OpIdx, OS); 7055 break; 7056 case 22: 7057 printSysCROperand(MI, OpIdx, OS); 7058 break; 7059 } 7060} 7061 7062static bool AArch64InstPrinterValidateMCOperand( 7063 MCOperand *MCOp, unsigned PredicateIndex) 7064{ 7065 switch (PredicateIndex) { 7066 default: 7067 // llvm_unreachable("Unknown MCOperandPredicate kind"); 7068 case 1: { 7069 return (MCOperand_isImm(MCOp) && 7070 MCOperand_getImm(MCOp) != ARM64_CC_AL && 7071 MCOperand_getImm(MCOp) != ARM64_CC_NV); 7072 } 7073 } 7074} 7075 7076static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) 7077{ 7078 #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) 7079 const char *AsmString; 7080 char *tmp, *AsmMnem, *AsmOps, *c; 7081 int OpIdx, PrintMethodIdx; 7082 MCRegisterInfo *MRI = (MCRegisterInfo *)info; 7083 switch (MCInst_getOpcode(MI)) { 7084 default: return NULL; 7085 case AArch64_ADDSWri: 7086 if (MCInst_getNumOperands(MI) == 4 && 7087 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7088 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7089 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1)) { 7090 // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) 7091 AsmString = "cmn $\x02, $\xFF\x03\x01"; 7092 break; 7093 } 7094 return NULL; 7095 case AArch64_ADDSWrs: 7096 if (MCInst_getNumOperands(MI) == 4 && 7097 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7098 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7099 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7100 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7101 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7102 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7103 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7104 // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) 7105 AsmString = "cmn $\x02, $\x03"; 7106 break; 7107 } 7108 if (MCInst_getNumOperands(MI) == 4 && 7109 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7110 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7111 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7112 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7113 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 7114 // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) 7115 AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; 7116 break; 7117 } 7118 if (MCInst_getNumOperands(MI) == 4 && 7119 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7120 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7121 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7122 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7123 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7124 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7125 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7126 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7127 // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7128 AsmString = "adds $\x01, $\x02, $\x03"; 7129 break; 7130 } 7131 return NULL; 7132 case AArch64_ADDSWrx: 7133 if (MCInst_getNumOperands(MI) == 4 && 7134 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7135 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7136 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && 7137 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7138 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7139 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7140 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 7141 // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) 7142 AsmString = "cmn $\x02, $\x03"; 7143 break; 7144 } 7145 if (MCInst_getNumOperands(MI) == 4 && 7146 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7147 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7148 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && 7149 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7150 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 7151 // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) 7152 AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; 7153 break; 7154 } 7155 if (MCInst_getNumOperands(MI) == 4 && 7156 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7157 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7158 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7159 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && 7160 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7161 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7162 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7163 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 7164 // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) 7165 AsmString = "adds $\x01, $\x02, $\x03"; 7166 break; 7167 } 7168 return NULL; 7169 case AArch64_ADDSXri: 7170 if (MCInst_getNumOperands(MI) == 4 && 7171 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7172 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7173 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1)) { 7174 // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) 7175 AsmString = "cmn $\x02, $\xFF\x03\x01"; 7176 break; 7177 } 7178 return NULL; 7179 case AArch64_ADDSXrs: 7180 if (MCInst_getNumOperands(MI) == 4 && 7181 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7182 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7183 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7184 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7185 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7186 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7187 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7188 // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) 7189 AsmString = "cmn $\x02, $\x03"; 7190 break; 7191 } 7192 if (MCInst_getNumOperands(MI) == 4 && 7193 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7194 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7195 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7196 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7197 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 7198 // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) 7199 AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; 7200 break; 7201 } 7202 if (MCInst_getNumOperands(MI) == 4 && 7203 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7204 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7205 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7206 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7207 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7208 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7209 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7210 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7211 // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7212 AsmString = "adds $\x01, $\x02, $\x03"; 7213 break; 7214 } 7215 return NULL; 7216 case AArch64_ADDSXrx: 7217 if (MCInst_getNumOperands(MI) == 4 && 7218 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7219 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7220 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 7221 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7222 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 7223 // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) 7224 AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; 7225 break; 7226 } 7227 return NULL; 7228 case AArch64_ADDSXrx64: 7229 if (MCInst_getNumOperands(MI) == 4 && 7230 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7231 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7232 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && 7233 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7234 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7235 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7236 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 7237 // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) 7238 AsmString = "cmn $\x02, $\x03"; 7239 break; 7240 } 7241 if (MCInst_getNumOperands(MI) == 4 && 7242 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7243 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7244 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 7245 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7246 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 7247 // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) 7248 AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; 7249 break; 7250 } 7251 if (MCInst_getNumOperands(MI) == 4 && 7252 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7253 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7254 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7255 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && 7256 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7257 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7258 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7259 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 7260 // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) 7261 AsmString = "adds $\x01, $\x02, $\x03"; 7262 break; 7263 } 7264 return NULL; 7265 case AArch64_ADDWri: 7266 if (MCInst_getNumOperands(MI) == 4 && 7267 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7268 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) && 7269 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7270 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && 7271 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7272 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 7273 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7274 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7275 // (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0) 7276 AsmString = "mov $\x01, $\x02"; 7277 break; 7278 } 7279 if (MCInst_getNumOperands(MI) == 4 && 7280 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7281 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) && 7282 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7283 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && 7284 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7285 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 7286 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7287 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7288 // (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0) 7289 AsmString = "mov $\x01, $\x02"; 7290 break; 7291 } 7292 return NULL; 7293 case AArch64_ADDWrs: 7294 if (MCInst_getNumOperands(MI) == 4 && 7295 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7296 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7297 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7298 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7299 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7300 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7301 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7302 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7303 // (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7304 AsmString = "add $\x01, $\x02, $\x03"; 7305 break; 7306 } 7307 return NULL; 7308 case AArch64_ADDWrx: 7309 if (MCInst_getNumOperands(MI) == 4 && 7310 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7311 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) && 7312 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7313 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && 7314 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7315 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7316 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7317 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 7318 // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) 7319 AsmString = "add $\x01, $\x02, $\x03"; 7320 break; 7321 } 7322 if (MCInst_getNumOperands(MI) == 4 && 7323 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7324 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) && 7325 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7326 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && 7327 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7328 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7329 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7330 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 7331 // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) 7332 AsmString = "add $\x01, $\x02, $\x03"; 7333 break; 7334 } 7335 return NULL; 7336 case AArch64_ADDXri: 7337 if (MCInst_getNumOperands(MI) == 4 && 7338 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7339 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) && 7340 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7341 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 7342 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7343 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 7344 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7345 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7346 // (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0) 7347 AsmString = "mov $\x01, $\x02"; 7348 break; 7349 } 7350 if (MCInst_getNumOperands(MI) == 4 && 7351 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7352 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 7353 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7354 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && 7355 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7356 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 7357 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7358 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7359 // (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0) 7360 AsmString = "mov $\x01, $\x02"; 7361 break; 7362 } 7363 return NULL; 7364 case AArch64_ADDXrs: 7365 if (MCInst_getNumOperands(MI) == 4 && 7366 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7367 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7368 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7369 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7370 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7371 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7372 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7373 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7374 // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7375 AsmString = "add $\x01, $\x02, $\x03"; 7376 break; 7377 } 7378 return NULL; 7379 case AArch64_ADDXrx64: 7380 if (MCInst_getNumOperands(MI) == 4 && 7381 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7382 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) && 7383 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7384 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 7385 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7386 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7387 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7388 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 7389 // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) 7390 AsmString = "add $\x01, $\x02, $\x03"; 7391 break; 7392 } 7393 if (MCInst_getNumOperands(MI) == 4 && 7394 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7395 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 7396 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7397 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && 7398 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7399 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7400 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7401 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 7402 // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) 7403 AsmString = "add $\x01, $\x02, $\x03"; 7404 break; 7405 } 7406 return NULL; 7407 case AArch64_ANDSWri: 7408 if (MCInst_getNumOperands(MI) == 3 && 7409 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7410 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7411 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1)) { 7412 // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) 7413 AsmString = "tst $\x02, $\xFF\x03\x04"; 7414 break; 7415 } 7416 return NULL; 7417 case AArch64_ANDSWrs: 7418 if (MCInst_getNumOperands(MI) == 4 && 7419 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7420 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7421 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7422 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7423 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7424 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7425 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7426 // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) 7427 AsmString = "tst $\x02, $\x03"; 7428 break; 7429 } 7430 if (MCInst_getNumOperands(MI) == 4 && 7431 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 7432 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7433 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7434 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7435 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 7436 // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh) 7437 AsmString = "tst $\x02, $\x03$\xFF\x04\x02"; 7438 break; 7439 } 7440 if (MCInst_getNumOperands(MI) == 4 && 7441 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7442 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7443 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7444 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7445 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7446 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7447 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7448 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7449 // (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7450 AsmString = "ands $\x01, $\x02, $\x03"; 7451 break; 7452 } 7453 return NULL; 7454 case AArch64_ANDSXri: 7455 if (MCInst_getNumOperands(MI) == 3 && 7456 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7457 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7458 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1)) { 7459 // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) 7460 AsmString = "tst $\x02, $\xFF\x03\x05"; 7461 break; 7462 } 7463 return NULL; 7464 case AArch64_ANDSXrs: 7465 if (MCInst_getNumOperands(MI) == 4 && 7466 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7467 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7468 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7469 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7470 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7471 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7472 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7473 // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) 7474 AsmString = "tst $\x02, $\x03"; 7475 break; 7476 } 7477 if (MCInst_getNumOperands(MI) == 4 && 7478 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 7479 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7480 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7481 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7482 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 7483 // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh) 7484 AsmString = "tst $\x02, $\x03$\xFF\x04\x02"; 7485 break; 7486 } 7487 if (MCInst_getNumOperands(MI) == 4 && 7488 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7489 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7490 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7491 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7492 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7493 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7494 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7495 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7496 // (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7497 AsmString = "ands $\x01, $\x02, $\x03"; 7498 break; 7499 } 7500 return NULL; 7501 case AArch64_ANDWrs: 7502 if (MCInst_getNumOperands(MI) == 4 && 7503 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7504 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7505 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7506 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7507 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7508 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7509 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7510 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7511 // (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7512 AsmString = "and $\x01, $\x02, $\x03"; 7513 break; 7514 } 7515 return NULL; 7516 case AArch64_ANDXrs: 7517 if (MCInst_getNumOperands(MI) == 4 && 7518 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7519 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7520 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7521 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7522 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7523 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7524 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7525 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7526 // (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7527 AsmString = "and $\x01, $\x02, $\x03"; 7528 break; 7529 } 7530 return NULL; 7531 case AArch64_BICSWrs: 7532 if (MCInst_getNumOperands(MI) == 4 && 7533 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7534 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7535 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7536 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7537 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7538 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7539 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7540 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7541 // (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7542 AsmString = "bics $\x01, $\x02, $\x03"; 7543 break; 7544 } 7545 return NULL; 7546 case AArch64_BICSXrs: 7547 if (MCInst_getNumOperands(MI) == 4 && 7548 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7549 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7550 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7551 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7552 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7553 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7554 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7555 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7556 // (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7557 AsmString = "bics $\x01, $\x02, $\x03"; 7558 break; 7559 } 7560 return NULL; 7561 case AArch64_BICWrs: 7562 if (MCInst_getNumOperands(MI) == 4 && 7563 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7564 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7565 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7566 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7567 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7568 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7569 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7570 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7571 // (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7572 AsmString = "bic $\x01, $\x02, $\x03"; 7573 break; 7574 } 7575 return NULL; 7576 case AArch64_BICXrs: 7577 if (MCInst_getNumOperands(MI) == 4 && 7578 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7579 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7580 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7581 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7582 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7583 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7584 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7585 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7586 // (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7587 AsmString = "bic $\x01, $\x02, $\x03"; 7588 break; 7589 } 7590 return NULL; 7591 case AArch64_BICv2i32: 7592 if (MCInst_getNumOperands(MI) == 3 && 7593 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7594 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 7595 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7596 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 7597 // (BICv2i32 V64:$Vd, imm0_255:$imm, 0) 7598 AsmString = "bic $\xFF\x01\x06.2s, $\xFF\x02\x07"; 7599 break; 7600 } 7601 return NULL; 7602 case AArch64_BICv4i16: 7603 if (MCInst_getNumOperands(MI) == 3 && 7604 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7605 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 7606 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7607 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 7608 // (BICv4i16 V64:$Vd, imm0_255:$imm, 0) 7609 AsmString = "bic $\xFF\x01\x06.4h, $\xFF\x02\x07"; 7610 break; 7611 } 7612 return NULL; 7613 case AArch64_BICv4i32: 7614 if (MCInst_getNumOperands(MI) == 3 && 7615 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7616 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7617 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7618 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 7619 // (BICv4i32 V128:$Vd, imm0_255:$imm, 0) 7620 AsmString = "bic $\xFF\x01\x06.4s, $\xFF\x02\x07"; 7621 break; 7622 } 7623 return NULL; 7624 case AArch64_BICv8i16: 7625 if (MCInst_getNumOperands(MI) == 3 && 7626 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7627 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7628 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 7629 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 7630 // (BICv8i16 V128:$Vd, imm0_255:$imm, 0) 7631 AsmString = "bic $\xFF\x01\x06.8h, $\xFF\x02\x07"; 7632 break; 7633 } 7634 return NULL; 7635 case AArch64_CLREX: 7636 if (MCInst_getNumOperands(MI) == 1 && 7637 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7638 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { 7639 // (CLREX 15) 7640 AsmString = "clrex"; 7641 break; 7642 } 7643 return NULL; 7644 case AArch64_CSINCWr: 7645 if (MCInst_getNumOperands(MI) == 4 && 7646 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7647 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7648 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 7649 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR && 7650 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7651 // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) 7652 AsmString = "cset $\x01, $\xFF\x04\x08"; 7653 break; 7654 } 7655 if (MCInst_getNumOperands(MI) == 4 && 7656 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7657 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7658 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7659 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7660 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7661 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && 7662 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7663 // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) 7664 AsmString = "cinc $\x01, $\x02, $\xFF\x04\x08"; 7665 break; 7666 } 7667 return NULL; 7668 case AArch64_CSINCXr: 7669 if (MCInst_getNumOperands(MI) == 4 && 7670 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7671 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7672 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 7673 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR && 7674 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7675 // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) 7676 AsmString = "cset $\x01, $\xFF\x04\x08"; 7677 break; 7678 } 7679 if (MCInst_getNumOperands(MI) == 4 && 7680 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7681 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7682 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7683 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7684 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7685 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && 7686 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7687 // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) 7688 AsmString = "cinc $\x01, $\x02, $\xFF\x04\x08"; 7689 break; 7690 } 7691 return NULL; 7692 case AArch64_CSINVWr: 7693 if (MCInst_getNumOperands(MI) == 4 && 7694 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7695 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7696 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 7697 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR && 7698 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7699 // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) 7700 AsmString = "csetm $\x01, $\xFF\x04\x08"; 7701 break; 7702 } 7703 if (MCInst_getNumOperands(MI) == 4 && 7704 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7705 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7706 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7707 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7708 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7709 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && 7710 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7711 // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) 7712 AsmString = "cinv $\x01, $\x02, $\xFF\x04\x08"; 7713 break; 7714 } 7715 return NULL; 7716 case AArch64_CSINVXr: 7717 if (MCInst_getNumOperands(MI) == 4 && 7718 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7719 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7720 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 7721 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR && 7722 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7723 // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) 7724 AsmString = "csetm $\x01, $\xFF\x04\x08"; 7725 break; 7726 } 7727 if (MCInst_getNumOperands(MI) == 4 && 7728 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7729 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7730 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7731 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7732 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7733 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && 7734 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7735 // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) 7736 AsmString = "cinv $\x01, $\x02, $\xFF\x04\x08"; 7737 break; 7738 } 7739 return NULL; 7740 case AArch64_CSNEGWr: 7741 if (MCInst_getNumOperands(MI) == 4 && 7742 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7743 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7744 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7745 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7746 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7747 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && 7748 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7749 // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) 7750 AsmString = "cneg $\x01, $\x02, $\xFF\x04\x08"; 7751 break; 7752 } 7753 return NULL; 7754 case AArch64_CSNEGXr: 7755 if (MCInst_getNumOperands(MI) == 4 && 7756 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7757 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7758 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7759 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7760 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7761 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && 7762 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { 7763 // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) 7764 AsmString = "cneg $\x01, $\x02, $\xFF\x04\x08"; 7765 break; 7766 } 7767 return NULL; 7768 case AArch64_DCPS1: 7769 if (MCInst_getNumOperands(MI) == 1 && 7770 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7771 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { 7772 // (DCPS1 0) 7773 AsmString = "dcps1"; 7774 break; 7775 } 7776 return NULL; 7777 case AArch64_DCPS2: 7778 if (MCInst_getNumOperands(MI) == 1 && 7779 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7780 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { 7781 // (DCPS2 0) 7782 AsmString = "dcps2"; 7783 break; 7784 } 7785 return NULL; 7786 case AArch64_DCPS3: 7787 if (MCInst_getNumOperands(MI) == 1 && 7788 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7789 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { 7790 // (DCPS3 0) 7791 AsmString = "dcps3"; 7792 break; 7793 } 7794 return NULL; 7795 case AArch64_EONWrs: 7796 if (MCInst_getNumOperands(MI) == 4 && 7797 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7798 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7799 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7800 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7801 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7802 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7803 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7804 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7805 // (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7806 AsmString = "eon $\x01, $\x02, $\x03"; 7807 break; 7808 } 7809 return NULL; 7810 case AArch64_EONXrs: 7811 if (MCInst_getNumOperands(MI) == 4 && 7812 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7813 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7814 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7815 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7816 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7817 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7818 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7819 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7820 // (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7821 AsmString = "eon $\x01, $\x02, $\x03"; 7822 break; 7823 } 7824 return NULL; 7825 case AArch64_EORWrs: 7826 if (MCInst_getNumOperands(MI) == 4 && 7827 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7828 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7829 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7830 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7831 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7832 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 7833 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7834 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7835 // (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7836 AsmString = "eor $\x01, $\x02, $\x03"; 7837 break; 7838 } 7839 return NULL; 7840 case AArch64_EORXrs: 7841 if (MCInst_getNumOperands(MI) == 4 && 7842 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7843 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7844 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7845 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7846 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7847 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 7848 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 7849 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 7850 // (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7851 AsmString = "eor $\x01, $\x02, $\x03"; 7852 break; 7853 } 7854 return NULL; 7855 case AArch64_EXTRWrri: 7856 if (MCInst_getNumOperands(MI) == 4 && 7857 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7858 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 7859 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7860 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 7861 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7862 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { 7863 // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) 7864 AsmString = "ror $\x01, $\x02, $\x04"; 7865 break; 7866 } 7867 return NULL; 7868 case AArch64_EXTRXrri: 7869 if (MCInst_getNumOperands(MI) == 4 && 7870 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7871 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 7872 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 7873 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 7874 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7875 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { 7876 // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) 7877 AsmString = "ror $\x01, $\x02, $\x04"; 7878 break; 7879 } 7880 return NULL; 7881 case AArch64_HINT: 7882 if (MCInst_getNumOperands(MI) == 1 && 7883 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7884 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { 7885 // (HINT { 0, 0, 0 }) 7886 AsmString = "nop"; 7887 break; 7888 } 7889 if (MCInst_getNumOperands(MI) == 1 && 7890 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7891 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { 7892 // (HINT { 0, 0, 1 }) 7893 AsmString = "yield"; 7894 break; 7895 } 7896 if (MCInst_getNumOperands(MI) == 1 && 7897 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7898 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { 7899 // (HINT { 0, 1, 0 }) 7900 AsmString = "wfe"; 7901 break; 7902 } 7903 if (MCInst_getNumOperands(MI) == 1 && 7904 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7905 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3) { 7906 // (HINT { 0, 1, 1 }) 7907 AsmString = "wfi"; 7908 break; 7909 } 7910 if (MCInst_getNumOperands(MI) == 1 && 7911 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7912 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4) { 7913 // (HINT { 1, 0, 0 }) 7914 AsmString = "sev"; 7915 break; 7916 } 7917 if (MCInst_getNumOperands(MI) == 1 && 7918 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 7919 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5) { 7920 // (HINT { 1, 0, 1 }) 7921 AsmString = "sevl"; 7922 break; 7923 } 7924 return NULL; 7925 case AArch64_INSvi16gpr: 7926 if (MCInst_getNumOperands(MI) == 3 && 7927 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7928 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7929 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7930 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 7931 // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) 7932 AsmString = "mov $\xFF\x01\x06.h$\xFF\x02\x09, $\x03"; 7933 break; 7934 } 7935 return NULL; 7936 case AArch64_INSvi16lane: 7937 if (MCInst_getNumOperands(MI) == 4 && 7938 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7939 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7940 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7941 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { 7942 // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) 7943 AsmString = "mov $\xFF\x01\x06.h$\xFF\x02\x09, $\xFF\x03\x06.h$\xFF\x04\x09"; 7944 break; 7945 } 7946 return NULL; 7947 case AArch64_INSvi32gpr: 7948 if (MCInst_getNumOperands(MI) == 3 && 7949 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7950 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7951 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7952 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 7953 // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) 7954 AsmString = "mov $\xFF\x01\x06.s$\xFF\x02\x09, $\x03"; 7955 break; 7956 } 7957 return NULL; 7958 case AArch64_INSvi32lane: 7959 if (MCInst_getNumOperands(MI) == 4 && 7960 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7961 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7962 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7963 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { 7964 // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) 7965 AsmString = "mov $\xFF\x01\x06.s$\xFF\x02\x09, $\xFF\x03\x06.s$\xFF\x04\x09"; 7966 break; 7967 } 7968 return NULL; 7969 case AArch64_INSvi64gpr: 7970 if (MCInst_getNumOperands(MI) == 3 && 7971 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7972 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7973 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7974 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 7975 // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) 7976 AsmString = "mov $\xFF\x01\x06.d$\xFF\x02\x09, $\x03"; 7977 break; 7978 } 7979 return NULL; 7980 case AArch64_INSvi64lane: 7981 if (MCInst_getNumOperands(MI) == 4 && 7982 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7983 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7984 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7985 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { 7986 // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) 7987 AsmString = "mov $\xFF\x01\x06.d$\xFF\x02\x09, $\xFF\x03\x06.d$\xFF\x04\x09"; 7988 break; 7989 } 7990 return NULL; 7991 case AArch64_INSvi8gpr: 7992 if (MCInst_getNumOperands(MI) == 3 && 7993 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 7994 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 7995 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 7996 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 7997 // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) 7998 AsmString = "mov $\xFF\x01\x06.b$\xFF\x02\x09, $\x03"; 7999 break; 8000 } 8001 return NULL; 8002 case AArch64_INSvi8lane: 8003 if (MCInst_getNumOperands(MI) == 4 && 8004 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8005 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 8006 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 8007 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { 8008 // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) 8009 AsmString = "mov $\xFF\x01\x06.b$\xFF\x02\x09, $\xFF\x03\x06.b$\xFF\x04\x09"; 8010 break; 8011 } 8012 return NULL; 8013 case AArch64_ISB: 8014 if (MCInst_getNumOperands(MI) == 1 && 8015 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 8016 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { 8017 // (ISB 15) 8018 AsmString = "isb"; 8019 break; 8020 } 8021 return NULL; 8022 case AArch64_LD1Fourv16b_POST: 8023 if (MCInst_getNumOperands(MI) == 3 && 8024 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8025 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8026 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8027 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 8028 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8029 // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) 8030 AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #64"; 8031 break; 8032 } 8033 return NULL; 8034 case AArch64_LD1Fourv1d_POST: 8035 if (MCInst_getNumOperands(MI) == 3 && 8036 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8037 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8038 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8039 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 8040 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8041 // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) 8042 AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #32"; 8043 break; 8044 } 8045 return NULL; 8046 case AArch64_LD1Fourv2d_POST: 8047 if (MCInst_getNumOperands(MI) == 3 && 8048 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8049 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8050 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8051 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 8052 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8053 // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) 8054 AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #64"; 8055 break; 8056 } 8057 return NULL; 8058 case AArch64_LD1Fourv2s_POST: 8059 if (MCInst_getNumOperands(MI) == 3 && 8060 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8061 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8062 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8063 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 8064 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8065 // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) 8066 AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #32"; 8067 break; 8068 } 8069 return NULL; 8070 case AArch64_LD1Fourv4h_POST: 8071 if (MCInst_getNumOperands(MI) == 3 && 8072 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8073 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8074 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8075 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 8076 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8077 // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) 8078 AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #32"; 8079 break; 8080 } 8081 return NULL; 8082 case AArch64_LD1Fourv4s_POST: 8083 if (MCInst_getNumOperands(MI) == 3 && 8084 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8085 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8086 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8087 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 8088 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8089 // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) 8090 AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #64"; 8091 break; 8092 } 8093 return NULL; 8094 case AArch64_LD1Fourv8b_POST: 8095 if (MCInst_getNumOperands(MI) == 3 && 8096 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8097 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8098 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8099 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 8100 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8101 // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) 8102 AsmString = "ld1 $\xFF\x02\x10, [$\x01], #32"; 8103 break; 8104 } 8105 return NULL; 8106 case AArch64_LD1Fourv8h_POST: 8107 if (MCInst_getNumOperands(MI) == 3 && 8108 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8109 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8110 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8111 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 8112 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8113 // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) 8114 AsmString = "ld1 $\xFF\x02\x11, [$\x01], #64"; 8115 break; 8116 } 8117 return NULL; 8118 case AArch64_LD1Onev16b_POST: 8119 if (MCInst_getNumOperands(MI) == 3 && 8120 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8121 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8122 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8123 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8124 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8125 // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) 8126 AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #16"; 8127 break; 8128 } 8129 return NULL; 8130 case AArch64_LD1Onev1d_POST: 8131 if (MCInst_getNumOperands(MI) == 3 && 8132 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8133 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8134 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8135 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8136 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8137 // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) 8138 AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #8"; 8139 break; 8140 } 8141 return NULL; 8142 case AArch64_LD1Onev2d_POST: 8143 if (MCInst_getNumOperands(MI) == 3 && 8144 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8145 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8146 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8147 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8148 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8149 // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) 8150 AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #16"; 8151 break; 8152 } 8153 return NULL; 8154 case AArch64_LD1Onev2s_POST: 8155 if (MCInst_getNumOperands(MI) == 3 && 8156 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8157 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8158 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8159 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8160 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8161 // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) 8162 AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #8"; 8163 break; 8164 } 8165 return NULL; 8166 case AArch64_LD1Onev4h_POST: 8167 if (MCInst_getNumOperands(MI) == 3 && 8168 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8169 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8170 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8171 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8172 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8173 // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) 8174 AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #8"; 8175 break; 8176 } 8177 return NULL; 8178 case AArch64_LD1Onev4s_POST: 8179 if (MCInst_getNumOperands(MI) == 3 && 8180 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8181 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8182 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8183 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8184 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8185 // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) 8186 AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #16"; 8187 break; 8188 } 8189 return NULL; 8190 case AArch64_LD1Onev8b_POST: 8191 if (MCInst_getNumOperands(MI) == 3 && 8192 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8193 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8194 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8195 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8196 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8197 // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) 8198 AsmString = "ld1 $\xFF\x02\x10, [$\x01], #8"; 8199 break; 8200 } 8201 return NULL; 8202 case AArch64_LD1Onev8h_POST: 8203 if (MCInst_getNumOperands(MI) == 3 && 8204 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8205 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8206 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8207 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8208 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8209 // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) 8210 AsmString = "ld1 $\xFF\x02\x11, [$\x01], #16"; 8211 break; 8212 } 8213 return NULL; 8214 case AArch64_LD1Rv16b_POST: 8215 if (MCInst_getNumOperands(MI) == 3 && 8216 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8217 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8218 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8219 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8220 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8221 // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) 8222 AsmString = "ld1r $\xFF\x02\x0A, [$\x01], #1"; 8223 break; 8224 } 8225 return NULL; 8226 case AArch64_LD1Rv1d_POST: 8227 if (MCInst_getNumOperands(MI) == 3 && 8228 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8229 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8230 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8231 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8232 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8233 // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) 8234 AsmString = "ld1r $\xFF\x02\x0B, [$\x01], #8"; 8235 break; 8236 } 8237 return NULL; 8238 case AArch64_LD1Rv2d_POST: 8239 if (MCInst_getNumOperands(MI) == 3 && 8240 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8241 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8242 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8243 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8244 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8245 // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) 8246 AsmString = "ld1r $\xFF\x02\x0C, [$\x01], #8"; 8247 break; 8248 } 8249 return NULL; 8250 case AArch64_LD1Rv2s_POST: 8251 if (MCInst_getNumOperands(MI) == 3 && 8252 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8253 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8254 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8255 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8256 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8257 // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) 8258 AsmString = "ld1r $\xFF\x02\x0D, [$\x01], #4"; 8259 break; 8260 } 8261 return NULL; 8262 case AArch64_LD1Rv4h_POST: 8263 if (MCInst_getNumOperands(MI) == 3 && 8264 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8265 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8266 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8267 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8268 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8269 // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) 8270 AsmString = "ld1r $\xFF\x02\x0E, [$\x01], #2"; 8271 break; 8272 } 8273 return NULL; 8274 case AArch64_LD1Rv4s_POST: 8275 if (MCInst_getNumOperands(MI) == 3 && 8276 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8277 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8278 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8279 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8280 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8281 // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) 8282 AsmString = "ld1r $\xFF\x02\x0F, [$\x01], #4"; 8283 break; 8284 } 8285 return NULL; 8286 case AArch64_LD1Rv8b_POST: 8287 if (MCInst_getNumOperands(MI) == 3 && 8288 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8289 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8290 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8291 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 8292 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8293 // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) 8294 AsmString = "ld1r $\xFF\x02\x10, [$\x01], #1"; 8295 break; 8296 } 8297 return NULL; 8298 case AArch64_LD1Rv8h_POST: 8299 if (MCInst_getNumOperands(MI) == 3 && 8300 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8301 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8302 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8303 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8304 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8305 // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) 8306 AsmString = "ld1r $\xFF\x02\x11, [$\x01], #2"; 8307 break; 8308 } 8309 return NULL; 8310 case AArch64_LD1Threev16b_POST: 8311 if (MCInst_getNumOperands(MI) == 3 && 8312 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8313 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8314 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8315 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8316 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8317 // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) 8318 AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #48"; 8319 break; 8320 } 8321 return NULL; 8322 case AArch64_LD1Threev1d_POST: 8323 if (MCInst_getNumOperands(MI) == 3 && 8324 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8325 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8326 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8327 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8328 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8329 // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) 8330 AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #24"; 8331 break; 8332 } 8333 return NULL; 8334 case AArch64_LD1Threev2d_POST: 8335 if (MCInst_getNumOperands(MI) == 3 && 8336 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8337 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8338 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8339 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8340 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8341 // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) 8342 AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #48"; 8343 break; 8344 } 8345 return NULL; 8346 case AArch64_LD1Threev2s_POST: 8347 if (MCInst_getNumOperands(MI) == 3 && 8348 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8349 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8350 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8351 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8352 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8353 // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) 8354 AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #24"; 8355 break; 8356 } 8357 return NULL; 8358 case AArch64_LD1Threev4h_POST: 8359 if (MCInst_getNumOperands(MI) == 3 && 8360 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8361 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8362 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8363 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8364 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8365 // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) 8366 AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #24"; 8367 break; 8368 } 8369 return NULL; 8370 case AArch64_LD1Threev4s_POST: 8371 if (MCInst_getNumOperands(MI) == 3 && 8372 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8373 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8374 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8375 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8376 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8377 // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) 8378 AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #48"; 8379 break; 8380 } 8381 return NULL; 8382 case AArch64_LD1Threev8b_POST: 8383 if (MCInst_getNumOperands(MI) == 3 && 8384 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8385 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8386 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8387 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8388 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8389 // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) 8390 AsmString = "ld1 $\xFF\x02\x10, [$\x01], #24"; 8391 break; 8392 } 8393 return NULL; 8394 case AArch64_LD1Threev8h_POST: 8395 if (MCInst_getNumOperands(MI) == 3 && 8396 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8397 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8398 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8399 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8400 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8401 // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) 8402 AsmString = "ld1 $\xFF\x02\x11, [$\x01], #48"; 8403 break; 8404 } 8405 return NULL; 8406 case AArch64_LD1Twov16b_POST: 8407 if (MCInst_getNumOperands(MI) == 3 && 8408 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8409 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8410 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8411 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8412 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8413 // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) 8414 AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #32"; 8415 break; 8416 } 8417 return NULL; 8418 case AArch64_LD1Twov1d_POST: 8419 if (MCInst_getNumOperands(MI) == 3 && 8420 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8421 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8422 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8423 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8424 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8425 // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) 8426 AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #16"; 8427 break; 8428 } 8429 return NULL; 8430 case AArch64_LD1Twov2d_POST: 8431 if (MCInst_getNumOperands(MI) == 3 && 8432 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8433 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8434 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8435 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8436 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8437 // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) 8438 AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #32"; 8439 break; 8440 } 8441 return NULL; 8442 case AArch64_LD1Twov2s_POST: 8443 if (MCInst_getNumOperands(MI) == 3 && 8444 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8445 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8446 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8447 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8448 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8449 // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) 8450 AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #16"; 8451 break; 8452 } 8453 return NULL; 8454 case AArch64_LD1Twov4h_POST: 8455 if (MCInst_getNumOperands(MI) == 3 && 8456 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8457 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8458 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8459 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8460 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8461 // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) 8462 AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #16"; 8463 break; 8464 } 8465 return NULL; 8466 case AArch64_LD1Twov4s_POST: 8467 if (MCInst_getNumOperands(MI) == 3 && 8468 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8469 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8470 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8471 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8472 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8473 // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) 8474 AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #32"; 8475 break; 8476 } 8477 return NULL; 8478 case AArch64_LD1Twov8b_POST: 8479 if (MCInst_getNumOperands(MI) == 3 && 8480 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8481 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8482 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8483 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8484 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8485 // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) 8486 AsmString = "ld1 $\xFF\x02\x10, [$\x01], #16"; 8487 break; 8488 } 8489 return NULL; 8490 case AArch64_LD1Twov8h_POST: 8491 if (MCInst_getNumOperands(MI) == 3 && 8492 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8493 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8494 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8495 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8496 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8497 // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) 8498 AsmString = "ld1 $\xFF\x02\x11, [$\x01], #32"; 8499 break; 8500 } 8501 return NULL; 8502 case AArch64_LD1i16_POST: 8503 if (MCInst_getNumOperands(MI) == 4 && 8504 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8505 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8506 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8507 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8508 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8509 // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) 8510 AsmString = "ld1 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #2"; 8511 break; 8512 } 8513 return NULL; 8514 case AArch64_LD1i32_POST: 8515 if (MCInst_getNumOperands(MI) == 4 && 8516 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8517 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8518 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8519 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8520 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8521 // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) 8522 AsmString = "ld1 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #4"; 8523 break; 8524 } 8525 return NULL; 8526 case AArch64_LD1i64_POST: 8527 if (MCInst_getNumOperands(MI) == 4 && 8528 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8529 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8530 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8531 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8532 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8533 // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) 8534 AsmString = "ld1 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #8"; 8535 break; 8536 } 8537 return NULL; 8538 case AArch64_LD1i8_POST: 8539 if (MCInst_getNumOperands(MI) == 4 && 8540 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8541 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8542 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8543 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 8544 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8545 // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) 8546 AsmString = "ld1 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #1"; 8547 break; 8548 } 8549 return NULL; 8550 case AArch64_LD2Rv16b_POST: 8551 if (MCInst_getNumOperands(MI) == 3 && 8552 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8553 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8554 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8555 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8556 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8557 // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) 8558 AsmString = "ld2r $\xFF\x02\x0A, [$\x01], #2"; 8559 break; 8560 } 8561 return NULL; 8562 case AArch64_LD2Rv1d_POST: 8563 if (MCInst_getNumOperands(MI) == 3 && 8564 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8565 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8566 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8567 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8568 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8569 // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) 8570 AsmString = "ld2r $\xFF\x02\x0B, [$\x01], #16"; 8571 break; 8572 } 8573 return NULL; 8574 case AArch64_LD2Rv2d_POST: 8575 if (MCInst_getNumOperands(MI) == 3 && 8576 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8577 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8578 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8579 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8580 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8581 // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) 8582 AsmString = "ld2r $\xFF\x02\x0C, [$\x01], #16"; 8583 break; 8584 } 8585 return NULL; 8586 case AArch64_LD2Rv2s_POST: 8587 if (MCInst_getNumOperands(MI) == 3 && 8588 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8589 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8590 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8591 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8592 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8593 // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) 8594 AsmString = "ld2r $\xFF\x02\x0D, [$\x01], #8"; 8595 break; 8596 } 8597 return NULL; 8598 case AArch64_LD2Rv4h_POST: 8599 if (MCInst_getNumOperands(MI) == 3 && 8600 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8601 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8602 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8603 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8604 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8605 // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) 8606 AsmString = "ld2r $\xFF\x02\x0E, [$\x01], #4"; 8607 break; 8608 } 8609 return NULL; 8610 case AArch64_LD2Rv4s_POST: 8611 if (MCInst_getNumOperands(MI) == 3 && 8612 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8613 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8614 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8615 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8616 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8617 // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) 8618 AsmString = "ld2r $\xFF\x02\x0F, [$\x01], #8"; 8619 break; 8620 } 8621 return NULL; 8622 case AArch64_LD2Rv8b_POST: 8623 if (MCInst_getNumOperands(MI) == 3 && 8624 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8625 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8626 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8627 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8628 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8629 // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) 8630 AsmString = "ld2r $\xFF\x02\x10, [$\x01], #2"; 8631 break; 8632 } 8633 return NULL; 8634 case AArch64_LD2Rv8h_POST: 8635 if (MCInst_getNumOperands(MI) == 3 && 8636 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8637 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8638 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8639 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8640 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8641 // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) 8642 AsmString = "ld2r $\xFF\x02\x11, [$\x01], #4"; 8643 break; 8644 } 8645 return NULL; 8646 case AArch64_LD2Twov16b_POST: 8647 if (MCInst_getNumOperands(MI) == 3 && 8648 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8649 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8650 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8651 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8652 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8653 // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) 8654 AsmString = "ld2 $\xFF\x02\x0A, [$\x01], #32"; 8655 break; 8656 } 8657 return NULL; 8658 case AArch64_LD2Twov2d_POST: 8659 if (MCInst_getNumOperands(MI) == 3 && 8660 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8661 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8662 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8663 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8664 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8665 // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) 8666 AsmString = "ld2 $\xFF\x02\x0C, [$\x01], #32"; 8667 break; 8668 } 8669 return NULL; 8670 case AArch64_LD2Twov2s_POST: 8671 if (MCInst_getNumOperands(MI) == 3 && 8672 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8673 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8674 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8675 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8676 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8677 // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) 8678 AsmString = "ld2 $\xFF\x02\x0D, [$\x01], #16"; 8679 break; 8680 } 8681 return NULL; 8682 case AArch64_LD2Twov4h_POST: 8683 if (MCInst_getNumOperands(MI) == 3 && 8684 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8685 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8686 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8687 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8688 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8689 // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) 8690 AsmString = "ld2 $\xFF\x02\x0E, [$\x01], #16"; 8691 break; 8692 } 8693 return NULL; 8694 case AArch64_LD2Twov4s_POST: 8695 if (MCInst_getNumOperands(MI) == 3 && 8696 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8697 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8698 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8699 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8700 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8701 // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) 8702 AsmString = "ld2 $\xFF\x02\x0F, [$\x01], #32"; 8703 break; 8704 } 8705 return NULL; 8706 case AArch64_LD2Twov8b_POST: 8707 if (MCInst_getNumOperands(MI) == 3 && 8708 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8709 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8710 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8711 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 8712 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8713 // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) 8714 AsmString = "ld2 $\xFF\x02\x10, [$\x01], #16"; 8715 break; 8716 } 8717 return NULL; 8718 case AArch64_LD2Twov8h_POST: 8719 if (MCInst_getNumOperands(MI) == 3 && 8720 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8721 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8722 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8723 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8724 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8725 // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) 8726 AsmString = "ld2 $\xFF\x02\x11, [$\x01], #32"; 8727 break; 8728 } 8729 return NULL; 8730 case AArch64_LD2i16_POST: 8731 if (MCInst_getNumOperands(MI) == 4 && 8732 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8733 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8734 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8735 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8736 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8737 // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) 8738 AsmString = "ld2 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #4"; 8739 break; 8740 } 8741 return NULL; 8742 case AArch64_LD2i32_POST: 8743 if (MCInst_getNumOperands(MI) == 4 && 8744 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8745 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8746 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8747 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8748 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8749 // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) 8750 AsmString = "ld2 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #8"; 8751 break; 8752 } 8753 return NULL; 8754 case AArch64_LD2i64_POST: 8755 if (MCInst_getNumOperands(MI) == 4 && 8756 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8757 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8758 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8759 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8760 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8761 // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) 8762 AsmString = "ld2 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #16"; 8763 break; 8764 } 8765 return NULL; 8766 case AArch64_LD2i8_POST: 8767 if (MCInst_getNumOperands(MI) == 4 && 8768 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8769 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8770 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8771 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 8772 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8773 // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) 8774 AsmString = "ld2 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #2"; 8775 break; 8776 } 8777 return NULL; 8778 case AArch64_LD3Rv16b_POST: 8779 if (MCInst_getNumOperands(MI) == 3 && 8780 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8781 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8782 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8783 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8784 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8785 // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) 8786 AsmString = "ld3r $\xFF\x02\x0A, [$\x01], #3"; 8787 break; 8788 } 8789 return NULL; 8790 case AArch64_LD3Rv1d_POST: 8791 if (MCInst_getNumOperands(MI) == 3 && 8792 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8793 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8794 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8795 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8796 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8797 // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) 8798 AsmString = "ld3r $\xFF\x02\x0B, [$\x01], #24"; 8799 break; 8800 } 8801 return NULL; 8802 case AArch64_LD3Rv2d_POST: 8803 if (MCInst_getNumOperands(MI) == 3 && 8804 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8805 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8806 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8807 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8808 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8809 // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) 8810 AsmString = "ld3r $\xFF\x02\x0C, [$\x01], #24"; 8811 break; 8812 } 8813 return NULL; 8814 case AArch64_LD3Rv2s_POST: 8815 if (MCInst_getNumOperands(MI) == 3 && 8816 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8817 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8818 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8819 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8820 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8821 // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) 8822 AsmString = "ld3r $\xFF\x02\x0D, [$\x01], #12"; 8823 break; 8824 } 8825 return NULL; 8826 case AArch64_LD3Rv4h_POST: 8827 if (MCInst_getNumOperands(MI) == 3 && 8828 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8829 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8830 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8831 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8832 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8833 // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) 8834 AsmString = "ld3r $\xFF\x02\x0E, [$\x01], #6"; 8835 break; 8836 } 8837 return NULL; 8838 case AArch64_LD3Rv4s_POST: 8839 if (MCInst_getNumOperands(MI) == 3 && 8840 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8841 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8842 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8843 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8844 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8845 // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) 8846 AsmString = "ld3r $\xFF\x02\x0F, [$\x01], #12"; 8847 break; 8848 } 8849 return NULL; 8850 case AArch64_LD3Rv8b_POST: 8851 if (MCInst_getNumOperands(MI) == 3 && 8852 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8853 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8854 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8855 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8856 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8857 // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) 8858 AsmString = "ld3r $\xFF\x02\x10, [$\x01], #3"; 8859 break; 8860 } 8861 return NULL; 8862 case AArch64_LD3Rv8h_POST: 8863 if (MCInst_getNumOperands(MI) == 3 && 8864 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8865 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8866 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8867 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8868 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8869 // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) 8870 AsmString = "ld3r $\xFF\x02\x11, [$\x01], #6"; 8871 break; 8872 } 8873 return NULL; 8874 case AArch64_LD3Threev16b_POST: 8875 if (MCInst_getNumOperands(MI) == 3 && 8876 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8877 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8878 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8879 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8880 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8881 // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) 8882 AsmString = "ld3 $\xFF\x02\x0A, [$\x01], #48"; 8883 break; 8884 } 8885 return NULL; 8886 case AArch64_LD3Threev2d_POST: 8887 if (MCInst_getNumOperands(MI) == 3 && 8888 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8889 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8890 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8891 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8892 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8893 // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) 8894 AsmString = "ld3 $\xFF\x02\x0C, [$\x01], #48"; 8895 break; 8896 } 8897 return NULL; 8898 case AArch64_LD3Threev2s_POST: 8899 if (MCInst_getNumOperands(MI) == 3 && 8900 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8901 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8902 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8903 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8904 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8905 // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) 8906 AsmString = "ld3 $\xFF\x02\x0D, [$\x01], #24"; 8907 break; 8908 } 8909 return NULL; 8910 case AArch64_LD3Threev4h_POST: 8911 if (MCInst_getNumOperands(MI) == 3 && 8912 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8913 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8914 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8915 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8916 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8917 // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) 8918 AsmString = "ld3 $\xFF\x02\x0E, [$\x01], #24"; 8919 break; 8920 } 8921 return NULL; 8922 case AArch64_LD3Threev4s_POST: 8923 if (MCInst_getNumOperands(MI) == 3 && 8924 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8925 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8926 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8927 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8928 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8929 // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) 8930 AsmString = "ld3 $\xFF\x02\x0F, [$\x01], #48"; 8931 break; 8932 } 8933 return NULL; 8934 case AArch64_LD3Threev8b_POST: 8935 if (MCInst_getNumOperands(MI) == 3 && 8936 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8937 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8938 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8939 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 8940 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8941 // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) 8942 AsmString = "ld3 $\xFF\x02\x10, [$\x01], #24"; 8943 break; 8944 } 8945 return NULL; 8946 case AArch64_LD3Threev8h_POST: 8947 if (MCInst_getNumOperands(MI) == 3 && 8948 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8949 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8950 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8951 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8952 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 8953 // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) 8954 AsmString = "ld3 $\xFF\x02\x11, [$\x01], #48"; 8955 break; 8956 } 8957 return NULL; 8958 case AArch64_LD3i16_POST: 8959 if (MCInst_getNumOperands(MI) == 4 && 8960 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8961 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8962 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8963 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8964 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8965 // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) 8966 AsmString = "ld3 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #6"; 8967 break; 8968 } 8969 return NULL; 8970 case AArch64_LD3i32_POST: 8971 if (MCInst_getNumOperands(MI) == 4 && 8972 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8973 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8974 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8975 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8976 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8977 // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) 8978 AsmString = "ld3 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #12"; 8979 break; 8980 } 8981 return NULL; 8982 case AArch64_LD3i64_POST: 8983 if (MCInst_getNumOperands(MI) == 4 && 8984 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8985 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8986 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8987 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 8988 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 8989 // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) 8990 AsmString = "ld3 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #24"; 8991 break; 8992 } 8993 return NULL; 8994 case AArch64_LD3i8_POST: 8995 if (MCInst_getNumOperands(MI) == 4 && 8996 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 8997 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 8998 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 8999 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 9000 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 9001 // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) 9002 AsmString = "ld3 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #3"; 9003 break; 9004 } 9005 return NULL; 9006 case AArch64_LD4Fourv16b_POST: 9007 if (MCInst_getNumOperands(MI) == 3 && 9008 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9009 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9010 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9011 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9012 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9013 // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) 9014 AsmString = "ld4 $\xFF\x02\x0A, [$\x01], #64"; 9015 break; 9016 } 9017 return NULL; 9018 case AArch64_LD4Fourv2d_POST: 9019 if (MCInst_getNumOperands(MI) == 3 && 9020 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9021 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9022 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9023 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9024 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9025 // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) 9026 AsmString = "ld4 $\xFF\x02\x0C, [$\x01], #64"; 9027 break; 9028 } 9029 return NULL; 9030 case AArch64_LD4Fourv2s_POST: 9031 if (MCInst_getNumOperands(MI) == 3 && 9032 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9033 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9034 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9035 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 9036 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9037 // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) 9038 AsmString = "ld4 $\xFF\x02\x0D, [$\x01], #32"; 9039 break; 9040 } 9041 return NULL; 9042 case AArch64_LD4Fourv4h_POST: 9043 if (MCInst_getNumOperands(MI) == 3 && 9044 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9045 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9046 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9047 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 9048 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9049 // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) 9050 AsmString = "ld4 $\xFF\x02\x0E, [$\x01], #32"; 9051 break; 9052 } 9053 return NULL; 9054 case AArch64_LD4Fourv4s_POST: 9055 if (MCInst_getNumOperands(MI) == 3 && 9056 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9057 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9058 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9059 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9060 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9061 // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) 9062 AsmString = "ld4 $\xFF\x02\x0F, [$\x01], #64"; 9063 break; 9064 } 9065 return NULL; 9066 case AArch64_LD4Fourv8b_POST: 9067 if (MCInst_getNumOperands(MI) == 3 && 9068 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9069 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9070 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9071 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 9072 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9073 // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) 9074 AsmString = "ld4 $\xFF\x02\x10, [$\x01], #32"; 9075 break; 9076 } 9077 return NULL; 9078 case AArch64_LD4Fourv8h_POST: 9079 if (MCInst_getNumOperands(MI) == 3 && 9080 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9081 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9082 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9083 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9084 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9085 // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) 9086 AsmString = "ld4 $\xFF\x02\x11, [$\x01], #64"; 9087 break; 9088 } 9089 return NULL; 9090 case AArch64_LD4Rv16b_POST: 9091 if (MCInst_getNumOperands(MI) == 3 && 9092 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9093 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9094 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9095 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9096 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9097 // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) 9098 AsmString = "ld4r $\xFF\x02\x0A, [$\x01], #4"; 9099 break; 9100 } 9101 return NULL; 9102 case AArch64_LD4Rv1d_POST: 9103 if (MCInst_getNumOperands(MI) == 3 && 9104 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9105 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9106 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9107 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 9108 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9109 // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) 9110 AsmString = "ld4r $\xFF\x02\x0B, [$\x01], #32"; 9111 break; 9112 } 9113 return NULL; 9114 case AArch64_LD4Rv2d_POST: 9115 if (MCInst_getNumOperands(MI) == 3 && 9116 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9117 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9118 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9119 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9120 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9121 // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) 9122 AsmString = "ld4r $\xFF\x02\x0C, [$\x01], #32"; 9123 break; 9124 } 9125 return NULL; 9126 case AArch64_LD4Rv2s_POST: 9127 if (MCInst_getNumOperands(MI) == 3 && 9128 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9129 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9130 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9131 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 9132 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9133 // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) 9134 AsmString = "ld4r $\xFF\x02\x0D, [$\x01], #16"; 9135 break; 9136 } 9137 return NULL; 9138 case AArch64_LD4Rv4h_POST: 9139 if (MCInst_getNumOperands(MI) == 3 && 9140 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9141 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9142 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9143 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 9144 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9145 // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) 9146 AsmString = "ld4r $\xFF\x02\x0E, [$\x01], #8"; 9147 break; 9148 } 9149 return NULL; 9150 case AArch64_LD4Rv4s_POST: 9151 if (MCInst_getNumOperands(MI) == 3 && 9152 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9153 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9154 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9155 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9156 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9157 // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) 9158 AsmString = "ld4r $\xFF\x02\x0F, [$\x01], #16"; 9159 break; 9160 } 9161 return NULL; 9162 case AArch64_LD4Rv8b_POST: 9163 if (MCInst_getNumOperands(MI) == 3 && 9164 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9165 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9166 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9167 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 9168 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9169 // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) 9170 AsmString = "ld4r $\xFF\x02\x10, [$\x01], #4"; 9171 break; 9172 } 9173 return NULL; 9174 case AArch64_LD4Rv8h_POST: 9175 if (MCInst_getNumOperands(MI) == 3 && 9176 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9177 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9178 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9179 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9180 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 9181 // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) 9182 AsmString = "ld4r $\xFF\x02\x11, [$\x01], #8"; 9183 break; 9184 } 9185 return NULL; 9186 case AArch64_LD4i16_POST: 9187 if (MCInst_getNumOperands(MI) == 4 && 9188 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9189 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9190 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9191 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9192 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 9193 // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) 9194 AsmString = "ld4 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #8"; 9195 break; 9196 } 9197 return NULL; 9198 case AArch64_LD4i32_POST: 9199 if (MCInst_getNumOperands(MI) == 4 && 9200 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9201 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9202 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9203 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9204 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 9205 // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) 9206 AsmString = "ld4 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #16"; 9207 break; 9208 } 9209 return NULL; 9210 case AArch64_LD4i64_POST: 9211 if (MCInst_getNumOperands(MI) == 4 && 9212 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9213 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9214 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9215 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9216 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 9217 // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) 9218 AsmString = "ld4 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #32"; 9219 break; 9220 } 9221 return NULL; 9222 case AArch64_LD4i8_POST: 9223 if (MCInst_getNumOperands(MI) == 4 && 9224 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9225 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 9226 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9227 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 9228 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 9229 // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) 9230 AsmString = "ld4 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #4"; 9231 break; 9232 } 9233 return NULL; 9234 case AArch64_LDNPDi: 9235 if (MCInst_getNumOperands(MI) == 4 && 9236 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9237 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 9238 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9239 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 9240 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9241 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9242 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9243 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9244 // (LDNPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) 9245 AsmString = "ldnp $\x01, $\x02, [$\x03]"; 9246 break; 9247 } 9248 return NULL; 9249 case AArch64_LDNPQi: 9250 if (MCInst_getNumOperands(MI) == 4 && 9251 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9252 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 9253 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9254 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 9255 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9256 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9257 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9258 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9259 // (LDNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) 9260 AsmString = "ldnp $\x01, $\x02, [$\x03]"; 9261 break; 9262 } 9263 return NULL; 9264 case AArch64_LDNPSi: 9265 if (MCInst_getNumOperands(MI) == 4 && 9266 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9267 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 9268 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9269 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && 9270 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9271 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9272 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9273 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9274 // (LDNPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) 9275 AsmString = "ldnp $\x01, $\x02, [$\x03]"; 9276 break; 9277 } 9278 return NULL; 9279 case AArch64_LDNPWi: 9280 if (MCInst_getNumOperands(MI) == 4 && 9281 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9282 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9283 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9284 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 9285 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9286 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9287 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9288 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9289 // (LDNPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) 9290 AsmString = "ldnp $\x01, $\x02, [$\x03]"; 9291 break; 9292 } 9293 return NULL; 9294 case AArch64_LDNPXi: 9295 if (MCInst_getNumOperands(MI) == 4 && 9296 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9297 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9298 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9299 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 9300 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9301 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9302 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9303 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9304 // (LDNPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) 9305 AsmString = "ldnp $\x01, $\x02, [$\x03]"; 9306 break; 9307 } 9308 return NULL; 9309 case AArch64_LDPDi: 9310 if (MCInst_getNumOperands(MI) == 4 && 9311 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9312 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 9313 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9314 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 9315 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9316 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9317 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9318 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9319 // (LDPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) 9320 AsmString = "ldp $\x01, $\x02, [$\x03]"; 9321 break; 9322 } 9323 return NULL; 9324 case AArch64_LDPQi: 9325 if (MCInst_getNumOperands(MI) == 4 && 9326 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9327 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 9328 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9329 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 9330 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9331 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9332 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9333 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9334 // (LDPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) 9335 AsmString = "ldp $\x01, $\x02, [$\x03]"; 9336 break; 9337 } 9338 return NULL; 9339 case AArch64_LDPSWi: 9340 if (MCInst_getNumOperands(MI) == 4 && 9341 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9342 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9343 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9344 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 9345 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9346 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9347 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9348 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9349 // (LDPSWi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) 9350 AsmString = "ldpsw $\x01, $\x02, [$\x03]"; 9351 break; 9352 } 9353 return NULL; 9354 case AArch64_LDPSi: 9355 if (MCInst_getNumOperands(MI) == 4 && 9356 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9357 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 9358 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9359 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && 9360 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9361 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9362 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9363 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9364 // (LDPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) 9365 AsmString = "ldp $\x01, $\x02, [$\x03]"; 9366 break; 9367 } 9368 return NULL; 9369 case AArch64_LDPWi: 9370 if (MCInst_getNumOperands(MI) == 4 && 9371 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9372 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9373 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9374 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 9375 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9376 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9377 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9378 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9379 // (LDPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) 9380 AsmString = "ldp $\x01, $\x02, [$\x03]"; 9381 break; 9382 } 9383 return NULL; 9384 case AArch64_LDPXi: 9385 if (MCInst_getNumOperands(MI) == 4 && 9386 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9387 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9388 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9389 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 9390 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9391 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 9392 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9393 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 9394 // (LDPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) 9395 AsmString = "ldp $\x01, $\x02, [$\x03]"; 9396 break; 9397 } 9398 return NULL; 9399 case AArch64_LDRBBroX: 9400 if (MCInst_getNumOperands(MI) == 5 && 9401 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9402 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9403 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9404 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9405 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9406 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9407 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9408 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9409 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9410 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9411 // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9412 AsmString = "ldrb $\x01, [$\x02, $\x03]"; 9413 break; 9414 } 9415 return NULL; 9416 case AArch64_LDRBBui: 9417 if (MCInst_getNumOperands(MI) == 3 && 9418 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9419 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9420 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9421 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9422 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9423 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9424 // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) 9425 AsmString = "ldrb $\x01, [$\x02]"; 9426 break; 9427 } 9428 return NULL; 9429 case AArch64_LDRBroX: 9430 if (MCInst_getNumOperands(MI) == 5 && 9431 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9432 GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && 9433 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9434 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9435 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9436 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9437 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9438 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9439 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9440 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9441 // (LDRBroX FPR8:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9442 AsmString = "ldr $\x01, [$\x02, $\x03]"; 9443 break; 9444 } 9445 return NULL; 9446 case AArch64_LDRBui: 9447 if (MCInst_getNumOperands(MI) == 3 && 9448 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9449 GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && 9450 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9451 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9452 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9453 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9454 // (LDRBui FPR8:$Rt, GPR64sp:$Rn, 0) 9455 AsmString = "ldr $\x01, [$\x02]"; 9456 break; 9457 } 9458 return NULL; 9459 case AArch64_LDRDroX: 9460 if (MCInst_getNumOperands(MI) == 5 && 9461 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9462 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 9463 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9464 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9465 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9466 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9467 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9468 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9469 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9470 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9471 // (LDRDroX FPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9472 AsmString = "ldr $\x01, [$\x02, $\x03]"; 9473 break; 9474 } 9475 return NULL; 9476 case AArch64_LDRDui: 9477 if (MCInst_getNumOperands(MI) == 3 && 9478 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9479 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 9480 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9481 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9482 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9483 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9484 // (LDRDui FPR64:$Rt, GPR64sp:$Rn, 0) 9485 AsmString = "ldr $\x01, [$\x02]"; 9486 break; 9487 } 9488 return NULL; 9489 case AArch64_LDRHHroX: 9490 if (MCInst_getNumOperands(MI) == 5 && 9491 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9492 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9493 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9494 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9495 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9496 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9497 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9498 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9499 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9500 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9501 // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9502 AsmString = "ldrh $\x01, [$\x02, $\x03]"; 9503 break; 9504 } 9505 return NULL; 9506 case AArch64_LDRHHui: 9507 if (MCInst_getNumOperands(MI) == 3 && 9508 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9509 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9510 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9511 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9512 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9513 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9514 // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) 9515 AsmString = "ldrh $\x01, [$\x02]"; 9516 break; 9517 } 9518 return NULL; 9519 case AArch64_LDRHroX: 9520 if (MCInst_getNumOperands(MI) == 5 && 9521 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9522 GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && 9523 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9524 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9525 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9526 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9527 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9528 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9529 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9530 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9531 // (LDRHroX FPR16:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9532 AsmString = "ldr $\x01, [$\x02, $\x03]"; 9533 break; 9534 } 9535 return NULL; 9536 case AArch64_LDRHui: 9537 if (MCInst_getNumOperands(MI) == 3 && 9538 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9539 GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && 9540 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9541 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9542 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9543 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9544 // (LDRHui FPR16:$Rt, GPR64sp:$Rn, 0) 9545 AsmString = "ldr $\x01, [$\x02]"; 9546 break; 9547 } 9548 return NULL; 9549 case AArch64_LDRQroX: 9550 if (MCInst_getNumOperands(MI) == 5 && 9551 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9552 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 9553 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9554 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9555 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9556 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9557 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9558 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9559 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9560 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9561 // (LDRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9562 AsmString = "ldr $\x01, [$\x02, $\x03]"; 9563 break; 9564 } 9565 return NULL; 9566 case AArch64_LDRQui: 9567 if (MCInst_getNumOperands(MI) == 3 && 9568 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9569 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 9570 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9571 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9572 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9573 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9574 // (LDRQui FPR128:$Rt, GPR64sp:$Rn, 0) 9575 AsmString = "ldr $\x01, [$\x02]"; 9576 break; 9577 } 9578 return NULL; 9579 case AArch64_LDRSBWroX: 9580 if (MCInst_getNumOperands(MI) == 5 && 9581 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9582 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9583 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9584 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9585 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9586 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9587 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9588 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9589 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9590 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9591 // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9592 AsmString = "ldrsb $\x01, [$\x02, $\x03]"; 9593 break; 9594 } 9595 return NULL; 9596 case AArch64_LDRSBWui: 9597 if (MCInst_getNumOperands(MI) == 3 && 9598 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9599 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9600 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9601 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9602 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9603 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9604 // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) 9605 AsmString = "ldrsb $\x01, [$\x02]"; 9606 break; 9607 } 9608 return NULL; 9609 case AArch64_LDRSBXroX: 9610 if (MCInst_getNumOperands(MI) == 5 && 9611 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9612 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9613 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9614 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9615 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9616 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9617 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9618 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9619 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9620 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9621 // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9622 AsmString = "ldrsb $\x01, [$\x02, $\x03]"; 9623 break; 9624 } 9625 return NULL; 9626 case AArch64_LDRSBXui: 9627 if (MCInst_getNumOperands(MI) == 3 && 9628 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9629 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9630 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9631 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9632 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9633 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9634 // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) 9635 AsmString = "ldrsb $\x01, [$\x02]"; 9636 break; 9637 } 9638 return NULL; 9639 case AArch64_LDRSHWroX: 9640 if (MCInst_getNumOperands(MI) == 5 && 9641 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9642 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9643 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9644 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9645 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9646 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9647 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9648 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9649 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9650 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9651 // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9652 AsmString = "ldrsh $\x01, [$\x02, $\x03]"; 9653 break; 9654 } 9655 return NULL; 9656 case AArch64_LDRSHWui: 9657 if (MCInst_getNumOperands(MI) == 3 && 9658 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9659 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9660 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9661 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9662 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9663 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9664 // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) 9665 AsmString = "ldrsh $\x01, [$\x02]"; 9666 break; 9667 } 9668 return NULL; 9669 case AArch64_LDRSHXroX: 9670 if (MCInst_getNumOperands(MI) == 5 && 9671 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9672 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9673 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9674 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9675 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9676 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9677 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9678 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9679 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9680 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9681 // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9682 AsmString = "ldrsh $\x01, [$\x02, $\x03]"; 9683 break; 9684 } 9685 return NULL; 9686 case AArch64_LDRSHXui: 9687 if (MCInst_getNumOperands(MI) == 3 && 9688 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9689 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9690 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9691 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9692 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9693 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9694 // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) 9695 AsmString = "ldrsh $\x01, [$\x02]"; 9696 break; 9697 } 9698 return NULL; 9699 case AArch64_LDRSWroX: 9700 if (MCInst_getNumOperands(MI) == 5 && 9701 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9702 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9703 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9704 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9705 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9706 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9707 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9708 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9709 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9710 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9711 // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9712 AsmString = "ldrsw $\x01, [$\x02, $\x03]"; 9713 break; 9714 } 9715 return NULL; 9716 case AArch64_LDRSWui: 9717 if (MCInst_getNumOperands(MI) == 3 && 9718 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9719 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9720 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9721 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9722 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9723 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9724 // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) 9725 AsmString = "ldrsw $\x01, [$\x02]"; 9726 break; 9727 } 9728 return NULL; 9729 case AArch64_LDRSroX: 9730 if (MCInst_getNumOperands(MI) == 5 && 9731 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9732 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 9733 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9734 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9735 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9736 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9737 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9738 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9739 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9740 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9741 // (LDRSroX FPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9742 AsmString = "ldr $\x01, [$\x02, $\x03]"; 9743 break; 9744 } 9745 return NULL; 9746 case AArch64_LDRSui: 9747 if (MCInst_getNumOperands(MI) == 3 && 9748 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9749 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 9750 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9751 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9752 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9753 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9754 // (LDRSui FPR32:$Rt, GPR64sp:$Rn, 0) 9755 AsmString = "ldr $\x01, [$\x02]"; 9756 break; 9757 } 9758 return NULL; 9759 case AArch64_LDRWroX: 9760 if (MCInst_getNumOperands(MI) == 5 && 9761 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9762 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9763 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9764 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9765 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9766 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9767 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9768 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9769 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9770 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9771 // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9772 AsmString = "ldr $\x01, [$\x02, $\x03]"; 9773 break; 9774 } 9775 return NULL; 9776 case AArch64_LDRWui: 9777 if (MCInst_getNumOperands(MI) == 3 && 9778 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9779 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9780 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9781 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9782 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9783 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9784 // (LDRWui GPR32:$Rt, GPR64sp:$Rn, 0) 9785 AsmString = "ldr $\x01, [$\x02]"; 9786 break; 9787 } 9788 return NULL; 9789 case AArch64_LDRXroX: 9790 if (MCInst_getNumOperands(MI) == 5 && 9791 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9792 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9793 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9794 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9795 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 9796 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 9797 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 9798 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 9799 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 9800 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 9801 // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 9802 AsmString = "ldr $\x01, [$\x02, $\x03]"; 9803 break; 9804 } 9805 return NULL; 9806 case AArch64_LDRXui: 9807 if (MCInst_getNumOperands(MI) == 3 && 9808 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9809 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9810 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9811 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9812 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9813 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9814 // (LDRXui GPR64:$Rt, GPR64sp:$Rn, 0) 9815 AsmString = "ldr $\x01, [$\x02]"; 9816 break; 9817 } 9818 return NULL; 9819 case AArch64_LDTRBi: 9820 if (MCInst_getNumOperands(MI) == 3 && 9821 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9822 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9823 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9824 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9825 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9826 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9827 // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) 9828 AsmString = "ldtrb $\x01, [$\x02]"; 9829 break; 9830 } 9831 return NULL; 9832 case AArch64_LDTRHi: 9833 if (MCInst_getNumOperands(MI) == 3 && 9834 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9835 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9836 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9837 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9838 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9839 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9840 // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) 9841 AsmString = "ldtrh $\x01, [$\x02]"; 9842 break; 9843 } 9844 return NULL; 9845 case AArch64_LDTRSBWi: 9846 if (MCInst_getNumOperands(MI) == 3 && 9847 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9848 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9849 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9850 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9851 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9852 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9853 // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) 9854 AsmString = "ldtrsb $\x01, [$\x02]"; 9855 break; 9856 } 9857 return NULL; 9858 case AArch64_LDTRSBXi: 9859 if (MCInst_getNumOperands(MI) == 3 && 9860 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9861 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9862 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9863 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9864 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9865 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9866 // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) 9867 AsmString = "ldtrsb $\x01, [$\x02]"; 9868 break; 9869 } 9870 return NULL; 9871 case AArch64_LDTRSHWi: 9872 if (MCInst_getNumOperands(MI) == 3 && 9873 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9874 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9875 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9876 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9877 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9878 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9879 // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) 9880 AsmString = "ldtrsh $\x01, [$\x02]"; 9881 break; 9882 } 9883 return NULL; 9884 case AArch64_LDTRSHXi: 9885 if (MCInst_getNumOperands(MI) == 3 && 9886 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9887 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9888 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9889 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9890 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9891 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9892 // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) 9893 AsmString = "ldtrsh $\x01, [$\x02]"; 9894 break; 9895 } 9896 return NULL; 9897 case AArch64_LDTRSWi: 9898 if (MCInst_getNumOperands(MI) == 3 && 9899 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9900 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9901 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9902 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9903 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9904 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9905 // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) 9906 AsmString = "ldtrsw $\x01, [$\x02]"; 9907 break; 9908 } 9909 return NULL; 9910 case AArch64_LDTRWi: 9911 if (MCInst_getNumOperands(MI) == 3 && 9912 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9913 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9914 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9915 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9916 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9917 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9918 // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) 9919 AsmString = "ldtr $\x01, [$\x02]"; 9920 break; 9921 } 9922 return NULL; 9923 case AArch64_LDTRXi: 9924 if (MCInst_getNumOperands(MI) == 3 && 9925 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9926 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 9927 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9928 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9929 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9930 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9931 // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) 9932 AsmString = "ldtr $\x01, [$\x02]"; 9933 break; 9934 } 9935 return NULL; 9936 case AArch64_LDURBBi: 9937 if (MCInst_getNumOperands(MI) == 3 && 9938 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9939 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9940 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9941 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9942 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9943 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9944 // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) 9945 AsmString = "ldurb $\x01, [$\x02]"; 9946 break; 9947 } 9948 return NULL; 9949 case AArch64_LDURBi: 9950 if (MCInst_getNumOperands(MI) == 3 && 9951 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9952 GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && 9953 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9954 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9955 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9956 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9957 // (LDURBi FPR8:$Rt, GPR64sp:$Rn, 0) 9958 AsmString = "ldur $\x01, [$\x02]"; 9959 break; 9960 } 9961 return NULL; 9962 case AArch64_LDURDi: 9963 if (MCInst_getNumOperands(MI) == 3 && 9964 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9965 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 9966 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9967 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9968 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9969 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9970 // (LDURDi FPR64:$Rt, GPR64sp:$Rn, 0) 9971 AsmString = "ldur $\x01, [$\x02]"; 9972 break; 9973 } 9974 return NULL; 9975 case AArch64_LDURHHi: 9976 if (MCInst_getNumOperands(MI) == 3 && 9977 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9978 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 9979 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9980 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9981 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9982 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9983 // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) 9984 AsmString = "ldurh $\x01, [$\x02]"; 9985 break; 9986 } 9987 return NULL; 9988 case AArch64_LDURHi: 9989 if (MCInst_getNumOperands(MI) == 3 && 9990 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 9991 GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && 9992 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 9993 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 9994 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 9995 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 9996 // (LDURHi FPR16:$Rt, GPR64sp:$Rn, 0) 9997 AsmString = "ldur $\x01, [$\x02]"; 9998 break; 9999 } 10000 return NULL; 10001 case AArch64_LDURQi: 10002 if (MCInst_getNumOperands(MI) == 3 && 10003 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10004 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 10005 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10006 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10007 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10008 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10009 // (LDURQi FPR128:$Rt, GPR64sp:$Rn, 0) 10010 AsmString = "ldur $\x01, [$\x02]"; 10011 break; 10012 } 10013 return NULL; 10014 case AArch64_LDURSBWi: 10015 if (MCInst_getNumOperands(MI) == 3 && 10016 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10017 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10018 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10019 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10020 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10021 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10022 // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) 10023 AsmString = "ldursb $\x01, [$\x02]"; 10024 break; 10025 } 10026 return NULL; 10027 case AArch64_LDURSBXi: 10028 if (MCInst_getNumOperands(MI) == 3 && 10029 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10030 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10031 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10032 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10033 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10034 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10035 // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) 10036 AsmString = "ldursb $\x01, [$\x02]"; 10037 break; 10038 } 10039 return NULL; 10040 case AArch64_LDURSHWi: 10041 if (MCInst_getNumOperands(MI) == 3 && 10042 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10043 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10044 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10045 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10046 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10047 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10048 // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) 10049 AsmString = "ldursh $\x01, [$\x02]"; 10050 break; 10051 } 10052 return NULL; 10053 case AArch64_LDURSHXi: 10054 if (MCInst_getNumOperands(MI) == 3 && 10055 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10056 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10057 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10058 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10059 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10060 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10061 // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) 10062 AsmString = "ldursh $\x01, [$\x02]"; 10063 break; 10064 } 10065 return NULL; 10066 case AArch64_LDURSWi: 10067 if (MCInst_getNumOperands(MI) == 3 && 10068 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10069 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10070 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10071 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10072 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10073 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10074 // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) 10075 AsmString = "ldursw $\x01, [$\x02]"; 10076 break; 10077 } 10078 return NULL; 10079 case AArch64_LDURSi: 10080 if (MCInst_getNumOperands(MI) == 3 && 10081 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10082 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 10083 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10084 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10085 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10086 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10087 // (LDURSi FPR32:$Rt, GPR64sp:$Rn, 0) 10088 AsmString = "ldur $\x01, [$\x02]"; 10089 break; 10090 } 10091 return NULL; 10092 case AArch64_LDURWi: 10093 if (MCInst_getNumOperands(MI) == 3 && 10094 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10095 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10096 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10097 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10098 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10099 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10100 // (LDURWi GPR32:$Rt, GPR64sp:$Rn, 0) 10101 AsmString = "ldur $\x01, [$\x02]"; 10102 break; 10103 } 10104 return NULL; 10105 case AArch64_LDURXi: 10106 if (MCInst_getNumOperands(MI) == 3 && 10107 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10108 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10109 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10110 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10111 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10112 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10113 // (LDURXi GPR64:$Rt, GPR64sp:$Rn, 0) 10114 AsmString = "ldur $\x01, [$\x02]"; 10115 break; 10116 } 10117 return NULL; 10118 case AArch64_MADDWrrr: 10119 if (MCInst_getNumOperands(MI) == 4 && 10120 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10121 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10122 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10123 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10124 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10125 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10126 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) { 10127 // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) 10128 AsmString = "mul $\x01, $\x02, $\x03"; 10129 break; 10130 } 10131 return NULL; 10132 case AArch64_MADDXrrr: 10133 if (MCInst_getNumOperands(MI) == 4 && 10134 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10135 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10136 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10137 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10138 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10139 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 10140 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 10141 // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) 10142 AsmString = "mul $\x01, $\x02, $\x03"; 10143 break; 10144 } 10145 return NULL; 10146 case AArch64_MOVKWi: 10147 if (MCInst_getNumOperands(MI) == 3 && 10148 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10149 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10150 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10151 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16) { 10152 // (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16) 10153 AsmString = "movk $\x01, $\x02"; 10154 break; 10155 } 10156 return NULL; 10157 case AArch64_MOVKXi: 10158 if (MCInst_getNumOperands(MI) == 3 && 10159 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10160 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10161 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10162 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 48) { 10163 // (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48) 10164 AsmString = "movk $\x01, $\x02"; 10165 break; 10166 } 10167 if (MCInst_getNumOperands(MI) == 3 && 10168 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10169 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10170 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10171 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32) { 10172 // (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32) 10173 AsmString = "movk $\x01, $\x02"; 10174 break; 10175 } 10176 if (MCInst_getNumOperands(MI) == 3 && 10177 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10178 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10179 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10180 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16) { 10181 // (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16) 10182 AsmString = "movk $\x01, $\x02"; 10183 break; 10184 } 10185 return NULL; 10186 case AArch64_MSUBWrrr: 10187 if (MCInst_getNumOperands(MI) == 4 && 10188 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10189 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10190 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10191 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10192 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10193 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10194 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) { 10195 // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) 10196 AsmString = "mneg $\x01, $\x02, $\x03"; 10197 break; 10198 } 10199 return NULL; 10200 case AArch64_MSUBXrrr: 10201 if (MCInst_getNumOperands(MI) == 4 && 10202 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10203 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10204 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10205 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10206 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10207 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 10208 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 10209 // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) 10210 AsmString = "mneg $\x01, $\x02, $\x03"; 10211 break; 10212 } 10213 return NULL; 10214 case AArch64_NOTv16i8: 10215 if (MCInst_getNumOperands(MI) == 2 && 10216 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10217 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 10218 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10219 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { 10220 // (NOTv16i8 V128:$Vd, V128:$Vn) 10221 AsmString = "mvn $\xFF\x01\x06.16b, $\xFF\x02\x06.16b"; 10222 break; 10223 } 10224 return NULL; 10225 case AArch64_NOTv8i8: 10226 if (MCInst_getNumOperands(MI) == 2 && 10227 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10228 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 10229 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10230 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1)) { 10231 // (NOTv8i8 V64:$Vd, V64:$Vn) 10232 AsmString = "mvn $\xFF\x01\x06.8b, $\xFF\x02\x06.8b"; 10233 break; 10234 } 10235 return NULL; 10236 case AArch64_ORNWrs: 10237 if (MCInst_getNumOperands(MI) == 4 && 10238 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10239 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10240 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 10241 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10242 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10243 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10244 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10245 // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0) 10246 AsmString = "mvn $\x01, $\x03"; 10247 break; 10248 } 10249 if (MCInst_getNumOperands(MI) == 4 && 10250 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10251 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10252 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 10253 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10254 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 10255 // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh) 10256 AsmString = "mvn $\x01, $\x03$\xFF\x04\x02"; 10257 break; 10258 } 10259 if (MCInst_getNumOperands(MI) == 4 && 10260 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10261 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10262 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10263 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10264 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10265 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10266 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10267 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10268 // (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 10269 AsmString = "orn $\x01, $\x02, $\x03"; 10270 break; 10271 } 10272 return NULL; 10273 case AArch64_ORNXrs: 10274 if (MCInst_getNumOperands(MI) == 4 && 10275 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10276 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10277 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 10278 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10279 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 10280 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10281 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10282 // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0) 10283 AsmString = "mvn $\x01, $\x03"; 10284 break; 10285 } 10286 if (MCInst_getNumOperands(MI) == 4 && 10287 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10288 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10289 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 10290 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10291 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 10292 // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh) 10293 AsmString = "mvn $\x01, $\x03$\xFF\x04\x02"; 10294 break; 10295 } 10296 if (MCInst_getNumOperands(MI) == 4 && 10297 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10298 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10299 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10300 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10301 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10302 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 10303 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10304 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10305 // (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 10306 AsmString = "orn $\x01, $\x02, $\x03"; 10307 break; 10308 } 10309 return NULL; 10310 case AArch64_ORRWrs: 10311 if (MCInst_getNumOperands(MI) == 4 && 10312 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10313 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10314 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 10315 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10316 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10317 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10318 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10319 // (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0) 10320 AsmString = "mov $\x01, $\x03"; 10321 break; 10322 } 10323 if (MCInst_getNumOperands(MI) == 4 && 10324 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10325 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10326 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10327 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10328 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10329 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10330 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10331 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10332 // (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 10333 AsmString = "orr $\x01, $\x02, $\x03"; 10334 break; 10335 } 10336 return NULL; 10337 case AArch64_ORRXrs: 10338 if (MCInst_getNumOperands(MI) == 4 && 10339 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10340 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10341 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 10342 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10343 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 10344 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10345 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10346 // (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0) 10347 AsmString = "mov $\x01, $\x03"; 10348 break; 10349 } 10350 if (MCInst_getNumOperands(MI) == 4 && 10351 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10352 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10353 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10354 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10355 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10356 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 10357 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10358 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 10359 // (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 10360 AsmString = "orr $\x01, $\x02, $\x03"; 10361 break; 10362 } 10363 return NULL; 10364 case AArch64_ORRv16i8: 10365 if (MCInst_getNumOperands(MI) == 3 && 10366 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10367 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 10368 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10369 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 10370 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10371 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { 10372 // (ORRv16i8 V128:$dst, V128:$src, V128:$src) 10373 AsmString = "mov $\xFF\x01\x06.16b, $\xFF\x02\x06.16b"; 10374 break; 10375 } 10376 return NULL; 10377 case AArch64_ORRv2i32: 10378 if (MCInst_getNumOperands(MI) == 3 && 10379 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10380 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 10381 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10382 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10383 // (ORRv2i32 V64:$Vd, imm0_255:$imm, 0) 10384 AsmString = "orr $\xFF\x01\x06.2s, $\xFF\x02\x07"; 10385 break; 10386 } 10387 return NULL; 10388 case AArch64_ORRv4i16: 10389 if (MCInst_getNumOperands(MI) == 3 && 10390 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10391 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 10392 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10393 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10394 // (ORRv4i16 V64:$Vd, imm0_255:$imm, 0) 10395 AsmString = "orr $\xFF\x01\x06.4h, $\xFF\x02\x07"; 10396 break; 10397 } 10398 return NULL; 10399 case AArch64_ORRv4i32: 10400 if (MCInst_getNumOperands(MI) == 3 && 10401 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10402 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 10403 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10404 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10405 // (ORRv4i32 V128:$Vd, imm0_255:$imm, 0) 10406 AsmString = "orr $\xFF\x01\x06.4s, $\xFF\x02\x07"; 10407 break; 10408 } 10409 return NULL; 10410 case AArch64_ORRv8i16: 10411 if (MCInst_getNumOperands(MI) == 3 && 10412 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10413 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 10414 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10415 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10416 // (ORRv8i16 V128:$Vd, imm0_255:$imm, 0) 10417 AsmString = "orr $\xFF\x01\x06.8h, $\xFF\x02\x07"; 10418 break; 10419 } 10420 return NULL; 10421 case AArch64_ORRv8i8: 10422 if (MCInst_getNumOperands(MI) == 3 && 10423 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10424 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 10425 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10426 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 10427 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10428 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { 10429 // (ORRv8i8 V64:$dst, V64:$src, V64:$src) 10430 AsmString = "mov $\xFF\x01\x06.8b, $\xFF\x02\x06.8b"; 10431 break; 10432 } 10433 return NULL; 10434 case AArch64_PRFMroX: 10435 if (MCInst_getNumOperands(MI) == 5 && 10436 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10437 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10438 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10439 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 10440 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10441 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 10442 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 10443 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 10444 // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 10445 AsmString = "prfm $\xFF\x01\x16, [$\x02, $\x03]"; 10446 break; 10447 } 10448 return NULL; 10449 case AArch64_PRFMui: 10450 if (MCInst_getNumOperands(MI) == 3 && 10451 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10452 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10453 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10454 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10455 // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) 10456 AsmString = "prfm $\xFF\x01\x16, [$\x02]"; 10457 break; 10458 } 10459 return NULL; 10460 case AArch64_PRFUMi: 10461 if (MCInst_getNumOperands(MI) == 3 && 10462 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10463 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 10464 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10465 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 10466 // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) 10467 AsmString = "prfum $\xFF\x01\x16, [$\x02]"; 10468 break; 10469 } 10470 return NULL; 10471 case AArch64_RET: 10472 if (MCInst_getNumOperands(MI) == 1 && 10473 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_LR) { 10474 // (RET LR) 10475 AsmString = "ret"; 10476 break; 10477 } 10478 return NULL; 10479 case AArch64_SBCSWr: 10480 if (MCInst_getNumOperands(MI) == 3 && 10481 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10482 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10483 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 10484 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10485 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 10486 // (SBCSWr GPR32:$dst, WZR, GPR32:$src) 10487 AsmString = "ngcs $\x01, $\x03"; 10488 break; 10489 } 10490 return NULL; 10491 case AArch64_SBCSXr: 10492 if (MCInst_getNumOperands(MI) == 3 && 10493 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10494 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10495 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 10496 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10497 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 10498 // (SBCSXr GPR64:$dst, XZR, GPR64:$src) 10499 AsmString = "ngcs $\x01, $\x03"; 10500 break; 10501 } 10502 return NULL; 10503 case AArch64_SBCWr: 10504 if (MCInst_getNumOperands(MI) == 3 && 10505 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10506 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10507 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 10508 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10509 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 10510 // (SBCWr GPR32:$dst, WZR, GPR32:$src) 10511 AsmString = "ngc $\x01, $\x03"; 10512 break; 10513 } 10514 return NULL; 10515 case AArch64_SBCXr: 10516 if (MCInst_getNumOperands(MI) == 3 && 10517 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10518 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10519 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 10520 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10521 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 10522 // (SBCXr GPR64:$dst, XZR, GPR64:$src) 10523 AsmString = "ngc $\x01, $\x03"; 10524 break; 10525 } 10526 return NULL; 10527 case AArch64_SBFMWri: 10528 if (MCInst_getNumOperands(MI) == 4 && 10529 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10530 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10531 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10532 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10533 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10534 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { 10535 // (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) 10536 AsmString = "asr $\x01, $\x02, $\x03"; 10537 break; 10538 } 10539 if (MCInst_getNumOperands(MI) == 4 && 10540 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10541 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10542 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10543 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10544 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10545 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 10546 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10547 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 10548 // (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) 10549 AsmString = "sxtb $\x01, $\x02"; 10550 break; 10551 } 10552 if (MCInst_getNumOperands(MI) == 4 && 10553 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10554 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 10555 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10556 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10557 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10558 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 10559 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10560 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { 10561 // (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) 10562 AsmString = "sxth $\x01, $\x02"; 10563 break; 10564 } 10565 return NULL; 10566 case AArch64_SBFMXri: 10567 if (MCInst_getNumOperands(MI) == 4 && 10568 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10569 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10570 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10571 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10572 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10573 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 63) { 10574 // (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) 10575 AsmString = "asr $\x01, $\x02, $\x03"; 10576 break; 10577 } 10578 if (MCInst_getNumOperands(MI) == 4 && 10579 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10580 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10581 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10582 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10583 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10584 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 10585 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10586 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 10587 // (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) 10588 AsmString = "sxtb $\x01, $\x02"; 10589 break; 10590 } 10591 if (MCInst_getNumOperands(MI) == 4 && 10592 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10593 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10594 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10595 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10596 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10597 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 10598 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10599 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { 10600 // (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) 10601 AsmString = "sxth $\x01, $\x02"; 10602 break; 10603 } 10604 if (MCInst_getNumOperands(MI) == 4 && 10605 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10606 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10607 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10608 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 10609 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 10610 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 10611 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 10612 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { 10613 // (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) 10614 AsmString = "sxtw $\x01, $\x02"; 10615 break; 10616 } 10617 return NULL; 10618 case AArch64_SMADDLrrr: 10619 if (MCInst_getNumOperands(MI) == 4 && 10620 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10621 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10622 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10623 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10624 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10625 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10626 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 10627 // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) 10628 AsmString = "smull $\x01, $\x02, $\x03"; 10629 break; 10630 } 10631 return NULL; 10632 case AArch64_SMSUBLrrr: 10633 if (MCInst_getNumOperands(MI) == 4 && 10634 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10635 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 10636 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10637 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 10638 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 10639 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 10640 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 10641 // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) 10642 AsmString = "smnegl $\x01, $\x02, $\x03"; 10643 break; 10644 } 10645 return NULL; 10646 case AArch64_ST1Fourv16b_POST: 10647 if (MCInst_getNumOperands(MI) == 3 && 10648 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10649 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10650 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10651 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 10652 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10653 // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) 10654 AsmString = "st1 $\xFF\x02\x0A, [$\x01], #64"; 10655 break; 10656 } 10657 return NULL; 10658 case AArch64_ST1Fourv1d_POST: 10659 if (MCInst_getNumOperands(MI) == 3 && 10660 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10661 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10662 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10663 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 10664 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10665 // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) 10666 AsmString = "st1 $\xFF\x02\x0B, [$\x01], #32"; 10667 break; 10668 } 10669 return NULL; 10670 case AArch64_ST1Fourv2d_POST: 10671 if (MCInst_getNumOperands(MI) == 3 && 10672 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10673 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10674 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10675 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 10676 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10677 // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) 10678 AsmString = "st1 $\xFF\x02\x0C, [$\x01], #64"; 10679 break; 10680 } 10681 return NULL; 10682 case AArch64_ST1Fourv2s_POST: 10683 if (MCInst_getNumOperands(MI) == 3 && 10684 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10685 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10686 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10687 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 10688 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10689 // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) 10690 AsmString = "st1 $\xFF\x02\x0D, [$\x01], #32"; 10691 break; 10692 } 10693 return NULL; 10694 case AArch64_ST1Fourv4h_POST: 10695 if (MCInst_getNumOperands(MI) == 3 && 10696 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10697 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10698 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10699 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 10700 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10701 // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) 10702 AsmString = "st1 $\xFF\x02\x0E, [$\x01], #32"; 10703 break; 10704 } 10705 return NULL; 10706 case AArch64_ST1Fourv4s_POST: 10707 if (MCInst_getNumOperands(MI) == 3 && 10708 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10709 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10710 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10711 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 10712 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10713 // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) 10714 AsmString = "st1 $\xFF\x02\x0F, [$\x01], #64"; 10715 break; 10716 } 10717 return NULL; 10718 case AArch64_ST1Fourv8b_POST: 10719 if (MCInst_getNumOperands(MI) == 3 && 10720 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10721 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10722 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10723 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 10724 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10725 // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) 10726 AsmString = "st1 $\xFF\x02\x10, [$\x01], #32"; 10727 break; 10728 } 10729 return NULL; 10730 case AArch64_ST1Fourv8h_POST: 10731 if (MCInst_getNumOperands(MI) == 3 && 10732 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10733 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10734 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10735 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 10736 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10737 // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) 10738 AsmString = "st1 $\xFF\x02\x11, [$\x01], #64"; 10739 break; 10740 } 10741 return NULL; 10742 case AArch64_ST1Onev16b_POST: 10743 if (MCInst_getNumOperands(MI) == 3 && 10744 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10745 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10746 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10747 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 10748 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10749 // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) 10750 AsmString = "st1 $\xFF\x02\x0A, [$\x01], #16"; 10751 break; 10752 } 10753 return NULL; 10754 case AArch64_ST1Onev1d_POST: 10755 if (MCInst_getNumOperands(MI) == 3 && 10756 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10757 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10758 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10759 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 10760 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10761 // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) 10762 AsmString = "st1 $\xFF\x02\x0B, [$\x01], #8"; 10763 break; 10764 } 10765 return NULL; 10766 case AArch64_ST1Onev2d_POST: 10767 if (MCInst_getNumOperands(MI) == 3 && 10768 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10769 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10770 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10771 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 10772 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10773 // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) 10774 AsmString = "st1 $\xFF\x02\x0C, [$\x01], #16"; 10775 break; 10776 } 10777 return NULL; 10778 case AArch64_ST1Onev2s_POST: 10779 if (MCInst_getNumOperands(MI) == 3 && 10780 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10781 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10782 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10783 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 10784 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10785 // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) 10786 AsmString = "st1 $\xFF\x02\x0D, [$\x01], #8"; 10787 break; 10788 } 10789 return NULL; 10790 case AArch64_ST1Onev4h_POST: 10791 if (MCInst_getNumOperands(MI) == 3 && 10792 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10793 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10794 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10795 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 10796 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10797 // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) 10798 AsmString = "st1 $\xFF\x02\x0E, [$\x01], #8"; 10799 break; 10800 } 10801 return NULL; 10802 case AArch64_ST1Onev4s_POST: 10803 if (MCInst_getNumOperands(MI) == 3 && 10804 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10805 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10806 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10807 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 10808 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10809 // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) 10810 AsmString = "st1 $\xFF\x02\x0F, [$\x01], #16"; 10811 break; 10812 } 10813 return NULL; 10814 case AArch64_ST1Onev8b_POST: 10815 if (MCInst_getNumOperands(MI) == 3 && 10816 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10817 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10818 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10819 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 10820 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10821 // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) 10822 AsmString = "st1 $\xFF\x02\x10, [$\x01], #8"; 10823 break; 10824 } 10825 return NULL; 10826 case AArch64_ST1Onev8h_POST: 10827 if (MCInst_getNumOperands(MI) == 3 && 10828 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10829 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10830 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10831 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 10832 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10833 // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) 10834 AsmString = "st1 $\xFF\x02\x11, [$\x01], #16"; 10835 break; 10836 } 10837 return NULL; 10838 case AArch64_ST1Threev16b_POST: 10839 if (MCInst_getNumOperands(MI) == 3 && 10840 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10841 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10842 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10843 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 10844 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10845 // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) 10846 AsmString = "st1 $\xFF\x02\x0A, [$\x01], #48"; 10847 break; 10848 } 10849 return NULL; 10850 case AArch64_ST1Threev1d_POST: 10851 if (MCInst_getNumOperands(MI) == 3 && 10852 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10853 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10854 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10855 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 10856 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10857 // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) 10858 AsmString = "st1 $\xFF\x02\x0B, [$\x01], #24"; 10859 break; 10860 } 10861 return NULL; 10862 case AArch64_ST1Threev2d_POST: 10863 if (MCInst_getNumOperands(MI) == 3 && 10864 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10865 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10866 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10867 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 10868 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10869 // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) 10870 AsmString = "st1 $\xFF\x02\x0C, [$\x01], #48"; 10871 break; 10872 } 10873 return NULL; 10874 case AArch64_ST1Threev2s_POST: 10875 if (MCInst_getNumOperands(MI) == 3 && 10876 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10877 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10878 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10879 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 10880 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10881 // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) 10882 AsmString = "st1 $\xFF\x02\x0D, [$\x01], #24"; 10883 break; 10884 } 10885 return NULL; 10886 case AArch64_ST1Threev4h_POST: 10887 if (MCInst_getNumOperands(MI) == 3 && 10888 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10889 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10890 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10891 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 10892 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10893 // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) 10894 AsmString = "st1 $\xFF\x02\x0E, [$\x01], #24"; 10895 break; 10896 } 10897 return NULL; 10898 case AArch64_ST1Threev4s_POST: 10899 if (MCInst_getNumOperands(MI) == 3 && 10900 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10901 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10902 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10903 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 10904 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10905 // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) 10906 AsmString = "st1 $\xFF\x02\x0F, [$\x01], #48"; 10907 break; 10908 } 10909 return NULL; 10910 case AArch64_ST1Threev8b_POST: 10911 if (MCInst_getNumOperands(MI) == 3 && 10912 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10913 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10914 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10915 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 10916 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10917 // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) 10918 AsmString = "st1 $\xFF\x02\x10, [$\x01], #24"; 10919 break; 10920 } 10921 return NULL; 10922 case AArch64_ST1Threev8h_POST: 10923 if (MCInst_getNumOperands(MI) == 3 && 10924 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10925 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10926 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10927 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 10928 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10929 // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) 10930 AsmString = "st1 $\xFF\x02\x11, [$\x01], #48"; 10931 break; 10932 } 10933 return NULL; 10934 case AArch64_ST1Twov16b_POST: 10935 if (MCInst_getNumOperands(MI) == 3 && 10936 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10937 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10938 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10939 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 10940 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10941 // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) 10942 AsmString = "st1 $\xFF\x02\x0A, [$\x01], #32"; 10943 break; 10944 } 10945 return NULL; 10946 case AArch64_ST1Twov1d_POST: 10947 if (MCInst_getNumOperands(MI) == 3 && 10948 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10949 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10950 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10951 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 10952 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10953 // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) 10954 AsmString = "st1 $\xFF\x02\x0B, [$\x01], #16"; 10955 break; 10956 } 10957 return NULL; 10958 case AArch64_ST1Twov2d_POST: 10959 if (MCInst_getNumOperands(MI) == 3 && 10960 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10961 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10962 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10963 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 10964 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10965 // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) 10966 AsmString = "st1 $\xFF\x02\x0C, [$\x01], #32"; 10967 break; 10968 } 10969 return NULL; 10970 case AArch64_ST1Twov2s_POST: 10971 if (MCInst_getNumOperands(MI) == 3 && 10972 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10973 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10974 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10975 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 10976 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10977 // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) 10978 AsmString = "st1 $\xFF\x02\x0D, [$\x01], #16"; 10979 break; 10980 } 10981 return NULL; 10982 case AArch64_ST1Twov4h_POST: 10983 if (MCInst_getNumOperands(MI) == 3 && 10984 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10985 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10986 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10987 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 10988 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 10989 // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) 10990 AsmString = "st1 $\xFF\x02\x0E, [$\x01], #16"; 10991 break; 10992 } 10993 return NULL; 10994 case AArch64_ST1Twov4s_POST: 10995 if (MCInst_getNumOperands(MI) == 3 && 10996 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 10997 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 10998 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 10999 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11000 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11001 // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) 11002 AsmString = "st1 $\xFF\x02\x0F, [$\x01], #32"; 11003 break; 11004 } 11005 return NULL; 11006 case AArch64_ST1Twov8b_POST: 11007 if (MCInst_getNumOperands(MI) == 3 && 11008 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11009 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11010 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11011 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 11012 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11013 // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) 11014 AsmString = "st1 $\xFF\x02\x10, [$\x01], #16"; 11015 break; 11016 } 11017 return NULL; 11018 case AArch64_ST1Twov8h_POST: 11019 if (MCInst_getNumOperands(MI) == 3 && 11020 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11021 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11022 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11023 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11024 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11025 // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) 11026 AsmString = "st1 $\xFF\x02\x11, [$\x01], #32"; 11027 break; 11028 } 11029 return NULL; 11030 case AArch64_ST1i16_POST: 11031 if (MCInst_getNumOperands(MI) == 4 && 11032 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11033 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11034 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11035 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 11036 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11037 // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) 11038 AsmString = "st1 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #2"; 11039 break; 11040 } 11041 return NULL; 11042 case AArch64_ST1i32_POST: 11043 if (MCInst_getNumOperands(MI) == 4 && 11044 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11045 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11046 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11047 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 11048 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11049 // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) 11050 AsmString = "st1 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #4"; 11051 break; 11052 } 11053 return NULL; 11054 case AArch64_ST1i64_POST: 11055 if (MCInst_getNumOperands(MI) == 4 && 11056 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11057 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11058 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11059 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 11060 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11061 // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) 11062 AsmString = "st1 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #8"; 11063 break; 11064 } 11065 return NULL; 11066 case AArch64_ST1i8_POST: 11067 if (MCInst_getNumOperands(MI) == 4 && 11068 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11069 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11070 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11071 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 11072 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11073 // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) 11074 AsmString = "st1 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #1"; 11075 break; 11076 } 11077 return NULL; 11078 case AArch64_ST2Twov16b_POST: 11079 if (MCInst_getNumOperands(MI) == 3 && 11080 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11081 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11082 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11083 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11084 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11085 // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) 11086 AsmString = "st2 $\xFF\x02\x0A, [$\x01], #32"; 11087 break; 11088 } 11089 return NULL; 11090 case AArch64_ST2Twov2d_POST: 11091 if (MCInst_getNumOperands(MI) == 3 && 11092 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11093 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11094 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11095 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11096 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11097 // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) 11098 AsmString = "st2 $\xFF\x02\x0C, [$\x01], #32"; 11099 break; 11100 } 11101 return NULL; 11102 case AArch64_ST2Twov2s_POST: 11103 if (MCInst_getNumOperands(MI) == 3 && 11104 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11105 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11106 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11107 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 11108 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11109 // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) 11110 AsmString = "st2 $\xFF\x02\x0D, [$\x01], #16"; 11111 break; 11112 } 11113 return NULL; 11114 case AArch64_ST2Twov4h_POST: 11115 if (MCInst_getNumOperands(MI) == 3 && 11116 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11117 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11118 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11119 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 11120 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11121 // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) 11122 AsmString = "st2 $\xFF\x02\x0E, [$\x01], #16"; 11123 break; 11124 } 11125 return NULL; 11126 case AArch64_ST2Twov4s_POST: 11127 if (MCInst_getNumOperands(MI) == 3 && 11128 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11129 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11130 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11131 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11132 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11133 // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) 11134 AsmString = "st2 $\xFF\x02\x0F, [$\x01], #32"; 11135 break; 11136 } 11137 return NULL; 11138 case AArch64_ST2Twov8b_POST: 11139 if (MCInst_getNumOperands(MI) == 3 && 11140 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11141 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11142 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11143 GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && 11144 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11145 // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) 11146 AsmString = "st2 $\xFF\x02\x10, [$\x01], #16"; 11147 break; 11148 } 11149 return NULL; 11150 case AArch64_ST2Twov8h_POST: 11151 if (MCInst_getNumOperands(MI) == 3 && 11152 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11153 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11154 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11155 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11156 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11157 // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) 11158 AsmString = "st2 $\xFF\x02\x11, [$\x01], #32"; 11159 break; 11160 } 11161 return NULL; 11162 case AArch64_ST2i16_POST: 11163 if (MCInst_getNumOperands(MI) == 4 && 11164 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11165 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11166 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11167 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11168 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11169 // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) 11170 AsmString = "st2 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #4"; 11171 break; 11172 } 11173 return NULL; 11174 case AArch64_ST2i32_POST: 11175 if (MCInst_getNumOperands(MI) == 4 && 11176 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11177 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11178 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11179 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11180 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11181 // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) 11182 AsmString = "st2 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #8"; 11183 break; 11184 } 11185 return NULL; 11186 case AArch64_ST2i64_POST: 11187 if (MCInst_getNumOperands(MI) == 4 && 11188 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11189 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11190 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11191 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11192 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11193 // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) 11194 AsmString = "st2 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #16"; 11195 break; 11196 } 11197 return NULL; 11198 case AArch64_ST2i8_POST: 11199 if (MCInst_getNumOperands(MI) == 4 && 11200 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11201 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11202 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11203 GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && 11204 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11205 // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) 11206 AsmString = "st2 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #2"; 11207 break; 11208 } 11209 return NULL; 11210 case AArch64_ST3Threev16b_POST: 11211 if (MCInst_getNumOperands(MI) == 3 && 11212 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11213 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11214 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11215 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11216 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11217 // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) 11218 AsmString = "st3 $\xFF\x02\x0A, [$\x01], #48"; 11219 break; 11220 } 11221 return NULL; 11222 case AArch64_ST3Threev2d_POST: 11223 if (MCInst_getNumOperands(MI) == 3 && 11224 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11225 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11226 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11227 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11228 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11229 // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) 11230 AsmString = "st3 $\xFF\x02\x0C, [$\x01], #48"; 11231 break; 11232 } 11233 return NULL; 11234 case AArch64_ST3Threev2s_POST: 11235 if (MCInst_getNumOperands(MI) == 3 && 11236 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11237 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11238 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11239 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 11240 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11241 // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) 11242 AsmString = "st3 $\xFF\x02\x0D, [$\x01], #24"; 11243 break; 11244 } 11245 return NULL; 11246 case AArch64_ST3Threev4h_POST: 11247 if (MCInst_getNumOperands(MI) == 3 && 11248 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11249 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11250 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11251 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 11252 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11253 // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) 11254 AsmString = "st3 $\xFF\x02\x0E, [$\x01], #24"; 11255 break; 11256 } 11257 return NULL; 11258 case AArch64_ST3Threev4s_POST: 11259 if (MCInst_getNumOperands(MI) == 3 && 11260 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11261 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11262 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11263 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11264 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11265 // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) 11266 AsmString = "st3 $\xFF\x02\x0F, [$\x01], #48"; 11267 break; 11268 } 11269 return NULL; 11270 case AArch64_ST3Threev8b_POST: 11271 if (MCInst_getNumOperands(MI) == 3 && 11272 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11273 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11274 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11275 GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && 11276 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11277 // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) 11278 AsmString = "st3 $\xFF\x02\x10, [$\x01], #24"; 11279 break; 11280 } 11281 return NULL; 11282 case AArch64_ST3Threev8h_POST: 11283 if (MCInst_getNumOperands(MI) == 3 && 11284 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11285 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11286 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11287 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11288 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11289 // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) 11290 AsmString = "st3 $\xFF\x02\x11, [$\x01], #48"; 11291 break; 11292 } 11293 return NULL; 11294 case AArch64_ST3i16_POST: 11295 if (MCInst_getNumOperands(MI) == 4 && 11296 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11297 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11298 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11299 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11300 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11301 // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) 11302 AsmString = "st3 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #6"; 11303 break; 11304 } 11305 return NULL; 11306 case AArch64_ST3i32_POST: 11307 if (MCInst_getNumOperands(MI) == 4 && 11308 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11309 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11310 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11311 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11312 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11313 // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) 11314 AsmString = "st3 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #12"; 11315 break; 11316 } 11317 return NULL; 11318 case AArch64_ST3i64_POST: 11319 if (MCInst_getNumOperands(MI) == 4 && 11320 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11321 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11322 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11323 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11324 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11325 // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) 11326 AsmString = "st3 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #24"; 11327 break; 11328 } 11329 return NULL; 11330 case AArch64_ST3i8_POST: 11331 if (MCInst_getNumOperands(MI) == 4 && 11332 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11333 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11334 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11335 GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && 11336 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11337 // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) 11338 AsmString = "st3 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #3"; 11339 break; 11340 } 11341 return NULL; 11342 case AArch64_ST4Fourv16b_POST: 11343 if (MCInst_getNumOperands(MI) == 3 && 11344 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11345 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11346 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11347 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11348 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11349 // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) 11350 AsmString = "st4 $\xFF\x02\x0A, [$\x01], #64"; 11351 break; 11352 } 11353 return NULL; 11354 case AArch64_ST4Fourv2d_POST: 11355 if (MCInst_getNumOperands(MI) == 3 && 11356 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11357 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11358 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11359 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11360 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11361 // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) 11362 AsmString = "st4 $\xFF\x02\x0C, [$\x01], #64"; 11363 break; 11364 } 11365 return NULL; 11366 case AArch64_ST4Fourv2s_POST: 11367 if (MCInst_getNumOperands(MI) == 3 && 11368 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11369 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11370 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11371 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 11372 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11373 // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) 11374 AsmString = "st4 $\xFF\x02\x0D, [$\x01], #32"; 11375 break; 11376 } 11377 return NULL; 11378 case AArch64_ST4Fourv4h_POST: 11379 if (MCInst_getNumOperands(MI) == 3 && 11380 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11381 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11382 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11383 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 11384 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11385 // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) 11386 AsmString = "st4 $\xFF\x02\x0E, [$\x01], #32"; 11387 break; 11388 } 11389 return NULL; 11390 case AArch64_ST4Fourv4s_POST: 11391 if (MCInst_getNumOperands(MI) == 3 && 11392 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11393 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11394 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11395 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11396 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11397 // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) 11398 AsmString = "st4 $\xFF\x02\x0F, [$\x01], #64"; 11399 break; 11400 } 11401 return NULL; 11402 case AArch64_ST4Fourv8b_POST: 11403 if (MCInst_getNumOperands(MI) == 3 && 11404 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11405 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11406 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11407 GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && 11408 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11409 // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) 11410 AsmString = "st4 $\xFF\x02\x10, [$\x01], #32"; 11411 break; 11412 } 11413 return NULL; 11414 case AArch64_ST4Fourv8h_POST: 11415 if (MCInst_getNumOperands(MI) == 3 && 11416 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11417 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11418 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11419 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11420 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { 11421 // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) 11422 AsmString = "st4 $\xFF\x02\x11, [$\x01], #64"; 11423 break; 11424 } 11425 return NULL; 11426 case AArch64_ST4i16_POST: 11427 if (MCInst_getNumOperands(MI) == 4 && 11428 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11429 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11430 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11431 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11432 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11433 // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) 11434 AsmString = "st4 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #8"; 11435 break; 11436 } 11437 return NULL; 11438 case AArch64_ST4i32_POST: 11439 if (MCInst_getNumOperands(MI) == 4 && 11440 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11441 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11442 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11443 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11444 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11445 // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) 11446 AsmString = "st4 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #16"; 11447 break; 11448 } 11449 return NULL; 11450 case AArch64_ST4i64_POST: 11451 if (MCInst_getNumOperands(MI) == 4 && 11452 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11453 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11454 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11455 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11456 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11457 // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) 11458 AsmString = "st4 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #32"; 11459 break; 11460 } 11461 return NULL; 11462 case AArch64_ST4i8_POST: 11463 if (MCInst_getNumOperands(MI) == 4 && 11464 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11465 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 11466 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11467 GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && 11468 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 11469 // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) 11470 AsmString = "st4 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #4"; 11471 break; 11472 } 11473 return NULL; 11474 case AArch64_STNPDi: 11475 if (MCInst_getNumOperands(MI) == 4 && 11476 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11477 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 11478 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11479 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 11480 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11481 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11482 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11483 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11484 // (STNPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) 11485 AsmString = "stnp $\x01, $\x02, [$\x03]"; 11486 break; 11487 } 11488 return NULL; 11489 case AArch64_STNPQi: 11490 if (MCInst_getNumOperands(MI) == 4 && 11491 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11492 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 11493 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11494 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 11495 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11496 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11497 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11498 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11499 // (STNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) 11500 AsmString = "stnp $\x01, $\x02, [$\x03]"; 11501 break; 11502 } 11503 return NULL; 11504 case AArch64_STNPSi: 11505 if (MCInst_getNumOperands(MI) == 4 && 11506 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11507 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 11508 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11509 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && 11510 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11511 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11512 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11513 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11514 // (STNPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) 11515 AsmString = "stnp $\x01, $\x02, [$\x03]"; 11516 break; 11517 } 11518 return NULL; 11519 case AArch64_STNPWi: 11520 if (MCInst_getNumOperands(MI) == 4 && 11521 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11522 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11523 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11524 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 11525 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11526 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11527 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11528 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11529 // (STNPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) 11530 AsmString = "stnp $\x01, $\x02, [$\x03]"; 11531 break; 11532 } 11533 return NULL; 11534 case AArch64_STNPXi: 11535 if (MCInst_getNumOperands(MI) == 4 && 11536 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11537 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 11538 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11539 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 11540 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11541 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11542 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11543 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11544 // (STNPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) 11545 AsmString = "stnp $\x01, $\x02, [$\x03]"; 11546 break; 11547 } 11548 return NULL; 11549 case AArch64_STPDi: 11550 if (MCInst_getNumOperands(MI) == 4 && 11551 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11552 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 11553 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11554 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && 11555 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11556 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11557 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11558 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11559 // (STPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) 11560 AsmString = "stp $\x01, $\x02, [$\x03]"; 11561 break; 11562 } 11563 return NULL; 11564 case AArch64_STPQi: 11565 if (MCInst_getNumOperands(MI) == 4 && 11566 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11567 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 11568 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11569 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && 11570 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11571 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11572 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11573 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11574 // (STPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) 11575 AsmString = "stp $\x01, $\x02, [$\x03]"; 11576 break; 11577 } 11578 return NULL; 11579 case AArch64_STPSi: 11580 if (MCInst_getNumOperands(MI) == 4 && 11581 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11582 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 11583 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11584 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && 11585 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11586 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11587 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11588 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11589 // (STPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) 11590 AsmString = "stp $\x01, $\x02, [$\x03]"; 11591 break; 11592 } 11593 return NULL; 11594 case AArch64_STPWi: 11595 if (MCInst_getNumOperands(MI) == 4 && 11596 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11597 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11598 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11599 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 11600 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11601 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11602 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11603 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11604 // (STPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) 11605 AsmString = "stp $\x01, $\x02, [$\x03]"; 11606 break; 11607 } 11608 return NULL; 11609 case AArch64_STPXi: 11610 if (MCInst_getNumOperands(MI) == 4 && 11611 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11612 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 11613 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11614 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 11615 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11616 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && 11617 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11618 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 11619 // (STPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) 11620 AsmString = "stp $\x01, $\x02, [$\x03]"; 11621 break; 11622 } 11623 return NULL; 11624 case AArch64_STRBBroX: 11625 if (MCInst_getNumOperands(MI) == 5 && 11626 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11627 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11628 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11629 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11630 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11631 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11632 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11633 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11634 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11635 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11636 // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11637 AsmString = "strb $\x01, [$\x02, $\x03]"; 11638 break; 11639 } 11640 return NULL; 11641 case AArch64_STRBBui: 11642 if (MCInst_getNumOperands(MI) == 3 && 11643 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11644 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11645 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11646 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11647 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11648 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11649 // (STRBBui GPR32:$Rt, GPR64sp:$Rn, 0) 11650 AsmString = "strb $\x01, [$\x02]"; 11651 break; 11652 } 11653 return NULL; 11654 case AArch64_STRBroX: 11655 if (MCInst_getNumOperands(MI) == 5 && 11656 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11657 GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && 11658 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11659 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11660 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11661 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11662 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11663 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11664 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11665 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11666 // (STRBroX FPR8:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11667 AsmString = "str $\x01, [$\x02, $\x03]"; 11668 break; 11669 } 11670 return NULL; 11671 case AArch64_STRBui: 11672 if (MCInst_getNumOperands(MI) == 3 && 11673 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11674 GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && 11675 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11676 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11677 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11678 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11679 // (STRBui FPR8:$Rt, GPR64sp:$Rn, 0) 11680 AsmString = "str $\x01, [$\x02]"; 11681 break; 11682 } 11683 return NULL; 11684 case AArch64_STRDroX: 11685 if (MCInst_getNumOperands(MI) == 5 && 11686 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11687 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 11688 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11689 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11690 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11691 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11692 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11693 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11694 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11695 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11696 // (STRDroX FPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11697 AsmString = "str $\x01, [$\x02, $\x03]"; 11698 break; 11699 } 11700 return NULL; 11701 case AArch64_STRDui: 11702 if (MCInst_getNumOperands(MI) == 3 && 11703 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11704 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 11705 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11706 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11707 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11708 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11709 // (STRDui FPR64:$Rt, GPR64sp:$Rn, 0) 11710 AsmString = "str $\x01, [$\x02]"; 11711 break; 11712 } 11713 return NULL; 11714 case AArch64_STRHHroX: 11715 if (MCInst_getNumOperands(MI) == 5 && 11716 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11717 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11718 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11719 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11720 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11721 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11722 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11723 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11724 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11725 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11726 // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11727 AsmString = "strh $\x01, [$\x02, $\x03]"; 11728 break; 11729 } 11730 return NULL; 11731 case AArch64_STRHHui: 11732 if (MCInst_getNumOperands(MI) == 3 && 11733 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11734 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11735 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11736 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11737 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11738 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11739 // (STRHHui GPR32:$Rt, GPR64sp:$Rn, 0) 11740 AsmString = "strh $\x01, [$\x02]"; 11741 break; 11742 } 11743 return NULL; 11744 case AArch64_STRHroX: 11745 if (MCInst_getNumOperands(MI) == 5 && 11746 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11747 GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && 11748 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11749 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11750 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11751 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11752 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11753 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11754 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11755 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11756 // (STRHroX FPR16:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11757 AsmString = "str $\x01, [$\x02, $\x03]"; 11758 break; 11759 } 11760 return NULL; 11761 case AArch64_STRHui: 11762 if (MCInst_getNumOperands(MI) == 3 && 11763 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11764 GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && 11765 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11766 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11767 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11768 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11769 // (STRHui FPR16:$Rt, GPR64sp:$Rn, 0) 11770 AsmString = "str $\x01, [$\x02]"; 11771 break; 11772 } 11773 return NULL; 11774 case AArch64_STRQroX: 11775 if (MCInst_getNumOperands(MI) == 5 && 11776 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11777 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 11778 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11779 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11780 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11781 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11782 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11783 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11784 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11785 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11786 // (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11787 AsmString = "str $\x01, [$\x02, $\x03]"; 11788 break; 11789 } 11790 return NULL; 11791 case AArch64_STRQui: 11792 if (MCInst_getNumOperands(MI) == 3 && 11793 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11794 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 11795 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11796 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11797 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11798 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11799 // (STRQui FPR128:$Rt, GPR64sp:$Rn, 0) 11800 AsmString = "str $\x01, [$\x02]"; 11801 break; 11802 } 11803 return NULL; 11804 case AArch64_STRSroX: 11805 if (MCInst_getNumOperands(MI) == 5 && 11806 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11807 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 11808 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11809 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11810 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11811 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11812 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11813 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11814 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11815 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11816 // (STRSroX FPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11817 AsmString = "str $\x01, [$\x02, $\x03]"; 11818 break; 11819 } 11820 return NULL; 11821 case AArch64_STRSui: 11822 if (MCInst_getNumOperands(MI) == 3 && 11823 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11824 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 11825 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11826 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11827 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11828 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11829 // (STRSui FPR32:$Rt, GPR64sp:$Rn, 0) 11830 AsmString = "str $\x01, [$\x02]"; 11831 break; 11832 } 11833 return NULL; 11834 case AArch64_STRWroX: 11835 if (MCInst_getNumOperands(MI) == 5 && 11836 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11837 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11838 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11839 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11840 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11841 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11842 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11843 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11844 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11845 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11846 // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11847 AsmString = "str $\x01, [$\x02, $\x03]"; 11848 break; 11849 } 11850 return NULL; 11851 case AArch64_STRWui: 11852 if (MCInst_getNumOperands(MI) == 3 && 11853 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11854 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11855 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11856 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11857 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11858 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11859 // (STRWui GPR32:$Rt, GPR64sp:$Rn, 0) 11860 AsmString = "str $\x01, [$\x02]"; 11861 break; 11862 } 11863 return NULL; 11864 case AArch64_STRXroX: 11865 if (MCInst_getNumOperands(MI) == 5 && 11866 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11867 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 11868 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11869 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11870 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 11871 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 11872 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 11873 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && 11874 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 11875 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { 11876 // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) 11877 AsmString = "str $\x01, [$\x02, $\x03]"; 11878 break; 11879 } 11880 return NULL; 11881 case AArch64_STRXui: 11882 if (MCInst_getNumOperands(MI) == 3 && 11883 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11884 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 11885 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11886 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11887 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11888 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11889 // (STRXui GPR64:$Rt, GPR64sp:$Rn, 0) 11890 AsmString = "str $\x01, [$\x02]"; 11891 break; 11892 } 11893 return NULL; 11894 case AArch64_STTRBi: 11895 if (MCInst_getNumOperands(MI) == 3 && 11896 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11897 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11898 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11899 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11900 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11901 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11902 // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) 11903 AsmString = "sttrb $\x01, [$\x02]"; 11904 break; 11905 } 11906 return NULL; 11907 case AArch64_STTRHi: 11908 if (MCInst_getNumOperands(MI) == 3 && 11909 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11910 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11911 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11912 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11913 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11914 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11915 // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) 11916 AsmString = "sttrh $\x01, [$\x02]"; 11917 break; 11918 } 11919 return NULL; 11920 case AArch64_STTRWi: 11921 if (MCInst_getNumOperands(MI) == 3 && 11922 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11923 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11924 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11925 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11926 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11927 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11928 // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) 11929 AsmString = "sttr $\x01, [$\x02]"; 11930 break; 11931 } 11932 return NULL; 11933 case AArch64_STTRXi: 11934 if (MCInst_getNumOperands(MI) == 3 && 11935 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11936 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 11937 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11938 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11939 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11940 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11941 // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) 11942 AsmString = "sttr $\x01, [$\x02]"; 11943 break; 11944 } 11945 return NULL; 11946 case AArch64_STURBBi: 11947 if (MCInst_getNumOperands(MI) == 3 && 11948 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11949 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11950 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11951 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11952 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11953 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11954 // (STURBBi GPR32:$Rt, GPR64sp:$Rn, 0) 11955 AsmString = "sturb $\x01, [$\x02]"; 11956 break; 11957 } 11958 return NULL; 11959 case AArch64_STURBi: 11960 if (MCInst_getNumOperands(MI) == 3 && 11961 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11962 GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && 11963 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11964 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11965 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11966 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11967 // (STURBi FPR8:$Rt, GPR64sp:$Rn, 0) 11968 AsmString = "stur $\x01, [$\x02]"; 11969 break; 11970 } 11971 return NULL; 11972 case AArch64_STURDi: 11973 if (MCInst_getNumOperands(MI) == 3 && 11974 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11975 GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && 11976 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11977 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11978 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11979 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11980 // (STURDi FPR64:$Rt, GPR64sp:$Rn, 0) 11981 AsmString = "stur $\x01, [$\x02]"; 11982 break; 11983 } 11984 return NULL; 11985 case AArch64_STURHHi: 11986 if (MCInst_getNumOperands(MI) == 3 && 11987 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 11988 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 11989 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 11990 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 11991 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 11992 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 11993 // (STURHHi GPR32:$Rt, GPR64sp:$Rn, 0) 11994 AsmString = "sturh $\x01, [$\x02]"; 11995 break; 11996 } 11997 return NULL; 11998 case AArch64_STURHi: 11999 if (MCInst_getNumOperands(MI) == 3 && 12000 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12001 GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && 12002 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12003 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12004 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12005 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 12006 // (STURHi FPR16:$Rt, GPR64sp:$Rn, 0) 12007 AsmString = "stur $\x01, [$\x02]"; 12008 break; 12009 } 12010 return NULL; 12011 case AArch64_STURQi: 12012 if (MCInst_getNumOperands(MI) == 3 && 12013 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12014 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && 12015 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12016 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12017 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12018 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 12019 // (STURQi FPR128:$Rt, GPR64sp:$Rn, 0) 12020 AsmString = "stur $\x01, [$\x02]"; 12021 break; 12022 } 12023 return NULL; 12024 case AArch64_STURSi: 12025 if (MCInst_getNumOperands(MI) == 3 && 12026 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12027 GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && 12028 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12029 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12030 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12031 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 12032 // (STURSi FPR32:$Rt, GPR64sp:$Rn, 0) 12033 AsmString = "stur $\x01, [$\x02]"; 12034 break; 12035 } 12036 return NULL; 12037 case AArch64_STURWi: 12038 if (MCInst_getNumOperands(MI) == 3 && 12039 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12040 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12041 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12042 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12043 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12044 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 12045 // (STURWi GPR32:$Rt, GPR64sp:$Rn, 0) 12046 AsmString = "stur $\x01, [$\x02]"; 12047 break; 12048 } 12049 return NULL; 12050 case AArch64_STURXi: 12051 if (MCInst_getNumOperands(MI) == 3 && 12052 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12053 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12054 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12055 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12056 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12057 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 12058 // (STURXi GPR64:$Rt, GPR64sp:$Rn, 0) 12059 AsmString = "stur $\x01, [$\x02]"; 12060 break; 12061 } 12062 return NULL; 12063 case AArch64_SUBSWri: 12064 if (MCInst_getNumOperands(MI) == 4 && 12065 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 12066 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12067 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1)) { 12068 // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) 12069 AsmString = "cmp $\x02, $\xFF\x03\x01"; 12070 break; 12071 } 12072 return NULL; 12073 case AArch64_SUBSWrs: 12074 if (MCInst_getNumOperands(MI) == 4 && 12075 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 12076 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12077 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12078 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12079 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12080 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12081 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12082 // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) 12083 AsmString = "cmp $\x02, $\x03"; 12084 break; 12085 } 12086 if (MCInst_getNumOperands(MI) == 4 && 12087 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 12088 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12089 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12090 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12091 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 12092 // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) 12093 AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; 12094 break; 12095 } 12096 if (MCInst_getNumOperands(MI) == 4 && 12097 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12098 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12099 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 12100 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12101 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12102 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12103 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12104 // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0) 12105 AsmString = "negs $\x01, $\x03"; 12106 break; 12107 } 12108 if (MCInst_getNumOperands(MI) == 4 && 12109 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12110 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12111 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 12112 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12113 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 12114 // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) 12115 AsmString = "negs $\x01, $\x03$\xFF\x04\x02"; 12116 break; 12117 } 12118 if (MCInst_getNumOperands(MI) == 4 && 12119 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12120 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12121 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12122 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12123 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12124 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12125 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12126 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12127 // (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 12128 AsmString = "subs $\x01, $\x02, $\x03"; 12129 break; 12130 } 12131 return NULL; 12132 case AArch64_SUBSWrx: 12133 if (MCInst_getNumOperands(MI) == 4 && 12134 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 12135 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12136 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && 12137 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12138 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12139 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12140 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 12141 // (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) 12142 AsmString = "cmp $\x02, $\x03"; 12143 break; 12144 } 12145 if (MCInst_getNumOperands(MI) == 4 && 12146 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && 12147 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12148 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && 12149 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12150 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 12151 // (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) 12152 AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; 12153 break; 12154 } 12155 if (MCInst_getNumOperands(MI) == 4 && 12156 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12157 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12158 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12159 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && 12160 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12161 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12162 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12163 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 12164 // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) 12165 AsmString = "subs $\x01, $\x02, $\x03"; 12166 break; 12167 } 12168 return NULL; 12169 case AArch64_SUBSXri: 12170 if (MCInst_getNumOperands(MI) == 4 && 12171 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 12172 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12173 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1)) { 12174 // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) 12175 AsmString = "cmp $\x02, $\xFF\x03\x01"; 12176 break; 12177 } 12178 return NULL; 12179 case AArch64_SUBSXrs: 12180 if (MCInst_getNumOperands(MI) == 4 && 12181 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 12182 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12183 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12184 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12185 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12186 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12187 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12188 // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) 12189 AsmString = "cmp $\x02, $\x03"; 12190 break; 12191 } 12192 if (MCInst_getNumOperands(MI) == 4 && 12193 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 12194 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12195 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12196 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12197 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 12198 // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) 12199 AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; 12200 break; 12201 } 12202 if (MCInst_getNumOperands(MI) == 4 && 12203 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12204 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12205 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 12206 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12207 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12208 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12209 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12210 // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0) 12211 AsmString = "negs $\x01, $\x03"; 12212 break; 12213 } 12214 if (MCInst_getNumOperands(MI) == 4 && 12215 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12216 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12217 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 12218 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12219 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 12220 // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) 12221 AsmString = "negs $\x01, $\x03$\xFF\x04\x02"; 12222 break; 12223 } 12224 if (MCInst_getNumOperands(MI) == 4 && 12225 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12226 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12227 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12228 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12229 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12230 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12231 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12232 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12233 // (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 12234 AsmString = "subs $\x01, $\x02, $\x03"; 12235 break; 12236 } 12237 return NULL; 12238 case AArch64_SUBSXrx: 12239 if (MCInst_getNumOperands(MI) == 4 && 12240 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 12241 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12242 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12243 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12244 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 12245 // (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) 12246 AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; 12247 break; 12248 } 12249 return NULL; 12250 case AArch64_SUBSXrx64: 12251 if (MCInst_getNumOperands(MI) == 4 && 12252 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 12253 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12254 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && 12255 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12256 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12257 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12258 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 12259 // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) 12260 AsmString = "cmp $\x02, $\x03"; 12261 break; 12262 } 12263 if (MCInst_getNumOperands(MI) == 4 && 12264 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && 12265 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12266 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12267 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12268 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 12269 // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) 12270 AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; 12271 break; 12272 } 12273 if (MCInst_getNumOperands(MI) == 4 && 12274 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12275 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12276 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12277 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && 12278 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12279 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12280 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12281 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 12282 // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) 12283 AsmString = "subs $\x01, $\x02, $\x03"; 12284 break; 12285 } 12286 return NULL; 12287 case AArch64_SUBWrs: 12288 if (MCInst_getNumOperands(MI) == 4 && 12289 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12290 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12291 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 12292 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12293 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12294 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12295 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12296 // (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0) 12297 AsmString = "neg $\x01, $\x03"; 12298 break; 12299 } 12300 if (MCInst_getNumOperands(MI) == 4 && 12301 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12302 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12303 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && 12304 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12305 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { 12306 // (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) 12307 AsmString = "neg $\x01, $\x03$\xFF\x04\x02"; 12308 break; 12309 } 12310 if (MCInst_getNumOperands(MI) == 4 && 12311 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12312 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12313 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12314 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12315 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12316 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12317 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12318 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12319 // (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 12320 AsmString = "sub $\x01, $\x02, $\x03"; 12321 break; 12322 } 12323 return NULL; 12324 case AArch64_SUBWrx: 12325 if (MCInst_getNumOperands(MI) == 4 && 12326 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12327 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) && 12328 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12329 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && 12330 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12331 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12332 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12333 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 12334 // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) 12335 AsmString = "sub $\x01, $\x02, $\x03"; 12336 break; 12337 } 12338 if (MCInst_getNumOperands(MI) == 4 && 12339 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12340 GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) && 12341 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12342 GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && 12343 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12344 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12345 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12346 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { 12347 // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) 12348 AsmString = "sub $\x01, $\x02, $\x03"; 12349 break; 12350 } 12351 return NULL; 12352 case AArch64_SUBXrs: 12353 if (MCInst_getNumOperands(MI) == 4 && 12354 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12355 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12356 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 12357 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12358 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12359 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12360 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12361 // (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0) 12362 AsmString = "neg $\x01, $\x03"; 12363 break; 12364 } 12365 if (MCInst_getNumOperands(MI) == 4 && 12366 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12367 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12368 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && 12369 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12370 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { 12371 // (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) 12372 AsmString = "neg $\x01, $\x03$\xFF\x04\x02"; 12373 break; 12374 } 12375 if (MCInst_getNumOperands(MI) == 4 && 12376 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12377 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12378 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12379 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12380 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12381 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12382 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12383 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { 12384 // (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 12385 AsmString = "sub $\x01, $\x02, $\x03"; 12386 break; 12387 } 12388 return NULL; 12389 case AArch64_SUBXrx64: 12390 if (MCInst_getNumOperands(MI) == 4 && 12391 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12392 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) && 12393 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12394 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && 12395 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12396 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12397 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12398 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 12399 // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) 12400 AsmString = "sub $\x01, $\x02, $\x03"; 12401 break; 12402 } 12403 if (MCInst_getNumOperands(MI) == 4 && 12404 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12405 GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && 12406 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12407 GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && 12408 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12409 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && 12410 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12411 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { 12412 // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) 12413 AsmString = "sub $\x01, $\x02, $\x03"; 12414 break; 12415 } 12416 return NULL; 12417 case AArch64_SYSxt: 12418 if (MCInst_getNumOperands(MI) == 5 && 12419 MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR) { 12420 // (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) 12421 AsmString = "sys $\x01, $\xFF\x02\x17, $\xFF\x03\x17, $\x04"; 12422 break; 12423 } 12424 return NULL; 12425 case AArch64_UBFMWri: 12426 if (MCInst_getNumOperands(MI) == 4 && 12427 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12428 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12429 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12430 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12431 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12432 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { 12433 // (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) 12434 AsmString = "lsr $\x01, $\x02, $\x03"; 12435 break; 12436 } 12437 if (MCInst_getNumOperands(MI) == 4 && 12438 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12439 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12440 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12441 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12442 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12443 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 12444 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12445 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 12446 // (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) 12447 AsmString = "uxtb $\x01, $\x02"; 12448 break; 12449 } 12450 if (MCInst_getNumOperands(MI) == 4 && 12451 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12452 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12453 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12454 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12455 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12456 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 12457 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12458 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { 12459 // (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) 12460 AsmString = "uxth $\x01, $\x02"; 12461 break; 12462 } 12463 return NULL; 12464 case AArch64_UBFMXri: 12465 if (MCInst_getNumOperands(MI) == 4 && 12466 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12467 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12468 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12469 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12470 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12471 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 63) { 12472 // (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) 12473 AsmString = "lsr $\x01, $\x02, $\x03"; 12474 break; 12475 } 12476 if (MCInst_getNumOperands(MI) == 4 && 12477 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12478 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12479 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12480 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12481 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12482 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 12483 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12484 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 12485 // (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) 12486 AsmString = "uxtb $\x01, $\x02"; 12487 break; 12488 } 12489 if (MCInst_getNumOperands(MI) == 4 && 12490 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12491 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12492 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12493 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12494 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12495 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 12496 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12497 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { 12498 // (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) 12499 AsmString = "uxth $\x01, $\x02"; 12500 break; 12501 } 12502 if (MCInst_getNumOperands(MI) == 4 && 12503 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12504 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12505 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12506 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && 12507 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 12508 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && 12509 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 12510 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { 12511 // (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) 12512 AsmString = "uxtw $\x01, $\x02"; 12513 break; 12514 } 12515 return NULL; 12516 case AArch64_UMADDLrrr: 12517 if (MCInst_getNumOperands(MI) == 4 && 12518 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12519 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12520 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12521 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12522 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12523 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12524 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 12525 // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) 12526 AsmString = "umull $\x01, $\x02, $\x03"; 12527 break; 12528 } 12529 return NULL; 12530 case AArch64_UMOVvi32: 12531 if (MCInst_getNumOperands(MI) == 3 && 12532 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12533 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && 12534 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12535 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { 12536 // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) 12537 AsmString = "mov $\x01, $\xFF\x02\x06.s$\xFF\x03\x09"; 12538 break; 12539 } 12540 return NULL; 12541 case AArch64_UMOVvi64: 12542 if (MCInst_getNumOperands(MI) == 3 && 12543 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12544 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12545 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12546 GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { 12547 // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) 12548 AsmString = "mov $\x01, $\xFF\x02\x06.d$\xFF\x03\x09"; 12549 break; 12550 } 12551 return NULL; 12552 case AArch64_UMSUBLrrr: 12553 if (MCInst_getNumOperands(MI) == 4 && 12554 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 12555 GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && 12556 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 12557 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && 12558 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 12559 GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && 12560 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { 12561 // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) 12562 AsmString = "umnegl $\x01, $\x02, $\x03"; 12563 break; 12564 } 12565 return NULL; 12566 } 12567 12568 tmp = cs_strdup(AsmString); 12569 AsmMnem = tmp; 12570 for(AsmOps = tmp; *AsmOps; AsmOps++) { 12571 if (*AsmOps == ' ' || *AsmOps == '\t') { 12572 *AsmOps = '\0'; 12573 AsmOps++; 12574 break; 12575 } 12576 } 12577 SStream_concat0(OS, AsmMnem); 12578 if (*AsmOps) { 12579 SStream_concat0(OS, "\t"); 12580 for (c = AsmOps; *c; c++) { 12581 if (*c == '[') { 12582 SStream_concat0(OS, "["); 12583 set_mem_access(MI, true); 12584 } 12585 else if (*c == ']') { 12586 SStream_concat0(OS, "]"); 12587 set_mem_access(MI, false); 12588 } 12589 else if (*c == '$') { 12590 c += 1; 12591 if (*c == (char)0xff) { 12592 c += 1; 12593 OpIdx = *c - 1; 12594 c += 1; 12595 PrintMethodIdx = *c - 1; 12596 printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS, MRI); 12597 } else 12598 printOperand(MI, *c - 1, OS); 12599 } else { 12600 SStream_concat(OS, "%c", *c); 12601 } 12602 } 12603 } 12604 return tmp; 12605} 12606 12607#endif // PRINT_ALIAS_INSTR 12608