1//===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10/* Capstone Disassembly Engine */
11/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
12
13#ifndef CS_SYSTEMZMCTARGETDESC_H
14#define CS_SYSTEMZMCTARGETDESC_H
15
16// Maps of asm register numbers to LLVM register numbers, with 0 indicating
17// an invalid register.  In principle we could use 32-bit and 64-bit register
18// classes directly, provided that we relegated the GPR allocation order
19// in SystemZRegisterInfo.td to an AltOrder and left the default order
20// as %r0-%r15.  It seems better to provide the same interface for
21// all classes though.
22extern const unsigned SystemZMC_GR32Regs[16];
23extern const unsigned SystemZMC_GRH32Regs[16];
24extern const unsigned SystemZMC_GR64Regs[16];
25extern const unsigned SystemZMC_GR128Regs[16];
26extern const unsigned SystemZMC_FP32Regs[16];
27extern const unsigned SystemZMC_FP64Regs[16];
28extern const unsigned SystemZMC_FP128Regs[16];
29
30// Return the 0-based number of the first architectural register that
31// contains the given LLVM register.   E.g. R1D -> 1.
32unsigned SystemZMC_getFirstReg(unsigned Reg);
33
34// Defines symbolic names for SystemZ registers.
35// This defines a mapping from register name to register number.
36//#define GET_REGINFO_ENUM
37//#include "SystemZGenRegisterInfo.inc"
38
39// Defines symbolic names for the SystemZ instructions.
40//#define GET_INSTRINFO_ENUM
41//#include "SystemZGenInstrInfo.inc"
42
43//#define GET_SUBTARGETINFO_ENUM
44//#include "SystemZGenSubtargetInfo.inc"
45
46#endif
47