XCoreGenRegisterInfo.inc revision c80d840ffce9f9bcb1ab0aeb9e890884cad7ebbf 
1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|*Target Register Enum Values                                                 *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9/* Capstone Disassembly Engine */
10/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
11
12
13#ifdef GET_REGINFO_ENUM
14#undef GET_REGINFO_ENUM
15
16enum {
17  XCore_NoRegister,
18  XCore_CP = 1,
19  XCore_DP = 2,
20  XCore_LR = 3,
21  XCore_SP = 4,
22  XCore_R0 = 5,
23  XCore_R1 = 6,
24  XCore_R2 = 7,
25  XCore_R3 = 8,
26  XCore_R4 = 9,
27  XCore_R5 = 10,
28  XCore_R6 = 11,
29  XCore_R7 = 12,
30  XCore_R8 = 13,
31  XCore_R9 = 14,
32  XCore_R10 = 15,
33  XCore_R11 = 16,
34  XCore_NUM_TARGET_REGS 	// 17
35};
36
37// Register classes
38enum {
39  XCore_RRegsRegClassID = 0,
40  XCore_GRRegsRegClassID = 1
41};
42
43#endif // GET_REGINFO_ENUM
44
45/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
46|*                                                                            *|
47|*MC Register Information                                                     *|
48|*                                                                            *|
49|* Automatically generated file, do not edit!                                 *|
50|*                                                                            *|
51\*===----------------------------------------------------------------------===*/
52
53
54#ifdef GET_REGINFO_MC_DESC
55#undef GET_REGINFO_MC_DESC
56
57static MCPhysReg XCoreRegDiffLists[] = {
58  /* 0 */ 65535, 0,
59};
60
61static uint16_t XCoreSubRegIdxLists[] = {
62  /* 0 */ 0,
63};
64
65static MCRegisterDesc XCoreRegDesc[] = { // Descriptors
66  { 3, 0, 0, 0, 0 },
67  { 38, 1, 1, 0, 1 },
68  { 41, 1, 1, 0, 1 },
69  { 47, 1, 1, 0, 1 },
70  { 44, 1, 1, 0, 1 },
71  { 4, 1, 1, 0, 1 },
72  { 11, 1, 1, 0, 1 },
73  { 14, 1, 1, 0, 1 },
74  { 17, 1, 1, 0, 1 },
75  { 20, 1, 1, 0, 1 },
76  { 23, 1, 1, 0, 1 },
77  { 26, 1, 1, 0, 1 },
78  { 29, 1, 1, 0, 1 },
79  { 32, 1, 1, 0, 1 },
80  { 35, 1, 1, 0, 1 },
81  { 0, 1, 1, 0, 1 },
82  { 7, 1, 1, 0, 1 },
83};
84
85  // RRegs Register Class...
86  static MCPhysReg RRegs[] = {
87    XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, XCore_CP, XCore_DP, XCore_SP, XCore_LR,
88  };
89
90  // RRegs Bit set.
91  static uint8_t RRegsBits[] = {
92    0xfe, 0xff, 0x01,
93  };
94
95  // GRRegs Register Class...
96  static MCPhysReg GRRegs[] = {
97    XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11,
98  };
99
100  // GRRegs Bit set.
101  static uint8_t GRRegsBits[] = {
102    0xe0, 0xff, 0x01,
103  };
104
105static MCRegisterClass XCoreMCRegisterClasses[] = {
106  { "RRegs", RRegs, RRegsBits, 16, sizeof(RRegsBits), XCore_RRegsRegClassID, 4, 4, 1, 0 },
107  { "GRRegs", GRRegs, GRRegsBits, 12, sizeof(GRRegsBits), XCore_GRRegsRegClassID, 4, 4, 1, 1 },
108};
109
110#endif // GET_REGINFO_MC_DESC
111