arm64.h revision 6b9b6647c1d506017d4fd1b9bfd44d3f300c0961 
1#ifndef __CS_ARM64_H__
2#define __CS_ARM64_H__
3
4/* Capstone Disassembler Engine */
5/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
6
7#ifdef __cplusplus
8extern "C" {
9#endif
10
11#include <stdint.h>
12#include <stdbool.h>
13
14typedef enum arm64_shifter {
15	ARM64_SFT_INVALID = 0,
16	ARM64_SFT_LSL = 1,
17	ARM64_SFT_MSL = 2,
18	ARM64_SFT_LSR = 3,
19	ARM64_SFT_ASR = 4,
20	ARM64_SFT_ROR = 1,
21} arm64_shifter;
22
23typedef enum arm64_extender {
24	ARM64_EXT_INVALID = 0,
25	ARM64_EXT_UXTB = 1,
26	ARM64_EXT_UXTH = 2,
27	ARM64_EXT_UXTW = 3,
28	ARM64_EXT_UXTX = 4,
29	ARM64_EXT_SXTB = 5,
30	ARM64_EXT_SXTH = 6,
31	ARM64_EXT_SXTW = 7,
32	ARM64_EXT_SXTX = 8,
33} arm64_extender;
34
35// ARM64 condition code
36typedef enum arm64_cc {
37	ARM64_CC_INVALID = 0,
38	ARM64_CC_EQ = 1,     // Equal
39	ARM64_CC_NE = 2,     // Not equal:                 Not equal, or unordered
40	ARM64_CC_HS = 3,     // Unsigned higher or same:   >, ==, or unordered
41	ARM64_CC_LO = 4,     // Unsigned lower or same:    Less than
42	ARM64_CC_MI = 5,     // Minus, negative:           Less than
43	ARM64_CC_PL = 6,     // Plus, positive or zero:    >, ==, or unordered
44	ARM64_CC_VS = 7,     // Overflow:                  Unordered
45	ARM64_CC_VC = 8,     // No overflow:               Ordered
46	ARM64_CC_HI = 9,     // Unsigned higher:           Greater than, or unordered
47	ARM64_CC_LS = 10,     // Unsigned lower or same:    Less than or equal
48	ARM64_CC_GE = 11,     // Greater than or equal:     Greater than or equal
49	ARM64_CC_LT = 12,     // Less than:                 Less than, or unordered
50	ARM64_CC_GT = 13,     // Signed greater than:       Greater than
51	ARM64_CC_LE = 14,     // Signed less than or equal: <, ==, or unordered
52	ARM64_CC_AL = 15,     // Always (unconditional):    Always (unconditional)
53	ARM64_CC_NV = 16,     // Always (unconditional):   Always (unconditional)
54	// Note the NV exists purely to disassemble 0b1111. Execution
55	// is "always".
56} arm64_cc;
57
58// Operand type for instruction's operands
59typedef enum arm64_op_type {
60	ARM64_OP_INVALID = 0,	// Uninitialized.
61	ARM64_OP_REG,	// Register operand.
62	ARM64_OP_CIMM, // C-Immediate
63	ARM64_OP_IMM,	// Immediate operand.
64	ARM64_OP_FP,	// Floating-Point immediate operand.
65	ARM64_OP_MEM,	// Memory operand
66} arm64_op_type;
67
68// Instruction's operand referring to memory
69// This is associated with ARM64_OP_MEM operand type above
70typedef struct arm64_op_mem {
71	unsigned int base;	// base register
72	unsigned int index;	// index register
73	int32_t disp;	// displacement/offset value
74} arm64_op_mem;
75
76// Instruction operand
77typedef struct cs_arm64_op {
78	struct {
79		arm64_shifter type;	// shifter type of this operand
80		unsigned int value;	// shifter value of this operand
81	} shift;
82	arm64_extender ext;		// extender type of this operand
83	arm64_op_type type;	// operand type
84	union {
85		unsigned int reg;	// register value for REG operand
86		int32_t imm;		// immediate value, or index for C-IMM or IMM operand
87		double fp;			// floating point value for FP operand
88		arm64_op_mem mem;		// base/index/scale/disp value for MEM operand
89	};
90} cs_arm64_op;
91
92// Instruction structure
93typedef struct cs_arm64 {
94	arm64_cc cc;	// conditional code for this insn
95	bool update_flags;	// does this insn update flags?
96	bool writeback;	// does this insn request writeback? 'True' means 'yes'
97
98	// Number of operands of this instruction,
99	// or 0 when instruction has no operand.
100	uint8_t op_count;
101
102	cs_arm64_op operands[8]; // operands for this instruction.
103} cs_arm64;
104
105// ARM64 registers
106typedef enum arm64_reg {
107	ARM64_REG_INVALID = 0,
108	ARM64_REG_NZCV = 1,
109	ARM64_REG_WSP = 2,
110	ARM64_REG_WZR = 3,
111	ARM64_REG_SP = 4,
112	ARM64_REG_XZR = 5,
113	ARM64_REG_B0 = 6,
114	ARM64_REG_B1 = 7,
115	ARM64_REG_B2 = 8,
116	ARM64_REG_B3 = 9,
117	ARM64_REG_B4 = 10,
118	ARM64_REG_B5 = 11,
119	ARM64_REG_B6 = 12,
120	ARM64_REG_B7 = 13,
121	ARM64_REG_B8 = 14,
122	ARM64_REG_B9 = 15,
123	ARM64_REG_B10 = 16,
124	ARM64_REG_B11 = 17,
125	ARM64_REG_B12 = 18,
126	ARM64_REG_B13 = 19,
127	ARM64_REG_B14 = 20,
128	ARM64_REG_B15 = 21,
129	ARM64_REG_B16 = 22,
130	ARM64_REG_B17 = 23,
131	ARM64_REG_B18 = 24,
132	ARM64_REG_B19 = 25,
133	ARM64_REG_B20 = 26,
134	ARM64_REG_B21 = 27,
135	ARM64_REG_B22 = 28,
136	ARM64_REG_B23 = 29,
137	ARM64_REG_B24 = 30,
138	ARM64_REG_B25 = 31,
139	ARM64_REG_B26 = 32,
140	ARM64_REG_B27 = 33,
141	ARM64_REG_B28 = 34,
142	ARM64_REG_B29 = 35,
143	ARM64_REG_B30 = 36,
144	ARM64_REG_B31 = 37,
145	ARM64_REG_D0 = 38,
146	ARM64_REG_D1 = 39,
147	ARM64_REG_D2 = 40,
148	ARM64_REG_D3 = 41,
149	ARM64_REG_D4 = 42,
150	ARM64_REG_D5 = 43,
151	ARM64_REG_D6 = 44,
152	ARM64_REG_D7 = 45,
153	ARM64_REG_D8 = 46,
154	ARM64_REG_D9 = 47,
155	ARM64_REG_D10 = 48,
156	ARM64_REG_D11 = 49,
157	ARM64_REG_D12 = 50,
158	ARM64_REG_D13 = 51,
159	ARM64_REG_D14 = 52,
160	ARM64_REG_D15 = 53,
161	ARM64_REG_D16 = 54,
162	ARM64_REG_D17 = 55,
163	ARM64_REG_D18 = 56,
164	ARM64_REG_D19 = 57,
165	ARM64_REG_D20 = 58,
166	ARM64_REG_D21 = 59,
167	ARM64_REG_D22 = 60,
168	ARM64_REG_D23 = 61,
169	ARM64_REG_D24 = 62,
170	ARM64_REG_D25 = 63,
171	ARM64_REG_D26 = 64,
172	ARM64_REG_D27 = 65,
173	ARM64_REG_D28 = 66,
174	ARM64_REG_D29 = 67,
175	ARM64_REG_D30 = 68,
176	ARM64_REG_D31 = 69,
177	ARM64_REG_H0 = 70,
178	ARM64_REG_H1 = 71,
179	ARM64_REG_H2 = 72,
180	ARM64_REG_H3 = 73,
181	ARM64_REG_H4 = 74,
182	ARM64_REG_H5 = 75,
183	ARM64_REG_H6 = 76,
184	ARM64_REG_H7 = 77,
185	ARM64_REG_H8 = 78,
186	ARM64_REG_H9 = 79,
187	ARM64_REG_H10 = 80,
188	ARM64_REG_H11 = 81,
189	ARM64_REG_H12 = 82,
190	ARM64_REG_H13 = 83,
191	ARM64_REG_H14 = 84,
192	ARM64_REG_H15 = 85,
193	ARM64_REG_H16 = 86,
194	ARM64_REG_H17 = 87,
195	ARM64_REG_H18 = 88,
196	ARM64_REG_H19 = 89,
197	ARM64_REG_H20 = 90,
198	ARM64_REG_H21 = 91,
199	ARM64_REG_H22 = 92,
200	ARM64_REG_H23 = 93,
201	ARM64_REG_H24 = 94,
202	ARM64_REG_H25 = 95,
203	ARM64_REG_H26 = 96,
204	ARM64_REG_H27 = 97,
205	ARM64_REG_H28 = 98,
206	ARM64_REG_H29 = 99,
207	ARM64_REG_H30 = 100,
208	ARM64_REG_H31 = 101,
209	ARM64_REG_Q0 = 102,
210	ARM64_REG_Q1 = 103,
211	ARM64_REG_Q2 = 104,
212	ARM64_REG_Q3 = 105,
213	ARM64_REG_Q4 = 106,
214	ARM64_REG_Q5 = 107,
215	ARM64_REG_Q6 = 108,
216	ARM64_REG_Q7 = 109,
217	ARM64_REG_Q8 = 110,
218	ARM64_REG_Q9 = 111,
219	ARM64_REG_Q10 = 112,
220	ARM64_REG_Q11 = 113,
221	ARM64_REG_Q12 = 114,
222	ARM64_REG_Q13 = 115,
223	ARM64_REG_Q14 = 116,
224	ARM64_REG_Q15 = 117,
225	ARM64_REG_Q16 = 118,
226	ARM64_REG_Q17 = 119,
227	ARM64_REG_Q18 = 120,
228	ARM64_REG_Q19 = 121,
229	ARM64_REG_Q20 = 122,
230	ARM64_REG_Q21 = 123,
231	ARM64_REG_Q22 = 124,
232	ARM64_REG_Q23 = 125,
233	ARM64_REG_Q24 = 126,
234	ARM64_REG_Q25 = 127,
235	ARM64_REG_Q26 = 128,
236	ARM64_REG_Q27 = 129,
237	ARM64_REG_Q28 = 130,
238	ARM64_REG_Q29 = 131,
239	ARM64_REG_Q30 = 132,
240	ARM64_REG_Q31 = 133,
241	ARM64_REG_S0 = 134,
242	ARM64_REG_S1 = 135,
243	ARM64_REG_S2 = 136,
244	ARM64_REG_S3 = 137,
245	ARM64_REG_S4 = 138,
246	ARM64_REG_S5 = 139,
247	ARM64_REG_S6 = 140,
248	ARM64_REG_S7 = 141,
249	ARM64_REG_S8 = 142,
250	ARM64_REG_S9 = 143,
251	ARM64_REG_S10 = 144,
252	ARM64_REG_S11 = 145,
253	ARM64_REG_S12 = 146,
254	ARM64_REG_S13 = 147,
255	ARM64_REG_S14 = 148,
256	ARM64_REG_S15 = 149,
257	ARM64_REG_S16 = 150,
258	ARM64_REG_S17 = 151,
259	ARM64_REG_S18 = 152,
260	ARM64_REG_S19 = 153,
261	ARM64_REG_S20 = 154,
262	ARM64_REG_S21 = 155,
263	ARM64_REG_S22 = 156,
264	ARM64_REG_S23 = 157,
265	ARM64_REG_S24 = 158,
266	ARM64_REG_S25 = 159,
267	ARM64_REG_S26 = 160,
268	ARM64_REG_S27 = 161,
269	ARM64_REG_S28 = 162,
270	ARM64_REG_S29 = 163,
271	ARM64_REG_S30 = 164,
272	ARM64_REG_S31 = 165,
273	ARM64_REG_W0 = 166,
274	ARM64_REG_W1 = 167,
275	ARM64_REG_W2 = 168,
276	ARM64_REG_W3 = 169,
277	ARM64_REG_W4 = 170,
278	ARM64_REG_W5 = 171,
279	ARM64_REG_W6 = 172,
280	ARM64_REG_W7 = 173,
281	ARM64_REG_W8 = 174,
282	ARM64_REG_W9 = 175,
283	ARM64_REG_W10 = 176,
284	ARM64_REG_W11 = 177,
285	ARM64_REG_W12 = 178,
286	ARM64_REG_W13 = 179,
287	ARM64_REG_W14 = 180,
288	ARM64_REG_W15 = 181,
289	ARM64_REG_W16 = 182,
290	ARM64_REG_W17 = 183,
291	ARM64_REG_W18 = 184,
292	ARM64_REG_W19 = 185,
293	ARM64_REG_W20 = 186,
294	ARM64_REG_W21 = 187,
295	ARM64_REG_W22 = 188,
296	ARM64_REG_W23 = 189,
297	ARM64_REG_W24 = 190,
298	ARM64_REG_W25 = 191,
299	ARM64_REG_W26 = 192,
300	ARM64_REG_W27 = 193,
301	ARM64_REG_W28 = 194,
302	ARM64_REG_W29 = 195,
303	ARM64_REG_W30 = 196,
304	ARM64_REG_X0 = 197,
305	ARM64_REG_X1 = 198,
306	ARM64_REG_X2 = 199,
307	ARM64_REG_X3 = 200,
308	ARM64_REG_X4 = 201,
309	ARM64_REG_X5 = 202,
310	ARM64_REG_X6 = 203,
311	ARM64_REG_X7 = 204,
312	ARM64_REG_X8 = 205,
313	ARM64_REG_X9 = 206,
314	ARM64_REG_X10 = 207,
315	ARM64_REG_X11 = 208,
316	ARM64_REG_X12 = 209,
317	ARM64_REG_X13 = 210,
318	ARM64_REG_X14 = 211,
319	ARM64_REG_X15 = 212,
320	ARM64_REG_X16 = 213,
321	ARM64_REG_X17 = 214,
322	ARM64_REG_X18 = 215,
323	ARM64_REG_X19 = 216,
324	ARM64_REG_X20 = 217,
325	ARM64_REG_X21 = 218,
326	ARM64_REG_X22 = 219,
327	ARM64_REG_X23 = 220,
328	ARM64_REG_X24 = 221,
329	ARM64_REG_X25 = 222,
330	ARM64_REG_X26 = 223,
331	ARM64_REG_X27 = 224,
332	ARM64_REG_X28 = 225,
333	ARM64_REG_X29 = 226,
334	ARM64_REG_X30 = 227,
335	ARM64_REG_MAX = 228,
336} arm64_reg;
337
338// ARM64 instruction
339typedef enum arm64_insn {
340	ARM64_INS_INVALID = 0,
341	ARM64_INS_ADC,
342	ARM64_INS_ADDHN2,
343	ARM64_INS_ADDHN,
344	ARM64_INS_ADDP,
345	ARM64_INS_ADD,
346	ARM64_INS_CMN,
347	ARM64_INS_ADRP,
348	ARM64_INS_ADR,
349	ARM64_INS_AND,
350	ARM64_INS_ASR,
351	ARM64_INS_AT,
352	ARM64_INS_BFI,
353	ARM64_INS_BFM,
354	ARM64_INS_BFXIL,
355	ARM64_INS_BIC,
356	ARM64_INS_BIF,
357	ARM64_INS_BIT,
358	ARM64_INS_BLR,
359	ARM64_INS_BL,
360	ARM64_INS_BRK,
361	ARM64_INS_BR,
362	ARM64_INS_BSL,
363	ARM64_INS_B,
364	ARM64_INS_CBNZ,
365	ARM64_INS_CBZ,
366	ARM64_INS_CCMN,
367	ARM64_INS_CCMP,
368	ARM64_INS_CLREX,
369	ARM64_INS_CLS,
370	ARM64_INS_CLZ,
371	ARM64_INS_CMEQ,
372	ARM64_INS_CMGE,
373	ARM64_INS_CMGT,
374	ARM64_INS_CMHI,
375	ARM64_INS_CMHS,
376	ARM64_INS_CMLE,
377	ARM64_INS_CMLT,
378	ARM64_INS_CMP,
379	ARM64_INS_CMTST,
380	ARM64_INS_CRC32B,
381	ARM64_INS_CRC32CB,
382	ARM64_INS_CRC32CH,
383	ARM64_INS_CRC32CW,
384	ARM64_INS_CRC32CX,
385	ARM64_INS_CRC32H,
386	ARM64_INS_CRC32W,
387	ARM64_INS_CRC32X,
388	ARM64_INS_CSEL,
389	ARM64_INS_CSINC,
390	ARM64_INS_CSINV,
391	ARM64_INS_CSNEG,
392	ARM64_INS_DCPS1,
393	ARM64_INS_DCPS2,
394	ARM64_INS_DCPS3,
395	ARM64_INS_DC,
396	ARM64_INS_DMB,
397	ARM64_INS_DRPS,
398	ARM64_INS_DSB,
399	ARM64_INS_EON,
400	ARM64_INS_EOR,
401	ARM64_INS_ERET,
402	ARM64_INS_EXTR,
403	ARM64_INS_FABD,
404	ARM64_INS_FABS,
405	ARM64_INS_FACGE,
406	ARM64_INS_FACGT,
407	ARM64_INS_FADDP,
408	ARM64_INS_FADD,
409	ARM64_INS_FCCMPE,
410	ARM64_INS_FCCMP,
411	ARM64_INS_FCMEQ,
412	ARM64_INS_FCMGE,
413	ARM64_INS_FCMGT,
414	ARM64_INS_FCMLE,
415	ARM64_INS_FCMLT,
416	ARM64_INS_FCMP,
417	ARM64_INS_FCMPE,
418	ARM64_INS_FCSEL,
419	ARM64_INS_FCVTAS,
420	ARM64_INS_FCVTAU,
421	ARM64_INS_FCVTMS,
422	ARM64_INS_FCVTMU,
423	ARM64_INS_FCVTNS,
424	ARM64_INS_FCVTNU,
425	ARM64_INS_FCVTPS,
426	ARM64_INS_FCVTPU,
427	ARM64_INS_FCVTZS,
428	ARM64_INS_FCVTZU,
429	ARM64_INS_FCVT,
430	ARM64_INS_FDIV,
431	ARM64_INS_FMADD,
432	ARM64_INS_FMAXNMP,
433	ARM64_INS_FMAXNM,
434	ARM64_INS_FMAXP,
435	ARM64_INS_FMAX,
436	ARM64_INS_FMINNMP,
437	ARM64_INS_FMINNM,
438	ARM64_INS_FMINP,
439	ARM64_INS_FMIN,
440	ARM64_INS_FMLA,
441	ARM64_INS_FMLS,
442	ARM64_INS_FMOV,
443	ARM64_INS_FMSUB,
444	ARM64_INS_FMULX,
445	ARM64_INS_FMUL,
446	ARM64_INS_FNEG,
447	ARM64_INS_FNMADD,
448	ARM64_INS_FNMSUB,
449	ARM64_INS_FNMUL,
450	ARM64_INS_FRECPS,
451	ARM64_INS_FRINTA,
452	ARM64_INS_FRINTI,
453	ARM64_INS_FRINTM,
454	ARM64_INS_FRINTN,
455	ARM64_INS_FRINTP,
456	ARM64_INS_FRINTX,
457	ARM64_INS_FRINTZ,
458	ARM64_INS_FRSQRTS,
459	ARM64_INS_FSQRT,
460	ARM64_INS_FSUB,
461	ARM64_INS_HINT,
462	ARM64_INS_HLT,
463	ARM64_INS_HVC,
464	ARM64_INS_IC,
465	ARM64_INS_INS,
466	ARM64_INS_ISB,
467	ARM64_INS_LDARB,
468	ARM64_INS_LDAR,
469	ARM64_INS_LDARH,
470	ARM64_INS_LDAXP,
471	ARM64_INS_LDAXRB,
472	ARM64_INS_LDAXR,
473	ARM64_INS_LDAXRH,
474	ARM64_INS_LDPSW,
475	ARM64_INS_LDRSB,
476	ARM64_INS_LDURSB,
477	ARM64_INS_LDRSH,
478	ARM64_INS_LDURSH,
479	ARM64_INS_LDRSW,
480	ARM64_INS_LDR,
481	ARM64_INS_LDTRSB,
482	ARM64_INS_LDTRSH,
483	ARM64_INS_LDTRSW,
484	ARM64_INS_LDURSW,
485	ARM64_INS_LDXP,
486	ARM64_INS_LDXRB,
487	ARM64_INS_LDXR,
488	ARM64_INS_LDXRH,
489	ARM64_INS_LDRH,
490	ARM64_INS_LDURH,
491	ARM64_INS_STRH,
492	ARM64_INS_STURH,
493	ARM64_INS_LDTRH,
494	ARM64_INS_STTRH,
495	ARM64_INS_LDUR,
496	ARM64_INS_STR,
497	ARM64_INS_STUR,
498	ARM64_INS_LDTR,
499	ARM64_INS_STTR,
500	ARM64_INS_LDRB,
501	ARM64_INS_LDURB,
502	ARM64_INS_STRB,
503	ARM64_INS_STURB,
504	ARM64_INS_LDTRB,
505	ARM64_INS_STTRB,
506	ARM64_INS_LDP,
507	ARM64_INS_LDNP,
508	ARM64_INS_STNP,
509	ARM64_INS_STP,
510	ARM64_INS_LSL,
511	ARM64_INS_LSR,
512	ARM64_INS_MADD,
513	ARM64_INS_MLA,
514	ARM64_INS_MLS,
515	ARM64_INS_MOVI,
516	ARM64_INS_MOVK,
517	ARM64_INS_MOVN,
518	ARM64_INS_MOVZ,
519	ARM64_INS_MRS,
520	ARM64_INS_MSR,
521	ARM64_INS_MSUB,
522	ARM64_INS_MUL,
523	ARM64_INS_MVNI,
524	ARM64_INS_MVN,
525	ARM64_INS_ORN,
526	ARM64_INS_ORR,
527	ARM64_INS_PMULL2,
528	ARM64_INS_PMULL,
529	ARM64_INS_PMUL,
530	ARM64_INS_PRFM,
531	ARM64_INS_PRFUM,
532	ARM64_INS_SQRSHRUN2,
533	ARM64_INS_SQRSHRUN,
534	ARM64_INS_SQSHRUN2,
535	ARM64_INS_SQSHRUN,
536	ARM64_INS_RADDHN2,
537	ARM64_INS_RADDHN,
538	ARM64_INS_RBIT,
539	ARM64_INS_RET,
540	ARM64_INS_REV16,
541	ARM64_INS_REV32,
542	ARM64_INS_REV,
543	ARM64_INS_ROR,
544	ARM64_INS_RSHRN2,
545	ARM64_INS_RSHRN,
546	ARM64_INS_RSUBHN2,
547	ARM64_INS_RSUBHN,
548	ARM64_INS_SABAL2,
549	ARM64_INS_SABAL,
550	ARM64_INS_SABA,
551	ARM64_INS_SABDL2,
552	ARM64_INS_SABDL,
553	ARM64_INS_SABD,
554	ARM64_INS_SADDL2,
555	ARM64_INS_SADDL,
556	ARM64_INS_SADDW2,
557	ARM64_INS_SADDW,
558	ARM64_INS_SBC,
559	ARM64_INS_SBFIZ,
560	ARM64_INS_SBFM,
561	ARM64_INS_SBFX,
562	ARM64_INS_SCVTF,
563	ARM64_INS_SDIV,
564	ARM64_INS_SHADD,
565	ARM64_INS_SHL,
566	ARM64_INS_SHRN2,
567	ARM64_INS_SHRN,
568	ARM64_INS_SHSUB,
569	ARM64_INS_SLI,
570	ARM64_INS_SMADDL,
571	ARM64_INS_SMAXP,
572	ARM64_INS_SMAX,
573	ARM64_INS_SMC,
574	ARM64_INS_SMINP,
575	ARM64_INS_SMIN,
576	ARM64_INS_SMLAL2,
577	ARM64_INS_SMLAL,
578	ARM64_INS_SMLSL2,
579	ARM64_INS_SMLSL,
580	ARM64_INS_SMOV,
581	ARM64_INS_SMSUBL,
582	ARM64_INS_SMULH,
583	ARM64_INS_SMULL2,
584	ARM64_INS_SMULL,
585	ARM64_INS_SQADD,
586	ARM64_INS_SQDMLAL2,
587	ARM64_INS_SQDMLAL,
588	ARM64_INS_SQDMLSL2,
589	ARM64_INS_SQDMLSL,
590	ARM64_INS_SQDMULH,
591	ARM64_INS_SQDMULL2,
592	ARM64_INS_SQDMULL,
593	ARM64_INS_SQRDMULH,
594	ARM64_INS_SQRSHL,
595	ARM64_INS_SQRSHRN2,
596	ARM64_INS_SQRSHRN,
597	ARM64_INS_SQSHLU,
598	ARM64_INS_SQSHL,
599	ARM64_INS_SQSHRN2,
600	ARM64_INS_SQSHRN,
601	ARM64_INS_SQSUB,
602	ARM64_INS_SRHADD,
603	ARM64_INS_SRI,
604	ARM64_INS_SRSHL,
605	ARM64_INS_SRSHR,
606	ARM64_INS_SRSRA,
607	ARM64_INS_SSHLL2,
608	ARM64_INS_SSHLL,
609	ARM64_INS_SSHL,
610	ARM64_INS_SSHR,
611	ARM64_INS_SSRA,
612	ARM64_INS_SSUBL2,
613	ARM64_INS_SSUBL,
614	ARM64_INS_SSUBW2,
615	ARM64_INS_SSUBW,
616	ARM64_INS_STLRB,
617	ARM64_INS_STLR,
618	ARM64_INS_STLRH,
619	ARM64_INS_STLXP,
620	ARM64_INS_STLXRB,
621	ARM64_INS_STLXR,
622	ARM64_INS_STLXRH,
623	ARM64_INS_STXP,
624	ARM64_INS_STXRB,
625	ARM64_INS_STXR,
626	ARM64_INS_STXRH,
627	ARM64_INS_SUBHN2,
628	ARM64_INS_SUBHN,
629	ARM64_INS_SUB,
630	ARM64_INS_SVC,
631	ARM64_INS_SXTB,
632	ARM64_INS_SXTH,
633	ARM64_INS_SXTW,
634	ARM64_INS_SYSL,
635	ARM64_INS_SYS,
636	ARM64_INS_TBNZ,
637	ARM64_INS_TBZ,
638	ARM64_INS_TLBI,
639	ARM64_INS_TST,
640	ARM64_INS_UABAL2,
641	ARM64_INS_UABAL,
642	ARM64_INS_UABA,
643	ARM64_INS_UABDL2,
644	ARM64_INS_UABDL,
645	ARM64_INS_UABD,
646	ARM64_INS_UADDL2,
647	ARM64_INS_UADDL,
648	ARM64_INS_UADDW2,
649	ARM64_INS_UADDW,
650	ARM64_INS_UBFIZ,
651	ARM64_INS_UBFM,
652	ARM64_INS_UBFX,
653	ARM64_INS_UCVTF,
654	ARM64_INS_UDIV,
655	ARM64_INS_UHADD,
656	ARM64_INS_UHSUB,
657	ARM64_INS_UMADDL,
658	ARM64_INS_UMAXP,
659	ARM64_INS_UMAX,
660	ARM64_INS_UMINP,
661	ARM64_INS_UMIN,
662	ARM64_INS_UMLAL2,
663	ARM64_INS_UMLAL,
664	ARM64_INS_UMLSL2,
665	ARM64_INS_UMLSL,
666	ARM64_INS_UMOV,
667	ARM64_INS_UMSUBL,
668	ARM64_INS_UMULH,
669	ARM64_INS_UMULL2,
670	ARM64_INS_UMULL,
671	ARM64_INS_UQADD,
672	ARM64_INS_UQRSHL,
673	ARM64_INS_UQRSHRN2,
674	ARM64_INS_UQRSHRN,
675	ARM64_INS_UQSHL,
676	ARM64_INS_UQSHRN2,
677	ARM64_INS_UQSHRN,
678	ARM64_INS_UQSUB,
679	ARM64_INS_URHADD,
680	ARM64_INS_URSHL,
681	ARM64_INS_URSHR,
682	ARM64_INS_URSRA,
683	ARM64_INS_USHLL2,
684	ARM64_INS_USHLL,
685	ARM64_INS_USHL,
686	ARM64_INS_USHR,
687	ARM64_INS_USRA,
688	ARM64_INS_USUBL2,
689	ARM64_INS_USUBL,
690	ARM64_INS_USUBW2,
691	ARM64_INS_USUBW,
692	ARM64_INS_UXTB,
693	ARM64_INS_UXTH,
694
695	// alias insn
696	ARM64_INS_MNEG,
697	ARM64_INS_UMNEGL,
698	ARM64_INS_SMNEGL,
699	ARM64_INS_MOV,
700	ARM64_INS_NOP,
701	ARM64_INS_YIELD,
702	ARM64_INS_WFE,
703	ARM64_INS_WFI,
704	ARM64_INS_SEV,
705	ARM64_INS_SEVL,
706	ARM64_INS_NGC,
707	ARM64_INS_NEG,
708
709	ARM64_INS_MAX,
710} arm64_insn;
711
712// group of ARM64 instructions
713typedef enum arm64_insn_group {
714	ARM64_GRP_INVALID = 0,
715	ARM64_GRP_NEON,
716	ARM64_GRP_MAX,
717} arm64_insn_group;
718
719#ifdef __cplusplus
720}
721#endif
722
723#endif
724