14967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s 20aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 30aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu// Test new aarch64 intrinsics and types 40aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 50aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu#include <arm_neon.h> 60aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 74967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmla_lane_s16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %v) #0 { 84967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 94967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i16> %a, [[MUL]] 114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[ADD]] 120aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x4_t test_vmla_lane_s16(int16x4_t a, int16x4_t b, int16x4_t v) { 1351d85463d5debc70d034c257c60b245591495367Bill Wendling return vmla_lane_s16(a, b, v, 3); 140aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 150aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlaq_lane_s16(<8 x i16> %a, <8 x i16> %b, <4 x i16> %v) #0 { 174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> 184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <8 x i16> %a, [[MUL]] 204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[ADD]] 210aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x8_t test_vmlaq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t v) { 2251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlaq_lane_s16(a, b, v, 3); 230aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 240aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmla_lane_s32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %v) #0 { 264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i32> %a, [[MUL]] 294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[ADD]] 300aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x2_t test_vmla_lane_s32(int32x2_t a, int32x2_t b, int32x2_t v) { 310aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmla_lane_s32(a, b, v, 1); 320aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 330aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlaq_lane_s32(<4 x i32> %a, <4 x i32> %b, <2 x i32> %v) #0 { 354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[MUL]] 384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 390aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlaq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t v) { 400aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmlaq_lane_s32(a, b, v, 1); 410aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 420aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmla_laneq_s16(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) #0 { 444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i16> %a, [[MUL]] 474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[ADD]] 480aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x4_t test_vmla_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v) { 4951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmla_laneq_s16(a, b, v, 7); 500aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 510aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlaq_laneq_s16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %v) #0 { 534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7> 544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <8 x i16> %a, [[MUL]] 564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[ADD]] 570aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x8_t test_vmlaq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v) { 5851d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlaq_laneq_s16(a, b, v, 7); 590aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 600aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmla_laneq_s32(<2 x i32> %a, <2 x i32> %b, <4 x i32> %v) #0 { 624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i32> %a, [[MUL]] 654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[ADD]] 660aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x2_t test_vmla_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v) { 6751d85463d5debc70d034c257c60b245591495367Bill Wendling return vmla_laneq_s32(a, b, v, 3); 680aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 690aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlaq_laneq_s32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %v) #0 { 714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[MUL]] 744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 750aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlaq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v) { 7651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlaq_laneq_s32(a, b, v, 3); 770aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 780aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmls_lane_s16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %v) #0 { 804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i16> %a, [[MUL]] 834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[SUB]] 840aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x4_t test_vmls_lane_s16(int16x4_t a, int16x4_t b, int16x4_t v) { 8551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmls_lane_s16(a, b, v, 3); 860aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 870aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlsq_lane_s16(<8 x i16> %a, <8 x i16> %b, <4 x i16> %v) #0 { 894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> 904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <8 x i16> %a, [[MUL]] 924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[SUB]] 930aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x8_t test_vmlsq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t v) { 9451d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsq_lane_s16(a, b, v, 3); 950aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 960aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmls_lane_s32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %v) #0 { 984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 1004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i32> %a, [[MUL]] 1014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[SUB]] 1020aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x2_t test_vmls_lane_s32(int32x2_t a, int32x2_t b, int32x2_t v) { 1030aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmls_lane_s32(a, b, v, 1); 1040aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 1050aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 1064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsq_lane_s32(<4 x i32> %a, <4 x i32> %b, <2 x i32> %v) #0 { 1074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 1084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 1094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[MUL]] 1104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 1110aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlsq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t v) { 1120aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmlsq_lane_s32(a, b, v, 1); 1130aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 1140aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 1154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmls_laneq_s16(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) #0 { 1164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 1174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 1184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i16> %a, [[MUL]] 1194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[SUB]] 1200aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x4_t test_vmls_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v) { 12151d85463d5debc70d034c257c60b245591495367Bill Wendling return vmls_laneq_s16(a, b, v, 7); 1220aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 1230aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 1244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlsq_laneq_s16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %v) #0 { 1254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7> 1264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 1274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <8 x i16> %a, [[MUL]] 1284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[SUB]] 1290aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x8_t test_vmlsq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v) { 13051d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsq_laneq_s16(a, b, v, 7); 1310aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 1320aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 1334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmls_laneq_s32(<2 x i32> %a, <2 x i32> %b, <4 x i32> %v) #0 { 1344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 1354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 1364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i32> %a, [[MUL]] 1374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[SUB]] 1380aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x2_t test_vmls_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v) { 13951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmls_laneq_s32(a, b, v, 3); 1400aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 1410aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 1424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsq_laneq_s32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %v) #0 { 1434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 1444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 1454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[MUL]] 1464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 1470aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlsq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v) { 14851d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsq_laneq_s32(a, b, v, 3); 1490aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 1500aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 1514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmul_lane_s16(<4 x i16> %a, <4 x i16> %v) #0 { 1524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 1534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %a, [[SHUFFLE]] 1544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[MUL]] 1550aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x4_t test_vmul_lane_s16(int16x4_t a, int16x4_t v) { 15651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_lane_s16(a, v, 3); 1570aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 1580aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 1594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmulq_lane_s16(<8 x i16> %a, <4 x i16> %v) #0 { 1604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> 1614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %a, [[SHUFFLE]] 1624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[MUL]] 1630aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x8_t test_vmulq_lane_s16(int16x8_t a, int16x4_t v) { 16451d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_lane_s16(a, v, 3); 1650aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 1660aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 1674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmul_lane_s32(<2 x i32> %a, <2 x i32> %v) #0 { 1684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 1694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %a, [[SHUFFLE]] 1704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[MUL]] 1710aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x2_t test_vmul_lane_s32(int32x2_t a, int32x2_t v) { 1720aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmul_lane_s32(a, v, 1); 1730aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 1740aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 1754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmulq_lane_s32(<4 x i32> %a, <2 x i32> %v) #0 { 1764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 1774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %a, [[SHUFFLE]] 1784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[MUL]] 1790aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmulq_lane_s32(int32x4_t a, int32x2_t v) { 1800aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmulq_lane_s32(a, v, 1); 1810aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 1820aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 1834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmul_lane_u16(<4 x i16> %a, <4 x i16> %v) #0 { 1844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 1854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %a, [[SHUFFLE]] 1864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[MUL]] 1870aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint16x4_t test_vmul_lane_u16(uint16x4_t a, uint16x4_t v) { 18851d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_lane_u16(a, v, 3); 1890aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 1900aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 1914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmulq_lane_u16(<8 x i16> %a, <4 x i16> %v) #0 { 1924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> 1934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %a, [[SHUFFLE]] 1944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[MUL]] 1950aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint16x8_t test_vmulq_lane_u16(uint16x8_t a, uint16x4_t v) { 19651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_lane_u16(a, v, 3); 1970aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 1980aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 1994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmul_lane_u32(<2 x i32> %a, <2 x i32> %v) #0 { 2004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 2014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %a, [[SHUFFLE]] 2024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[MUL]] 2030aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint32x2_t test_vmul_lane_u32(uint32x2_t a, uint32x2_t v) { 2040aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmul_lane_u32(a, v, 1); 2050aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 2060aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 2074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmulq_lane_u32(<4 x i32> %a, <2 x i32> %v) #0 { 2084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 2094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %a, [[SHUFFLE]] 2104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[MUL]] 2110aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint32x4_t test_vmulq_lane_u32(uint32x4_t a, uint32x2_t v) { 2120aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmulq_lane_u32(a, v, 1); 2130aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 2140aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 2154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmul_laneq_s16(<4 x i16> %a, <8 x i16> %v) #0 { 2164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 2174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %a, [[SHUFFLE]] 2184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[MUL]] 2190aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x4_t test_vmul_laneq_s16(int16x4_t a, int16x8_t v) { 22051d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_laneq_s16(a, v, 7); 2210aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 2220aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 2234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmulq_laneq_s16(<8 x i16> %a, <8 x i16> %v) #0 { 2244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7> 2254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %a, [[SHUFFLE]] 2264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[MUL]] 2270aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x8_t test_vmulq_laneq_s16(int16x8_t a, int16x8_t v) { 22851d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_laneq_s16(a, v, 7); 2290aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 2300aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 2314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmul_laneq_s32(<2 x i32> %a, <4 x i32> %v) #0 { 2324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 2334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %a, [[SHUFFLE]] 2344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[MUL]] 2350aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x2_t test_vmul_laneq_s32(int32x2_t a, int32x4_t v) { 23651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_laneq_s32(a, v, 3); 2370aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 2380aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 2394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmulq_laneq_s32(<4 x i32> %a, <4 x i32> %v) #0 { 2404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 2414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %a, [[SHUFFLE]] 2424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[MUL]] 2430aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmulq_laneq_s32(int32x4_t a, int32x4_t v) { 24451d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_laneq_s32(a, v, 3); 2450aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 2460aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 2474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmul_laneq_u16(<4 x i16> %a, <8 x i16> %v) #0 { 2484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 2494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %a, [[SHUFFLE]] 2504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[MUL]] 2510aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint16x4_t test_vmul_laneq_u16(uint16x4_t a, uint16x8_t v) { 25251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_laneq_u16(a, v, 7); 2530aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 2540aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 2554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmulq_laneq_u16(<8 x i16> %a, <8 x i16> %v) #0 { 2564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7> 2574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %a, [[SHUFFLE]] 2584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[MUL]] 2590aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint16x8_t test_vmulq_laneq_u16(uint16x8_t a, uint16x8_t v) { 26051d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_laneq_u16(a, v, 7); 2610aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 2620aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 2634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmul_laneq_u32(<2 x i32> %a, <4 x i32> %v) #0 { 2644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 2654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %a, [[SHUFFLE]] 2664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[MUL]] 2670aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint32x2_t test_vmul_laneq_u32(uint32x2_t a, uint32x4_t v) { 26851d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_laneq_u32(a, v, 3); 2690aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 2700aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 2714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmulq_laneq_u32(<4 x i32> %a, <4 x i32> %v) #0 { 2724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 2734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %a, [[SHUFFLE]] 2744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[MUL]] 2750aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint32x4_t test_vmulq_laneq_u32(uint32x4_t a, uint32x4_t v) { 27651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_laneq_u32(a, v, 3); 2770aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 2780aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 2794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vfma_lane_f32(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 { 2804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 2814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8> 2824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x float> %v to <8 x i8> 2834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float> 2844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> [[TMP3]], <2 x i32> <i32 1, i32 1> 2854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> 2864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 2874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA2:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[FMLA]], <2 x float> [[LANE]], <2 x float> [[FMLA1]]) 2884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[FMLA2]] 2890aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x2_t test_vfma_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) { 2900aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vfma_lane_f32(a, b, v, 1); 2910aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 2920aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 2934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vfmaq_lane_f32(<4 x float> %a, <4 x float> %b, <2 x float> %v) #0 { 2944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 2954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8> 2964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x float> %v to <8 x i8> 2974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float> 2984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> [[TMP3]], <4 x i32> <i32 1, i32 1, i32 1, i32 1> 2994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 3004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 3014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA2:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[FMLA]], <4 x float> [[LANE]], <4 x float> [[FMLA1]]) 3024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[FMLA2]] 3030aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x4_t test_vfmaq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v) { 3040aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vfmaq_lane_f32(a, b, v, 1); 3050aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 3060aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 3074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vfma_laneq_f32(<2 x float> %a, <2 x float> %b, <4 x float> %v) #0 { 3084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 3094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8> 3104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x float> %v to <16 x i8> 3114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 3124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> 3134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float> 3144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> [[TMP5]], <2 x i32> <i32 3, i32 3> 3154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[LANE]], <2 x float> [[TMP4]], <2 x float> [[TMP3]]) 3164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[TMP6]] 3170aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x2_t test_vfma_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v) { 31851d85463d5debc70d034c257c60b245591495367Bill Wendling return vfma_laneq_f32(a, b, v, 3); 3190aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 3200aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 3214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vfmaq_laneq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %v) #0 { 3224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 3234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8> 3244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x float> %v to <16 x i8> 3254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 3264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 3274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float> 3284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> [[TMP5]], <4 x i32> <i32 3, i32 3, i32 3, i32 3> 3294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[LANE]], <4 x float> [[TMP4]], <4 x float> [[TMP3]]) 3304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[TMP6]] 3310aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x4_t test_vfmaq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v) { 33251d85463d5debc70d034c257c60b245591495367Bill Wendling return vfmaq_laneq_f32(a, b, v, 3); 3330aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 3340aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 3354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vfms_lane_f32(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 { 3364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %b 3374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 3384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x float> [[SUB]] to <8 x i8> 3394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x float> %v to <8 x i8> 3404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float> 3414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> [[TMP3]], <2 x i32> <i32 1, i32 1> 3424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> 3434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 3444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA2:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[FMLA]], <2 x float> [[LANE]], <2 x float> [[FMLA1]]) 3454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[FMLA2]] 3460aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x2_t test_vfms_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) { 3470aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vfms_lane_f32(a, b, v, 1); 3480aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 3490aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 3504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vfmsq_lane_f32(<4 x float> %a, <4 x float> %b, <2 x float> %v) #0 { 3514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %b 3524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 3534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x float> [[SUB]] to <16 x i8> 3544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x float> %v to <8 x i8> 3554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float> 3564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> [[TMP3]], <4 x i32> <i32 1, i32 1, i32 1, i32 1> 3574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 3584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 3594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA2:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[FMLA]], <4 x float> [[LANE]], <4 x float> [[FMLA1]]) 3604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[FMLA2]] 3610aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x4_t test_vfmsq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v) { 3620aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vfmsq_lane_f32(a, b, v, 1); 3630aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 3640aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 3654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vfms_laneq_f32(<2 x float> %a, <2 x float> %b, <4 x float> %v) #0 { 3664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %b 3674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 3684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x float> [[SUB]] to <8 x i8> 3694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x float> %v to <16 x i8> 3704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 3714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> 3724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float> 3734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> [[TMP5]], <2 x i32> <i32 3, i32 3> 3744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[LANE]], <2 x float> [[TMP4]], <2 x float> [[TMP3]]) 3754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[TMP6]] 3760aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x2_t test_vfms_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v) { 37751d85463d5debc70d034c257c60b245591495367Bill Wendling return vfms_laneq_f32(a, b, v, 3); 3780aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 3790aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 3804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vfmsq_laneq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %v) #0 { 3814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %b 3824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 3834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x float> [[SUB]] to <16 x i8> 3844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x float> %v to <16 x i8> 3854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 3864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 3874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float> 3884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> [[TMP5]], <4 x i32> <i32 3, i32 3, i32 3, i32 3> 3894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[LANE]], <4 x float> [[TMP4]], <4 x float> [[TMP3]]) 3904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[TMP6]] 3910aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x4_t test_vfmsq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v) { 39251d85463d5debc70d034c257c60b245591495367Bill Wendling return vfmsq_laneq_f32(a, b, v, 3); 3930aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 3940aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 3954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vfmaq_lane_f64(<2 x double> %a, <2 x double> %b, <1 x double> %v) #0 { 3964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8> 3974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x double> %b to <16 x i8> 3984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <1 x double> %v to <8 x i8> 3994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double> 4004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <1 x double> [[TMP3]], <1 x double> [[TMP3]], <2 x i32> zeroinitializer 4014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> 4024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double> 4034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA2:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[FMLA]], <2 x double> [[LANE]], <2 x double> [[FMLA1]]) 4044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[FMLA2]] 4050aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat64x2_t test_vfmaq_lane_f64(float64x2_t a, float64x2_t b, float64x1_t v) { 4060aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vfmaq_lane_f64(a, b, v, 0); 4070aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 4080aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 4094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vfmaq_laneq_f64(<2 x double> %a, <2 x double> %b, <2 x double> %v) #0 { 4104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8> 4114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x double> %b to <16 x i8> 4124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x double> %v to <16 x i8> 4134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double> 4144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> 4154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x double> 4164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x double> [[TMP5]], <2 x i32> <i32 1, i32 1> 4174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[LANE]], <2 x double> [[TMP4]], <2 x double> [[TMP3]]) 4184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[TMP6]] 4190aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat64x2_t test_vfmaq_laneq_f64(float64x2_t a, float64x2_t b, float64x2_t v) { 4200aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vfmaq_laneq_f64(a, b, v, 1); 4210aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 4220aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 4234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vfmsq_lane_f64(<2 x double> %a, <2 x double> %b, <1 x double> %v) #0 { 4244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %b 4254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8> 4264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x double> [[SUB]] to <16 x i8> 4274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <1 x double> %v to <8 x i8> 4284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double> 4294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <1 x double> [[TMP3]], <1 x double> [[TMP3]], <2 x i32> zeroinitializer 4304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> 4314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double> 4324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA2:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[FMLA]], <2 x double> [[LANE]], <2 x double> [[FMLA1]]) 4334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[FMLA2]] 4340aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat64x2_t test_vfmsq_lane_f64(float64x2_t a, float64x2_t b, float64x1_t v) { 4350aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vfmsq_lane_f64(a, b, v, 0); 4360aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 4370aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 4384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vfmsq_laneq_f64(<2 x double> %a, <2 x double> %b, <2 x double> %v) #0 { 4394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %b 4404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8> 4414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x double> [[SUB]] to <16 x i8> 4424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x double> %v to <16 x i8> 4434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double> 4444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> 4454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x double> 4464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x double> [[TMP5]], <2 x i32> <i32 1, i32 1> 4474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[LANE]], <2 x double> [[TMP4]], <2 x double> [[TMP3]]) 4484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[TMP6]] 4490aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat64x2_t test_vfmsq_laneq_f64(float64x2_t a, float64x2_t b, float64x2_t v) { 4500aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vfmsq_laneq_f64(a, b, v, 1); 4510aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 4520aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 4534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define float @test_vfmas_laneq_f32(float %a, float %b, <4 x float> %v) #0 { 4544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %v to <16 x i8> 4554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 4564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[EXTRACT:%.*]] = extractelement <4 x float> [[TMP1]], i32 3 4574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = call float @llvm.fma.f32(float %b, float [[EXTRACT]], float %a) 4584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret float [[TMP2]] 459651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesfloat32_t test_vfmas_laneq_f32(float32_t a, float32_t b, float32x4_t v) { 460651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vfmas_laneq_f32(a, b, v, 3); 461651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 462651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 4634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define double @test_vfmsd_lane_f64(double %a, double %b, <1 x double> %v) #0 { 4644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = fsub double -0.000000e+00, %b 4654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <1 x double> %v to <8 x i8> 4664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x double> 4674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[EXTRACT:%.*]] = extractelement <1 x double> [[TMP1]], i32 0 4684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = call double @llvm.fma.f64(double [[SUB]], double [[EXTRACT]], double %a) 4694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret double [[TMP2]] 470651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesfloat64_t test_vfmsd_lane_f64(float64_t a, float64_t b, float64x1_t v) { 471651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vfmsd_lane_f64(a, b, v, 0); 472651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 473651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 4744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define float @test_vfmss_laneq_f32(float %a, float %b, <4 x float> %v) #0 { 4754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = fsub float -0.000000e+00, %b 4764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %v to <16 x i8> 4774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 4784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[EXTRACT:%.*]] = extractelement <4 x float> [[TMP1]], i32 3 4794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = call float @llvm.fma.f32(float [[SUB]], float [[EXTRACT]], float %a) 4804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret float [[TMP2]] 481651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesfloat32_t test_vfmss_laneq_f32(float32_t a, float32_t b, float32x4_t v) { 482651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vfmss_laneq_f32(a, b, v, 3); 483651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 484651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 4854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define double @test_vfmsd_laneq_f64(double %a, double %b, <2 x double> %v) #0 { 4864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = fsub double -0.000000e+00, %b 4874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %v to <16 x i8> 4884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double> 4894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[EXTRACT:%.*]] = extractelement <2 x double> [[TMP1]], i32 1 4904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = call double @llvm.fma.f64(double [[SUB]], double [[EXTRACT]], double %a) 4914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret double [[TMP2]] 492651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesfloat64_t test_vfmsd_laneq_f64(float64_t a, float64_t b, float64x2_t v) { 493651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vfmsd_laneq_f64(a, b, v, 1); 494651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 495651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 4964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_lane_s16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %v) #0 { 4974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 4984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 4994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 5004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 5014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 5024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 5034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 5044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 5050aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlal_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v) { 50651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_lane_s16(a, b, v, 3); 5070aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 5080aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 5094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_lane_s32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %v) #0 { 5104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 5114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 5124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 5134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 5144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 5154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 5164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 5174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 5180aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlal_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v) { 5190aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmlal_lane_s32(a, b, v, 1); 5200aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 5210aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 5224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_laneq_s16(<4 x i32> %a, <4 x i16> %b, <8 x i16> %v) #0 { 5234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 5244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 5254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 5264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 5274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 5284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 5294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 5304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 5310aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlal_laneq_s16(int32x4_t a, int16x4_t b, int16x8_t v) { 53251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_laneq_s16(a, b, v, 7); 5330aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 5340aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 5354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_laneq_s32(<2 x i64> %a, <2 x i32> %b, <4 x i32> %v) #0 { 5364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 5374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 5384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 5394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 5404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 5414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 5424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 5434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 5440aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlal_laneq_s32(int64x2_t a, int32x2_t b, int32x4_t v) { 54551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_laneq_s32(a, b, v, 3); 5460aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 5470aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 5484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_high_lane_s16(<4 x i32> %a, <8 x i16> %b, <4 x i16> %v) #0 { 5494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 5504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 5514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 5524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 5534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 5544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 5554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 5564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 5574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 5580aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlal_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t v) { 55951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_high_lane_s16(a, b, v, 3); 5600aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 5610aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 5624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_high_lane_s32(<2 x i64> %a, <4 x i32> %b, <2 x i32> %v) #0 { 5634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 5644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 5654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 5664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 5674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 5684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 5694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 5704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 5714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 5720aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlal_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t v) { 5730aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmlal_high_lane_s32(a, b, v, 1); 5740aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 5750aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 5764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_high_laneq_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %v) #0 { 5774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 5784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 5794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 5804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 5814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 5824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 5834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 5844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 5854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 5860aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlal_high_laneq_s16(int32x4_t a, int16x8_t b, int16x8_t v) { 58751d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_high_laneq_s16(a, b, v, 7); 5880aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 5890aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 5904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_high_laneq_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %v) #0 { 5914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 5924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 5934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 5944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 5954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 5964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 5974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 5984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 5994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 6000aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlal_high_laneq_s32(int64x2_t a, int32x4_t b, int32x4_t v) { 60151d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_high_laneq_s32(a, b, v, 3); 6020aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 6030aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 6044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_lane_s16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %v) #0 { 6054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 6064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 6074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 6084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 6094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 6104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 6114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 6124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 6130aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlsl_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v) { 61451d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_lane_s16(a, b, v, 3); 6150aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 6160aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 6174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_lane_s32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %v) #0 { 6184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 6194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 6204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 6214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 6224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 6234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 6244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 6254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 6260aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlsl_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v) { 6270aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmlsl_lane_s32(a, b, v, 1); 6280aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 6290aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 6304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_laneq_s16(<4 x i32> %a, <4 x i16> %b, <8 x i16> %v) #0 { 6314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 6324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 6334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 6344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 6354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 6364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 6374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 6384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 6390aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlsl_laneq_s16(int32x4_t a, int16x4_t b, int16x8_t v) { 64051d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_laneq_s16(a, b, v, 7); 6410aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 6420aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 6434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_laneq_s32(<2 x i64> %a, <2 x i32> %b, <4 x i32> %v) #0 { 6444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 6454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 6464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 6474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 6484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 6494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 6504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 6514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 6520aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlsl_laneq_s32(int64x2_t a, int32x2_t b, int32x4_t v) { 65351d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_laneq_s32(a, b, v, 3); 6540aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 6550aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 6564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_high_lane_s16(<4 x i32> %a, <8 x i16> %b, <4 x i16> %v) #0 { 6574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 6584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 6594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 6604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 6614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 6624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 6634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 6644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 6654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 6660aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlsl_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t v) { 66751d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_high_lane_s16(a, b, v, 3); 6680aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 6690aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 6704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_high_lane_s32(<2 x i64> %a, <4 x i32> %b, <2 x i32> %v) #0 { 6714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 6724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 6734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 6744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 6754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 6764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 6774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 6784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 6794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 6800aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlsl_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t v) { 6810aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmlsl_high_lane_s32(a, b, v, 1); 6820aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 6830aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 6844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_high_laneq_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %v) #0 { 6854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 6864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 6874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 6884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 6894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 6904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 6914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 6924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 6934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 6940aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlsl_high_laneq_s16(int32x4_t a, int16x8_t b, int16x8_t v) { 69551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_high_laneq_s16(a, b, v, 7); 6960aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 6970aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 6984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_high_laneq_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %v) #0 { 6994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 7004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 7014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 7024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 7034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 7044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 7054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 7064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 7074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 7080aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlsl_high_laneq_s32(int64x2_t a, int32x4_t b, int32x4_t v) { 70951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_high_laneq_s32(a, b, v, 3); 7100aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 7110aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 7124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_lane_u16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %v) #0 { 7134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 7144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 7154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 7164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 7174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 7184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 7194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 7204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 7210aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlal_lane_u16(int32x4_t a, int16x4_t b, int16x4_t v) { 72251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_lane_u16(a, b, v, 3); 7230aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 7240aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 7254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_lane_u32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %v) #0 { 7264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 7274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 7284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 7294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 7304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 7314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 7324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 7334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 7340aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlal_lane_u32(int64x2_t a, int32x2_t b, int32x2_t v) { 7350aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmlal_lane_u32(a, b, v, 1); 7360aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 7370aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 7384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_laneq_u16(<4 x i32> %a, <4 x i16> %b, <8 x i16> %v) #0 { 7394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 7404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 7414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 7424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 7434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 7444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 7454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 7464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 7470aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlal_laneq_u16(int32x4_t a, int16x4_t b, int16x8_t v) { 74851d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_laneq_u16(a, b, v, 7); 7490aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 7500aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 7514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_laneq_u32(<2 x i64> %a, <2 x i32> %b, <4 x i32> %v) #0 { 7524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 7534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 7544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 7554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 7564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 7574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 7584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 7594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 7600aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlal_laneq_u32(int64x2_t a, int32x2_t b, int32x4_t v) { 76151d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_laneq_u32(a, b, v, 3); 7620aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 7630aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 7644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_high_lane_u16(<4 x i32> %a, <8 x i16> %b, <4 x i16> %v) #0 { 7654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 7664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 7674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 7684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 7694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 7704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 7714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 7724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 7734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 7740aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlal_high_lane_u16(int32x4_t a, int16x8_t b, int16x4_t v) { 77551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_high_lane_u16(a, b, v, 3); 7760aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 7770aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 7784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_high_lane_u32(<2 x i64> %a, <4 x i32> %b, <2 x i32> %v) #0 { 7794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 7804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 7814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 7824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 7834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 7844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 7854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 7864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 7874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 7880aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlal_high_lane_u32(int64x2_t a, int32x4_t b, int32x2_t v) { 7890aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmlal_high_lane_u32(a, b, v, 1); 7900aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 7910aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 7924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_high_laneq_u16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %v) #0 { 7934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 7944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 7954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 7964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 7974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 7984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 7994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 8004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 8014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 8020aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlal_high_laneq_u16(int32x4_t a, int16x8_t b, int16x8_t v) { 80351d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_high_laneq_u16(a, b, v, 7); 8040aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 8050aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 8064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_high_laneq_u32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %v) #0 { 8074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 8084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 8094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 8104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 8114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 8124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 8134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 8144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 8154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 8160aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlal_high_laneq_u32(int64x2_t a, int32x4_t b, int32x4_t v) { 81751d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_high_laneq_u32(a, b, v, 3); 8180aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 8190aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 8204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_lane_u16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %v) #0 { 8214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 8224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 8234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 8244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 8254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 8264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 8274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 8284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 8290aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlsl_lane_u16(int32x4_t a, int16x4_t b, int16x4_t v) { 83051d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_lane_u16(a, b, v, 3); 8310aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 8320aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 8334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_lane_u32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %v) #0 { 8344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 8354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 8364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 8374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 8384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 8394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 8404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 8414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 8420aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlsl_lane_u32(int64x2_t a, int32x2_t b, int32x2_t v) { 8430aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmlsl_lane_u32(a, b, v, 1); 8440aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 8450aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 8464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_laneq_u16(<4 x i32> %a, <4 x i16> %b, <8 x i16> %v) #0 { 8474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 8484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 8494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 8504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 8514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 8524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 8534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 8544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 8550aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlsl_laneq_u16(int32x4_t a, int16x4_t b, int16x8_t v) { 85651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_laneq_u16(a, b, v, 7); 8570aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 8580aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 8594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_laneq_u32(<2 x i64> %a, <2 x i32> %b, <4 x i32> %v) #0 { 8604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 8614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 8624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 8634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 8644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 8654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 8664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 8674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 8680aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlsl_laneq_u32(int64x2_t a, int32x2_t b, int32x4_t v) { 86951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_laneq_u32(a, b, v, 3); 8700aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 8710aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 8724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_high_lane_u16(<4 x i32> %a, <8 x i16> %b, <4 x i16> %v) #0 { 8734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 8744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 8754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 8764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 8774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 8784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 8794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 8804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 8814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 8820aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlsl_high_lane_u16(int32x4_t a, int16x8_t b, int16x4_t v) { 88351d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_high_lane_u16(a, b, v, 3); 8840aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 8850aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 8864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_high_lane_u32(<2 x i64> %a, <4 x i32> %b, <2 x i32> %v) #0 { 8874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 8884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 8894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 8904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 8914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 8924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 8934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 8944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 8954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 8960aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlsl_high_lane_u32(int64x2_t a, int32x4_t b, int32x2_t v) { 8970aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmlsl_high_lane_u32(a, b, v, 1); 8980aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 8990aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 9004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_high_laneq_u16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %v) #0 { 9014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 9024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 9034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 9044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 9054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 9064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 9074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 9084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 9094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 9100aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmlsl_high_laneq_u16(int32x4_t a, int16x8_t b, int16x8_t v) { 91151d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_high_laneq_u16(a, b, v, 7); 9120aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 9130aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 9144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_high_laneq_u32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %v) #0 { 9154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 9164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 9174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 9184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 9194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 9204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 9214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 9224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 9234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 9240aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmlsl_high_laneq_u32(int64x2_t a, int32x4_t b, int32x4_t v) { 92551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_high_laneq_u32(a, b, v, 3); 9260aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 9270aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 9284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_lane_s16(<4 x i16> %a, <4 x i16> %v) #0 { 9294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 9304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 9314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 9324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 9334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 9344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 9354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 9360aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmull_lane_s16(int16x4_t a, int16x4_t v) { 93751d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_lane_s16(a, v, 3); 9380aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 9390aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 9404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_lane_s32(<2 x i32> %a, <2 x i32> %v) #0 { 9414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 9424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 9434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 9444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 9454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 9464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 9474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 9480aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmull_lane_s32(int32x2_t a, int32x2_t v) { 9490aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmull_lane_s32(a, v, 1); 9500aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 9510aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 9524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_lane_u16(<4 x i16> %a, <4 x i16> %v) #0 { 9534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 9544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 9554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 9564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 9574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 9584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 9594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 9600aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint32x4_t test_vmull_lane_u16(uint16x4_t a, uint16x4_t v) { 96151d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_lane_u16(a, v, 3); 9620aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 9630aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 9644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_lane_u32(<2 x i32> %a, <2 x i32> %v) #0 { 9654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 9664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 9674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 9684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 9694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 9704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 9714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 9720aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint64x2_t test_vmull_lane_u32(uint32x2_t a, uint32x2_t v) { 9730aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmull_lane_u32(a, v, 1); 9740aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 9750aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 9764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_high_lane_s16(<8 x i16> %a, <4 x i16> %v) #0 { 9774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 9784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 9794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 9804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 9814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 9824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 9834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 9844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 9850aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmull_high_lane_s16(int16x8_t a, int16x4_t v) { 98651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_high_lane_s16(a, v, 3); 9870aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 9880aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 9894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_high_lane_s32(<4 x i32> %a, <2 x i32> %v) #0 { 9904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 9914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 9924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 9934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 9944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 9954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 9964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 9974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 9980aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmull_high_lane_s32(int32x4_t a, int32x2_t v) { 9990aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmull_high_lane_s32(a, v, 1); 10000aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 10010aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 10024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_high_lane_u16(<8 x i16> %a, <4 x i16> %v) #0 { 10034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 10044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 10054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 10064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 10074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 10084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 10094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 10104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 10110aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint32x4_t test_vmull_high_lane_u16(uint16x8_t a, uint16x4_t v) { 101251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_high_lane_u16(a, v, 3); 10130aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 10140aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 10154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_high_lane_u32(<4 x i32> %a, <2 x i32> %v) #0 { 10164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 10174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 10184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 10194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 10204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 10214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 10224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 10234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 10240aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint64x2_t test_vmull_high_lane_u32(uint32x4_t a, uint32x2_t v) { 10250aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmull_high_lane_u32(a, v, 1); 10260aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 10270aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 10284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_laneq_s16(<4 x i16> %a, <8 x i16> %v) #0 { 10294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 10304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 10314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 10324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 10334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 10344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 10354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 10360aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmull_laneq_s16(int16x4_t a, int16x8_t v) { 103751d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_laneq_s16(a, v, 7); 10380aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 10390aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 10404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_laneq_s32(<2 x i32> %a, <4 x i32> %v) #0 { 10414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 10424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 10434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 10444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 10454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 10464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 10474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 10480aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmull_laneq_s32(int32x2_t a, int32x4_t v) { 104951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_laneq_s32(a, v, 3); 10500aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 10510aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 10524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_laneq_u16(<4 x i16> %a, <8 x i16> %v) #0 { 10534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 10544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 10554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 10564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 10574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 10584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 10594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 10600aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint32x4_t test_vmull_laneq_u16(uint16x4_t a, uint16x8_t v) { 106151d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_laneq_u16(a, v, 7); 10620aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 10630aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 10644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_laneq_u32(<2 x i32> %a, <4 x i32> %v) #0 { 10654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 10664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 10674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 10684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 10694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 10704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 10714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 10720aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint64x2_t test_vmull_laneq_u32(uint32x2_t a, uint32x4_t v) { 107351d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_laneq_u32(a, v, 3); 10740aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 10750aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 10764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_high_laneq_s16(<8 x i16> %a, <8 x i16> %v) #0 { 10774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 10784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 10794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 10804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 10814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 10824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 10834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 10844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 10850aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vmull_high_laneq_s16(int16x8_t a, int16x8_t v) { 108651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_high_laneq_s16(a, v, 7); 10870aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 10880aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 10894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_high_laneq_s32(<4 x i32> %a, <4 x i32> %v) #0 { 10904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 10914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 10924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 10934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 10944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 10954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 10964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 10974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 10980aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vmull_high_laneq_s32(int32x4_t a, int32x4_t v) { 109951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_high_laneq_s32(a, v, 3); 11000aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 11010aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 11024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_high_laneq_u16(<8 x i16> %a, <8 x i16> %v) #0 { 11034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 11044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 11054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 11064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 11074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 11084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 11094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 11104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 11110aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint32x4_t test_vmull_high_laneq_u16(uint16x8_t a, uint16x8_t v) { 111251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_high_laneq_u16(a, v, 7); 11130aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 11140aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 11154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_high_laneq_u32(<4 x i32> %a, <4 x i32> %v) #0 { 11164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 11174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 11184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 11194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 11204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 11214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 11224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 11234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 11240aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuuint64x2_t test_vmull_high_laneq_u32(uint32x4_t a, uint32x4_t v) { 112551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_high_laneq_u32(a, v, 3); 11260aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 11270aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 11284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlal_lane_s16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %v) #0 { 11294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 11304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 11314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> 11324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 11334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 11344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 11354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 11364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 11374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[VQDMLAL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 11384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLAL_V3_I]] 11390aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vqdmlal_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v) { 114051d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmlal_lane_s16(a, b, v, 3); 11410aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 11420aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 11434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlal_lane_s32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %v) #0 { 11444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 11454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 11464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> 11474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 11484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 11494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 11504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 11514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 11524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[VQDMLAL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 11534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLAL_V3_I]] 11540aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vqdmlal_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v) { 11550aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vqdmlal_lane_s32(a, b, v, 1); 11560aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 11570aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 11584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlal_high_lane_s16(<4 x i32> %a, <8 x i16> %b, <4 x i16> %v) #0 { 11594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 11604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 11614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 11624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 11634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 11644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 11654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 11664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 11674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 11684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[VQDMLAL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 11694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLAL_V3_I]] 11700aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vqdmlal_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t v) { 117151d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmlal_high_lane_s16(a, b, v, 3); 11720aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 11730aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 11744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlal_high_lane_s32(<2 x i64> %a, <4 x i32> %b, <2 x i32> %v) #0 { 11754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 11764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 11774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 11784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 11794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 11804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 11814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 11824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 11834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 11844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[VQDMLAL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 11854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLAL_V3_I]] 11860aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vqdmlal_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t v) { 11870aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vqdmlal_high_lane_s32(a, b, v, 1); 11880aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 11890aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 11904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlsl_lane_s16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %v) #0 { 11914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 11924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 11934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> 11944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 11954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 11964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 11974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 11984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 11994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[VQDMLSL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 12004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLSL_V3_I]] 12010aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vqdmlsl_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v) { 120251d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmlsl_lane_s16(a, b, v, 3); 12030aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 12040aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 12054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlsl_lane_s32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %v) #0 { 12064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 12074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 12084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> 12094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 12104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 12114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 12124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 12134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 12144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[VQDMLSL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 12154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLSL_V3_I]] 12160aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vqdmlsl_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v) { 12170aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vqdmlsl_lane_s32(a, b, v, 1); 12180aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 12190aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 12204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlsl_high_lane_s16(<4 x i32> %a, <8 x i16> %b, <4 x i16> %v) #0 { 12214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 12224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 12234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 12244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 12254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 12264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 12274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 12284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 12294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 12304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[VQDMLSL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 12314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLSL_V3_I]] 12320aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vqdmlsl_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t v) { 123351d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmlsl_high_lane_s16(a, b, v, 3); 12340aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 12350aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 12364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlsl_high_lane_s32(<2 x i64> %a, <4 x i32> %b, <2 x i32> %v) #0 { 12374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 12384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 12394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 12404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 12414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 12424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 12434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 12444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 12454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 12464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[VQDMLSL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 12474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLSL_V3_I]] 12480aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vqdmlsl_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t v) { 12490aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vqdmlsl_high_lane_s32(a, b, v, 1); 12500aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 12510aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 12524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmull_lane_s16(<4 x i16> %a, <4 x i16> %v) #0 { 12534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 12544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 12554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 12564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 12574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 12584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMULL_V_I]], <4 x i16> [[VQDMULL_V1_I]]) #2 12594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V2_I]] to <16 x i8> 12604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <4 x i32> 12614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 12620aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vqdmull_lane_s16(int16x4_t a, int16x4_t v) { 126351d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmull_lane_s16(a, v, 3); 12640aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 12650aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 12664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmull_lane_s32(<2 x i32> %a, <2 x i32> %v) #0 { 12674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 12684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 12694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 12704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 12714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 12724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMULL_V_I]], <2 x i32> [[VQDMULL_V1_I]]) #2 12734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V2_I]] to <16 x i8> 12744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <2 x i64> 12754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[TMP2]] 12760aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vqdmull_lane_s32(int32x2_t a, int32x2_t v) { 12770aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vqdmull_lane_s32(a, v, 1); 12780aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 12790aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 12804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmull_laneq_s16(<4 x i16> %a, <8 x i16> %v) #0 { 12814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 12824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 12834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 12844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 12854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 12864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMULL_V_I]], <4 x i16> [[VQDMULL_V1_I]]) #2 12874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V2_I]] to <16 x i8> 12884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <4 x i32> 12894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 12900aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vqdmull_laneq_s16(int16x4_t a, int16x8_t v) { 129151d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmull_laneq_s16(a, v, 3); 12920aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 12930aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 12944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmull_laneq_s32(<2 x i32> %a, <4 x i32> %v) #0 { 12954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 12964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 12974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 12984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 12994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 13004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMULL_V_I]], <2 x i32> [[VQDMULL_V1_I]]) #2 13014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V2_I]] to <16 x i8> 13024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <2 x i64> 13034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[TMP2]] 13040aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vqdmull_laneq_s32(int32x2_t a, int32x4_t v) { 130551d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmull_laneq_s32(a, v, 3); 13060aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 13070aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 13084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmull_high_lane_s16(<8 x i16> %a, <4 x i16> %v) #0 { 13094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 13104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 13114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 13124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 13134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 13144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 13154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMULL_V_I]], <4 x i16> [[VQDMULL_V1_I]]) #2 13164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V2_I]] to <16 x i8> 13174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <4 x i32> 13184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 13190aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vqdmull_high_lane_s16(int16x8_t a, int16x4_t v) { 132051d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmull_high_lane_s16(a, v, 3); 13210aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 13220aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 13234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmull_high_lane_s32(<4 x i32> %a, <2 x i32> %v) #0 { 13244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 13254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 13264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 13274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 13284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 13294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 13304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMULL_V_I]], <2 x i32> [[VQDMULL_V1_I]]) #2 13314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V2_I]] to <16 x i8> 13324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <2 x i64> 13334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[TMP2]] 13340aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vqdmull_high_lane_s32(int32x4_t a, int32x2_t v) { 13350aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vqdmull_high_lane_s32(a, v, 1); 13360aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 13370aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 13384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmull_high_laneq_s16(<8 x i16> %a, <8 x i16> %v) #0 { 13394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 13404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 13414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 13424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 13434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 13444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 13454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMULL_V_I]], <4 x i16> [[VQDMULL_V1_I]]) #2 13464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V2_I]] to <16 x i8> 13474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <4 x i32> 13484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 13490aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vqdmull_high_laneq_s16(int16x8_t a, int16x8_t v) { 135051d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmull_high_laneq_s16(a, v, 7); 13510aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 13520aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 13534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmull_high_laneq_s32(<4 x i32> %a, <4 x i32> %v) #0 { 13544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 13554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 13564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 13574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 13584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 13594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 13604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMULL_V_I]], <2 x i32> [[VQDMULL_V1_I]]) #2 13614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V2_I]] to <16 x i8> 13624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <2 x i64> 13634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[TMP2]] 13640aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint64x2_t test_vqdmull_high_laneq_s32(int32x4_t a, int32x4_t v) { 136551d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmull_high_laneq_s32(a, v, 3); 13660aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 13670aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 13684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vqdmulh_lane_s16(<4 x i16> %a, <4 x i16> %v) #0 { 13694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 13704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 13714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 13724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 13734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 13744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> [[VQDMULH_V_I]], <4 x i16> [[VQDMULH_V1_I]]) #2 13754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V3_I:%.*]] = bitcast <4 x i16> [[VQDMULH_V2_I]] to <8 x i8> 13764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQDMULH_V3_I]] to <4 x i16> 13774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[TMP2]] 13780aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x4_t test_vqdmulh_lane_s16(int16x4_t a, int16x4_t v) { 137951d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmulh_lane_s16(a, v, 3); 13800aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 13810aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 13824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vqdmulhq_lane_s16(<8 x i16> %a, <4 x i16> %v) #0 { 13834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> 13844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> 13854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> [[SHUFFLE]] to <16 x i8> 13864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 13874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> 13884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> [[VQDMULHQ_V_I]], <8 x i16> [[VQDMULHQ_V1_I]]) #2 13894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V3_I:%.*]] = bitcast <8 x i16> [[VQDMULHQ_V2_I]] to <16 x i8> 13904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V3_I]] to <8 x i16> 13914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[TMP2]] 13920aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x8_t test_vqdmulhq_lane_s16(int16x8_t a, int16x4_t v) { 139351d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmulhq_lane_s16(a, v, 3); 13940aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 13950aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 13964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vqdmulh_lane_s32(<2 x i32> %a, <2 x i32> %v) #0 { 13974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 13984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 13994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 14004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 14014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 14024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> [[VQDMULH_V_I]], <2 x i32> [[VQDMULH_V1_I]]) #2 14034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V3_I:%.*]] = bitcast <2 x i32> [[VQDMULH_V2_I]] to <8 x i8> 14044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQDMULH_V3_I]] to <2 x i32> 14054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[TMP2]] 14060aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x2_t test_vqdmulh_lane_s32(int32x2_t a, int32x2_t v) { 14070aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vqdmulh_lane_s32(a, v, 1); 14080aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 14090aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 14104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmulhq_lane_s32(<4 x i32> %a, <2 x i32> %v) #0 { 14114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 14124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 14134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8> 14144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 14154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 14164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> [[VQDMULHQ_V_I]], <4 x i32> [[VQDMULHQ_V1_I]]) #2 14174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULHQ_V2_I]] to <16 x i8> 14184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V3_I]] to <4 x i32> 14194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 14200aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vqdmulhq_lane_s32(int32x4_t a, int32x2_t v) { 14210aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vqdmulhq_lane_s32(a, v, 1); 14220aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 14230aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 14244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vqrdmulh_lane_s16(<4 x i16> %a, <4 x i16> %v) #0 { 14254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 14264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 14274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 14284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 14294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 14304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> [[VQRDMULH_V_I]], <4 x i16> [[VQRDMULH_V1_I]]) #2 14314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V3_I:%.*]] = bitcast <4 x i16> [[VQRDMULH_V2_I]] to <8 x i8> 14324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRDMULH_V3_I]] to <4 x i16> 14334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[TMP2]] 14340aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x4_t test_vqrdmulh_lane_s16(int16x4_t a, int16x4_t v) { 143551d85463d5debc70d034c257c60b245591495367Bill Wendling return vqrdmulh_lane_s16(a, v, 3); 14360aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 14370aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 14384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vqrdmulhq_lane_s16(<8 x i16> %a, <4 x i16> %v) #0 { 14394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> 14404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> 14414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> [[SHUFFLE]] to <16 x i8> 14424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 14434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> 14444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> [[VQRDMULHQ_V_I]], <8 x i16> [[VQRDMULHQ_V1_I]]) #2 14454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V3_I:%.*]] = bitcast <8 x i16> [[VQRDMULHQ_V2_I]] to <16 x i8> 14464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V3_I]] to <8 x i16> 14474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[TMP2]] 14480aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint16x8_t test_vqrdmulhq_lane_s16(int16x8_t a, int16x4_t v) { 144951d85463d5debc70d034c257c60b245591495367Bill Wendling return vqrdmulhq_lane_s16(a, v, 3); 14500aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 14510aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 14524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vqrdmulh_lane_s32(<2 x i32> %a, <2 x i32> %v) #0 { 14534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 14544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 14554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 14564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 14574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 14584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> [[VQRDMULH_V_I]], <2 x i32> [[VQRDMULH_V1_I]]) #2 14594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V3_I:%.*]] = bitcast <2 x i32> [[VQRDMULH_V2_I]] to <8 x i8> 14604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRDMULH_V3_I]] to <2 x i32> 14614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[TMP2]] 14620aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x2_t test_vqrdmulh_lane_s32(int32x2_t a, int32x2_t v) { 14630aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vqrdmulh_lane_s32(a, v, 1); 14640aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 14650aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 14664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqrdmulhq_lane_s32(<4 x i32> %a, <2 x i32> %v) #0 { 14674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 14684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 14694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8> 14704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 14714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 14724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> [[VQRDMULHQ_V_I]], <4 x i32> [[VQRDMULHQ_V1_I]]) #2 14734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V3_I:%.*]] = bitcast <4 x i32> [[VQRDMULHQ_V2_I]] to <16 x i8> 14744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V3_I]] to <4 x i32> 14754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 14760aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liuint32x4_t test_vqrdmulhq_lane_s32(int32x4_t a, int32x2_t v) { 14770aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vqrdmulhq_lane_s32(a, v, 1); 14780aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 14790aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 14804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vmul_lane_f32(<2 x float> %a, <2 x float> %v) #0 { 14814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x float> %v, <2 x float> %v, <2 x i32> <i32 1, i32 1> 14824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = fmul <2 x float> %a, [[SHUFFLE]] 14834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[MUL]] 14840aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x2_t test_vmul_lane_f32(float32x2_t a, float32x2_t v) { 14850aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmul_lane_f32(a, v, 1); 14860aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 14870aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 148851cc0172a173599b769968696e20638754d1dcd6Ana Pazos 14894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <1 x double> @test_vmul_lane_f64(<1 x double> %a, <1 x double> %v) #0 { 14904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8> 14914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <1 x double> %v to <8 x i8> 14924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to double 14934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double> 14944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[EXTRACT:%.*]] = extractelement <1 x double> [[TMP3]], i32 0 14954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = fmul double [[TMP2]], [[EXTRACT]] 14964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast double [[TMP4]] to <1 x double> 14974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <1 x double> [[TMP5]] 149851cc0172a173599b769968696e20638754d1dcd6Ana Pazosfloat64x1_t test_vmul_lane_f64(float64x1_t a, float64x1_t v) { 149951cc0172a173599b769968696e20638754d1dcd6Ana Pazos return vmul_lane_f64(a, v, 0); 150051cc0172a173599b769968696e20638754d1dcd6Ana Pazos} 150151cc0172a173599b769968696e20638754d1dcd6Ana Pazos 150251cc0172a173599b769968696e20638754d1dcd6Ana Pazos 15034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vmulq_lane_f32(<4 x float> %a, <2 x float> %v) #0 { 15044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x float> %v, <2 x float> %v, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 15054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = fmul <4 x float> %a, [[SHUFFLE]] 15064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[MUL]] 15070aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x4_t test_vmulq_lane_f32(float32x4_t a, float32x2_t v) { 15080aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmulq_lane_f32(a, v, 1); 15090aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 15100aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 15114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vmulq_lane_f64(<2 x double> %a, <1 x double> %v) #0 { 15124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <1 x double> %v, <1 x double> %v, <2 x i32> zeroinitializer 15134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = fmul <2 x double> %a, [[SHUFFLE]] 15144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[MUL]] 15150aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat64x2_t test_vmulq_lane_f64(float64x2_t a, float64x1_t v) { 15160aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmulq_lane_f64(a, v, 0); 15170aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 15180aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 15194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vmul_laneq_f32(<2 x float> %a, <4 x float> %v) #0 { 15204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x float> %v, <4 x float> %v, <2 x i32> <i32 3, i32 3> 15214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = fmul <2 x float> %a, [[SHUFFLE]] 15224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[MUL]] 15230aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x2_t test_vmul_laneq_f32(float32x2_t a, float32x4_t v) { 152451d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_laneq_f32(a, v, 3); 15250aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 15260aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 15274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <1 x double> @test_vmul_laneq_f64(<1 x double> %a, <2 x double> %v) #0 { 15284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8> 15294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x double> %v to <16 x i8> 15304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to double 15314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> 15324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[EXTRACT:%.*]] = extractelement <2 x double> [[TMP3]], i32 1 15334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = fmul double [[TMP2]], [[EXTRACT]] 15344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast double [[TMP4]] to <1 x double> 15354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <1 x double> [[TMP5]] 153651d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat64x1_t test_vmul_laneq_f64(float64x1_t a, float64x2_t v) { 153751d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_laneq_f64(a, v, 1); 153851cc0172a173599b769968696e20638754d1dcd6Ana Pazos} 153951cc0172a173599b769968696e20638754d1dcd6Ana Pazos 154051cc0172a173599b769968696e20638754d1dcd6Ana Pazos 15414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vmulq_laneq_f32(<4 x float> %a, <4 x float> %v) #0 { 15424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x float> %v, <4 x float> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 15434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = fmul <4 x float> %a, [[SHUFFLE]] 15444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[MUL]] 15450aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x4_t test_vmulq_laneq_f32(float32x4_t a, float32x4_t v) { 154651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_laneq_f32(a, v, 3); 15470aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 15480aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 15494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vmulq_laneq_f64(<2 x double> %a, <2 x double> %v) #0 { 15504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x double> %v, <2 x double> %v, <2 x i32> <i32 1, i32 1> 15514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = fmul <2 x double> %a, [[SHUFFLE]] 15524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[MUL]] 15530aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat64x2_t test_vmulq_laneq_f64(float64x2_t a, float64x2_t v) { 15540aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmulq_laneq_f64(a, v, 1); 15550aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 15560aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 15574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vmulx_lane_f32(<2 x float> %a, <2 x float> %v) #0 { 15584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x float> %v, <2 x float> %v, <2 x i32> <i32 1, i32 1> 15594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 15604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x float> [[SHUFFLE]] to <8 x i8> 15614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 15624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> 15634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX2_I:%.*]] = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> [[VMULX_I]], <2 x float> [[VMULX1_I]]) #2 15644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[VMULX2_I]] 15650aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x2_t test_vmulx_lane_f32(float32x2_t a, float32x2_t v) { 15660aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmulx_lane_f32(a, v, 1); 15670aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 15680aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 15694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vmulxq_lane_f32(<4 x float> %a, <2 x float> %v) #0 { 15704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x float> %v, <2 x float> %v, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 15714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 15724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x float> [[SHUFFLE]] to <16 x i8> 15734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 15744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 15754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX2_I:%.*]] = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> [[VMULX_I]], <4 x float> [[VMULX1_I]]) #2 15764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[VMULX2_I]] 15770aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x4_t test_vmulxq_lane_f32(float32x4_t a, float32x2_t v) { 15780aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmulxq_lane_f32(a, v, 1); 15790aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 15800aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 15814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vmulxq_lane_f64(<2 x double> %a, <1 x double> %v) #0 { 15824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <1 x double> %v, <1 x double> %v, <2 x i32> zeroinitializer 15834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8> 15844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x double> [[SHUFFLE]] to <16 x i8> 15854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double> 15864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> 15874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX2_I:%.*]] = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> [[VMULX_I]], <2 x double> [[VMULX1_I]]) #2 15884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[VMULX2_I]] 15890aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat64x2_t test_vmulxq_lane_f64(float64x2_t a, float64x1_t v) { 15900aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmulxq_lane_f64(a, v, 0); 15910aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 15920aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 15934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vmulx_laneq_f32(<2 x float> %a, <4 x float> %v) #0 { 15944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x float> %v, <4 x float> %v, <2 x i32> <i32 3, i32 3> 15954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 15964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x float> [[SHUFFLE]] to <8 x i8> 15974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 15984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> 15994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX2_I:%.*]] = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> [[VMULX_I]], <2 x float> [[VMULX1_I]]) #2 16004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[VMULX2_I]] 16010aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x2_t test_vmulx_laneq_f32(float32x2_t a, float32x4_t v) { 160251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulx_laneq_f32(a, v, 3); 16030aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 16040aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 16054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vmulxq_laneq_f32(<4 x float> %a, <4 x float> %v) #0 { 16064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x float> %v, <4 x float> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 16074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 16084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x float> [[SHUFFLE]] to <16 x i8> 16094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 16104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 16114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX2_I:%.*]] = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> [[VMULX_I]], <4 x float> [[VMULX1_I]]) #2 16124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[VMULX2_I]] 16130aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat32x4_t test_vmulxq_laneq_f32(float32x4_t a, float32x4_t v) { 161451d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulxq_laneq_f32(a, v, 3); 16150aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 16160aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 16174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vmulxq_laneq_f64(<2 x double> %a, <2 x double> %v) #0 { 16184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x double> %v, <2 x double> %v, <2 x i32> <i32 1, i32 1> 16194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8> 16204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x double> [[SHUFFLE]] to <16 x i8> 16214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double> 16224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> 16234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX2_I:%.*]] = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> [[VMULX_I]], <2 x double> [[VMULX1_I]]) #2 16244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[VMULX2_I]] 16250aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liufloat64x2_t test_vmulxq_laneq_f64(float64x2_t a, float64x2_t v) { 16260aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu return vmulxq_laneq_f64(a, v, 1); 16270aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu} 16280aa1a88e19235574481e46e9e6e9ce66a9e6624fJiangning Liu 16294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmla_lane_s16_0(<4 x i16> %a, <4 x i16> %b, <4 x i16> %v) #0 { 16304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 16314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 16324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i16> %a, [[MUL]] 16334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[ADD]] 163451d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x4_t test_vmla_lane_s16_0(int16x4_t a, int16x4_t b, int16x4_t v) { 163551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmla_lane_s16(a, b, v, 0); 163651d85463d5debc70d034c257c60b245591495367Bill Wendling} 163751d85463d5debc70d034c257c60b245591495367Bill Wendling 16384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlaq_lane_s16_0(<8 x i16> %a, <8 x i16> %b, <4 x i16> %v) #0 { 16394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> zeroinitializer 16404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 16414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <8 x i16> %a, [[MUL]] 16424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[ADD]] 164351d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x8_t test_vmlaq_lane_s16_0(int16x8_t a, int16x8_t b, int16x4_t v) { 164451d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlaq_lane_s16(a, b, v, 0); 164551d85463d5debc70d034c257c60b245591495367Bill Wendling} 164651d85463d5debc70d034c257c60b245591495367Bill Wendling 16474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmla_lane_s32_0(<2 x i32> %a, <2 x i32> %b, <2 x i32> %v) #0 { 16484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 16494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 16504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i32> %a, [[MUL]] 16514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[ADD]] 165251d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x2_t test_vmla_lane_s32_0(int32x2_t a, int32x2_t b, int32x2_t v) { 165351d85463d5debc70d034c257c60b245591495367Bill Wendling return vmla_lane_s32(a, b, v, 0); 165451d85463d5debc70d034c257c60b245591495367Bill Wendling} 165551d85463d5debc70d034c257c60b245591495367Bill Wendling 16564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlaq_lane_s32_0(<4 x i32> %a, <4 x i32> %b, <2 x i32> %v) #0 { 16574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> zeroinitializer 16584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 16594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[MUL]] 16604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 166151d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlaq_lane_s32_0(int32x4_t a, int32x4_t b, int32x2_t v) { 166251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlaq_lane_s32(a, b, v, 0); 166351d85463d5debc70d034c257c60b245591495367Bill Wendling} 166451d85463d5debc70d034c257c60b245591495367Bill Wendling 16654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmla_laneq_s16_0(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) #0 { 16664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 16674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 16684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i16> %a, [[MUL]] 16694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[ADD]] 167051d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x4_t test_vmla_laneq_s16_0(int16x4_t a, int16x4_t b, int16x8_t v) { 167151d85463d5debc70d034c257c60b245591495367Bill Wendling return vmla_laneq_s16(a, b, v, 0); 167251d85463d5debc70d034c257c60b245591495367Bill Wendling} 167351d85463d5debc70d034c257c60b245591495367Bill Wendling 16744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlaq_laneq_s16_0(<8 x i16> %a, <8 x i16> %b, <8 x i16> %v) #0 { 16754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> zeroinitializer 16764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 16774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <8 x i16> %a, [[MUL]] 16784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[ADD]] 167951d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x8_t test_vmlaq_laneq_s16_0(int16x8_t a, int16x8_t b, int16x8_t v) { 168051d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlaq_laneq_s16(a, b, v, 0); 168151d85463d5debc70d034c257c60b245591495367Bill Wendling} 168251d85463d5debc70d034c257c60b245591495367Bill Wendling 16834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmla_laneq_s32_0(<2 x i32> %a, <2 x i32> %b, <4 x i32> %v) #0 { 16844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 16854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 16864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i32> %a, [[MUL]] 16874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[ADD]] 168851d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x2_t test_vmla_laneq_s32_0(int32x2_t a, int32x2_t b, int32x4_t v) { 168951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmla_laneq_s32(a, b, v, 0); 169051d85463d5debc70d034c257c60b245591495367Bill Wendling} 169151d85463d5debc70d034c257c60b245591495367Bill Wendling 16924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlaq_laneq_s32_0(<4 x i32> %a, <4 x i32> %b, <4 x i32> %v) #0 { 16934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> zeroinitializer 16944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 16954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[MUL]] 16964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 169751d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlaq_laneq_s32_0(int32x4_t a, int32x4_t b, int32x4_t v) { 169851d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlaq_laneq_s32(a, b, v, 0); 169951d85463d5debc70d034c257c60b245591495367Bill Wendling} 170051d85463d5debc70d034c257c60b245591495367Bill Wendling 17014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmls_lane_s16_0(<4 x i16> %a, <4 x i16> %b, <4 x i16> %v) #0 { 17024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 17034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 17044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i16> %a, [[MUL]] 17054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[SUB]] 170651d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x4_t test_vmls_lane_s16_0(int16x4_t a, int16x4_t b, int16x4_t v) { 170751d85463d5debc70d034c257c60b245591495367Bill Wendling return vmls_lane_s16(a, b, v, 0); 170851d85463d5debc70d034c257c60b245591495367Bill Wendling} 170951d85463d5debc70d034c257c60b245591495367Bill Wendling 17104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlsq_lane_s16_0(<8 x i16> %a, <8 x i16> %b, <4 x i16> %v) #0 { 17114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> zeroinitializer 17124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 17134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <8 x i16> %a, [[MUL]] 17144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[SUB]] 171551d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x8_t test_vmlsq_lane_s16_0(int16x8_t a, int16x8_t b, int16x4_t v) { 171651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsq_lane_s16(a, b, v, 0); 171751d85463d5debc70d034c257c60b245591495367Bill Wendling} 171851d85463d5debc70d034c257c60b245591495367Bill Wendling 17194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmls_lane_s32_0(<2 x i32> %a, <2 x i32> %b, <2 x i32> %v) #0 { 17204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 17214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 17224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i32> %a, [[MUL]] 17234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[SUB]] 172451d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x2_t test_vmls_lane_s32_0(int32x2_t a, int32x2_t b, int32x2_t v) { 172551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmls_lane_s32(a, b, v, 0); 172651d85463d5debc70d034c257c60b245591495367Bill Wendling} 172751d85463d5debc70d034c257c60b245591495367Bill Wendling 17284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsq_lane_s32_0(<4 x i32> %a, <4 x i32> %b, <2 x i32> %v) #0 { 17294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> zeroinitializer 17304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 17314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[MUL]] 17324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 173351d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlsq_lane_s32_0(int32x4_t a, int32x4_t b, int32x2_t v) { 173451d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsq_lane_s32(a, b, v, 0); 173551d85463d5debc70d034c257c60b245591495367Bill Wendling} 173651d85463d5debc70d034c257c60b245591495367Bill Wendling 17374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmls_laneq_s16_0(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) #0 { 17384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 17394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 17404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i16> %a, [[MUL]] 17414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[SUB]] 174251d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x4_t test_vmls_laneq_s16_0(int16x4_t a, int16x4_t b, int16x8_t v) { 174351d85463d5debc70d034c257c60b245591495367Bill Wendling return vmls_laneq_s16(a, b, v, 0); 174451d85463d5debc70d034c257c60b245591495367Bill Wendling} 174551d85463d5debc70d034c257c60b245591495367Bill Wendling 17464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlsq_laneq_s16_0(<8 x i16> %a, <8 x i16> %b, <8 x i16> %v) #0 { 17474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> zeroinitializer 17484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 17494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <8 x i16> %a, [[MUL]] 17504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[SUB]] 175151d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x8_t test_vmlsq_laneq_s16_0(int16x8_t a, int16x8_t b, int16x8_t v) { 175251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsq_laneq_s16(a, b, v, 0); 175351d85463d5debc70d034c257c60b245591495367Bill Wendling} 175451d85463d5debc70d034c257c60b245591495367Bill Wendling 17554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmls_laneq_s32_0(<2 x i32> %a, <2 x i32> %b, <4 x i32> %v) #0 { 17564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 17574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 17584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i32> %a, [[MUL]] 17594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[SUB]] 176051d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x2_t test_vmls_laneq_s32_0(int32x2_t a, int32x2_t b, int32x4_t v) { 176151d85463d5debc70d034c257c60b245591495367Bill Wendling return vmls_laneq_s32(a, b, v, 0); 176251d85463d5debc70d034c257c60b245591495367Bill Wendling} 176351d85463d5debc70d034c257c60b245591495367Bill Wendling 17644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsq_laneq_s32_0(<4 x i32> %a, <4 x i32> %b, <4 x i32> %v) #0 { 17654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> zeroinitializer 17664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 17674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[MUL]] 17684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 176951d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlsq_laneq_s32_0(int32x4_t a, int32x4_t b, int32x4_t v) { 177051d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsq_laneq_s32(a, b, v, 0); 177151d85463d5debc70d034c257c60b245591495367Bill Wendling} 177251d85463d5debc70d034c257c60b245591495367Bill Wendling 17734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmul_lane_s16_0(<4 x i16> %a, <4 x i16> %v) #0 { 17744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 17754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %a, [[SHUFFLE]] 17764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[MUL]] 177751d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x4_t test_vmul_lane_s16_0(int16x4_t a, int16x4_t v) { 177851d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_lane_s16(a, v, 0); 177951d85463d5debc70d034c257c60b245591495367Bill Wendling} 178051d85463d5debc70d034c257c60b245591495367Bill Wendling 17814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmulq_lane_s16_0(<8 x i16> %a, <4 x i16> %v) #0 { 17824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> zeroinitializer 17834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %a, [[SHUFFLE]] 17844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[MUL]] 178551d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x8_t test_vmulq_lane_s16_0(int16x8_t a, int16x4_t v) { 178651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_lane_s16(a, v, 0); 178751d85463d5debc70d034c257c60b245591495367Bill Wendling} 178851d85463d5debc70d034c257c60b245591495367Bill Wendling 17894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmul_lane_s32_0(<2 x i32> %a, <2 x i32> %v) #0 { 17904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 17914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %a, [[SHUFFLE]] 17924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[MUL]] 179351d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x2_t test_vmul_lane_s32_0(int32x2_t a, int32x2_t v) { 179451d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_lane_s32(a, v, 0); 179551d85463d5debc70d034c257c60b245591495367Bill Wendling} 179651d85463d5debc70d034c257c60b245591495367Bill Wendling 17974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmulq_lane_s32_0(<4 x i32> %a, <2 x i32> %v) #0 { 17984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> zeroinitializer 17994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %a, [[SHUFFLE]] 18004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[MUL]] 180151d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmulq_lane_s32_0(int32x4_t a, int32x2_t v) { 180251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_lane_s32(a, v, 0); 180351d85463d5debc70d034c257c60b245591495367Bill Wendling} 180451d85463d5debc70d034c257c60b245591495367Bill Wendling 18054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmul_lane_u16_0(<4 x i16> %a, <4 x i16> %v) #0 { 18064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 18074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %a, [[SHUFFLE]] 18084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[MUL]] 180951d85463d5debc70d034c257c60b245591495367Bill Wendlinguint16x4_t test_vmul_lane_u16_0(uint16x4_t a, uint16x4_t v) { 181051d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_lane_u16(a, v, 0); 181151d85463d5debc70d034c257c60b245591495367Bill Wendling} 181251d85463d5debc70d034c257c60b245591495367Bill Wendling 18134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmulq_lane_u16_0(<8 x i16> %a, <4 x i16> %v) #0 { 18144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> zeroinitializer 18154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %a, [[SHUFFLE]] 18164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[MUL]] 181751d85463d5debc70d034c257c60b245591495367Bill Wendlinguint16x8_t test_vmulq_lane_u16_0(uint16x8_t a, uint16x4_t v) { 181851d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_lane_u16(a, v, 0); 181951d85463d5debc70d034c257c60b245591495367Bill Wendling} 182051d85463d5debc70d034c257c60b245591495367Bill Wendling 18214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmul_lane_u32_0(<2 x i32> %a, <2 x i32> %v) #0 { 18224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 18234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %a, [[SHUFFLE]] 18244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[MUL]] 182551d85463d5debc70d034c257c60b245591495367Bill Wendlinguint32x2_t test_vmul_lane_u32_0(uint32x2_t a, uint32x2_t v) { 182651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_lane_u32(a, v, 0); 182751d85463d5debc70d034c257c60b245591495367Bill Wendling} 182851d85463d5debc70d034c257c60b245591495367Bill Wendling 18294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmulq_lane_u32_0(<4 x i32> %a, <2 x i32> %v) #0 { 18304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> zeroinitializer 18314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %a, [[SHUFFLE]] 18324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[MUL]] 183351d85463d5debc70d034c257c60b245591495367Bill Wendlinguint32x4_t test_vmulq_lane_u32_0(uint32x4_t a, uint32x2_t v) { 183451d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_lane_u32(a, v, 0); 183551d85463d5debc70d034c257c60b245591495367Bill Wendling} 183651d85463d5debc70d034c257c60b245591495367Bill Wendling 18374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmul_laneq_s16_0(<4 x i16> %a, <8 x i16> %v) #0 { 18384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 18394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %a, [[SHUFFLE]] 18404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[MUL]] 184151d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x4_t test_vmul_laneq_s16_0(int16x4_t a, int16x8_t v) { 184251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_laneq_s16(a, v, 0); 184351d85463d5debc70d034c257c60b245591495367Bill Wendling} 184451d85463d5debc70d034c257c60b245591495367Bill Wendling 18454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmulq_laneq_s16_0(<8 x i16> %a, <8 x i16> %v) #0 { 18464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> zeroinitializer 18474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %a, [[SHUFFLE]] 18484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[MUL]] 184951d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x8_t test_vmulq_laneq_s16_0(int16x8_t a, int16x8_t v) { 185051d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_laneq_s16(a, v, 0); 185151d85463d5debc70d034c257c60b245591495367Bill Wendling} 185251d85463d5debc70d034c257c60b245591495367Bill Wendling 18534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmul_laneq_s32_0(<2 x i32> %a, <4 x i32> %v) #0 { 18544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 18554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %a, [[SHUFFLE]] 18564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[MUL]] 185751d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x2_t test_vmul_laneq_s32_0(int32x2_t a, int32x4_t v) { 185851d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_laneq_s32(a, v, 0); 185951d85463d5debc70d034c257c60b245591495367Bill Wendling} 186051d85463d5debc70d034c257c60b245591495367Bill Wendling 18614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmulq_laneq_s32_0(<4 x i32> %a, <4 x i32> %v) #0 { 18624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> zeroinitializer 18634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %a, [[SHUFFLE]] 18644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[MUL]] 186551d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmulq_laneq_s32_0(int32x4_t a, int32x4_t v) { 186651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_laneq_s32(a, v, 0); 186751d85463d5debc70d034c257c60b245591495367Bill Wendling} 186851d85463d5debc70d034c257c60b245591495367Bill Wendling 18694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmul_laneq_u16_0(<4 x i16> %a, <8 x i16> %v) #0 { 18704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 18714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %a, [[SHUFFLE]] 18724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[MUL]] 187351d85463d5debc70d034c257c60b245591495367Bill Wendlinguint16x4_t test_vmul_laneq_u16_0(uint16x4_t a, uint16x8_t v) { 187451d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_laneq_u16(a, v, 0); 187551d85463d5debc70d034c257c60b245591495367Bill Wendling} 187651d85463d5debc70d034c257c60b245591495367Bill Wendling 18774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmulq_laneq_u16_0(<8 x i16> %a, <8 x i16> %v) #0 { 18784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> zeroinitializer 18794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %a, [[SHUFFLE]] 18804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[MUL]] 188151d85463d5debc70d034c257c60b245591495367Bill Wendlinguint16x8_t test_vmulq_laneq_u16_0(uint16x8_t a, uint16x8_t v) { 188251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_laneq_u16(a, v, 0); 188351d85463d5debc70d034c257c60b245591495367Bill Wendling} 188451d85463d5debc70d034c257c60b245591495367Bill Wendling 18854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmul_laneq_u32_0(<2 x i32> %a, <4 x i32> %v) #0 { 18864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 18874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %a, [[SHUFFLE]] 18884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[MUL]] 188951d85463d5debc70d034c257c60b245591495367Bill Wendlinguint32x2_t test_vmul_laneq_u32_0(uint32x2_t a, uint32x4_t v) { 189051d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_laneq_u32(a, v, 0); 189151d85463d5debc70d034c257c60b245591495367Bill Wendling} 189251d85463d5debc70d034c257c60b245591495367Bill Wendling 18934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmulq_laneq_u32_0(<4 x i32> %a, <4 x i32> %v) #0 { 18944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> zeroinitializer 18954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %a, [[SHUFFLE]] 18964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[MUL]] 189751d85463d5debc70d034c257c60b245591495367Bill Wendlinguint32x4_t test_vmulq_laneq_u32_0(uint32x4_t a, uint32x4_t v) { 189851d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_laneq_u32(a, v, 0); 189951d85463d5debc70d034c257c60b245591495367Bill Wendling} 190051d85463d5debc70d034c257c60b245591495367Bill Wendling 19014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vfma_lane_f32_0(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 { 19024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 19034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8> 19044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x float> %v to <8 x i8> 19054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float> 19064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> [[TMP3]], <2 x i32> zeroinitializer 19074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> 19084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 19094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA2:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[FMLA]], <2 x float> [[LANE]], <2 x float> [[FMLA1]]) 19104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[FMLA2]] 191151d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x2_t test_vfma_lane_f32_0(float32x2_t a, float32x2_t b, float32x2_t v) { 191251d85463d5debc70d034c257c60b245591495367Bill Wendling return vfma_lane_f32(a, b, v, 0); 191351d85463d5debc70d034c257c60b245591495367Bill Wendling} 191451d85463d5debc70d034c257c60b245591495367Bill Wendling 19154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vfmaq_lane_f32_0(<4 x float> %a, <4 x float> %b, <2 x float> %v) #0 { 19164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 19174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8> 19184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x float> %v to <8 x i8> 19194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float> 19204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> [[TMP3]], <4 x i32> zeroinitializer 19214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 19224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 19234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA2:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[FMLA]], <4 x float> [[LANE]], <4 x float> [[FMLA1]]) 19244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[FMLA2]] 192551d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x4_t test_vfmaq_lane_f32_0(float32x4_t a, float32x4_t b, float32x2_t v) { 192651d85463d5debc70d034c257c60b245591495367Bill Wendling return vfmaq_lane_f32(a, b, v, 0); 192751d85463d5debc70d034c257c60b245591495367Bill Wendling} 192851d85463d5debc70d034c257c60b245591495367Bill Wendling 19294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vfma_laneq_f32_0(<2 x float> %a, <2 x float> %b, <4 x float> %v) #0 { 19304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 19314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8> 19324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x float> %v to <16 x i8> 19334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 19344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> 19354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float> 19364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> [[TMP5]], <2 x i32> zeroinitializer 19374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[LANE]], <2 x float> [[TMP4]], <2 x float> [[TMP3]]) 19384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[TMP6]] 193951d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x2_t test_vfma_laneq_f32_0(float32x2_t a, float32x2_t b, float32x4_t v) { 194051d85463d5debc70d034c257c60b245591495367Bill Wendling return vfma_laneq_f32(a, b, v, 0); 194151d85463d5debc70d034c257c60b245591495367Bill Wendling} 194251d85463d5debc70d034c257c60b245591495367Bill Wendling 19434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vfmaq_laneq_f32_0(<4 x float> %a, <4 x float> %b, <4 x float> %v) #0 { 19444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 19454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8> 19464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x float> %v to <16 x i8> 19474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 19484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 19494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float> 19504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> [[TMP5]], <4 x i32> zeroinitializer 19514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[LANE]], <4 x float> [[TMP4]], <4 x float> [[TMP3]]) 19524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[TMP6]] 195351d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x4_t test_vfmaq_laneq_f32_0(float32x4_t a, float32x4_t b, float32x4_t v) { 195451d85463d5debc70d034c257c60b245591495367Bill Wendling return vfmaq_laneq_f32(a, b, v, 0); 195551d85463d5debc70d034c257c60b245591495367Bill Wendling} 195651d85463d5debc70d034c257c60b245591495367Bill Wendling 19574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vfms_lane_f32_0(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 { 19584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %b 19594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 19604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x float> [[SUB]] to <8 x i8> 19614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x float> %v to <8 x i8> 19624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float> 19634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> [[TMP3]], <2 x i32> zeroinitializer 19644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> 19654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 19664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA2:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[FMLA]], <2 x float> [[LANE]], <2 x float> [[FMLA1]]) 19674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[FMLA2]] 196851d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x2_t test_vfms_lane_f32_0(float32x2_t a, float32x2_t b, float32x2_t v) { 196951d85463d5debc70d034c257c60b245591495367Bill Wendling return vfms_lane_f32(a, b, v, 0); 197051d85463d5debc70d034c257c60b245591495367Bill Wendling} 197151d85463d5debc70d034c257c60b245591495367Bill Wendling 19724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vfmsq_lane_f32_0(<4 x float> %a, <4 x float> %b, <2 x float> %v) #0 { 19734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %b 19744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 19754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x float> [[SUB]] to <16 x i8> 19764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x float> %v to <8 x i8> 19774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float> 19784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> [[TMP3]], <4 x i32> zeroinitializer 19794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 19804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 19814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[FMLA2:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[FMLA]], <4 x float> [[LANE]], <4 x float> [[FMLA1]]) 19824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[FMLA2]] 198351d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x4_t test_vfmsq_lane_f32_0(float32x4_t a, float32x4_t b, float32x2_t v) { 198451d85463d5debc70d034c257c60b245591495367Bill Wendling return vfmsq_lane_f32(a, b, v, 0); 198551d85463d5debc70d034c257c60b245591495367Bill Wendling} 198651d85463d5debc70d034c257c60b245591495367Bill Wendling 19874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vfms_laneq_f32_0(<2 x float> %a, <2 x float> %b, <4 x float> %v) #0 { 19884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %b 19894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 19904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x float> [[SUB]] to <8 x i8> 19914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x float> %v to <16 x i8> 19924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 19934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> 19944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float> 19954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> [[TMP5]], <2 x i32> zeroinitializer 19964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[LANE]], <2 x float> [[TMP4]], <2 x float> [[TMP3]]) 19974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[TMP6]] 199851d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x2_t test_vfms_laneq_f32_0(float32x2_t a, float32x2_t b, float32x4_t v) { 199951d85463d5debc70d034c257c60b245591495367Bill Wendling return vfms_laneq_f32(a, b, v, 0); 200051d85463d5debc70d034c257c60b245591495367Bill Wendling} 200151d85463d5debc70d034c257c60b245591495367Bill Wendling 20024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vfmsq_laneq_f32_0(<4 x float> %a, <4 x float> %b, <4 x float> %v) #0 { 20034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %b 20044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 20054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x float> [[SUB]] to <16 x i8> 20064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x float> %v to <16 x i8> 20074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 20084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 20094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float> 20104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> [[TMP5]], <4 x i32> zeroinitializer 20114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[LANE]], <4 x float> [[TMP4]], <4 x float> [[TMP3]]) 20124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[TMP6]] 201351d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x4_t test_vfmsq_laneq_f32_0(float32x4_t a, float32x4_t b, float32x4_t v) { 201451d85463d5debc70d034c257c60b245591495367Bill Wendling return vfmsq_laneq_f32(a, b, v, 0); 201551d85463d5debc70d034c257c60b245591495367Bill Wendling} 201651d85463d5debc70d034c257c60b245591495367Bill Wendling 20174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vfmaq_laneq_f64_0(<2 x double> %a, <2 x double> %b, <2 x double> %v) #0 { 20184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8> 20194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x double> %b to <16 x i8> 20204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x double> %v to <16 x i8> 20214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double> 20224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> 20234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x double> 20244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x double> [[TMP5]], <2 x i32> zeroinitializer 20254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[LANE]], <2 x double> [[TMP4]], <2 x double> [[TMP3]]) 20264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[TMP6]] 202751d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat64x2_t test_vfmaq_laneq_f64_0(float64x2_t a, float64x2_t b, float64x2_t v) { 202851d85463d5debc70d034c257c60b245591495367Bill Wendling return vfmaq_laneq_f64(a, b, v, 0); 202951d85463d5debc70d034c257c60b245591495367Bill Wendling} 203051d85463d5debc70d034c257c60b245591495367Bill Wendling 20314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vfmsq_laneq_f64_0(<2 x double> %a, <2 x double> %b, <2 x double> %v) #0 { 20324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %b 20334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8> 20344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x double> [[SUB]] to <16 x i8> 20354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x double> %v to <16 x i8> 20364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double> 20374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> 20384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x double> 20394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[LANE:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x double> [[TMP5]], <2 x i32> zeroinitializer 20404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[LANE]], <2 x double> [[TMP4]], <2 x double> [[TMP3]]) 20414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[TMP6]] 204251d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat64x2_t test_vfmsq_laneq_f64_0(float64x2_t a, float64x2_t b, float64x2_t v) { 204351d85463d5debc70d034c257c60b245591495367Bill Wendling return vfmsq_laneq_f64(a, b, v, 0); 204451d85463d5debc70d034c257c60b245591495367Bill Wendling} 204551d85463d5debc70d034c257c60b245591495367Bill Wendling 20464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_lane_s16_0(<4 x i32> %a, <4 x i16> %b, <4 x i16> %v) #0 { 20474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 20484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 20494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 20504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 20514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 20524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 20534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 20544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 205551d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlal_lane_s16_0(int32x4_t a, int16x4_t b, int16x4_t v) { 205651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_lane_s16(a, b, v, 0); 205751d85463d5debc70d034c257c60b245591495367Bill Wendling} 205851d85463d5debc70d034c257c60b245591495367Bill Wendling 20594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_lane_s32_0(<2 x i64> %a, <2 x i32> %b, <2 x i32> %v) #0 { 20604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 20614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 20624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 20634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 20644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 20654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 20664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 20674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 206851d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlal_lane_s32_0(int64x2_t a, int32x2_t b, int32x2_t v) { 206951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_lane_s32(a, b, v, 0); 207051d85463d5debc70d034c257c60b245591495367Bill Wendling} 207151d85463d5debc70d034c257c60b245591495367Bill Wendling 20724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_laneq_s16_0(<4 x i32> %a, <4 x i16> %b, <8 x i16> %v) #0 { 20734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 20744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 20754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 20764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 20774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 20784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 20794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 20804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 208151d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlal_laneq_s16_0(int32x4_t a, int16x4_t b, int16x8_t v) { 208251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_laneq_s16(a, b, v, 0); 208351d85463d5debc70d034c257c60b245591495367Bill Wendling} 208451d85463d5debc70d034c257c60b245591495367Bill Wendling 20854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_laneq_s32_0(<2 x i64> %a, <2 x i32> %b, <4 x i32> %v) #0 { 20864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 20874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 20884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 20894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 20904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 20914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 20924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 20934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 209451d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlal_laneq_s32_0(int64x2_t a, int32x2_t b, int32x4_t v) { 209551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_laneq_s32(a, b, v, 0); 209651d85463d5debc70d034c257c60b245591495367Bill Wendling} 209751d85463d5debc70d034c257c60b245591495367Bill Wendling 20984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_high_lane_s16_0(<4 x i32> %a, <8 x i16> %b, <4 x i16> %v) #0 { 20994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 21004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 21014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 21024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 21034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 21044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 21054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 21064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 21074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 210851d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlal_high_lane_s16_0(int32x4_t a, int16x8_t b, int16x4_t v) { 210951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_high_lane_s16(a, b, v, 0); 211051d85463d5debc70d034c257c60b245591495367Bill Wendling} 211151d85463d5debc70d034c257c60b245591495367Bill Wendling 21124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_high_lane_s32_0(<2 x i64> %a, <4 x i32> %b, <2 x i32> %v) #0 { 21134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 21144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 21154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 21164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 21174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 21184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 21194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 21204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 21214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 212251d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlal_high_lane_s32_0(int64x2_t a, int32x4_t b, int32x2_t v) { 212351d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_high_lane_s32(a, b, v, 0); 212451d85463d5debc70d034c257c60b245591495367Bill Wendling} 212551d85463d5debc70d034c257c60b245591495367Bill Wendling 21264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_high_laneq_s16_0(<4 x i32> %a, <8 x i16> %b, <8 x i16> %v) #0 { 21274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 21284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 21294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 21304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 21314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 21324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 21334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 21344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 21354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 213651d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlal_high_laneq_s16_0(int32x4_t a, int16x8_t b, int16x8_t v) { 213751d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_high_laneq_s16(a, b, v, 0); 213851d85463d5debc70d034c257c60b245591495367Bill Wendling} 213951d85463d5debc70d034c257c60b245591495367Bill Wendling 21404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_high_laneq_s32_0(<2 x i64> %a, <4 x i32> %b, <4 x i32> %v) #0 { 21414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 21424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 21434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 21444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 21454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 21464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 21474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 21484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 21494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 215051d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlal_high_laneq_s32_0(int64x2_t a, int32x4_t b, int32x4_t v) { 215151d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_high_laneq_s32(a, b, v, 0); 215251d85463d5debc70d034c257c60b245591495367Bill Wendling} 215351d85463d5debc70d034c257c60b245591495367Bill Wendling 21544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_lane_s16_0(<4 x i32> %a, <4 x i16> %b, <4 x i16> %v) #0 { 21554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 21564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 21574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 21584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 21594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 21604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 21614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 21624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 216351d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlsl_lane_s16_0(int32x4_t a, int16x4_t b, int16x4_t v) { 216451d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_lane_s16(a, b, v, 0); 216551d85463d5debc70d034c257c60b245591495367Bill Wendling} 216651d85463d5debc70d034c257c60b245591495367Bill Wendling 21674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_lane_s32_0(<2 x i64> %a, <2 x i32> %b, <2 x i32> %v) #0 { 21684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 21694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 21704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 21714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 21724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 21734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 21744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 21754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 217651d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlsl_lane_s32_0(int64x2_t a, int32x2_t b, int32x2_t v) { 217751d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_lane_s32(a, b, v, 0); 217851d85463d5debc70d034c257c60b245591495367Bill Wendling} 217951d85463d5debc70d034c257c60b245591495367Bill Wendling 21804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_laneq_s16_0(<4 x i32> %a, <4 x i16> %b, <8 x i16> %v) #0 { 21814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 21824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 21834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 21844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 21854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 21864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 21874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 21884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 218951d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlsl_laneq_s16_0(int32x4_t a, int16x4_t b, int16x8_t v) { 219051d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_laneq_s16(a, b, v, 0); 219151d85463d5debc70d034c257c60b245591495367Bill Wendling} 219251d85463d5debc70d034c257c60b245591495367Bill Wendling 21934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_laneq_s32_0(<2 x i64> %a, <2 x i32> %b, <4 x i32> %v) #0 { 21944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 21954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 21964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 21974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 21984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 21994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 22004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 22014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 220251d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlsl_laneq_s32_0(int64x2_t a, int32x2_t b, int32x4_t v) { 220351d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_laneq_s32(a, b, v, 0); 220451d85463d5debc70d034c257c60b245591495367Bill Wendling} 220551d85463d5debc70d034c257c60b245591495367Bill Wendling 22064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_high_lane_s16_0(<4 x i32> %a, <8 x i16> %b, <4 x i16> %v) #0 { 22074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 22084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 22094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 22104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 22114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 22124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 22134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 22144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 22154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 221651d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlsl_high_lane_s16_0(int32x4_t a, int16x8_t b, int16x4_t v) { 221751d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_high_lane_s16(a, b, v, 0); 221851d85463d5debc70d034c257c60b245591495367Bill Wendling} 221951d85463d5debc70d034c257c60b245591495367Bill Wendling 22204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_high_lane_s32_0(<2 x i64> %a, <4 x i32> %b, <2 x i32> %v) #0 { 22214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 22224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 22234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 22244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 22254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 22264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 22274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 22284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 22294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 223051d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlsl_high_lane_s32_0(int64x2_t a, int32x4_t b, int32x2_t v) { 223151d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_high_lane_s32(a, b, v, 0); 223251d85463d5debc70d034c257c60b245591495367Bill Wendling} 223351d85463d5debc70d034c257c60b245591495367Bill Wendling 22344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_high_laneq_s16_0(<4 x i32> %a, <8 x i16> %b, <8 x i16> %v) #0 { 22354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 22364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 22374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 22384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 22394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 22404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 22414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 22424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 22434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 224451d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlsl_high_laneq_s16_0(int32x4_t a, int16x8_t b, int16x8_t v) { 224551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_high_laneq_s16(a, b, v, 0); 224651d85463d5debc70d034c257c60b245591495367Bill Wendling} 224751d85463d5debc70d034c257c60b245591495367Bill Wendling 22484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_high_laneq_s32_0(<2 x i64> %a, <4 x i32> %b, <4 x i32> %v) #0 { 22494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 22504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 22514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 22524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 22534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 22544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 22554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 22564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 22574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 225851d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlsl_high_laneq_s32_0(int64x2_t a, int32x4_t b, int32x4_t v) { 225951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_high_laneq_s32(a, b, v, 0); 226051d85463d5debc70d034c257c60b245591495367Bill Wendling} 226151d85463d5debc70d034c257c60b245591495367Bill Wendling 22624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_lane_u16_0(<4 x i32> %a, <4 x i16> %b, <4 x i16> %v) #0 { 22634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 22644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 22654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 22664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 22674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 22684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 22694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 22704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 227151d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlal_lane_u16_0(int32x4_t a, int16x4_t b, int16x4_t v) { 227251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_lane_u16(a, b, v, 0); 227351d85463d5debc70d034c257c60b245591495367Bill Wendling} 227451d85463d5debc70d034c257c60b245591495367Bill Wendling 22754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_lane_u32_0(<2 x i64> %a, <2 x i32> %b, <2 x i32> %v) #0 { 22764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 22774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 22784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 22794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 22804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 22814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 22824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 22834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 228451d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlal_lane_u32_0(int64x2_t a, int32x2_t b, int32x2_t v) { 228551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_lane_u32(a, b, v, 0); 228651d85463d5debc70d034c257c60b245591495367Bill Wendling} 228751d85463d5debc70d034c257c60b245591495367Bill Wendling 22884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_laneq_u16_0(<4 x i32> %a, <4 x i16> %b, <8 x i16> %v) #0 { 22894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 22904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 22914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 22924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 22934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 22944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 22954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 22964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 229751d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlal_laneq_u16_0(int32x4_t a, int16x4_t b, int16x8_t v) { 229851d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_laneq_u16(a, b, v, 0); 229951d85463d5debc70d034c257c60b245591495367Bill Wendling} 230051d85463d5debc70d034c257c60b245591495367Bill Wendling 23014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_laneq_u32_0(<2 x i64> %a, <2 x i32> %b, <4 x i32> %v) #0 { 23024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 23034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 23044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 23054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 23064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 23074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 23084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 23094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 231051d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlal_laneq_u32_0(int64x2_t a, int32x2_t b, int32x4_t v) { 231151d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_laneq_u32(a, b, v, 0); 231251d85463d5debc70d034c257c60b245591495367Bill Wendling} 231351d85463d5debc70d034c257c60b245591495367Bill Wendling 23144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_high_lane_u16_0(<4 x i32> %a, <8 x i16> %b, <4 x i16> %v) #0 { 23154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 23164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 23174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 23184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 23194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 23204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 23214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 23224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 23234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 232451d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlal_high_lane_u16_0(int32x4_t a, int16x8_t b, int16x4_t v) { 232551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_high_lane_u16(a, b, v, 0); 232651d85463d5debc70d034c257c60b245591495367Bill Wendling} 232751d85463d5debc70d034c257c60b245591495367Bill Wendling 23284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_high_lane_u32_0(<2 x i64> %a, <4 x i32> %b, <2 x i32> %v) #0 { 23294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 23304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 23314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 23324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 23334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 23344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 23354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 23364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 23374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 233851d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlal_high_lane_u32_0(int64x2_t a, int32x4_t b, int32x2_t v) { 233951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_high_lane_u32(a, b, v, 0); 234051d85463d5debc70d034c257c60b245591495367Bill Wendling} 234151d85463d5debc70d034c257c60b245591495367Bill Wendling 23424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_high_laneq_u16_0(<4 x i32> %a, <8 x i16> %b, <8 x i16> %v) #0 { 23434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 23444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 23454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 23464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 23474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 23484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 23494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 23504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]] 23514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 235251d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlal_high_laneq_u16_0(int32x4_t a, int16x8_t b, int16x8_t v) { 235351d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_high_laneq_u16(a, b, v, 0); 235451d85463d5debc70d034c257c60b245591495367Bill Wendling} 235551d85463d5debc70d034c257c60b245591495367Bill Wendling 23564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_high_laneq_u32_0(<2 x i64> %a, <4 x i32> %b, <4 x i32> %v) #0 { 23574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 23584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 23594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 23604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 23614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 23624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 23634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 23644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]] 23654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD]] 236651d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlal_high_laneq_u32_0(int64x2_t a, int32x4_t b, int32x4_t v) { 236751d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlal_high_laneq_u32(a, b, v, 0); 236851d85463d5debc70d034c257c60b245591495367Bill Wendling} 236951d85463d5debc70d034c257c60b245591495367Bill Wendling 23704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_lane_u16_0(<4 x i32> %a, <4 x i16> %b, <4 x i16> %v) #0 { 23714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 23724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 23734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 23744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 23754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 23764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 23774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 23784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 237951d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlsl_lane_u16_0(int32x4_t a, int16x4_t b, int16x4_t v) { 238051d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_lane_u16(a, b, v, 0); 238151d85463d5debc70d034c257c60b245591495367Bill Wendling} 238251d85463d5debc70d034c257c60b245591495367Bill Wendling 23834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_lane_u32_0(<2 x i64> %a, <2 x i32> %b, <2 x i32> %v) #0 { 23844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 23854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 23864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 23874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 23884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 23894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 23904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 23914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 239251d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlsl_lane_u32_0(int64x2_t a, int32x2_t b, int32x2_t v) { 239351d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_lane_u32(a, b, v, 0); 239451d85463d5debc70d034c257c60b245591495367Bill Wendling} 239551d85463d5debc70d034c257c60b245591495367Bill Wendling 23964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_laneq_u16_0(<4 x i32> %a, <4 x i16> %b, <8 x i16> %v) #0 { 23974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 23984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 23994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 24004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 24014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 24024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 24034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 24044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 240551d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlsl_laneq_u16_0(int32x4_t a, int16x4_t b, int16x8_t v) { 240651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_laneq_u16(a, b, v, 0); 240751d85463d5debc70d034c257c60b245591495367Bill Wendling} 240851d85463d5debc70d034c257c60b245591495367Bill Wendling 24094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_laneq_u32_0(<2 x i64> %a, <2 x i32> %b, <4 x i32> %v) #0 { 24104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 24114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 24124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 24134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 24144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 24154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 24164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 24174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 241851d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlsl_laneq_u32_0(int64x2_t a, int32x2_t b, int32x4_t v) { 241951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_laneq_u32(a, b, v, 0); 242051d85463d5debc70d034c257c60b245591495367Bill Wendling} 242151d85463d5debc70d034c257c60b245591495367Bill Wendling 24224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_high_lane_u16_0(<4 x i32> %a, <8 x i16> %b, <4 x i16> %v) #0 { 24234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 24244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 24254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 24264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 24274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 24284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 24294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 24304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 24314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 243251d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlsl_high_lane_u16_0(int32x4_t a, int16x8_t b, int16x4_t v) { 243351d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_high_lane_u16(a, b, v, 0); 243451d85463d5debc70d034c257c60b245591495367Bill Wendling} 243551d85463d5debc70d034c257c60b245591495367Bill Wendling 24364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_high_lane_u32_0(<2 x i64> %a, <4 x i32> %b, <2 x i32> %v) #0 { 24374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 24384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 24394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 24404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 24414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 24424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 24434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 24444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 24454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 244651d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlsl_high_lane_u32_0(int64x2_t a, int32x4_t b, int32x2_t v) { 244751d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_high_lane_u32(a, b, v, 0); 244851d85463d5debc70d034c257c60b245591495367Bill Wendling} 244951d85463d5debc70d034c257c60b245591495367Bill Wendling 24504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_high_laneq_u16_0(<4 x i32> %a, <8 x i16> %b, <8 x i16> %v) #0 { 24514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 24524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 24534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 24544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 24554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 24564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 24574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 24584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]] 24594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 246051d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmlsl_high_laneq_u16_0(int32x4_t a, int16x8_t b, int16x8_t v) { 246151d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_high_laneq_u16(a, b, v, 0); 246251d85463d5debc70d034c257c60b245591495367Bill Wendling} 246351d85463d5debc70d034c257c60b245591495367Bill Wendling 24644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_high_laneq_u32_0(<2 x i64> %a, <4 x i32> %b, <4 x i32> %v) #0 { 24654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 24664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 24674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 24684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 24694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 24704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 24714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 24724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]] 24734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB]] 247451d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmlsl_high_laneq_u32_0(int64x2_t a, int32x4_t b, int32x4_t v) { 247551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmlsl_high_laneq_u32(a, b, v, 0); 247651d85463d5debc70d034c257c60b245591495367Bill Wendling} 247751d85463d5debc70d034c257c60b245591495367Bill Wendling 24784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_lane_s16_0(<4 x i16> %a, <4 x i16> %v) #0 { 24794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 24804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 24814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 24824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 24834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 24844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 24854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 248651d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmull_lane_s16_0(int16x4_t a, int16x4_t v) { 248751d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_lane_s16(a, v, 0); 248851d85463d5debc70d034c257c60b245591495367Bill Wendling} 248951d85463d5debc70d034c257c60b245591495367Bill Wendling 24904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_lane_s32_0(<2 x i32> %a, <2 x i32> %v) #0 { 24914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 24924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 24934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 24944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 24954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 24964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 24974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 249851d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmull_lane_s32_0(int32x2_t a, int32x2_t v) { 249951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_lane_s32(a, v, 0); 250051d85463d5debc70d034c257c60b245591495367Bill Wendling} 250151d85463d5debc70d034c257c60b245591495367Bill Wendling 25024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_lane_u16_0(<4 x i16> %a, <4 x i16> %v) #0 { 25034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 25044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 25054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 25064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 25074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 25084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 25094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 251051d85463d5debc70d034c257c60b245591495367Bill Wendlinguint32x4_t test_vmull_lane_u16_0(uint16x4_t a, uint16x4_t v) { 251151d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_lane_u16(a, v, 0); 251251d85463d5debc70d034c257c60b245591495367Bill Wendling} 251351d85463d5debc70d034c257c60b245591495367Bill Wendling 25144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_lane_u32_0(<2 x i32> %a, <2 x i32> %v) #0 { 25154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 25164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 25174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 25184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 25194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 25204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 25214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 252251d85463d5debc70d034c257c60b245591495367Bill Wendlinguint64x2_t test_vmull_lane_u32_0(uint32x2_t a, uint32x2_t v) { 252351d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_lane_u32(a, v, 0); 252451d85463d5debc70d034c257c60b245591495367Bill Wendling} 252551d85463d5debc70d034c257c60b245591495367Bill Wendling 25264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_high_lane_s16_0(<8 x i16> %a, <4 x i16> %v) #0 { 25274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 25284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 25294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 25304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 25314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 25324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 25334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 25344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 253551d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmull_high_lane_s16_0(int16x8_t a, int16x4_t v) { 253651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_high_lane_s16(a, v, 0); 253751d85463d5debc70d034c257c60b245591495367Bill Wendling} 253851d85463d5debc70d034c257c60b245591495367Bill Wendling 25394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_high_lane_s32_0(<4 x i32> %a, <2 x i32> %v) #0 { 25404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 25414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 25424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 25434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 25444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 25454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 25464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 25474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 254851d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmull_high_lane_s32_0(int32x4_t a, int32x2_t v) { 254951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_high_lane_s32(a, v, 0); 255051d85463d5debc70d034c257c60b245591495367Bill Wendling} 255151d85463d5debc70d034c257c60b245591495367Bill Wendling 25524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_high_lane_u16_0(<8 x i16> %a, <4 x i16> %v) #0 { 25534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 25544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 25554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 25564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 25574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 25584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 25594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 25604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 256151d85463d5debc70d034c257c60b245591495367Bill Wendlinguint32x4_t test_vmull_high_lane_u16_0(uint16x8_t a, uint16x4_t v) { 256251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_high_lane_u16(a, v, 0); 256351d85463d5debc70d034c257c60b245591495367Bill Wendling} 256451d85463d5debc70d034c257c60b245591495367Bill Wendling 25654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_high_lane_u32_0(<4 x i32> %a, <2 x i32> %v) #0 { 25664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 25674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 25684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 25694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 25704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 25714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 25724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 25734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 257451d85463d5debc70d034c257c60b245591495367Bill Wendlinguint64x2_t test_vmull_high_lane_u32_0(uint32x4_t a, uint32x2_t v) { 257551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_high_lane_u32(a, v, 0); 257651d85463d5debc70d034c257c60b245591495367Bill Wendling} 257751d85463d5debc70d034c257c60b245591495367Bill Wendling 25784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_laneq_s16_0(<4 x i16> %a, <8 x i16> %v) #0 { 25794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 25804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 25814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 25824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 25834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 25844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 25854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 258651d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmull_laneq_s16_0(int16x4_t a, int16x8_t v) { 258751d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_laneq_s16(a, v, 0); 258851d85463d5debc70d034c257c60b245591495367Bill Wendling} 258951d85463d5debc70d034c257c60b245591495367Bill Wendling 25904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_laneq_s32_0(<2 x i32> %a, <4 x i32> %v) #0 { 25914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 25924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 25934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 25944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 25954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 25964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 25974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 259851d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmull_laneq_s32_0(int32x2_t a, int32x4_t v) { 259951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_laneq_s32(a, v, 0); 260051d85463d5debc70d034c257c60b245591495367Bill Wendling} 260151d85463d5debc70d034c257c60b245591495367Bill Wendling 26024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_laneq_u16_0(<4 x i16> %a, <8 x i16> %v) #0 { 26034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 26044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 26054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 26064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 26074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 26084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 26094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 261051d85463d5debc70d034c257c60b245591495367Bill Wendlinguint32x4_t test_vmull_laneq_u16_0(uint16x4_t a, uint16x8_t v) { 261151d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_laneq_u16(a, v, 0); 261251d85463d5debc70d034c257c60b245591495367Bill Wendling} 261351d85463d5debc70d034c257c60b245591495367Bill Wendling 26144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_laneq_u32_0(<2 x i32> %a, <4 x i32> %v) #0 { 26154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 26164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 26174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 26184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 26194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 26204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 26214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 262251d85463d5debc70d034c257c60b245591495367Bill Wendlinguint64x2_t test_vmull_laneq_u32_0(uint32x2_t a, uint32x4_t v) { 262351d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_laneq_u32(a, v, 0); 262451d85463d5debc70d034c257c60b245591495367Bill Wendling} 262551d85463d5debc70d034c257c60b245591495367Bill Wendling 26264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_high_laneq_s16_0(<8 x i16> %a, <8 x i16> %v) #0 { 26274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 26284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 26294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 26304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 26314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 26324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 26334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 26344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 263551d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vmull_high_laneq_s16_0(int16x8_t a, int16x8_t v) { 263651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_high_laneq_s16(a, v, 0); 263751d85463d5debc70d034c257c60b245591495367Bill Wendling} 263851d85463d5debc70d034c257c60b245591495367Bill Wendling 26394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_high_laneq_s32_0(<4 x i32> %a, <4 x i32> %v) #0 { 26404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 26414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 26424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 26434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 26444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 26454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 26464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 26474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 264851d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vmull_high_laneq_s32_0(int32x4_t a, int32x4_t v) { 264951d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_high_laneq_s32(a, v, 0); 265051d85463d5debc70d034c257c60b245591495367Bill Wendling} 265151d85463d5debc70d034c257c60b245591495367Bill Wendling 26524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_high_laneq_u16_0(<8 x i16> %a, <8 x i16> %v) #0 { 26534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 26544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 26554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 26564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 26574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 26584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 26594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) #2 26604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL2_I]] 266151d85463d5debc70d034c257c60b245591495367Bill Wendlinguint32x4_t test_vmull_high_laneq_u16_0(uint16x8_t a, uint16x8_t v) { 266251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_high_laneq_u16(a, v, 0); 266351d85463d5debc70d034c257c60b245591495367Bill Wendling} 266451d85463d5debc70d034c257c60b245591495367Bill Wendling 26654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_high_laneq_u32_0(<4 x i32> %a, <4 x i32> %v) #0 { 26664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 26674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 26684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 26694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 26704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 26714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 26724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2 26734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL2_I]] 267451d85463d5debc70d034c257c60b245591495367Bill Wendlinguint64x2_t test_vmull_high_laneq_u32_0(uint32x4_t a, uint32x4_t v) { 267551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmull_high_laneq_u32(a, v, 0); 267651d85463d5debc70d034c257c60b245591495367Bill Wendling} 267751d85463d5debc70d034c257c60b245591495367Bill Wendling 26784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlal_lane_s16_0(<4 x i32> %a, <4 x i16> %b, <4 x i16> %v) #0 { 26794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 26804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 26814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> 26824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 26834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 26844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 26854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 26864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 26874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[VQDMLAL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 26884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLAL_V3_I]] 268951d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vqdmlal_lane_s16_0(int32x4_t a, int16x4_t b, int16x4_t v) { 269051d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmlal_lane_s16(a, b, v, 0); 269151d85463d5debc70d034c257c60b245591495367Bill Wendling} 269251d85463d5debc70d034c257c60b245591495367Bill Wendling 26934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlal_lane_s32_0(<2 x i64> %a, <2 x i32> %b, <2 x i32> %v) #0 { 26944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 26954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 26964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> 26974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 26984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 26994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 27004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 27014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 27024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[VQDMLAL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 27034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLAL_V3_I]] 270451d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vqdmlal_lane_s32_0(int64x2_t a, int32x2_t b, int32x2_t v) { 270551d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmlal_lane_s32(a, b, v, 0); 270651d85463d5debc70d034c257c60b245591495367Bill Wendling} 270751d85463d5debc70d034c257c60b245591495367Bill Wendling 27084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlal_high_lane_s16_0(<4 x i32> %a, <8 x i16> %b, <4 x i16> %v) #0 { 27094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 27104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 27114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 27124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 27134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 27144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 27154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 27164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 27174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 27184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[VQDMLAL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 27194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLAL_V3_I]] 272051d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vqdmlal_high_lane_s16_0(int32x4_t a, int16x8_t b, int16x4_t v) { 272151d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmlal_high_lane_s16(a, b, v, 0); 272251d85463d5debc70d034c257c60b245591495367Bill Wendling} 272351d85463d5debc70d034c257c60b245591495367Bill Wendling 27244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlal_high_lane_s32_0(<2 x i64> %a, <4 x i32> %b, <2 x i32> %v) #0 { 27254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 27264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 27274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 27284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 27294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 27304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 27314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 27324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 27334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 27344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[VQDMLAL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 27354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLAL_V3_I]] 273651d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vqdmlal_high_lane_s32_0(int64x2_t a, int32x4_t b, int32x2_t v) { 273751d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmlal_high_lane_s32(a, b, v, 0); 273851d85463d5debc70d034c257c60b245591495367Bill Wendling} 273951d85463d5debc70d034c257c60b245591495367Bill Wendling 27404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlsl_lane_s16_0(<4 x i32> %a, <4 x i16> %b, <4 x i16> %v) #0 { 27414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 27424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 27434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> 27444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 27454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 27464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 27474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 27484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 27494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[VQDMLSL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 27504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLSL_V3_I]] 275151d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vqdmlsl_lane_s16_0(int32x4_t a, int16x4_t b, int16x4_t v) { 275251d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmlsl_lane_s16(a, b, v, 0); 275351d85463d5debc70d034c257c60b245591495367Bill Wendling} 275451d85463d5debc70d034c257c60b245591495367Bill Wendling 27554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlsl_lane_s32_0(<2 x i64> %a, <2 x i32> %b, <2 x i32> %v) #0 { 27564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 27574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 27584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> 27594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 27604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 27614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 27624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 27634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 27644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[VQDMLSL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 27654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLSL_V3_I]] 276651d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vqdmlsl_lane_s32_0(int64x2_t a, int32x2_t b, int32x2_t v) { 276751d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmlsl_lane_s32(a, b, v, 0); 276851d85463d5debc70d034c257c60b245591495367Bill Wendling} 276951d85463d5debc70d034c257c60b245591495367Bill Wendling 27704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlsl_high_lane_s16_0(<4 x i32> %a, <8 x i16> %b, <4 x i16> %v) #0 { 27714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 27724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 27734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 27744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 27754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 27764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 27774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 27784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 27794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 27804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[VQDMLSL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 27814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLSL_V3_I]] 278251d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vqdmlsl_high_lane_s16_0(int32x4_t a, int16x8_t b, int16x4_t v) { 278351d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmlsl_high_lane_s16(a, b, v, 0); 278451d85463d5debc70d034c257c60b245591495367Bill Wendling} 278551d85463d5debc70d034c257c60b245591495367Bill Wendling 27864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlsl_high_lane_s32_0(<2 x i64> %a, <4 x i32> %b, <2 x i32> %v) #0 { 27874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 27884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 27894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 27904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 27914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 27924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 27934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 27944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 27954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 27964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[VQDMLSL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 27974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLSL_V3_I]] 279851d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vqdmlsl_high_lane_s32_0(int64x2_t a, int32x4_t b, int32x2_t v) { 279951d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmlsl_high_lane_s32(a, b, v, 0); 280051d85463d5debc70d034c257c60b245591495367Bill Wendling} 280151d85463d5debc70d034c257c60b245591495367Bill Wendling 28024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmull_lane_s16_0(<4 x i16> %a, <4 x i16> %v) #0 { 28034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 28044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 28054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 28064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 28074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 28084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMULL_V_I]], <4 x i16> [[VQDMULL_V1_I]]) #2 28094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V2_I]] to <16 x i8> 28104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <4 x i32> 28114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 281251d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vqdmull_lane_s16_0(int16x4_t a, int16x4_t v) { 281351d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmull_lane_s16(a, v, 0); 281451d85463d5debc70d034c257c60b245591495367Bill Wendling} 281551d85463d5debc70d034c257c60b245591495367Bill Wendling 28164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmull_lane_s32_0(<2 x i32> %a, <2 x i32> %v) #0 { 28174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 28184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 28194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 28204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 28214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 28224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMULL_V_I]], <2 x i32> [[VQDMULL_V1_I]]) #2 28234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V2_I]] to <16 x i8> 28244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <2 x i64> 28254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[TMP2]] 282651d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vqdmull_lane_s32_0(int32x2_t a, int32x2_t v) { 282751d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmull_lane_s32(a, v, 0); 282851d85463d5debc70d034c257c60b245591495367Bill Wendling} 282951d85463d5debc70d034c257c60b245591495367Bill Wendling 28304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmull_laneq_s16_0(<4 x i16> %a, <8 x i16> %v) #0 { 28314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 28324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 28334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 28344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 28354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 28364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMULL_V_I]], <4 x i16> [[VQDMULL_V1_I]]) #2 28374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V2_I]] to <16 x i8> 28384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <4 x i32> 28394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 284051d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vqdmull_laneq_s16_0(int16x4_t a, int16x8_t v) { 284151d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmull_laneq_s16(a, v, 0); 284251d85463d5debc70d034c257c60b245591495367Bill Wendling} 284351d85463d5debc70d034c257c60b245591495367Bill Wendling 28444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmull_laneq_s32_0(<2 x i32> %a, <4 x i32> %v) #0 { 28454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 28464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 28474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 28484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 28494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 28504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMULL_V_I]], <2 x i32> [[VQDMULL_V1_I]]) #2 28514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V2_I]] to <16 x i8> 28524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <2 x i64> 28534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[TMP2]] 285451d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vqdmull_laneq_s32_0(int32x2_t a, int32x4_t v) { 285551d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmull_laneq_s32(a, v, 0); 285651d85463d5debc70d034c257c60b245591495367Bill Wendling} 285751d85463d5debc70d034c257c60b245591495367Bill Wendling 28584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmull_high_lane_s16_0(<8 x i16> %a, <4 x i16> %v) #0 { 28594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 28604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 28614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 28624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 28634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 28644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 28654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMULL_V_I]], <4 x i16> [[VQDMULL_V1_I]]) #2 28664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V2_I]] to <16 x i8> 28674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <4 x i32> 28684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 286951d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vqdmull_high_lane_s16_0(int16x8_t a, int16x4_t v) { 287051d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmull_high_lane_s16(a, v, 0); 287151d85463d5debc70d034c257c60b245591495367Bill Wendling} 287251d85463d5debc70d034c257c60b245591495367Bill Wendling 28734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmull_high_lane_s32_0(<4 x i32> %a, <2 x i32> %v) #0 { 28744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 28754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 28764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 28774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 28784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 28794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 28804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMULL_V_I]], <2 x i32> [[VQDMULL_V1_I]]) #2 28814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V2_I]] to <16 x i8> 28824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <2 x i64> 28834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[TMP2]] 288451d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vqdmull_high_lane_s32_0(int32x4_t a, int32x2_t v) { 288551d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmull_high_lane_s32(a, v, 0); 288651d85463d5debc70d034c257c60b245591495367Bill Wendling} 288751d85463d5debc70d034c257c60b245591495367Bill Wendling 28884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmull_high_laneq_s16_0(<8 x i16> %a, <8 x i16> %v) #0 { 28894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 28904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 28914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 28924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 28934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 28944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 28954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMULL_V_I]], <4 x i16> [[VQDMULL_V1_I]]) #2 28964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V2_I]] to <16 x i8> 28974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <4 x i32> 28984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 289951d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vqdmull_high_laneq_s16_0(int16x8_t a, int16x8_t v) { 290051d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmull_high_laneq_s16(a, v, 0); 290151d85463d5debc70d034c257c60b245591495367Bill Wendling} 290251d85463d5debc70d034c257c60b245591495367Bill Wendling 29034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmull_high_laneq_s32_0(<4 x i32> %a, <4 x i32> %v) #0 { 29044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 29054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 29064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 29074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 29084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 29094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 29104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMULL_V_I]], <2 x i32> [[VQDMULL_V1_I]]) #2 29114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V2_I]] to <16 x i8> 29124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <2 x i64> 29134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[TMP2]] 291451d85463d5debc70d034c257c60b245591495367Bill Wendlingint64x2_t test_vqdmull_high_laneq_s32_0(int32x4_t a, int32x4_t v) { 291551d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmull_high_laneq_s32(a, v, 0); 291651d85463d5debc70d034c257c60b245591495367Bill Wendling} 291751d85463d5debc70d034c257c60b245591495367Bill Wendling 29184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vqdmulh_lane_s16_0(<4 x i16> %a, <4 x i16> %v) #0 { 29194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 29204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 29214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 29224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 29234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 29244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> [[VQDMULH_V_I]], <4 x i16> [[VQDMULH_V1_I]]) #2 29254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V3_I:%.*]] = bitcast <4 x i16> [[VQDMULH_V2_I]] to <8 x i8> 29264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQDMULH_V3_I]] to <4 x i16> 29274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[TMP2]] 292851d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x4_t test_vqdmulh_lane_s16_0(int16x4_t a, int16x4_t v) { 292951d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmulh_lane_s16(a, v, 0); 293051d85463d5debc70d034c257c60b245591495367Bill Wendling} 293151d85463d5debc70d034c257c60b245591495367Bill Wendling 29324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vqdmulhq_lane_s16_0(<8 x i16> %a, <4 x i16> %v) #0 { 29334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> zeroinitializer 29344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> 29354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> [[SHUFFLE]] to <16 x i8> 29364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 29374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> 29384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> [[VQDMULHQ_V_I]], <8 x i16> [[VQDMULHQ_V1_I]]) #2 29394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V3_I:%.*]] = bitcast <8 x i16> [[VQDMULHQ_V2_I]] to <16 x i8> 29404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V3_I]] to <8 x i16> 29414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[TMP2]] 294251d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x8_t test_vqdmulhq_lane_s16_0(int16x8_t a, int16x4_t v) { 294351d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmulhq_lane_s16(a, v, 0); 294451d85463d5debc70d034c257c60b245591495367Bill Wendling} 294551d85463d5debc70d034c257c60b245591495367Bill Wendling 29464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vqdmulh_lane_s32_0(<2 x i32> %a, <2 x i32> %v) #0 { 29474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 29484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 29494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 29504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 29514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 29524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> [[VQDMULH_V_I]], <2 x i32> [[VQDMULH_V1_I]]) #2 29534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V3_I:%.*]] = bitcast <2 x i32> [[VQDMULH_V2_I]] to <8 x i8> 29544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQDMULH_V3_I]] to <2 x i32> 29554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[TMP2]] 295651d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x2_t test_vqdmulh_lane_s32_0(int32x2_t a, int32x2_t v) { 295751d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmulh_lane_s32(a, v, 0); 295851d85463d5debc70d034c257c60b245591495367Bill Wendling} 295951d85463d5debc70d034c257c60b245591495367Bill Wendling 29604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmulhq_lane_s32_0(<4 x i32> %a, <2 x i32> %v) #0 { 29614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> zeroinitializer 29624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 29634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8> 29644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 29654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 29664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> [[VQDMULHQ_V_I]], <4 x i32> [[VQDMULHQ_V1_I]]) #2 29674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULHQ_V2_I]] to <16 x i8> 29684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V3_I]] to <4 x i32> 29694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 297051d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vqdmulhq_lane_s32_0(int32x4_t a, int32x2_t v) { 297151d85463d5debc70d034c257c60b245591495367Bill Wendling return vqdmulhq_lane_s32(a, v, 0); 297251d85463d5debc70d034c257c60b245591495367Bill Wendling} 297351d85463d5debc70d034c257c60b245591495367Bill Wendling 29744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vqrdmulh_lane_s16_0(<4 x i16> %a, <4 x i16> %v) #0 { 29754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 29764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 29774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 29784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 29794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 29804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> [[VQRDMULH_V_I]], <4 x i16> [[VQRDMULH_V1_I]]) #2 29814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V3_I:%.*]] = bitcast <4 x i16> [[VQRDMULH_V2_I]] to <8 x i8> 29824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRDMULH_V3_I]] to <4 x i16> 29834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[TMP2]] 298451d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x4_t test_vqrdmulh_lane_s16_0(int16x4_t a, int16x4_t v) { 298551d85463d5debc70d034c257c60b245591495367Bill Wendling return vqrdmulh_lane_s16(a, v, 0); 298651d85463d5debc70d034c257c60b245591495367Bill Wendling} 298751d85463d5debc70d034c257c60b245591495367Bill Wendling 29884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vqrdmulhq_lane_s16_0(<8 x i16> %a, <4 x i16> %v) #0 { 29894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> zeroinitializer 29904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> 29914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> [[SHUFFLE]] to <16 x i8> 29924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 29934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> 29944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> [[VQRDMULHQ_V_I]], <8 x i16> [[VQRDMULHQ_V1_I]]) #2 29954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V3_I:%.*]] = bitcast <8 x i16> [[VQRDMULHQ_V2_I]] to <16 x i8> 29964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V3_I]] to <8 x i16> 29974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[TMP2]] 299851d85463d5debc70d034c257c60b245591495367Bill Wendlingint16x8_t test_vqrdmulhq_lane_s16_0(int16x8_t a, int16x4_t v) { 299951d85463d5debc70d034c257c60b245591495367Bill Wendling return vqrdmulhq_lane_s16(a, v, 0); 300051d85463d5debc70d034c257c60b245591495367Bill Wendling} 300151d85463d5debc70d034c257c60b245591495367Bill Wendling 30024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vqrdmulh_lane_s32_0(<2 x i32> %a, <2 x i32> %v) #0 { 30034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 30044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 30054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 30064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 30074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 30084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> [[VQRDMULH_V_I]], <2 x i32> [[VQRDMULH_V1_I]]) #2 30094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V3_I:%.*]] = bitcast <2 x i32> [[VQRDMULH_V2_I]] to <8 x i8> 30104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRDMULH_V3_I]] to <2 x i32> 30114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[TMP2]] 301251d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x2_t test_vqrdmulh_lane_s32_0(int32x2_t a, int32x2_t v) { 301351d85463d5debc70d034c257c60b245591495367Bill Wendling return vqrdmulh_lane_s32(a, v, 0); 301451d85463d5debc70d034c257c60b245591495367Bill Wendling} 301551d85463d5debc70d034c257c60b245591495367Bill Wendling 30164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqrdmulhq_lane_s32_0(<4 x i32> %a, <2 x i32> %v) #0 { 30174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> zeroinitializer 30184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 30194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8> 30204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 30214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 30224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> [[VQRDMULHQ_V_I]], <4 x i32> [[VQRDMULHQ_V1_I]]) #2 30234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V3_I:%.*]] = bitcast <4 x i32> [[VQRDMULHQ_V2_I]] to <16 x i8> 30244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V3_I]] to <4 x i32> 30254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 302651d85463d5debc70d034c257c60b245591495367Bill Wendlingint32x4_t test_vqrdmulhq_lane_s32_0(int32x4_t a, int32x2_t v) { 302751d85463d5debc70d034c257c60b245591495367Bill Wendling return vqrdmulhq_lane_s32(a, v, 0); 302851d85463d5debc70d034c257c60b245591495367Bill Wendling} 302951d85463d5debc70d034c257c60b245591495367Bill Wendling 30304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vmul_lane_f32_0(<2 x float> %a, <2 x float> %v) #0 { 30314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x float> %v, <2 x float> %v, <2 x i32> zeroinitializer 30324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = fmul <2 x float> %a, [[SHUFFLE]] 30334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[MUL]] 303451d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x2_t test_vmul_lane_f32_0(float32x2_t a, float32x2_t v) { 303551d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_lane_f32(a, v, 0); 303651d85463d5debc70d034c257c60b245591495367Bill Wendling} 303751d85463d5debc70d034c257c60b245591495367Bill Wendling 30384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vmulq_lane_f32_0(<4 x float> %a, <2 x float> %v) #0 { 30394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x float> %v, <2 x float> %v, <4 x i32> zeroinitializer 30404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = fmul <4 x float> %a, [[SHUFFLE]] 30414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[MUL]] 304251d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x4_t test_vmulq_lane_f32_0(float32x4_t a, float32x2_t v) { 304351d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_lane_f32(a, v, 0); 304451d85463d5debc70d034c257c60b245591495367Bill Wendling} 304551d85463d5debc70d034c257c60b245591495367Bill Wendling 30464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vmul_laneq_f32_0(<2 x float> %a, <4 x float> %v) #0 { 30474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x float> %v, <4 x float> %v, <2 x i32> zeroinitializer 30484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = fmul <2 x float> %a, [[SHUFFLE]] 30494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[MUL]] 305051d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x2_t test_vmul_laneq_f32_0(float32x2_t a, float32x4_t v) { 305151d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_laneq_f32(a, v, 0); 305251d85463d5debc70d034c257c60b245591495367Bill Wendling} 305351d85463d5debc70d034c257c60b245591495367Bill Wendling 30544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <1 x double> @test_vmul_laneq_f64_0(<1 x double> %a, <2 x double> %v) #0 { 30554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8> 30564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x double> %v to <16 x i8> 30574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to double 30584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> 30594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[EXTRACT:%.*]] = extractelement <2 x double> [[TMP3]], i32 0 30604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = fmul double [[TMP2]], [[EXTRACT]] 30614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast double [[TMP4]] to <1 x double> 30624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <1 x double> [[TMP5]] 306351d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat64x1_t test_vmul_laneq_f64_0(float64x1_t a, float64x2_t v) { 306451d85463d5debc70d034c257c60b245591495367Bill Wendling return vmul_laneq_f64(a, v, 0); 306551d85463d5debc70d034c257c60b245591495367Bill Wendling} 306651d85463d5debc70d034c257c60b245591495367Bill Wendling 30674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vmulq_laneq_f32_0(<4 x float> %a, <4 x float> %v) #0 { 30684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x float> %v, <4 x float> %v, <4 x i32> zeroinitializer 30694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = fmul <4 x float> %a, [[SHUFFLE]] 30704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[MUL]] 307151d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x4_t test_vmulq_laneq_f32_0(float32x4_t a, float32x4_t v) { 307251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_laneq_f32(a, v, 0); 307351d85463d5debc70d034c257c60b245591495367Bill Wendling} 307451d85463d5debc70d034c257c60b245591495367Bill Wendling 30754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vmulq_laneq_f64_0(<2 x double> %a, <2 x double> %v) #0 { 30764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x double> %v, <2 x double> %v, <2 x i32> zeroinitializer 30774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = fmul <2 x double> %a, [[SHUFFLE]] 30784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[MUL]] 307951d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat64x2_t test_vmulq_laneq_f64_0(float64x2_t a, float64x2_t v) { 308051d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulq_laneq_f64(a, v, 0); 308151d85463d5debc70d034c257c60b245591495367Bill Wendling} 308251d85463d5debc70d034c257c60b245591495367Bill Wendling 30834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vmulx_lane_f32_0(<2 x float> %a, <2 x float> %v) #0 { 30844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x float> %v, <2 x float> %v, <2 x i32> zeroinitializer 30854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 30864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x float> [[SHUFFLE]] to <8 x i8> 30874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 30884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> 30894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX2_I:%.*]] = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> [[VMULX_I]], <2 x float> [[VMULX1_I]]) #2 30904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[VMULX2_I]] 309151d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x2_t test_vmulx_lane_f32_0(float32x2_t a, float32x2_t v) { 309251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulx_lane_f32(a, v, 0); 309351d85463d5debc70d034c257c60b245591495367Bill Wendling} 309451d85463d5debc70d034c257c60b245591495367Bill Wendling 30954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vmulxq_lane_f32_0(<4 x float> %a, <2 x float> %v) #0 { 30964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x float> %v, <2 x float> %v, <4 x i32> zeroinitializer 30974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 30984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x float> [[SHUFFLE]] to <16 x i8> 30994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 31004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 31014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX2_I:%.*]] = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> [[VMULX_I]], <4 x float> [[VMULX1_I]]) #2 31024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[VMULX2_I]] 310351d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x4_t test_vmulxq_lane_f32_0(float32x4_t a, float32x2_t v) { 310451d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulxq_lane_f32(a, v, 0); 310551d85463d5debc70d034c257c60b245591495367Bill Wendling} 310651d85463d5debc70d034c257c60b245591495367Bill Wendling 31074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vmulxq_lane_f64_0(<2 x double> %a, <1 x double> %v) #0 { 31084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <1 x double> %v, <1 x double> %v, <2 x i32> zeroinitializer 31094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8> 31104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x double> [[SHUFFLE]] to <16 x i8> 31114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double> 31124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> 31134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX2_I:%.*]] = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> [[VMULX_I]], <2 x double> [[VMULX1_I]]) #2 31144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[VMULX2_I]] 311551d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat64x2_t test_vmulxq_lane_f64_0(float64x2_t a, float64x1_t v) { 311651d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulxq_lane_f64(a, v, 0); 311751d85463d5debc70d034c257c60b245591495367Bill Wendling} 311851d85463d5debc70d034c257c60b245591495367Bill Wendling 31194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vmulx_laneq_f32_0(<2 x float> %a, <4 x float> %v) #0 { 31204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x float> %v, <4 x float> %v, <2 x i32> zeroinitializer 31214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 31224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x float> [[SHUFFLE]] to <8 x i8> 31234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 31244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> 31254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX2_I:%.*]] = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> [[VMULX_I]], <2 x float> [[VMULX1_I]]) #2 31264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[VMULX2_I]] 312751d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x2_t test_vmulx_laneq_f32_0(float32x2_t a, float32x4_t v) { 312851d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulx_laneq_f32(a, v, 0); 312951d85463d5debc70d034c257c60b245591495367Bill Wendling} 313051d85463d5debc70d034c257c60b245591495367Bill Wendling 31314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vmulxq_laneq_f32_0(<4 x float> %a, <4 x float> %v) #0 { 31324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x float> %v, <4 x float> %v, <4 x i32> zeroinitializer 31334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 31344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x float> [[SHUFFLE]] to <16 x i8> 31354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 31364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 31374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX2_I:%.*]] = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> [[VMULX_I]], <4 x float> [[VMULX1_I]]) #2 31384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[VMULX2_I]] 313951d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat32x4_t test_vmulxq_laneq_f32_0(float32x4_t a, float32x4_t v) { 314051d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulxq_laneq_f32(a, v, 0); 314151d85463d5debc70d034c257c60b245591495367Bill Wendling} 314251d85463d5debc70d034c257c60b245591495367Bill Wendling 31434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vmulxq_laneq_f64_0(<2 x double> %a, <2 x double> %v) #0 { 31444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x double> %v, <2 x double> %v, <2 x i32> zeroinitializer 31454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8> 31464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x double> [[SHUFFLE]] to <16 x i8> 31474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double> 31484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> 31494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULX2_I:%.*]] = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> [[VMULX_I]], <2 x double> [[VMULX1_I]]) #2 31504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[VMULX2_I]] 315151d85463d5debc70d034c257c60b245591495367Bill Wendlingfloat64x2_t test_vmulxq_laneq_f64_0(float64x2_t a, float64x2_t v) { 315251d85463d5debc70d034c257c60b245591495367Bill Wendling return vmulxq_laneq_f64(a, v, 0); 315351d85463d5debc70d034c257c60b245591495367Bill Wendling} 315451d85463d5debc70d034c257c60b245591495367Bill Wendling 31554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_high_n_s16(<8 x i16> %a, i16 %b) #0 { 31564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 31574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> 31584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <4 x i16> undef, i16 %b, i32 0 31594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <4 x i16> [[VECINIT_I_I]], i16 %b, i32 1 31604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I_I]], i16 %b, i32 2 31614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I_I]], i16 %b, i32 3 31624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I_I]] to <8 x i8> 31634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 31644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL4_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 31654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL5_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL4_I_I]]) #2 31664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL5_I_I]] 316726476230652928491dd8b3eead189f928b48363cBill Wendlingint32x4_t test_vmull_high_n_s16(int16x8_t a, int16_t b) { 316826476230652928491dd8b3eead189f928b48363cBill Wendling return vmull_high_n_s16(a, b); 316926476230652928491dd8b3eead189f928b48363cBill Wendling} 317026476230652928491dd8b3eead189f928b48363cBill Wendling 31714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_high_n_s32(<4 x i32> %a, i32 %b) #0 { 31724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 31734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> 31744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <2 x i32> undef, i32 %b, i32 0 31754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <2 x i32> [[VECINIT_I_I]], i32 %b, i32 1 31764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I_I]] to <8 x i8> 31774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 31784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 31794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL3_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL2_I_I]]) #2 31804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL3_I_I]] 318126476230652928491dd8b3eead189f928b48363cBill Wendlingint64x2_t test_vmull_high_n_s32(int32x4_t a, int32_t b) { 318226476230652928491dd8b3eead189f928b48363cBill Wendling return vmull_high_n_s32(a, b); 318326476230652928491dd8b3eead189f928b48363cBill Wendling} 318426476230652928491dd8b3eead189f928b48363cBill Wendling 31854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_high_n_u16(<8 x i16> %a, i16 %b) #0 { 31864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 31874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> 31884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <4 x i16> undef, i16 %b, i32 0 31894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <4 x i16> [[VECINIT_I_I]], i16 %b, i32 1 31904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I_I]], i16 %b, i32 2 31914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I_I]], i16 %b, i32 3 31924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I_I]] to <8 x i8> 31934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 31944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL4_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 31954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL5_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL4_I_I]]) #2 31964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL5_I_I]] 319726476230652928491dd8b3eead189f928b48363cBill Wendlinguint32x4_t test_vmull_high_n_u16(uint16x8_t a, uint16_t b) { 319826476230652928491dd8b3eead189f928b48363cBill Wendling return vmull_high_n_u16(a, b); 319926476230652928491dd8b3eead189f928b48363cBill Wendling} 320026476230652928491dd8b3eead189f928b48363cBill Wendling 32014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_high_n_u32(<4 x i32> %a, i32 %b) #0 { 32024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 32034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> 32044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <2 x i32> undef, i32 %b, i32 0 32054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <2 x i32> [[VECINIT_I_I]], i32 %b, i32 1 32064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I_I]] to <8 x i8> 32074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 32084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 32094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL3_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL2_I_I]]) #2 32104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL3_I_I]] 321126476230652928491dd8b3eead189f928b48363cBill Wendlinguint64x2_t test_vmull_high_n_u32(uint32x4_t a, uint32_t b) { 321226476230652928491dd8b3eead189f928b48363cBill Wendling return vmull_high_n_u32(a, b); 321326476230652928491dd8b3eead189f928b48363cBill Wendling} 321426476230652928491dd8b3eead189f928b48363cBill Wendling 32154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmull_high_n_s16(<8 x i16> %a, i16 %b) #0 { 32164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 32174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> 32184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <4 x i16> undef, i16 %b, i32 0 32194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <4 x i16> [[VECINIT_I_I]], i16 %b, i32 1 32204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I_I]], i16 %b, i32 2 32214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I_I]], i16 %b, i32 3 32224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I_I]] to <8 x i8> 32234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 32244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V4_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 32254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V5_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMULL_V_I_I]], <4 x i16> [[VQDMULL_V4_I_I]]) #2 32264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V6_I_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V5_I_I]] to <16 x i8> 32274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V6_I_I]] to <4 x i32> 32284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 322926476230652928491dd8b3eead189f928b48363cBill Wendlingint32x4_t test_vqdmull_high_n_s16(int16x8_t a, int16_t b) { 323026476230652928491dd8b3eead189f928b48363cBill Wendling return vqdmull_high_n_s16(a, b); 323126476230652928491dd8b3eead189f928b48363cBill Wendling} 323226476230652928491dd8b3eead189f928b48363cBill Wendling 32334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmull_high_n_s32(<4 x i32> %a, i32 %b) #0 { 32344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 32354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> 32364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <2 x i32> undef, i32 %b, i32 0 32374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <2 x i32> [[VECINIT_I_I]], i32 %b, i32 1 32384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I_I]] to <8 x i8> 32394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 32404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 32414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMULL_V_I_I]], <2 x i32> [[VQDMULL_V2_I_I]]) #2 32424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V4_I_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V3_I_I]] to <16 x i8> 32434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V4_I_I]] to <2 x i64> 32444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[TMP2]] 324526476230652928491dd8b3eead189f928b48363cBill Wendlingint64x2_t test_vqdmull_high_n_s32(int32x4_t a, int32_t b) { 324626476230652928491dd8b3eead189f928b48363cBill Wendling return vqdmull_high_n_s32(a, b); 324726476230652928491dd8b3eead189f928b48363cBill Wendling} 324826476230652928491dd8b3eead189f928b48363cBill Wendling 32494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 { 32504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 32514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 32524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <4 x i16> [[VECINIT_I_I]], i16 %c, i32 1 32534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I_I]], i16 %c, i32 2 32544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I_I]], i16 %c, i32 3 32554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> 32564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I_I]] to <8 x i8> 32574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 32584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 32594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I_I_I]], <4 x i16> [[VMULL1_I_I_I]]) #2 32604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I_I:%.*]] = add <4 x i32> %a, [[VMULL2_I_I_I]] 32614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD_I_I]] 326226476230652928491dd8b3eead189f928b48363cBill Wendlingint32x4_t test_vmlal_high_n_s16(int32x4_t a, int16x8_t b, int16_t c) { 326326476230652928491dd8b3eead189f928b48363cBill Wendling return vmlal_high_n_s16(a, b, c); 326426476230652928491dd8b3eead189f928b48363cBill Wendling} 326526476230652928491dd8b3eead189f928b48363cBill Wendling 32664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 { 32674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 32684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 32694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <2 x i32> [[VECINIT_I_I]], i32 %c, i32 1 32704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> 32714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I_I]] to <8 x i8> 32724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 32734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 32744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I_I_I]], <2 x i32> [[VMULL1_I_I_I]]) #2 32754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I_I:%.*]] = add <2 x i64> %a, [[VMULL2_I_I_I]] 32764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD_I_I]] 327726476230652928491dd8b3eead189f928b48363cBill Wendlingint64x2_t test_vmlal_high_n_s32(int64x2_t a, int32x4_t b, int32_t c) { 327826476230652928491dd8b3eead189f928b48363cBill Wendling return vmlal_high_n_s32(a, b, c); 327926476230652928491dd8b3eead189f928b48363cBill Wendling} 328026476230652928491dd8b3eead189f928b48363cBill Wendling 32814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_high_n_u16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 { 32824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 32834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 32844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <4 x i16> [[VECINIT_I_I]], i16 %c, i32 1 32854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I_I]], i16 %c, i32 2 32864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I_I]], i16 %c, i32 3 32874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> 32884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I_I]] to <8 x i8> 32894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 32904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 32914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I_I_I]], <4 x i16> [[VMULL1_I_I_I]]) #2 32924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I_I:%.*]] = add <4 x i32> %a, [[VMULL2_I_I_I]] 32934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD_I_I]] 329426476230652928491dd8b3eead189f928b48363cBill Wendlinguint32x4_t test_vmlal_high_n_u16(uint32x4_t a, uint16x8_t b, uint16_t c) { 329526476230652928491dd8b3eead189f928b48363cBill Wendling return vmlal_high_n_u16(a, b, c); 329626476230652928491dd8b3eead189f928b48363cBill Wendling} 329726476230652928491dd8b3eead189f928b48363cBill Wendling 32984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_high_n_u32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 { 32994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 33004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 33014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <2 x i32> [[VECINIT_I_I]], i32 %c, i32 1 33024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> 33034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I_I]] to <8 x i8> 33044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 33054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 33064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I_I_I]], <2 x i32> [[VMULL1_I_I_I]]) #2 33074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I_I:%.*]] = add <2 x i64> %a, [[VMULL2_I_I_I]] 33084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD_I_I]] 330926476230652928491dd8b3eead189f928b48363cBill Wendlinguint64x2_t test_vmlal_high_n_u32(uint64x2_t a, uint32x4_t b, uint32_t c) { 331026476230652928491dd8b3eead189f928b48363cBill Wendling return vmlal_high_n_u32(a, b, c); 331126476230652928491dd8b3eead189f928b48363cBill Wendling} 331226476230652928491dd8b3eead189f928b48363cBill Wendling 33134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlal_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 { 33144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 33154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 33164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> 33174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 33184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <4 x i16> [[VECINIT_I_I]], i16 %c, i32 1 33194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I_I]], i16 %c, i32 2 33204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I_I]], i16 %c, i32 3 33214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[VECINIT3_I_I]] to <8 x i8> 33224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 33234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL4_I_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 33244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL5_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I_I]], <4 x i16> [[VQDMLAL4_I_I]]) #2 33254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 33264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V6_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[VQDMLAL_V_I_I]], <4 x i32> [[VQDMLAL5_I_I]]) #2 33274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLAL_V6_I_I]] 332826476230652928491dd8b3eead189f928b48363cBill Wendlingint32x4_t test_vqdmlal_high_n_s16(int32x4_t a, int16x8_t b, int16_t c) { 332926476230652928491dd8b3eead189f928b48363cBill Wendling return vqdmlal_high_n_s16(a, b, c); 333026476230652928491dd8b3eead189f928b48363cBill Wendling} 333126476230652928491dd8b3eead189f928b48363cBill Wendling 33324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlal_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 { 33334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 33344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 33354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> 33364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 33374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <2 x i32> [[VECINIT_I_I]], i32 %c, i32 1 33384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[VECINIT1_I_I]] to <8 x i8> 33394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 33404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 33414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL3_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I_I]], <2 x i32> [[VQDMLAL2_I_I]]) #2 33424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 33434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V4_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[VQDMLAL_V_I_I]], <2 x i64> [[VQDMLAL3_I_I]]) #2 33444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLAL_V4_I_I]] 334526476230652928491dd8b3eead189f928b48363cBill Wendlingint64x2_t test_vqdmlal_high_n_s32(int64x2_t a, int32x4_t b, int32_t c) { 334626476230652928491dd8b3eead189f928b48363cBill Wendling return vqdmlal_high_n_s32(a, b, c); 334726476230652928491dd8b3eead189f928b48363cBill Wendling} 334826476230652928491dd8b3eead189f928b48363cBill Wendling 33494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 { 33504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 33514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 33524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <4 x i16> [[VECINIT_I_I]], i16 %c, i32 1 33534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I_I]], i16 %c, i32 2 33544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I_I]], i16 %c, i32 3 33554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> 33564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I_I]] to <8 x i8> 33574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 33584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 33594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I_I_I]], <4 x i16> [[VMULL1_I_I_I]]) #2 33604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I_I:%.*]] = sub <4 x i32> %a, [[VMULL2_I_I_I]] 33614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB_I_I]] 336226476230652928491dd8b3eead189f928b48363cBill Wendlingint32x4_t test_vmlsl_high_n_s16(int32x4_t a, int16x8_t b, int16_t c) { 336326476230652928491dd8b3eead189f928b48363cBill Wendling return vmlsl_high_n_s16(a, b, c); 336426476230652928491dd8b3eead189f928b48363cBill Wendling} 336526476230652928491dd8b3eead189f928b48363cBill Wendling 33664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 { 33674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 33684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 33694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <2 x i32> [[VECINIT_I_I]], i32 %c, i32 1 33704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> 33714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I_I]] to <8 x i8> 33724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 33734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 33744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I_I_I]], <2 x i32> [[VMULL1_I_I_I]]) #2 33754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I_I:%.*]] = sub <2 x i64> %a, [[VMULL2_I_I_I]] 33764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB_I_I]] 337726476230652928491dd8b3eead189f928b48363cBill Wendlingint64x2_t test_vmlsl_high_n_s32(int64x2_t a, int32x4_t b, int32_t c) { 337826476230652928491dd8b3eead189f928b48363cBill Wendling return vmlsl_high_n_s32(a, b, c); 337926476230652928491dd8b3eead189f928b48363cBill Wendling} 338026476230652928491dd8b3eead189f928b48363cBill Wendling 33814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_high_n_u16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 { 33824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 33834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 33844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <4 x i16> [[VECINIT_I_I]], i16 %c, i32 1 33854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I_I]], i16 %c, i32 2 33864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I_I]], i16 %c, i32 3 33874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> 33884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I_I]] to <8 x i8> 33894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 33904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 33914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I_I_I]], <4 x i16> [[VMULL1_I_I_I]]) #2 33924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I_I:%.*]] = sub <4 x i32> %a, [[VMULL2_I_I_I]] 33934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB_I_I]] 339426476230652928491dd8b3eead189f928b48363cBill Wendlinguint32x4_t test_vmlsl_high_n_u16(uint32x4_t a, uint16x8_t b, uint16_t c) { 339526476230652928491dd8b3eead189f928b48363cBill Wendling return vmlsl_high_n_u16(a, b, c); 339626476230652928491dd8b3eead189f928b48363cBill Wendling} 339726476230652928491dd8b3eead189f928b48363cBill Wendling 33984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_high_n_u32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 { 33994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 34004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 34014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <2 x i32> [[VECINIT_I_I]], i32 %c, i32 1 34024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> 34034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I_I]] to <8 x i8> 34044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 34054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 34064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I_I_I]], <2 x i32> [[VMULL1_I_I_I]]) #2 34074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I_I:%.*]] = sub <2 x i64> %a, [[VMULL2_I_I_I]] 34084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB_I_I]] 340926476230652928491dd8b3eead189f928b48363cBill Wendlinguint64x2_t test_vmlsl_high_n_u32(uint64x2_t a, uint32x4_t b, uint32_t c) { 341026476230652928491dd8b3eead189f928b48363cBill Wendling return vmlsl_high_n_u32(a, b, c); 341126476230652928491dd8b3eead189f928b48363cBill Wendling} 341226476230652928491dd8b3eead189f928b48363cBill Wendling 34134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlsl_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 { 34144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 34154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 34164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> 34174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 34184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <4 x i16> [[VECINIT_I_I]], i16 %c, i32 1 34194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I_I]], i16 %c, i32 2 34204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I_I]], i16 %c, i32 3 34214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[VECINIT3_I_I]] to <8 x i8> 34224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 34234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL4_I_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 34244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL5_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I_I]], <4 x i16> [[VQDMLAL4_I_I]]) #2 34254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 34264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V6_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[VQDMLSL_V_I_I]], <4 x i32> [[VQDMLAL5_I_I]]) #2 34274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLSL_V6_I_I]] 342826476230652928491dd8b3eead189f928b48363cBill Wendlingint32x4_t test_vqdmlsl_high_n_s16(int32x4_t a, int16x8_t b, int16_t c) { 342926476230652928491dd8b3eead189f928b48363cBill Wendling return vqdmlsl_high_n_s16(a, b, c); 343026476230652928491dd8b3eead189f928b48363cBill Wendling} 343126476230652928491dd8b3eead189f928b48363cBill Wendling 34324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlsl_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 { 34334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 34344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 34354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> 34364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 34374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I_I:%.*]] = insertelement <2 x i32> [[VECINIT_I_I]], i32 %c, i32 1 34384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[VECINIT1_I_I]] to <8 x i8> 34394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 34404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 34414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL3_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I_I]], <2 x i32> [[VQDMLAL2_I_I]]) #2 34424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 34434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V4_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[VQDMLSL_V_I_I]], <2 x i64> [[VQDMLAL3_I_I]]) #2 34444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLSL_V4_I_I]] 344526476230652928491dd8b3eead189f928b48363cBill Wendlingint64x2_t test_vqdmlsl_high_n_s32(int64x2_t a, int32x4_t b, int32_t c) { 344626476230652928491dd8b3eead189f928b48363cBill Wendling return vqdmlsl_high_n_s32(a, b, c); 344726476230652928491dd8b3eead189f928b48363cBill Wendling} 344826476230652928491dd8b3eead189f928b48363cBill Wendling 34494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vmul_n_f32(<2 x float> %a, float %b) #0 { 34504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %b, i32 0 34514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %b, i32 1 34524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = fmul <2 x float> %a, [[VECINIT1_I]] 34534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[MUL_I]] 345426476230652928491dd8b3eead189f928b48363cBill Wendlingfloat32x2_t test_vmul_n_f32(float32x2_t a, float32_t b) { 345526476230652928491dd8b3eead189f928b48363cBill Wendling return vmul_n_f32(a, b); 345626476230652928491dd8b3eead189f928b48363cBill Wendling} 345726476230652928491dd8b3eead189f928b48363cBill Wendling 34584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vmulq_n_f32(<4 x float> %a, float %b) #0 { 34594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %b, i32 0 34604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %b, i32 1 34614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %b, i32 2 34624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float %b, i32 3 34634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = fmul <4 x float> %a, [[VECINIT3_I]] 34644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[MUL_I]] 346526476230652928491dd8b3eead189f928b48363cBill Wendlingfloat32x4_t test_vmulq_n_f32(float32x4_t a, float32_t b) { 346626476230652928491dd8b3eead189f928b48363cBill Wendling return vmulq_n_f32(a, b); 346726476230652928491dd8b3eead189f928b48363cBill Wendling} 346826476230652928491dd8b3eead189f928b48363cBill Wendling 34694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vmulq_n_f64(<2 x double> %a, double %b) #0 { 34704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %b, i32 0 34714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %b, i32 1 34724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = fmul <2 x double> %a, [[VECINIT1_I]] 34734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[MUL_I]] 347426476230652928491dd8b3eead189f928b48363cBill Wendlingfloat64x2_t test_vmulq_n_f64(float64x2_t a, float64_t b) { 347526476230652928491dd8b3eead189f928b48363cBill Wendling return vmulq_n_f64(a, b); 347626476230652928491dd8b3eead189f928b48363cBill Wendling} 347726476230652928491dd8b3eead189f928b48363cBill Wendling 34784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vfma_n_f32(<2 x float> %a, <2 x float> %b, float %n) #0 { 34794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %n, i32 0 34804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %n, i32 1 34814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 34824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8> 34834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x float> [[VECINIT1_I]] to <8 x i8> 34844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 34854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> 34864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float> 34874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[TMP4]], <2 x float> [[TMP5]], <2 x float> [[TMP3]]) #2 34884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[TMP6]] 348926476230652928491dd8b3eead189f928b48363cBill Wendlingfloat32x2_t test_vfma_n_f32(float32x2_t a, float32x2_t b, float32_t n) { 349026476230652928491dd8b3eead189f928b48363cBill Wendling return vfma_n_f32(a, b, n); 349126476230652928491dd8b3eead189f928b48363cBill Wendling} 349226476230652928491dd8b3eead189f928b48363cBill Wendling 34934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vfmaq_n_f32(<4 x float> %a, <4 x float> %b, float %n) #0 { 34944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0 34954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %n, i32 1 34964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %n, i32 2 34974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float %n, i32 3 34984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 34994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8> 35004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x float> [[VECINIT3_I]] to <16 x i8> 35014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 35024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 35034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float> 35044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP4]], <4 x float> [[TMP5]], <4 x float> [[TMP3]]) #2 35054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[TMP6]] 350626476230652928491dd8b3eead189f928b48363cBill Wendlingfloat32x4_t test_vfmaq_n_f32(float32x4_t a, float32x4_t b, float32_t n) { 350726476230652928491dd8b3eead189f928b48363cBill Wendling return vfmaq_n_f32(a, b, n); 350826476230652928491dd8b3eead189f928b48363cBill Wendling} 350926476230652928491dd8b3eead189f928b48363cBill Wendling 35104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vfms_n_f32(<2 x float> %a, <2 x float> %b, float %n) #0 { 35114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I:%.*]] = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %b 35124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %n, i32 0 35134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %n, i32 1 35144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 35154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x float> [[SUB_I]] to <8 x i8> 35164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x float> [[VECINIT1_I]] to <8 x i8> 35174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 35184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> 35194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float> 35204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[TMP4]], <2 x float> [[TMP5]], <2 x float> [[TMP3]]) #2 35214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[TMP6]] 352226476230652928491dd8b3eead189f928b48363cBill Wendlingfloat32x2_t test_vfms_n_f32(float32x2_t a, float32x2_t b, float32_t n) { 352326476230652928491dd8b3eead189f928b48363cBill Wendling return vfms_n_f32(a, b, n); 352426476230652928491dd8b3eead189f928b48363cBill Wendling} 352526476230652928491dd8b3eead189f928b48363cBill Wendling 35264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vfmsq_n_f32(<4 x float> %a, <4 x float> %b, float %n) #0 { 35274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I:%.*]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %b 35284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0 35294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %n, i32 1 35304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %n, i32 2 35314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float %n, i32 3 35324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 35334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x float> [[SUB_I]] to <16 x i8> 35344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x float> [[VECINIT3_I]] to <16 x i8> 35354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 35364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 35374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float> 35384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP4]], <4 x float> [[TMP5]], <4 x float> [[TMP3]]) #2 35394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[TMP6]] 354026476230652928491dd8b3eead189f928b48363cBill Wendlingfloat32x4_t test_vfmsq_n_f32(float32x4_t a, float32x4_t b, float32_t n) { 354126476230652928491dd8b3eead189f928b48363cBill Wendling return vfmsq_n_f32(a, b, n); 354226476230652928491dd8b3eead189f928b48363cBill Wendling} 3543651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 35444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmul_n_s16(<4 x i16> %a, i16 %b) #0 { 35454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %b, i32 0 35464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %b, i32 1 35474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %b, i32 2 35484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %b, i32 3 35494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <4 x i16> %a, [[VECINIT3_I]] 35504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[MUL_I]] 3551651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x4_t test_vmul_n_s16(int16x4_t a, int16_t b) { 3552651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmul_n_s16(a, b); 3553651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3554651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 35554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmulq_n_s16(<8 x i16> %a, i16 %b) #0 { 35564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <8 x i16> undef, i16 %b, i32 0 35574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 %b, i32 1 35584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 %b, i32 2 35594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 %b, i32 3 35604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 %b, i32 4 35614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 %b, i32 5 35624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 %b, i32 6 35634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 %b, i32 7 35644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <8 x i16> %a, [[VECINIT7_I]] 35654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[MUL_I]] 3566651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x8_t test_vmulq_n_s16(int16x8_t a, int16_t b) { 3567651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmulq_n_s16(a, b); 3568651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3569651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 35704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmul_n_s32(<2 x i32> %a, i32 %b) #0 { 35714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %b, i32 0 35724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %b, i32 1 35734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <2 x i32> %a, [[VECINIT1_I]] 35744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[MUL_I]] 3575651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x2_t test_vmul_n_s32(int32x2_t a, int32_t b) { 3576651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmul_n_s32(a, b); 3577651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3578651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 35794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmulq_n_s32(<4 x i32> %a, i32 %b) #0 { 35804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i32> undef, i32 %b, i32 0 35814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 %b, i32 1 35824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 %b, i32 2 35834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 %b, i32 3 35844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <4 x i32> %a, [[VECINIT3_I]] 35854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[MUL_I]] 3586651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vmulq_n_s32(int32x4_t a, int32_t b) { 3587651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmulq_n_s32(a, b); 3588651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3589651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 35904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmul_n_u16(<4 x i16> %a, i16 %b) #0 { 35914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %b, i32 0 35924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %b, i32 1 35934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %b, i32 2 35944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %b, i32 3 35954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <4 x i16> %a, [[VECINIT3_I]] 35964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[MUL_I]] 3597651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x4_t test_vmul_n_u16(uint16x4_t a, uint16_t b) { 3598651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmul_n_u16(a, b); 3599651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3600651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 36014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmulq_n_u16(<8 x i16> %a, i16 %b) #0 { 36024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <8 x i16> undef, i16 %b, i32 0 36034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 %b, i32 1 36044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 %b, i32 2 36054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 %b, i32 3 36064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 %b, i32 4 36074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 %b, i32 5 36084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 %b, i32 6 36094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 %b, i32 7 36104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <8 x i16> %a, [[VECINIT7_I]] 36114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[MUL_I]] 3612651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x8_t test_vmulq_n_u16(uint16x8_t a, uint16_t b) { 3613651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmulq_n_u16(a, b); 3614651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3615651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 36164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmul_n_u32(<2 x i32> %a, i32 %b) #0 { 36174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %b, i32 0 36184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %b, i32 1 36194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <2 x i32> %a, [[VECINIT1_I]] 36204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[MUL_I]] 3621651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x2_t test_vmul_n_u32(uint32x2_t a, uint32_t b) { 3622651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmul_n_u32(a, b); 3623651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3624651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 36254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmulq_n_u32(<4 x i32> %a, i32 %b) #0 { 36264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i32> undef, i32 %b, i32 0 36274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 %b, i32 1 36284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 %b, i32 2 36294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 %b, i32 3 36304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <4 x i32> %a, [[VECINIT3_I]] 36314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[MUL_I]] 3632651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x4_t test_vmulq_n_u32(uint32x4_t a, uint32_t b) { 3633651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmulq_n_u32(a, b); 3634651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3635651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 36364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_n_s16(<4 x i16> %a, i16 %b) #0 { 36374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 36384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %b, i32 0 36394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %b, i32 1 36404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %b, i32 2 36414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %b, i32 3 36424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8> 36434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 36444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL4_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 36454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL5_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL4_I]]) #2 36464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL5_I]] 3647651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vmull_n_s16(int16x4_t a, int16_t b) { 3648651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmull_n_s16(a, b); 3649651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3650651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 36514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_n_s32(<2 x i32> %a, i32 %b) #0 { 36524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 36534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %b, i32 0 36544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %b, i32 1 36554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8> 36564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 36574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 36584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL2_I]]) #2 36594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL3_I]] 3660651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint64x2_t test_vmull_n_s32(int32x2_t a, int32_t b) { 3661651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmull_n_s32(a, b); 3662651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3663651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 36644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmull_n_u16(<4 x i16> %a, i16 %b) #0 { 36654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 36664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %b, i32 0 36674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %b, i32 1 36684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %b, i32 2 36694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %b, i32 3 36704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8> 36714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 36724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL4_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 36734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL5_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL4_I]]) #2 36744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VMULL5_I]] 3675651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x4_t test_vmull_n_u16(uint16x4_t a, uint16_t b) { 3676651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmull_n_u16(a, b); 3677651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3678651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 36794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmull_n_u32(<2 x i32> %a, i32 %b) #0 { 36804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 36814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %b, i32 0 36824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %b, i32 1 36834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8> 36844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 36854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 36864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL2_I]]) #2 36874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VMULL3_I]] 3688651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint64x2_t test_vmull_n_u32(uint32x2_t a, uint32_t b) { 3689651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmull_n_u32(a, b); 3690651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3691651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 36924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmull_n_s16(<4 x i16> %a, i16 %b) #0 { 36934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 36944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %b, i32 0 36954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %b, i32 1 36964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %b, i32 2 36974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %b, i32 3 36984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8> 36994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 37004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V4_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 37014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V5_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMULL_V_I]], <4 x i16> [[VQDMULL_V4_I]]) #2 37024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V6_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V5_I]] to <16 x i8> 37034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V6_I]] to <4 x i32> 37044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 3705651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqdmull_n_s16(int16x4_t a, int16_t b) { 3706651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmull_n_s16(a, b); 3707651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3708651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 37094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmull_n_s32(<2 x i32> %a, i32 %b) #0 { 37104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 37114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %b, i32 0 37124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %b, i32 1 37134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8> 37144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 37154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V2_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 37164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMULL_V_I]], <2 x i32> [[VQDMULL_V2_I]]) #2 37174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULL_V4_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V3_I]] to <16 x i8> 37184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V4_I]] to <2 x i64> 37194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[TMP2]] 3720651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint64x2_t test_vqdmull_n_s32(int32x2_t a, int32_t b) { 3721651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmull_n_s32(a, b); 3722651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3723651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 37244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vqdmulh_n_s16(<4 x i16> %a, i16 %b) #0 { 37254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 37264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %b, i32 0 37274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %b, i32 1 37284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %b, i32 2 37294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %b, i32 3 37304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8> 37314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 37324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V4_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 37334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V5_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> [[VQDMULH_V_I]], <4 x i16> [[VQDMULH_V4_I]]) #2 37344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V6_I:%.*]] = bitcast <4 x i16> [[VQDMULH_V5_I]] to <8 x i8> 37354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQDMULH_V6_I]] to <4 x i16> 37364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[TMP2]] 3737651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x4_t test_vqdmulh_n_s16(int16x4_t a, int16_t b) { 3738651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmulh_n_s16(a, b); 3739651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3740651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 37414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vqdmulhq_n_s16(<8 x i16> %a, i16 %b) #0 { 37424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> 37434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <8 x i16> undef, i16 %b, i32 0 37444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 %b, i32 1 37454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 %b, i32 2 37464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 %b, i32 3 37474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 %b, i32 4 37484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 %b, i32 5 37494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 %b, i32 6 37504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 %b, i32 7 37514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> [[VECINIT7_I]] to <16 x i8> 37524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 37534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V8_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> 37544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V9_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> [[VQDMULHQ_V_I]], <8 x i16> [[VQDMULHQ_V8_I]]) #2 37554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V10_I:%.*]] = bitcast <8 x i16> [[VQDMULHQ_V9_I]] to <16 x i8> 37564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V10_I]] to <8 x i16> 37574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[TMP2]] 3758651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x8_t test_vqdmulhq_n_s16(int16x8_t a, int16_t b) { 3759651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmulhq_n_s16(a, b); 3760651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3761651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 37624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vqdmulh_n_s32(<2 x i32> %a, i32 %b) #0 { 37634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 37644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %b, i32 0 37654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %b, i32 1 37664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8> 37674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 37684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V2_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 37694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V3_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> [[VQDMULH_V_I]], <2 x i32> [[VQDMULH_V2_I]]) #2 37704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V4_I:%.*]] = bitcast <2 x i32> [[VQDMULH_V3_I]] to <8 x i8> 37714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQDMULH_V4_I]] to <2 x i32> 37724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[TMP2]] 3773651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x2_t test_vqdmulh_n_s32(int32x2_t a, int32_t b) { 3774651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmulh_n_s32(a, b); 3775651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3776651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 37774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmulhq_n_s32(<4 x i32> %a, i32 %b) #0 { 37784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 37794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i32> undef, i32 %b, i32 0 37804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 %b, i32 1 37814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 %b, i32 2 37824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 %b, i32 3 37834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i32> [[VECINIT3_I]] to <16 x i8> 37844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 37854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V4_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 37864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V5_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> [[VQDMULHQ_V_I]], <4 x i32> [[VQDMULHQ_V4_I]]) #2 37874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V6_I:%.*]] = bitcast <4 x i32> [[VQDMULHQ_V5_I]] to <16 x i8> 37884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V6_I]] to <4 x i32> 37894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 3790651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqdmulhq_n_s32(int32x4_t a, int32_t b) { 3791651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmulhq_n_s32(a, b); 3792651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3793651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 37944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vqrdmulh_n_s16(<4 x i16> %a, i16 %b) #0 { 37954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 37964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %b, i32 0 37974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %b, i32 1 37984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %b, i32 2 37994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %b, i32 3 38004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8> 38014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 38024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V4_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 38034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V5_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> [[VQRDMULH_V_I]], <4 x i16> [[VQRDMULH_V4_I]]) #2 38044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V6_I:%.*]] = bitcast <4 x i16> [[VQRDMULH_V5_I]] to <8 x i8> 38054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRDMULH_V6_I]] to <4 x i16> 38064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[TMP2]] 3807651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x4_t test_vqrdmulh_n_s16(int16x4_t a, int16_t b) { 3808651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqrdmulh_n_s16(a, b); 3809651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3810651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 38114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vqrdmulhq_n_s16(<8 x i16> %a, i16 %b) #0 { 38124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> 38134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <8 x i16> undef, i16 %b, i32 0 38144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 %b, i32 1 38154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 %b, i32 2 38164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 %b, i32 3 38174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 %b, i32 4 38184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 %b, i32 5 38194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 %b, i32 6 38204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 %b, i32 7 38214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> [[VECINIT7_I]] to <16 x i8> 38224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 38234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V8_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> 38244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V9_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> [[VQRDMULHQ_V_I]], <8 x i16> [[VQRDMULHQ_V8_I]]) #2 38254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V10_I:%.*]] = bitcast <8 x i16> [[VQRDMULHQ_V9_I]] to <16 x i8> 38264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V10_I]] to <8 x i16> 38274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[TMP2]] 3828651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x8_t test_vqrdmulhq_n_s16(int16x8_t a, int16_t b) { 3829651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqrdmulhq_n_s16(a, b); 3830651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3831651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 38324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vqrdmulh_n_s32(<2 x i32> %a, i32 %b) #0 { 38334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 38344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %b, i32 0 38354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %b, i32 1 38364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8> 38374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 38384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V2_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 38394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V3_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> [[VQRDMULH_V_I]], <2 x i32> [[VQRDMULH_V2_I]]) #2 38404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V4_I:%.*]] = bitcast <2 x i32> [[VQRDMULH_V3_I]] to <8 x i8> 38414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRDMULH_V4_I]] to <2 x i32> 38424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[TMP2]] 3843651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x2_t test_vqrdmulh_n_s32(int32x2_t a, int32_t b) { 3844651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqrdmulh_n_s32(a, b); 3845651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3846651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 38474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqrdmulhq_n_s32(<4 x i32> %a, i32 %b) #0 { 38484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 38494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i32> undef, i32 %b, i32 0 38504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 %b, i32 1 38514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 %b, i32 2 38524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 %b, i32 3 38534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i32> [[VECINIT3_I]] to <16 x i8> 38544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 38554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V4_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 38564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V5_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> [[VQRDMULHQ_V_I]], <4 x i32> [[VQRDMULHQ_V4_I]]) #2 38574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V6_I:%.*]] = bitcast <4 x i32> [[VQRDMULHQ_V5_I]] to <16 x i8> 38584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V6_I]] to <4 x i32> 38594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 3860651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqrdmulhq_n_s32(int32x4_t a, int32_t b) { 3861651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqrdmulhq_n_s32(a, b); 3862651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3863651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 38644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmla_n_s16(<4 x i16> %a, <4 x i16> %b, i16 %c) #0 { 38654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 38664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %c, i32 1 38674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %c, i32 2 38684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %c, i32 3 38694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <4 x i16> %b, [[VECINIT3_I]] 38704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I:%.*]] = add <4 x i16> %a, [[MUL_I]] 38714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[ADD_I]] 3872651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x4_t test_vmla_n_s16(int16x4_t a, int16x4_t b, int16_t c) { 3873651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmla_n_s16(a, b, c); 3874651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3875651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 38764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlaq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 %c) #0 { 38774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <8 x i16> undef, i16 %c, i32 0 38784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 %c, i32 1 38794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 %c, i32 2 38804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 %c, i32 3 38814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 %c, i32 4 38824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 %c, i32 5 38834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 %c, i32 6 38844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 %c, i32 7 38854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <8 x i16> %b, [[VECINIT7_I]] 38864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I:%.*]] = add <8 x i16> %a, [[MUL_I]] 38874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[ADD_I]] 3888651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x8_t test_vmlaq_n_s16(int16x8_t a, int16x8_t b, int16_t c) { 3889651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlaq_n_s16(a, b, c); 3890651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3891651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 38924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmla_n_s32(<2 x i32> %a, <2 x i32> %b, i32 %c) #0 { 38934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 38944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %c, i32 1 38954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <2 x i32> %b, [[VECINIT1_I]] 38964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I:%.*]] = add <2 x i32> %a, [[MUL_I]] 38974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[ADD_I]] 3898651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x2_t test_vmla_n_s32(int32x2_t a, int32x2_t b, int32_t c) { 3899651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmla_n_s32(a, b, c); 3900651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3901651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 39024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlaq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) #0 { 39034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i32> undef, i32 %c, i32 0 39044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 %c, i32 1 39054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 %c, i32 2 39064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 %c, i32 3 39074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <4 x i32> %b, [[VECINIT3_I]] 39084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I:%.*]] = add <4 x i32> %a, [[MUL_I]] 39094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD_I]] 3910651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vmlaq_n_s32(int32x4_t a, int32x4_t b, int32_t c) { 3911651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlaq_n_s32(a, b, c); 3912651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3913651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 39144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmla_n_u16(<4 x i16> %a, <4 x i16> %b, i16 %c) #0 { 39154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 39164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %c, i32 1 39174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %c, i32 2 39184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %c, i32 3 39194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <4 x i16> %b, [[VECINIT3_I]] 39204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I:%.*]] = add <4 x i16> %a, [[MUL_I]] 39214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[ADD_I]] 3922651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x4_t test_vmla_n_u16(uint16x4_t a, uint16x4_t b, uint16_t c) { 3923651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmla_n_u16(a, b, c); 3924651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3925651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 39264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlaq_n_u16(<8 x i16> %a, <8 x i16> %b, i16 %c) #0 { 39274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <8 x i16> undef, i16 %c, i32 0 39284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 %c, i32 1 39294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 %c, i32 2 39304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 %c, i32 3 39314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 %c, i32 4 39324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 %c, i32 5 39334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 %c, i32 6 39344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 %c, i32 7 39354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <8 x i16> %b, [[VECINIT7_I]] 39364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I:%.*]] = add <8 x i16> %a, [[MUL_I]] 39374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[ADD_I]] 3938651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x8_t test_vmlaq_n_u16(uint16x8_t a, uint16x8_t b, uint16_t c) { 3939651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlaq_n_u16(a, b, c); 3940651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3941651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 39424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmla_n_u32(<2 x i32> %a, <2 x i32> %b, i32 %c) #0 { 39434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 39444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %c, i32 1 39454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <2 x i32> %b, [[VECINIT1_I]] 39464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I:%.*]] = add <2 x i32> %a, [[MUL_I]] 39474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[ADD_I]] 3948651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x2_t test_vmla_n_u32(uint32x2_t a, uint32x2_t b, uint32_t c) { 3949651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmla_n_u32(a, b, c); 3950651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3951651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 39524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlaq_n_u32(<4 x i32> %a, <4 x i32> %b, i32 %c) #0 { 39534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i32> undef, i32 %c, i32 0 39544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 %c, i32 1 39554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 %c, i32 2 39564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 %c, i32 3 39574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <4 x i32> %b, [[VECINIT3_I]] 39584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I:%.*]] = add <4 x i32> %a, [[MUL_I]] 39594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD_I]] 3960651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x4_t test_vmlaq_n_u32(uint32x4_t a, uint32x4_t b, uint32_t c) { 3961651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlaq_n_u32(a, b, c); 3962651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3963651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 39644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_n_s16(<4 x i32> %a, <4 x i16> %b, i16 %c) #0 { 39654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 39664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %c, i32 1 39674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %c, i32 2 39684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %c, i32 3 39694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 39704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8> 39714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 39724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 39734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]]) #2 39744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I:%.*]] = add <4 x i32> %a, [[VMULL2_I_I]] 39754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD_I]] 3976651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vmlal_n_s16(int32x4_t a, int16x4_t b, int16_t c) { 3977651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlal_n_s16(a, b, c); 3978651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3979651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 39804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_n_s32(<2 x i64> %a, <2 x i32> %b, i32 %c) #0 { 39814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 39824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %c, i32 1 39834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 39844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8> 39854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 39864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 39874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]]) #2 39884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I:%.*]] = add <2 x i64> %a, [[VMULL2_I_I]] 39894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD_I]] 3990651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint64x2_t test_vmlal_n_s32(int64x2_t a, int32x2_t b, int32_t c) { 3991651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlal_n_s32(a, b, c); 3992651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 3993651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 39944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlal_n_u16(<4 x i32> %a, <4 x i16> %b, i16 %c) #0 { 39954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 39964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %c, i32 1 39974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %c, i32 2 39984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %c, i32 3 39994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 40004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8> 40014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 40024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 40034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]]) #2 40044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I:%.*]] = add <4 x i32> %a, [[VMULL2_I_I]] 40054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD_I]] 4006651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x4_t test_vmlal_n_u16(uint32x4_t a, uint16x4_t b, uint16_t c) { 4007651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlal_n_u16(a, b, c); 4008651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4009651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 40104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlal_n_u32(<2 x i64> %a, <2 x i32> %b, i32 %c) #0 { 40114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 40124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %c, i32 1 40134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 40144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8> 40154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 40164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 40174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]]) #2 40184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD_I:%.*]] = add <2 x i64> %a, [[VMULL2_I_I]] 40194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[ADD_I]] 4020651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint64x2_t test_vmlal_n_u32(uint64x2_t a, uint32x2_t b, uint32_t c) { 4021651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlal_n_u32(a, b, c); 4022651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4023651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 40244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlal_n_s16(<4 x i32> %a, <4 x i16> %b, i16 %c) #0 { 40254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 40264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> 40274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 40284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %c, i32 1 40294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %c, i32 2 40304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %c, i32 3 40314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8> 40324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 40334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL4_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 40344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL5_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL4_I]]) #2 40354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 40364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V6_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[VQDMLAL_V_I]], <4 x i32> [[VQDMLAL5_I]]) #2 40374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLAL_V6_I]] 4038651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqdmlal_n_s16(int32x4_t a, int16x4_t b, int16_t c) { 4039651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlal_n_s16(a, b, c); 4040651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4041651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 40424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlal_n_s32(<2 x i64> %a, <2 x i32> %b, i32 %c) #0 { 40434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 40444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> 40454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 40464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %c, i32 1 40474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8> 40484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 40494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 40504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL2_I]]) #2 40514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 40524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V4_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[VQDMLAL_V_I]], <2 x i64> [[VQDMLAL3_I]]) #2 40534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLAL_V4_I]] 4054651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint64x2_t test_vqdmlal_n_s32(int64x2_t a, int32x2_t b, int32_t c) { 4055651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlal_n_s32(a, b, c); 4056651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4057651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 40584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmls_n_s16(<4 x i16> %a, <4 x i16> %b, i16 %c) #0 { 40594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 40604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %c, i32 1 40614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %c, i32 2 40624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %c, i32 3 40634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <4 x i16> %b, [[VECINIT3_I]] 40644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I:%.*]] = sub <4 x i16> %a, [[MUL_I]] 40654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[SUB_I]] 4066651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x4_t test_vmls_n_s16(int16x4_t a, int16x4_t b, int16_t c) { 4067651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmls_n_s16(a, b, c); 4068651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4069651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 40704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlsq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 %c) #0 { 40714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <8 x i16> undef, i16 %c, i32 0 40724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 %c, i32 1 40734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 %c, i32 2 40744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 %c, i32 3 40754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 %c, i32 4 40764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 %c, i32 5 40774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 %c, i32 6 40784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 %c, i32 7 40794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <8 x i16> %b, [[VECINIT7_I]] 40804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I:%.*]] = sub <8 x i16> %a, [[MUL_I]] 40814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[SUB_I]] 4082651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x8_t test_vmlsq_n_s16(int16x8_t a, int16x8_t b, int16_t c) { 4083651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsq_n_s16(a, b, c); 4084651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4085651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 40864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmls_n_s32(<2 x i32> %a, <2 x i32> %b, i32 %c) #0 { 40874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 40884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %c, i32 1 40894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <2 x i32> %b, [[VECINIT1_I]] 40904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I:%.*]] = sub <2 x i32> %a, [[MUL_I]] 40914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[SUB_I]] 4092651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x2_t test_vmls_n_s32(int32x2_t a, int32x2_t b, int32_t c) { 4093651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmls_n_s32(a, b, c); 4094651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4095651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 40964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) #0 { 40974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i32> undef, i32 %c, i32 0 40984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 %c, i32 1 40994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 %c, i32 2 41004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 %c, i32 3 41014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <4 x i32> %b, [[VECINIT3_I]] 41024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I:%.*]] = sub <4 x i32> %a, [[MUL_I]] 41034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB_I]] 4104651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vmlsq_n_s32(int32x4_t a, int32x4_t b, int32_t c) { 4105651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsq_n_s32(a, b, c); 4106651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4107651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 41084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmls_n_u16(<4 x i16> %a, <4 x i16> %b, i16 %c) #0 { 41094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 41104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %c, i32 1 41114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %c, i32 2 41124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %c, i32 3 41134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <4 x i16> %b, [[VECINIT3_I]] 41144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I:%.*]] = sub <4 x i16> %a, [[MUL_I]] 41154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[SUB_I]] 4116651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x4_t test_vmls_n_u16(uint16x4_t a, uint16x4_t b, uint16_t c) { 4117651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmls_n_u16(a, b, c); 4118651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4119651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 41204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlsq_n_u16(<8 x i16> %a, <8 x i16> %b, i16 %c) #0 { 41214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <8 x i16> undef, i16 %c, i32 0 41224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 %c, i32 1 41234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 %c, i32 2 41244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 %c, i32 3 41254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 %c, i32 4 41264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 %c, i32 5 41274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 %c, i32 6 41284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 %c, i32 7 41294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <8 x i16> %b, [[VECINIT7_I]] 41304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I:%.*]] = sub <8 x i16> %a, [[MUL_I]] 41314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[SUB_I]] 4132651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x8_t test_vmlsq_n_u16(uint16x8_t a, uint16x8_t b, uint16_t c) { 4133651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsq_n_u16(a, b, c); 4134651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4135651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 41364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmls_n_u32(<2 x i32> %a, <2 x i32> %b, i32 %c) #0 { 41374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 41384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %c, i32 1 41394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <2 x i32> %b, [[VECINIT1_I]] 41404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I:%.*]] = sub <2 x i32> %a, [[MUL_I]] 41414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[SUB_I]] 4142651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x2_t test_vmls_n_u32(uint32x2_t a, uint32x2_t b, uint32_t c) { 4143651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmls_n_u32(a, b, c); 4144651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4145651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 41464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsq_n_u32(<4 x i32> %a, <4 x i32> %b, i32 %c) #0 { 41474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i32> undef, i32 %c, i32 0 41484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 %c, i32 1 41494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 %c, i32 2 41504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 %c, i32 3 41514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL_I:%.*]] = mul <4 x i32> %b, [[VECINIT3_I]] 41524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I:%.*]] = sub <4 x i32> %a, [[MUL_I]] 41534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB_I]] 4154651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x4_t test_vmlsq_n_u32(uint32x4_t a, uint32x4_t b, uint32_t c) { 4155651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsq_n_u32(a, b, c); 4156651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4157651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 41584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_n_s16(<4 x i32> %a, <4 x i16> %b, i16 %c) #0 { 41594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 41604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %c, i32 1 41614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %c, i32 2 41624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %c, i32 3 41634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 41644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8> 41654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 41664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 41674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]]) #2 41684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I:%.*]] = sub <4 x i32> %a, [[VMULL2_I_I]] 41694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB_I]] 4170651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vmlsl_n_s16(int32x4_t a, int16x4_t b, int16_t c) { 4171651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsl_n_s16(a, b, c); 4172651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4173651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 41744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_n_s32(<2 x i64> %a, <2 x i32> %b, i32 %c) #0 { 41754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 41764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %c, i32 1 41774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 41784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8> 41794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 41804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 41814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]]) #2 41824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I:%.*]] = sub <2 x i64> %a, [[VMULL2_I_I]] 41834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB_I]] 4184651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint64x2_t test_vmlsl_n_s32(int64x2_t a, int32x2_t b, int32_t c) { 4185651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsl_n_s32(a, b, c); 4186651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4187651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 41884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsl_n_u16(<4 x i32> %a, <4 x i16> %b, i16 %c) #0 { 41894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 41904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %c, i32 1 41914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %c, i32 2 41924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %c, i32 3 41934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 41944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8> 41954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 41964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 41974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]]) #2 41984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I:%.*]] = sub <4 x i32> %a, [[VMULL2_I_I]] 41994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB_I]] 4200651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x4_t test_vmlsl_n_u16(uint32x4_t a, uint16x4_t b, uint16_t c) { 4201651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsl_n_u16(a, b, c); 4202651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4203651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 42044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vmlsl_n_u32(<2 x i64> %a, <2 x i32> %b, i32 %c) #0 { 42054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 42064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %c, i32 1 42074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 42084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8> 42094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 42104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 42114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]]) #2 42124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB_I:%.*]] = sub <2 x i64> %a, [[VMULL2_I_I]] 42134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[SUB_I]] 4214651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint64x2_t test_vmlsl_n_u32(uint64x2_t a, uint32x2_t b, uint32_t c) { 4215651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsl_n_u32(a, b, c); 4216651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4217651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 42184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlsl_n_s16(<4 x i32> %a, <4 x i16> %b, i16 %c) #0 { 42194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 42204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> 42214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 %c, i32 0 42224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 %c, i32 1 42234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 %c, i32 2 42244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 %c, i32 3 42254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8> 42264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 42274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL4_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 42284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL5_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL4_I]]) #2 42294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 42304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V6_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[VQDMLSL_V_I]], <4 x i32> [[VQDMLAL5_I]]) #2 42314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLSL_V6_I]] 4232651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqdmlsl_n_s16(int32x4_t a, int16x4_t b, int16_t c) { 4233651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlsl_n_s16(a, b, c); 4234651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4235651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 42364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlsl_n_s32(<2 x i64> %a, <2 x i32> %b, i32 %c) #0 { 42374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 42384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> 42394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 %c, i32 0 42404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 %c, i32 1 42414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8> 42424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 42434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 42444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL2_I]]) #2 42454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 42464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V4_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[VQDMLSL_V_I]], <2 x i64> [[VQDMLAL3_I]]) #2 42474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLSL_V4_I]] 4248651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint64x2_t test_vqdmlsl_n_s32(int64x2_t a, int32x2_t b, int32_t c) { 4249651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlsl_n_s32(a, b, c); 4250651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4251651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 42524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmla_lane_u16_0(<4 x i16> %a, <4 x i16> %b, <4 x i16> %v) #0 { 42534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 42544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 42554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i16> %a, [[MUL]] 42564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[ADD]] 4257651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x4_t test_vmla_lane_u16_0(uint16x4_t a, uint16x4_t b, uint16x4_t v) { 4258651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmla_lane_u16(a, b, v, 0); 4259651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4260651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 42614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlaq_lane_u16_0(<8 x i16> %a, <8 x i16> %b, <4 x i16> %v) #0 { 42624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> zeroinitializer 42634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 42644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <8 x i16> %a, [[MUL]] 42654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[ADD]] 4266651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x8_t test_vmlaq_lane_u16_0(uint16x8_t a, uint16x8_t b, uint16x4_t v) { 4267651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlaq_lane_u16(a, b, v, 0); 4268651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4269651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 42704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmla_lane_u32_0(<2 x i32> %a, <2 x i32> %b, <2 x i32> %v) #0 { 42714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 42724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 42734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i32> %a, [[MUL]] 42744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[ADD]] 4275651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x2_t test_vmla_lane_u32_0(uint32x2_t a, uint32x2_t b, uint32x2_t v) { 4276651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmla_lane_u32(a, b, v, 0); 4277651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4278651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 42794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlaq_lane_u32_0(<4 x i32> %a, <4 x i32> %b, <2 x i32> %v) #0 { 42804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> zeroinitializer 42814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 42824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[MUL]] 42834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 4284651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x4_t test_vmlaq_lane_u32_0(uint32x4_t a, uint32x4_t b, uint32x2_t v) { 4285651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlaq_lane_u32(a, b, v, 0); 4286651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4287651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 42884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmla_laneq_u16_0(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) #0 { 42894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 42904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 42914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i16> %a, [[MUL]] 42924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[ADD]] 4293651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x4_t test_vmla_laneq_u16_0(uint16x4_t a, uint16x4_t b, uint16x8_t v) { 4294651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmla_laneq_u16(a, b, v, 0); 4295651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4296651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 42974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlaq_laneq_u16_0(<8 x i16> %a, <8 x i16> %b, <8 x i16> %v) #0 { 42984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> zeroinitializer 42994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 43004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <8 x i16> %a, [[MUL]] 43014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[ADD]] 4302651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x8_t test_vmlaq_laneq_u16_0(uint16x8_t a, uint16x8_t b, uint16x8_t v) { 4303651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlaq_laneq_u16(a, b, v, 0); 4304651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4305651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 43064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmla_laneq_u32_0(<2 x i32> %a, <2 x i32> %b, <4 x i32> %v) #0 { 43074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 43084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 43094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i32> %a, [[MUL]] 43104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[ADD]] 4311651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x2_t test_vmla_laneq_u32_0(uint32x2_t a, uint32x2_t b, uint32x4_t v) { 4312651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmla_laneq_u32(a, b, v, 0); 4313651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4314651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 43154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlaq_laneq_u32_0(<4 x i32> %a, <4 x i32> %b, <4 x i32> %v) #0 { 43164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> zeroinitializer 43174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 43184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[MUL]] 43194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 4320651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x4_t test_vmlaq_laneq_u32_0(uint32x4_t a, uint32x4_t b, uint32x4_t v) { 4321651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlaq_laneq_u32(a, b, v, 0); 4322651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4323651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 43244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlal_laneq_s16_0(<4 x i32> %a, <4 x i16> %b, <8 x i16> %v) #0 { 43254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 43264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 43274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> 43284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 43294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 43304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 43314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 43324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 43334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[VQDMLAL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 43344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLAL_V3_I]] 4335651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqdmlal_laneq_s16_0(int32x4_t a, int16x4_t b, int16x8_t v) { 4336651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlal_laneq_s16(a, b, v, 0); 4337651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4338651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 43394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlal_laneq_s32_0(<2 x i64> %a, <2 x i32> %b, <4 x i32> %v) #0 { 43404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 43414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 43424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> 43434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 43444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 43454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 43464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 43474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 43484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[VQDMLAL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 43494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLAL_V3_I]] 4350651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint64x2_t test_vqdmlal_laneq_s32_0(int64x2_t a, int32x2_t b, int32x4_t v) { 4351651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlal_laneq_s32(a, b, v, 0); 4352651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4353651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 43544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlal_high_laneq_s16_0(<4 x i32> %a, <8 x i16> %b, <8 x i16> %v) #0 { 43554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 43564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 43574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 43584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 43594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 43604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 43614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 43624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 43634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 43644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[VQDMLAL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 43654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLAL_V3_I]] 4366651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqdmlal_high_laneq_s16_0(int32x4_t a, int16x8_t b, int16x8_t v) { 4367651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlal_high_laneq_s16(a, b, v, 0); 4368651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4369651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 43704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlal_high_laneq_s32_0(<2 x i64> %a, <4 x i32> %b, <4 x i32> %v) #0 { 43714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 43724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 43734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 43744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 43754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 43764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 43774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 43784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 43794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 43804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[VQDMLAL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 43814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLAL_V3_I]] 4382651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint64x2_t test_vqdmlal_high_laneq_s32_0(int64x2_t a, int32x4_t b, int32x4_t v) { 4383651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlal_high_laneq_s32(a, b, v, 0); 4384651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4385651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 43864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmls_lane_u16_0(<4 x i16> %a, <4 x i16> %b, <4 x i16> %v) #0 { 43874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> zeroinitializer 43884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 43894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i16> %a, [[MUL]] 43904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[SUB]] 4391651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x4_t test_vmls_lane_u16_0(uint16x4_t a, uint16x4_t b, uint16x4_t v) { 4392651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmls_lane_u16(a, b, v, 0); 4393651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4394651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 43954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlsq_lane_u16_0(<8 x i16> %a, <8 x i16> %b, <4 x i16> %v) #0 { 43964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> zeroinitializer 43974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 43984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <8 x i16> %a, [[MUL]] 43994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[SUB]] 4400651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x8_t test_vmlsq_lane_u16_0(uint16x8_t a, uint16x8_t b, uint16x4_t v) { 4401651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsq_lane_u16(a, b, v, 0); 4402651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4403651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 44044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmls_lane_u32_0(<2 x i32> %a, <2 x i32> %b, <2 x i32> %v) #0 { 44054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> zeroinitializer 44064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 44074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i32> %a, [[MUL]] 44084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[SUB]] 4409651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x2_t test_vmls_lane_u32_0(uint32x2_t a, uint32x2_t b, uint32x2_t v) { 4410651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmls_lane_u32(a, b, v, 0); 4411651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4412651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 44134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsq_lane_u32_0(<4 x i32> %a, <4 x i32> %b, <2 x i32> %v) #0 { 44144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> zeroinitializer 44154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 44164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[MUL]] 44174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 4418651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x4_t test_vmlsq_lane_u32_0(uint32x4_t a, uint32x4_t b, uint32x2_t v) { 4419651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsq_lane_u32(a, b, v, 0); 4420651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4421651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 44224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmls_laneq_u16_0(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) #0 { 44234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 44244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 44254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i16> %a, [[MUL]] 44264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[SUB]] 4427651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x4_t test_vmls_laneq_u16_0(uint16x4_t a, uint16x4_t b, uint16x8_t v) { 4428651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmls_laneq_u16(a, b, v, 0); 4429651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4430651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 44314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlsq_laneq_u16_0(<8 x i16> %a, <8 x i16> %b, <8 x i16> %v) #0 { 44324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> zeroinitializer 44334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 44344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <8 x i16> %a, [[MUL]] 44354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[SUB]] 4436651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x8_t test_vmlsq_laneq_u16_0(uint16x8_t a, uint16x8_t b, uint16x8_t v) { 4437651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsq_laneq_u16(a, b, v, 0); 4438651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4439651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 44404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmls_laneq_u32_0(<2 x i32> %a, <2 x i32> %b, <4 x i32> %v) #0 { 44414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 44424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 44434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i32> %a, [[MUL]] 44444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[SUB]] 4445651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x2_t test_vmls_laneq_u32_0(uint32x2_t a, uint32x2_t b, uint32x4_t v) { 4446651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmls_laneq_u32(a, b, v, 0); 4447651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4448651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 44494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsq_laneq_u32_0(<4 x i32> %a, <4 x i32> %b, <4 x i32> %v) #0 { 44504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> zeroinitializer 44514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 44524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[MUL]] 44534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 4454651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x4_t test_vmlsq_laneq_u32_0(uint32x4_t a, uint32x4_t b, uint32x4_t v) { 4455651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsq_laneq_u32(a, b, v, 0); 4456651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4457651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 44584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlsl_laneq_s16_0(<4 x i32> %a, <4 x i16> %b, <8 x i16> %v) #0 { 44594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 44604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 44614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> 44624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 44634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 44644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 44654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 44664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 44674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[VQDMLSL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 44684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLSL_V3_I]] 4469651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqdmlsl_laneq_s16_0(int32x4_t a, int16x4_t b, int16x8_t v) { 4470651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlsl_laneq_s16(a, b, v, 0); 4471651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4472651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 44734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlsl_laneq_s32_0(<2 x i64> %a, <2 x i32> %b, <4 x i32> %v) #0 { 44744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 44754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 44764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> 44774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 44784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 44794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 44804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 44814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 44824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[VQDMLSL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 44834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLSL_V3_I]] 4484651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint64x2_t test_vqdmlsl_laneq_s32_0(int64x2_t a, int32x2_t b, int32x4_t v) { 4485651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlsl_laneq_s32(a, b, v, 0); 4486651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4487651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 44884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlsl_high_laneq_s16_0(<4 x i32> %a, <8 x i16> %b, <8 x i16> %v) #0 { 44894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 44904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 44914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 44924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 44934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 44944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 44954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 44964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 44974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 44984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[VQDMLSL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 44994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLSL_V3_I]] 4500651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqdmlsl_high_laneq_s16_0(int32x4_t a, int16x8_t b, int16x8_t v) { 4501651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlsl_high_laneq_s16(a, b, v, 0); 4502651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4503651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 45044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlsl_high_laneq_s32_0(<2 x i64> %a, <4 x i32> %b, <4 x i32> %v) #0 { 45054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 45064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 45074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 45084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 45094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 45104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 45114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 45124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 45134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 45144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[VQDMLSL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 45154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLSL_V3_I]] 4516651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint64x2_t test_vqdmlsl_high_laneq_s32_0(int64x2_t a, int32x4_t b, int32x4_t v) { 4517651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlsl_high_laneq_s32(a, b, v, 0); 4518651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4519651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 45204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vqdmulh_laneq_s16_0(<4 x i16> %a, <8 x i16> %v) #0 { 45214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 45224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 45234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 45244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 45254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 45264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> [[VQDMULH_V_I]], <4 x i16> [[VQDMULH_V1_I]]) #2 45274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V3_I:%.*]] = bitcast <4 x i16> [[VQDMULH_V2_I]] to <8 x i8> 45284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQDMULH_V3_I]] to <4 x i16> 45294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[TMP2]] 4530651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x4_t test_vqdmulh_laneq_s16_0(int16x4_t a, int16x8_t v) { 4531651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmulh_laneq_s16(a, v, 0); 4532651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4533651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 45344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vqdmulhq_laneq_s16_0(<8 x i16> %a, <8 x i16> %v) #0 { 45354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> zeroinitializer 45364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> 45374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> [[SHUFFLE]] to <16 x i8> 45384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 45394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> 45404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> [[VQDMULHQ_V_I]], <8 x i16> [[VQDMULHQ_V1_I]]) #2 45414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V3_I:%.*]] = bitcast <8 x i16> [[VQDMULHQ_V2_I]] to <16 x i8> 45424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V3_I]] to <8 x i16> 45434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[TMP2]] 4544651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x8_t test_vqdmulhq_laneq_s16_0(int16x8_t a, int16x8_t v) { 4545651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmulhq_laneq_s16(a, v, 0); 4546651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4547651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 45484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vqdmulh_laneq_s32_0(<2 x i32> %a, <4 x i32> %v) #0 { 45494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 45504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 45514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 45524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 45534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 45544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> [[VQDMULH_V_I]], <2 x i32> [[VQDMULH_V1_I]]) #2 45554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V3_I:%.*]] = bitcast <2 x i32> [[VQDMULH_V2_I]] to <8 x i8> 45564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQDMULH_V3_I]] to <2 x i32> 45574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[TMP2]] 4558651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x2_t test_vqdmulh_laneq_s32_0(int32x2_t a, int32x4_t v) { 4559651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmulh_laneq_s32(a, v, 0); 4560651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4561651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 45624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmulhq_laneq_s32_0(<4 x i32> %a, <4 x i32> %v) #0 { 45634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> zeroinitializer 45644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 45654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8> 45664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 45674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 45684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> [[VQDMULHQ_V_I]], <4 x i32> [[VQDMULHQ_V1_I]]) #2 45694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULHQ_V2_I]] to <16 x i8> 45704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V3_I]] to <4 x i32> 45714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 4572651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqdmulhq_laneq_s32_0(int32x4_t a, int32x4_t v) { 4573651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmulhq_laneq_s32(a, v, 0); 4574651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4575651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 45764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vqrdmulh_laneq_s16_0(<4 x i16> %a, <8 x i16> %v) #0 { 45774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> zeroinitializer 45784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 45794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 45804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 45814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 45824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> [[VQRDMULH_V_I]], <4 x i16> [[VQRDMULH_V1_I]]) #2 45834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V3_I:%.*]] = bitcast <4 x i16> [[VQRDMULH_V2_I]] to <8 x i8> 45844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRDMULH_V3_I]] to <4 x i16> 45854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[TMP2]] 4586651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x4_t test_vqrdmulh_laneq_s16_0(int16x4_t a, int16x8_t v) { 4587651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqrdmulh_laneq_s16(a, v, 0); 4588651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4589651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 45904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vqrdmulhq_laneq_s16_0(<8 x i16> %a, <8 x i16> %v) #0 { 45914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> zeroinitializer 45924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> 45934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> [[SHUFFLE]] to <16 x i8> 45944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 45954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> 45964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> [[VQRDMULHQ_V_I]], <8 x i16> [[VQRDMULHQ_V1_I]]) #2 45974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V3_I:%.*]] = bitcast <8 x i16> [[VQRDMULHQ_V2_I]] to <16 x i8> 45984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V3_I]] to <8 x i16> 45994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[TMP2]] 4600651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x8_t test_vqrdmulhq_laneq_s16_0(int16x8_t a, int16x8_t v) { 4601651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqrdmulhq_laneq_s16(a, v, 0); 4602651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4603651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 46044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vqrdmulh_laneq_s32_0(<2 x i32> %a, <4 x i32> %v) #0 { 46054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> zeroinitializer 46064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 46074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 46084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 46094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 46104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> [[VQRDMULH_V_I]], <2 x i32> [[VQRDMULH_V1_I]]) #2 46114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V3_I:%.*]] = bitcast <2 x i32> [[VQRDMULH_V2_I]] to <8 x i8> 46124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRDMULH_V3_I]] to <2 x i32> 46134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[TMP2]] 4614651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x2_t test_vqrdmulh_laneq_s32_0(int32x2_t a, int32x4_t v) { 4615651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqrdmulh_laneq_s32(a, v, 0); 4616651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4617651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 46184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqrdmulhq_laneq_s32_0(<4 x i32> %a, <4 x i32> %v) #0 { 46194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> zeroinitializer 46204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 46214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8> 46224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 46234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 46244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> [[VQRDMULHQ_V_I]], <4 x i32> [[VQRDMULHQ_V1_I]]) #2 46254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V3_I:%.*]] = bitcast <4 x i32> [[VQRDMULHQ_V2_I]] to <16 x i8> 46264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V3_I]] to <4 x i32> 46274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 4628651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqrdmulhq_laneq_s32_0(int32x4_t a, int32x4_t v) { 4629651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqrdmulhq_laneq_s32(a, v, 0); 4630651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4631651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 46324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmla_lane_u16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %v) #0 { 46334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 46344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 46354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i16> %a, [[MUL]] 46364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[ADD]] 4637651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x4_t test_vmla_lane_u16(uint16x4_t a, uint16x4_t b, uint16x4_t v) { 4638651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmla_lane_u16(a, b, v, 3); 4639651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4640651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 46414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlaq_lane_u16(<8 x i16> %a, <8 x i16> %b, <4 x i16> %v) #0 { 46424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> 46434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 46444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <8 x i16> %a, [[MUL]] 46454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[ADD]] 4646651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x8_t test_vmlaq_lane_u16(uint16x8_t a, uint16x8_t b, uint16x4_t v) { 4647651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlaq_lane_u16(a, b, v, 3); 4648651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4649651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 46504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmla_lane_u32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %v) #0 { 46514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 46524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 46534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i32> %a, [[MUL]] 46544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[ADD]] 4655651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x2_t test_vmla_lane_u32(uint32x2_t a, uint32x2_t b, uint32x2_t v) { 4656651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmla_lane_u32(a, b, v, 1); 4657651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4658651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 46594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlaq_lane_u32(<4 x i32> %a, <4 x i32> %b, <2 x i32> %v) #0 { 46604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 46614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 46624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[MUL]] 46634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 4664651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x4_t test_vmlaq_lane_u32(uint32x4_t a, uint32x4_t b, uint32x2_t v) { 4665651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlaq_lane_u32(a, b, v, 1); 4666651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4667651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 46684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmla_laneq_u16(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) #0 { 46694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 46704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 46714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i16> %a, [[MUL]] 46724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[ADD]] 4673651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x4_t test_vmla_laneq_u16(uint16x4_t a, uint16x4_t b, uint16x8_t v) { 4674651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmla_laneq_u16(a, b, v, 7); 4675651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4676651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 46774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlaq_laneq_u16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %v) #0 { 46784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7> 46794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 46804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <8 x i16> %a, [[MUL]] 46814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[ADD]] 4682651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x8_t test_vmlaq_laneq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t v) { 4683651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlaq_laneq_u16(a, b, v, 7); 4684651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4685651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 46864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmla_laneq_u32(<2 x i32> %a, <2 x i32> %b, <4 x i32> %v) #0 { 46874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 46884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 46894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <2 x i32> %a, [[MUL]] 46904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[ADD]] 4691651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x2_t test_vmla_laneq_u32(uint32x2_t a, uint32x2_t b, uint32x4_t v) { 4692651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmla_laneq_u32(a, b, v, 3); 4693651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4694651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 46954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlaq_laneq_u32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %v) #0 { 46964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 46974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 46984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[MUL]] 46994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[ADD]] 4700651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x4_t test_vmlaq_laneq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t v) { 4701651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlaq_laneq_u32(a, b, v, 3); 4702651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4703651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 47044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlal_laneq_s16(<4 x i32> %a, <4 x i16> %b, <8 x i16> %v) #0 { 47054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 47064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 47074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> 47084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 47094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 47104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 47114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 47124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 47134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[VQDMLAL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 47144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLAL_V3_I]] 4715651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqdmlal_laneq_s16(int32x4_t a, int16x4_t b, int16x8_t v) { 4716651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlal_laneq_s16(a, b, v, 7); 4717651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4718651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 47194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlal_laneq_s32(<2 x i64> %a, <2 x i32> %b, <4 x i32> %v) #0 { 47204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 47214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 47224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> 47234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 47244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 47254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 47264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 47274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 47284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[VQDMLAL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 47294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLAL_V3_I]] 4730651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint64x2_t test_vqdmlal_laneq_s32(int64x2_t a, int32x2_t b, int32x4_t v) { 4731651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlal_laneq_s32(a, b, v, 3); 4732651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4733651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 47344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlal_high_laneq_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %v) #0 { 47354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 47364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 47374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 47384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 47394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 47404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 47414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 47424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 47434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 47444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[VQDMLAL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 47454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLAL_V3_I]] 4746651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqdmlal_high_laneq_s16(int32x4_t a, int16x8_t b, int16x8_t v) { 4747651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlal_high_laneq_s16(a, b, v, 7); 4748651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4749651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 47504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlal_high_laneq_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %v) #0 { 47514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 47524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 47534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 47544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 47554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 47564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 47574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 47584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 47594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 47604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[VQDMLAL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 47614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLAL_V3_I]] 4762651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint64x2_t test_vqdmlal_high_laneq_s32(int64x2_t a, int32x4_t b, int32x4_t v) { 4763651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlal_high_laneq_s32(a, b, v, 3); 4764651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4765651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 47664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmls_lane_u16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %v) #0 { 47674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 47684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 47694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i16> %a, [[MUL]] 47704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[SUB]] 4771651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x4_t test_vmls_lane_u16(uint16x4_t a, uint16x4_t b, uint16x4_t v) { 4772651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmls_lane_u16(a, b, v, 3); 4773651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4774651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 47754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlsq_lane_u16(<8 x i16> %a, <8 x i16> %b, <4 x i16> %v) #0 { 47764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> 47774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 47784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <8 x i16> %a, [[MUL]] 47794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[SUB]] 4780651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x8_t test_vmlsq_lane_u16(uint16x8_t a, uint16x8_t b, uint16x4_t v) { 4781651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsq_lane_u16(a, b, v, 3); 4782651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4783651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 47844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmls_lane_u32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %v) #0 { 47854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <2 x i32> <i32 1, i32 1> 47864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 47874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i32> %a, [[MUL]] 47884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[SUB]] 4789651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x2_t test_vmls_lane_u32(uint32x2_t a, uint32x2_t b, uint32x2_t v) { 4790651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmls_lane_u32(a, b, v, 1); 4791651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4792651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 47934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsq_lane_u32(<4 x i32> %a, <4 x i32> %b, <2 x i32> %v) #0 { 47944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 47954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 47964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[MUL]] 47974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 4798651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x4_t test_vmlsq_lane_u32(uint32x4_t a, uint32x4_t b, uint32x2_t v) { 4799651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsq_lane_u32(a, b, v, 1); 4800651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4801651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 48024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vmls_laneq_u16(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) #0 { 48034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 48044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]] 48054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i16> %a, [[MUL]] 48064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[SUB]] 4807651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x4_t test_vmls_laneq_u16(uint16x4_t a, uint16x4_t b, uint16x8_t v) { 4808651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmls_laneq_u16(a, b, v, 7); 4809651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4810651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 48114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vmlsq_laneq_u16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %v) #0 { 48124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7> 48134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]] 48144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <8 x i16> %a, [[MUL]] 48154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[SUB]] 4816651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint16x8_t test_vmlsq_laneq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t v) { 4817651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsq_laneq_u16(a, b, v, 7); 4818651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4819651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 48204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vmls_laneq_u32(<2 x i32> %a, <2 x i32> %b, <4 x i32> %v) #0 { 48214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 48224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]] 48234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <2 x i32> %a, [[MUL]] 48244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[SUB]] 4825651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x2_t test_vmls_laneq_u32(uint32x2_t a, uint32x2_t b, uint32x4_t v) { 4826651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmls_laneq_u32(a, b, v, 3); 4827651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4828651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 48294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vmlsq_laneq_u32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %v) #0 { 48304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 48314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]] 48324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[MUL]] 48334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[SUB]] 4834651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesuint32x4_t test_vmlsq_laneq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t v) { 4835651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmlsq_laneq_u32(a, b, v, 3); 4836651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4837651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 48384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlsl_laneq_s16(<4 x i32> %a, <4 x i16> %b, <8 x i16> %v) #0 { 48394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 48404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 48414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> 48424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 48434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 48444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 48454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 48464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 48474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[VQDMLSL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 48484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLSL_V3_I]] 4849651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqdmlsl_laneq_s16(int32x4_t a, int16x4_t b, int16x8_t v) { 4850651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlsl_laneq_s16(a, b, v, 7); 4851651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4852651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 48534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlsl_laneq_s32(<2 x i64> %a, <2 x i32> %b, <4 x i32> %v) #0 { 48544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 48554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 48564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> 48574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 48584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 48594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 48604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 48614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 48624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[VQDMLSL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 48634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLSL_V3_I]] 4864651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint64x2_t test_vqdmlsl_laneq_s32(int64x2_t a, int32x2_t b, int32x4_t v) { 4865651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlsl_laneq_s32(a, b, v, 3); 4866651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4867651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 48684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmlsl_high_laneq_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %v) #0 { 48694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 48704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 48714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 48724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8> 48734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 48744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 48754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 48764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]]) #2 48774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 48784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[VQDMLSL_V_I]], <4 x i32> [[VQDMLAL2_I]]) #2 48794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VQDMLSL_V3_I]] 4880651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqdmlsl_high_laneq_s16(int32x4_t a, int16x8_t b, int16x8_t v) { 4881651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlsl_high_laneq_s16(a, b, v, 7); 4882651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4883651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 48844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vqdmlsl_high_laneq_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %v) #0 { 48854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b, <2 x i32> <i32 2, i32 3> 48864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 48874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 48884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8> 48894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 48904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 48914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32> 48924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]]) #2 48934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 48944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMLSL_V3_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[VQDMLSL_V_I]], <2 x i64> [[VQDMLAL2_I]]) #2 48954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VQDMLSL_V3_I]] 4896651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint64x2_t test_vqdmlsl_high_laneq_s32(int64x2_t a, int32x4_t b, int32x4_t v) { 4897651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmlsl_high_laneq_s32(a, b, v, 3); 4898651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4899651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 49004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vqdmulh_laneq_s16(<4 x i16> %a, <8 x i16> %v) #0 { 49014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 49024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 49034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 49044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 49054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 49064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> [[VQDMULH_V_I]], <4 x i16> [[VQDMULH_V1_I]]) #2 49074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V3_I:%.*]] = bitcast <4 x i16> [[VQDMULH_V2_I]] to <8 x i8> 49084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQDMULH_V3_I]] to <4 x i16> 49094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[TMP2]] 4910651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x4_t test_vqdmulh_laneq_s16(int16x4_t a, int16x8_t v) { 4911651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmulh_laneq_s16(a, v, 7); 4912651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4913651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 49144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vqdmulhq_laneq_s16(<8 x i16> %a, <8 x i16> %v) #0 { 49154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7> 49164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> 49174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> [[SHUFFLE]] to <16 x i8> 49184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 49194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> 49204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> [[VQDMULHQ_V_I]], <8 x i16> [[VQDMULHQ_V1_I]]) #2 49214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V3_I:%.*]] = bitcast <8 x i16> [[VQDMULHQ_V2_I]] to <16 x i8> 49224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V3_I]] to <8 x i16> 49234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[TMP2]] 4924651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x8_t test_vqdmulhq_laneq_s16(int16x8_t a, int16x8_t v) { 4925651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmulhq_laneq_s16(a, v, 7); 4926651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4927651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 49284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vqdmulh_laneq_s32(<2 x i32> %a, <4 x i32> %v) #0 { 49294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 49304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 49314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 49324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 49334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 49344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> [[VQDMULH_V_I]], <2 x i32> [[VQDMULH_V1_I]]) #2 49354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULH_V3_I:%.*]] = bitcast <2 x i32> [[VQDMULH_V2_I]] to <8 x i8> 49364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQDMULH_V3_I]] to <2 x i32> 49374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[TMP2]] 4938651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x2_t test_vqdmulh_laneq_s32(int32x2_t a, int32x4_t v) { 4939651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmulh_laneq_s32(a, v, 3); 4940651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4941651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 49424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqdmulhq_laneq_s32(<4 x i32> %a, <4 x i32> %v) #0 { 49434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 49444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 49454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8> 49464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 49474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 49484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> [[VQDMULHQ_V_I]], <4 x i32> [[VQDMULHQ_V1_I]]) #2 49494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQDMULHQ_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULHQ_V2_I]] to <16 x i8> 49504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V3_I]] to <4 x i32> 49514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 4952651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqdmulhq_laneq_s32(int32x4_t a, int32x4_t v) { 4953651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqdmulhq_laneq_s32(a, v, 3); 4954651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4955651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 49564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vqrdmulh_laneq_s16(<4 x i16> %a, <8 x i16> %v) #0 { 49574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <4 x i32> <i32 7, i32 7, i32 7, i32 7> 49584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 49594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8> 49604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 49614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> 49624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> [[VQRDMULH_V_I]], <4 x i16> [[VQRDMULH_V1_I]]) #2 49634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V3_I:%.*]] = bitcast <4 x i16> [[VQRDMULH_V2_I]] to <8 x i8> 49644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRDMULH_V3_I]] to <4 x i16> 49654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[TMP2]] 4966651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x4_t test_vqrdmulh_laneq_s16(int16x4_t a, int16x8_t v) { 4967651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqrdmulh_laneq_s16(a, v, 7); 4968651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4969651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 49704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vqrdmulhq_laneq_s16(<8 x i16> %a, <8 x i16> %v) #0 { 49714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7> 49724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> 49734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> [[SHUFFLE]] to <16 x i8> 49744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 49754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> 49764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> [[VQRDMULHQ_V_I]], <8 x i16> [[VQRDMULHQ_V1_I]]) #2 49774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V3_I:%.*]] = bitcast <8 x i16> [[VQRDMULHQ_V2_I]] to <16 x i8> 49784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V3_I]] to <8 x i16> 49794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[TMP2]] 4980651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint16x8_t test_vqrdmulhq_laneq_s16(int16x8_t a, int16x8_t v) { 4981651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqrdmulhq_laneq_s16(a, v, 7); 4982651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4983651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 49844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vqrdmulh_laneq_s32(<2 x i32> %a, <4 x i32> %v) #0 { 49854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <2 x i32> <i32 3, i32 3> 49864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 49874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> 49884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 49894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> 49904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> [[VQRDMULH_V_I]], <2 x i32> [[VQRDMULH_V1_I]]) #2 49914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULH_V3_I:%.*]] = bitcast <2 x i32> [[VQRDMULH_V2_I]] to <8 x i8> 49924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRDMULH_V3_I]] to <2 x i32> 49934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[TMP2]] 4994651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x2_t test_vqrdmulh_laneq_s32(int32x2_t a, int32x4_t v) { 4995651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqrdmulh_laneq_s32(a, v, 3); 4996651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 4997651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 49984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vqrdmulhq_laneq_s32(<4 x i32> %a, <4 x i32> %v) #0 { 49994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 50004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 50014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8> 50024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 50034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 50044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> [[VQRDMULHQ_V_I]], <4 x i32> [[VQRDMULHQ_V1_I]]) #2 50054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VQRDMULHQ_V3_I:%.*]] = bitcast <4 x i32> [[VQRDMULHQ_V2_I]] to <16 x i8> 50064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V3_I]] to <4 x i32> 50074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[TMP2]] 5008651f13cea278ec967336033dd032faef0e9fc2ecStephen Hinesint32x4_t test_vqrdmulhq_laneq_s32(int32x4_t a, int32x4_t v) { 5009651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vqrdmulhq_laneq_s32(a, v, 3); 5010651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 5011651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 5012