187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar// RUN: %clang_cc1 -triple arm64-apple-darwin -target-feature +neon \ 24967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// RUN: -fallow-half-arguments-and-returns -emit-llvm -o - %s \ 34967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// RUN: | opt -S -mem2reg | FileCheck %s 487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar#include <arm_neon.h> 687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 74967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i8 @test_vget_lane_u8(<8 x i8> %a) #0 { 84967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7 94967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i8 [[VGET_LANE]] 1087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint8_t test_vget_lane_u8(uint8x8_t a) { 1187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vget_lane_u8(a, 7); 1287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 1387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i16 @test_vget_lane_u16(<4 x i16> %a) #0 { 154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[TMP1]], i32 3 184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i16 [[VGET_LANE]] 1987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint16_t test_vget_lane_u16(uint16x4_t a) { 2087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vget_lane_u16(a, 3); 2187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 2287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i32 @test_vget_lane_u32(<2 x i32> %a) #0 { 244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1 274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i32 [[VGET_LANE]] 2887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint32_t test_vget_lane_u32(uint32x2_t a) { 2987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vget_lane_u32(a, 1); 3087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 3187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i8 @test_vget_lane_s8(<8 x i8> %a) #0 { 334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7 344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i8 [[VGET_LANE]] 3587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint8_t test_vget_lane_s8(int8x8_t a) { 3687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vget_lane_s8(a, 7); 3787d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 3887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i16 @test_vget_lane_s16(<4 x i16> %a) #0 { 404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[TMP1]], i32 3 434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i16 [[VGET_LANE]] 4487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint16_t test_vget_lane_s16(int16x4_t a) { 4587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vget_lane_s16(a, 3); 4687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 4787d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i32 @test_vget_lane_s32(<2 x i32> %a) #0 { 494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> 504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1 524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i32 [[VGET_LANE]] 5387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint32_t test_vget_lane_s32(int32x2_t a) { 5487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vget_lane_s32(a, 1); 5587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 5687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i8 @test_vget_lane_p8(<8 x i8> %a) #0 { 584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7 594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i8 [[VGET_LANE]] 6087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarpoly8_t test_vget_lane_p8(poly8x8_t a) { 6187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vget_lane_p8(a, 7); 6287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 6387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i16 @test_vget_lane_p16(<4 x i16> %a) #0 { 654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> 664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[TMP1]], i32 3 684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i16 [[VGET_LANE]] 6987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarpoly16_t test_vget_lane_p16(poly16x4_t a) { 7087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vget_lane_p16(a, 3); 7187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 7287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define float @test_vget_lane_f32(<2 x float> %a) #0 { 744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x float> [[TMP1]], i32 1 774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret float [[VGET_LANE]] 7887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarfloat32_t test_vget_lane_f32(float32x2_t a) { 7987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vget_lane_f32(a, 1); 8087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 8187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define float @test_vget_lane_f16(<4 x half> %a) #0 { 834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[__REINT_242:%.*]] = alloca <4 x half>, align 8 844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[__REINT1_242:%.*]] = alloca i16, align 2 854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: store <4 x half> %a, <4 x half>* [[__REINT_242]], align 8 864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x half>* [[__REINT_242]] to <4 x i16>* 874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = load <4 x i16>, <4 x i16>* [[TMP0]], align 8 884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8> 894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> 904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[TMP3]], i32 1 914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: store i16 [[VGET_LANE]], i16* [[__REINT1_242]], align 2 924967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast i16* [[__REINT1_242]] to half* 934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = load half, half* [[TMP4]], align 2 944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[CONV:%.*]] = fpext half [[TMP5]] to float 954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret float [[CONV]] 9687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarfloat32_t test_vget_lane_f16(float16x4_t a) { 9787d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vget_lane_f16(a, 1); 9887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 9987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 1004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i8 @test_vgetq_lane_u8(<16 x i8> %a) #0 { 1014967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15 1024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i8 [[VGETQ_LANE]] 10387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint8_t test_vgetq_lane_u8(uint8x16_t a) { 10487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vgetq_lane_u8(a, 15); 10587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 10687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 1074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i16 @test_vgetq_lane_u16(<8 x i16> %a) #0 { 1084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> 1094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 1104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[TMP1]], i32 7 1114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i16 [[VGETQ_LANE]] 11287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint16_t test_vgetq_lane_u16(uint16x8_t a) { 11387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vgetq_lane_u16(a, 7); 11487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 11587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 1164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i32 @test_vgetq_lane_u32(<4 x i32> %a) #0 { 1174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 1184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 1194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3 1204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i32 [[VGETQ_LANE]] 12187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint32_t test_vgetq_lane_u32(uint32x4_t a) { 12287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vgetq_lane_u32(a, 3); 12387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 12487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 1254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i8 @test_vgetq_lane_s8(<16 x i8> %a) #0 { 1264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15 1274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i8 [[VGETQ_LANE]] 12887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint8_t test_vgetq_lane_s8(int8x16_t a) { 12987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vgetq_lane_s8(a, 15); 13087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 13187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 1324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i16 @test_vgetq_lane_s16(<8 x i16> %a) #0 { 1334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> 1344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 1354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[TMP1]], i32 7 1364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i16 [[VGETQ_LANE]] 13787d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint16_t test_vgetq_lane_s16(int16x8_t a) { 13887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vgetq_lane_s16(a, 7); 13987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 14087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 1414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i32 @test_vgetq_lane_s32(<4 x i32> %a) #0 { 1424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> 1434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 1444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3 1454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i32 [[VGETQ_LANE]] 14687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint32_t test_vgetq_lane_s32(int32x4_t a) { 14787d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vgetq_lane_s32(a, 3); 14887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 14987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 1504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i8 @test_vgetq_lane_p8(<16 x i8> %a) #0 { 1514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15 1524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i8 [[VGETQ_LANE]] 15387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarpoly8_t test_vgetq_lane_p8(poly8x16_t a) { 15487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vgetq_lane_p8(a, 15); 15587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 15687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 1574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i16 @test_vgetq_lane_p16(<8 x i16> %a) #0 { 1584967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> 1594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 1604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[TMP1]], i32 7 1614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i16 [[VGETQ_LANE]] 16287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarpoly16_t test_vgetq_lane_p16(poly16x8_t a) { 16387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vgetq_lane_p16(a, 7); 16487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 16587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 1664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define float @test_vgetq_lane_f32(<4 x float> %a) #0 { 1674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 1684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 1694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x float> [[TMP1]], i32 3 1704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret float [[VGETQ_LANE]] 17187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarfloat32_t test_vgetq_lane_f32(float32x4_t a) { 17287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vgetq_lane_f32(a, 3); 17387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 17487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 1754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define float @test_vgetq_lane_f16(<8 x half> %a) #0 { 1764967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[__REINT_244:%.*]] = alloca <8 x half>, align 16 1774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[__REINT1_244:%.*]] = alloca i16, align 2 1784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: store <8 x half> %a, <8 x half>* [[__REINT_244]], align 16 1794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x half>* [[__REINT_244]] to <8 x i16>* 1804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[TMP0]], align 16 1814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP1]] to <16 x i8> 1824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16> 1834967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[TMP3]], i32 3 1844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: store i16 [[VGETQ_LANE]], i16* [[__REINT1_244]], align 2 1854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = bitcast i16* [[__REINT1_244]] to half* 1864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = load half, half* [[TMP4]], align 2 1874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[CONV:%.*]] = fpext half [[TMP5]] to float 1884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret float [[CONV]] 18987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarfloat32_t test_vgetq_lane_f16(float16x8_t a) { 19087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vgetq_lane_f16(a, 3); 19187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 19287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 1934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i64 @test_vget_lane_s64(<1 x i64> %a) #0 { 1944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8> 1954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> 1964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> [[TMP1]], i32 0 1974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i64 [[VGET_LANE]] 19887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint64_t test_vget_lane_s64(int64x1_t a) { 19987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vget_lane_s64(a, 0); 20087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 20187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 2024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i64 @test_vget_lane_u64(<1 x i64> %a) #0 { 2034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8> 2044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> 2054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> [[TMP1]], i32 0 2064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i64 [[VGET_LANE]] 20787d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint64_t test_vget_lane_u64(uint64x1_t a) { 20887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vget_lane_u64(a, 0); 20987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 21087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 2114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i64 @test_vgetq_lane_s64(<2 x i64> %a) #0 { 2124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 2134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 2144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1 2154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i64 [[VGETQ_LANE]] 21687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint64_t test_vgetq_lane_s64(int64x2_t a) { 21787d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vgetq_lane_s64(a, 1); 21887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 21987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 2204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define i64 @test_vgetq_lane_u64(<2 x i64> %a) #0 { 2214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> 2224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 2234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1 2244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret i64 [[VGETQ_LANE]] 22587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint64_t test_vgetq_lane_u64(uint64x2_t a) { 22687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vgetq_lane_u64(a, 1); 22787d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 22887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 22987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 2304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i8> @test_vset_lane_u8(i8 %a, <8 x i8> %b) #0 { 2314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7 2324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i8> [[VSET_LANE]] 23387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint8x8_t test_vset_lane_u8(uint8_t a, uint8x8_t b) { 23487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vset_lane_u8(a, b, 7); 23587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 23687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 2374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vset_lane_u16(i16 %a, <4 x i16> %b) #0 { 2384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 2394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 2404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> [[TMP1]], i16 %a, i32 3 2414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[VSET_LANE]] 24287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint16x4_t test_vset_lane_u16(uint16_t a, uint16x4_t b) { 24387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vset_lane_u16(a, b, 3); 24487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 24587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 2464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vset_lane_u32(i32 %a, <2 x i32> %b) #0 { 2474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 2484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 2494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i32> [[TMP1]], i32 %a, i32 1 2504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[VSET_LANE]] 25187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint32x2_t test_vset_lane_u32(uint32_t a, uint32x2_t b) { 25287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vset_lane_u32(a, b, 1); 25387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 25487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 2554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i8> @test_vset_lane_s8(i8 %a, <8 x i8> %b) #0 { 2564967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7 2574967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i8> [[VSET_LANE]] 25887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint8x8_t test_vset_lane_s8(int8_t a, int8x8_t b) { 25987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vset_lane_s8(a, b, 7); 26087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 26187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 2624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vset_lane_s16(i16 %a, <4 x i16> %b) #0 { 2634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 2644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 2654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> [[TMP1]], i16 %a, i32 3 2664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[VSET_LANE]] 26787d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint16x4_t test_vset_lane_s16(int16_t a, int16x4_t b) { 26887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vset_lane_s16(a, b, 3); 26987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 27087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 2714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i32> @test_vset_lane_s32(i32 %a, <2 x i32> %b) #0 { 2724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8> 2734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> 2744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i32> [[TMP1]], i32 %a, i32 1 2754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i32> [[VSET_LANE]] 27687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint32x2_t test_vset_lane_s32(int32_t a, int32x2_t b) { 27787d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vset_lane_s32(a, b, 1); 27887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 27987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 2804967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i8> @test_vset_lane_p8(i8 %a, <8 x i8> %b) #0 { 2814967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7 2824967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i8> [[VSET_LANE]] 28387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarpoly8x8_t test_vset_lane_p8(poly8_t a, poly8x8_t b) { 28487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vset_lane_p8(a, b, 7); 28587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 28687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 2874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i16> @test_vset_lane_p16(i16 %a, <4 x i16> %b) #0 { 2884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8> 2894967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> 2904967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> [[TMP1]], i16 %a, i32 3 2914967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i16> [[VSET_LANE]] 29287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarpoly16x4_t test_vset_lane_p16(poly16_t a, poly16x4_t b) { 29387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vset_lane_p16(a, b, 3); 29487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 29587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 2964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x float> @test_vset_lane_f32(float %a, <2 x float> %b) #0 { 2974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %b to <8 x i8> 2984967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 2994967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x float> [[TMP1]], float %a, i32 1 3004967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x float> [[VSET_LANE]] 30187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarfloat32x2_t test_vset_lane_f32(float32_t a, float32x2_t b) { 30287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vset_lane_f32(a, b, 1); 30387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 30487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 3054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x half> @test_vset_lane_f16(half* %a, <4 x half> %b) #0 { 3064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[__REINT_246:%.*]] = alloca half, align 2 3074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[__REINT1_246:%.*]] = alloca <4 x half>, align 8 3084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[__REINT2_246:%.*]] = alloca <4 x i16>, align 8 3094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = load half, half* %a, align 2 3104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: store half [[TMP0]], half* [[__REINT_246]], align 2 3114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: store <4 x half> %b, <4 x half>* [[__REINT1_246]], align 8 3124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast half* [[__REINT_246]] to i16* 3134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 2 3144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <4 x half>* [[__REINT1_246]] to <4 x i16>* 3154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = load <4 x i16>, <4 x i16>* [[TMP3]], align 8 3164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP4]] to <8 x i8> 3174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x i16> 3184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> [[TMP6]], i16 [[TMP2]], i32 3 3194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: store <4 x i16> [[VSET_LANE]], <4 x i16>* [[__REINT2_246]], align 8 3204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP7:%.*]] = bitcast <4 x i16>* [[__REINT2_246]] to <4 x half>* 3214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP8:%.*]] = load <4 x half>, <4 x half>* [[TMP7]], align 8 3224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x half> [[TMP8]] 32387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarfloat16x4_t test_vset_lane_f16(float16_t *a, float16x4_t b) { 32487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vset_lane_f16(*a, b, 3); 32587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 32687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 3274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <16 x i8> @test_vsetq_lane_u8(i8 %a, <16 x i8> %b) #0 { 3284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %b, i8 %a, i32 15 3294967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <16 x i8> [[VSET_LANE]] 33087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint8x16_t test_vsetq_lane_u8(uint8_t a, uint8x16_t b) { 33187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vsetq_lane_u8(a, b, 15); 33287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 33387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 3344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vsetq_lane_u16(i16 %a, <8 x i16> %b) #0 { 3354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %b to <16 x i8> 3364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 3374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> [[TMP1]], i16 %a, i32 7 3384967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[VSET_LANE]] 33987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint16x8_t test_vsetq_lane_u16(uint16_t a, uint16x8_t b) { 34087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vsetq_lane_u16(a, b, 7); 34187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 34287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 3434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vsetq_lane_u32(i32 %a, <4 x i32> %b) #0 { 3444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %b to <16 x i8> 3454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 3464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i32> [[TMP1]], i32 %a, i32 3 3474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VSET_LANE]] 34887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint32x4_t test_vsetq_lane_u32(uint32_t a, uint32x4_t b) { 34987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vsetq_lane_u32(a, b, 3); 35087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 35187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 3524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <16 x i8> @test_vsetq_lane_s8(i8 %a, <16 x i8> %b) #0 { 3534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %b, i8 %a, i32 15 3544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <16 x i8> [[VSET_LANE]] 35587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint8x16_t test_vsetq_lane_s8(int8_t a, int8x16_t b) { 35687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vsetq_lane_s8(a, b, 15); 35787d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 35887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 3594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vsetq_lane_s16(i16 %a, <8 x i16> %b) #0 { 3604967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %b to <16 x i8> 3614967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 3624967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> [[TMP1]], i16 %a, i32 7 3634967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[VSET_LANE]] 36487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint16x8_t test_vsetq_lane_s16(int16_t a, int16x8_t b) { 36587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vsetq_lane_s16(a, b, 7); 36687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 36787d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 3684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x i32> @test_vsetq_lane_s32(i32 %a, <4 x i32> %b) #0 { 3694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %b to <16 x i8> 3704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> 3714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i32> [[TMP1]], i32 %a, i32 3 3724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x i32> [[VSET_LANE]] 37387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint32x4_t test_vsetq_lane_s32(int32_t a, int32x4_t b) { 37487d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vsetq_lane_s32(a, b, 3); 37587d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 37687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 3774967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <16 x i8> @test_vsetq_lane_p8(i8 %a, <16 x i8> %b) #0 { 3784967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %b, i8 %a, i32 15 3794967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <16 x i8> [[VSET_LANE]] 38087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarpoly8x16_t test_vsetq_lane_p8(poly8_t a, poly8x16_t b) { 38187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vsetq_lane_p8(a, b, 15); 38287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 38387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 3844967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x i16> @test_vsetq_lane_p16(i16 %a, <8 x i16> %b) #0 { 3854967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %b to <16 x i8> 3864967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> 3874967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> [[TMP1]], i16 %a, i32 7 3884967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x i16> [[VSET_LANE]] 38987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarpoly16x8_t test_vsetq_lane_p16(poly16_t a, poly16x8_t b) { 39087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vsetq_lane_p16(a, b, 7); 39187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 39287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 3934967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vsetq_lane_f32(float %a, <4 x float> %b) #0 { 3944967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %b to <16 x i8> 3954967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 3964967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x float> [[TMP1]], float %a, i32 3 3974967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[VSET_LANE]] 39887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarfloat32x4_t test_vsetq_lane_f32(float32_t a, float32x4_t b) { 39987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vsetq_lane_f32(a, b, 3); 40087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 40187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 4024967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x half> @test_vsetq_lane_f16(half* %a, <8 x half> %b) #0 { 4034967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[__REINT_248:%.*]] = alloca half, align 2 4044967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[__REINT1_248:%.*]] = alloca <8 x half>, align 16 4054967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[__REINT2_248:%.*]] = alloca <8 x i16>, align 16 4064967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = load half, half* %a, align 2 4074967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: store half [[TMP0]], half* [[__REINT_248]], align 2 4084967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: store <8 x half> %b, <8 x half>* [[__REINT1_248]], align 16 4094967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast half* [[__REINT_248]] to i16* 4104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 2 4114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP3:%.*]] = bitcast <8 x half>* [[__REINT1_248]] to <8 x i16>* 4124967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP4:%.*]] = load <8 x i16>, <8 x i16>* [[TMP3]], align 16 4134967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP4]] to <16 x i8> 4144967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x i16> 4154967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[TMP2]], i32 7 4164967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: store <8 x i16> [[VSET_LANE]], <8 x i16>* [[__REINT2_248]], align 16 4174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP7:%.*]] = bitcast <8 x i16>* [[__REINT2_248]] to <8 x half>* 4184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP8:%.*]] = load <8 x half>, <8 x half>* [[TMP7]], align 16 4194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x half> [[TMP8]] 42087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarfloat16x8_t test_vsetq_lane_f16(float16_t *a, float16x8_t b) { 42187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vsetq_lane_f16(*a, b, 7); 42287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 42387d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 4244967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <1 x i64> @test_vset_lane_s64(i64 %a, <1 x i64> %b) #0 { 4254967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %b to <8 x i8> 4264967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> 4274967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <1 x i64> [[TMP1]], i64 %a, i32 0 4284967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <1 x i64> [[VSET_LANE]] 42987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint64x1_t test_vset_lane_s64(int64_t a, int64x1_t b) { 43087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vset_lane_s64(a, b, 0); 43187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 43287d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 4334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <1 x i64> @test_vset_lane_u64(i64 %a, <1 x i64> %b) #0 { 4344967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %b to <8 x i8> 4354967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> 4364967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <1 x i64> [[TMP1]], i64 %a, i32 0 4374967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <1 x i64> [[VSET_LANE]] 43887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint64x1_t test_vset_lane_u64(uint64_t a, uint64x1_t b) { 43987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vset_lane_u64(a, b, 0); 44087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 44187d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 4424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vsetq_lane_s64(i64 %a, <2 x i64> %b) #0 { 4434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %b to <16 x i8> 4444967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 4454967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> [[TMP1]], i64 %a, i32 1 4464967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VSET_LANE]] 44787d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainarint64x2_t test_vsetq_lane_s64(int64_t a, int64x2_t b) { 44887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vsetq_lane_s64(a, b, 1); 44987d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 45087d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar 4514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x i64> @test_vsetq_lane_u64(i64 %a, <2 x i64> %b) #0 { 4524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %b to <16 x i8> 4534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> 4544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> [[TMP1]], i64 %a, i32 1 4554967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x i64> [[VSET_LANE]] 45687d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainaruint64x2_t test_vsetq_lane_u64(uint64_t a, uint64x2_t b) { 45787d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar return vsetq_lane_u64(a, b, 1); 45887d948ecccffea9e9e37d0d053b246e2d6d6c47bPirama Arumuga Nainar} 459