14967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -fallow-half-arguments-and-returns -S -o - -emit-llvm %s | opt -S -mem2reg | FileCheck %s 2651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 3651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines#include <arm_neon.h> 4651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 5651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines// vdupq_n_f64 -> dup.2d v0, v0[0] 6651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines// 74967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vdupq_n_f64(double %w) #0 { 84967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %w, i32 0 94967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %w, i32 1 104967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[VECINIT1_I]] 114967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainarfloat64x2_t test_vdupq_n_f64(float64_t w) { 12651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vdupq_n_f64(w); 13651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 14651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 15651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines// might as well test this while we're here 16651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines// vdupq_n_f32 -> dup.4s v0, v0[0] 174967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x float> @test_vdupq_n_f32(float %w) #0 { 184967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %w, i32 0 194967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %w, i32 1 204967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %w, i32 2 214967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float %w, i32 3 224967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x float> [[VECINIT3_I]] 234967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainarfloat32x4_t test_vdupq_n_f32(float32_t w) { 24651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vdupq_n_f32(w); 25651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 26651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 27651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines// vdupq_lane_f64 -> dup.2d v0, v0[0] 28651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines// this was in <rdar://problem/11778405>, but had already been implemented, 29651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines// test anyway 304967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vdupq_lane_f64(<1 x double> %V) #0 { 314967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[SHUFFLE:%.*]] = shufflevector <1 x double> %V, <1 x double> %V, <2 x i32> zeroinitializer 324967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[SHUFFLE]] 334967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainarfloat64x2_t test_vdupq_lane_f64(float64x1_t V) { 34651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vdupq_lane_f64(V, 0); 35651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 36651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 37651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines// vmovq_n_f64 -> dup Vd.2d,X0 38651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines// this wasn't in <rdar://problem/11778405>, but it was between the vdups 394967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <2 x double> @test_vmovq_n_f64(double %w) #0 { 404967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %w, i32 0 414967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %w, i32 1 424967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <2 x double> [[VECINIT1_I]] 434967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainarfloat64x2_t test_vmovq_n_f64(float64_t w) { 44651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmovq_n_f64(w); 45651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 46651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 474967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <4 x half> @test_vmov_n_f16(half* %a1) #0 { 484967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = load half, half* %a1, align 2 494967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT:%.*]] = insertelement <4 x half> undef, half [[TMP0]], i32 0 504967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[TMP0]], i32 1 514967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[TMP0]], i32 2 524967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[TMP0]], i32 3 534967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <4 x half> [[VECINIT3]] 544967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainarfloat16x4_t test_vmov_n_f16(float16_t *a1) { 55651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmov_n_f16(*a1); 56651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 57651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 58651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines/* 594967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainarfloat64x1_t test_vmov_n_f64(float64_t a1) { 60651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmov_n_f64(a1); 61651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 62651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines*/ 63651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 644967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK-LABEL: define <8 x half> @test_vmovq_n_f16(half* %a1) #0 { 654967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[TMP0:%.*]] = load half, half* %a1, align 2 664967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT:%.*]] = insertelement <8 x half> undef, half [[TMP0]], i32 0 674967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[TMP0]], i32 1 684967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[TMP0]], i32 2 694967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[TMP0]], i32 3 704967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[TMP0]], i32 4 714967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[TMP0]], i32 5 724967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[TMP0]], i32 6 734967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[TMP0]], i32 7 744967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainar// CHECK: ret <8 x half> [[VECINIT7]] 754967a710c84587c654b56c828382219c3937dacbPirama Arumuga Nainarfloat16x8_t test_vmovq_n_f16(float16_t *a1) { 76651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines return vmovq_n_f16(*a1); 77651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines} 78651f13cea278ec967336033dd032faef0e9fc2ecStephen Hines 79