1224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 2224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * All Rights Reserved. 4224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 5224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Permission is hereby granted, free of charge, to any person obtaining a 6224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * copy of this software and associated documentation files (the 7224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * "Software"), to deal in the Software without restriction, including 8224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * without limitation the rights to use, copy, modify, merge, publish, 9224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * distribute, sub license, and/or sell copies of the Software, and to 10224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * permit persons to whom the Software is furnished to do so, subject to 11224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the following conditions: 12224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 13224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The above copyright notice and this permission notice (including the 14224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * next paragraph) shall be included in all copies or substantial portions 15224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * of the Software. 16224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 17224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 25224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 26224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 27224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#ifndef _UAPI_I915_DRM_H_ 28224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define _UAPI_I915_DRM_H_ 29224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 30ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#include "drm.h" 31ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris 32ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#if defined(__cplusplus) 33ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferrisextern "C" { 34ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#endif 35224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 36224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Please note that modifications to all structs defined here are 37224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * subject to backwards-compatibility constraints. 38224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 39224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 40e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris/** 41e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * DOC: uevents generated by i915 on it's device node 42e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 43e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 44e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * event from the gpu l3 cache. Additional information supplied is ROW, 45e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 46e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * track of these events and if a specific cache-line seems to have a 47e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * persistent error remap it with the l3 remapping tool supplied in 48e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * intel-gpu-tools. The value supplied with the event is always 1. 49e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 50e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_ERROR_UEVENT - Generated upon error detection, currently only via 51e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * hangcheck. The error detection event is a good indicator of when things 52e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * began to go badly. The value supplied with the event is a 1 upon error 53e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * detection, and a 0 upon reset completion, signifying no more error 54e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * exists. NOTE: Disabling hangcheck or reset via module parameter will 55e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * cause the related events to not be seen. 56e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 57e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 58e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * the GPU. The value supplied with the event is always 1. NOTE: Disable 59e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * reset via module parameter will cause this event to not be seen. 60e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris */ 61e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 62e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_ERROR_UEVENT "ERROR" 63e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_RESET_UEVENT "RESET" 64224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 653318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris/* 663318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * MOCS indexes used for GPU surfaces, defining the cacheability of the 673318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * surface data and the coherency for this data wrt. CPU vs. GPU accesses. 683318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris */ 693318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferrisenum i915_mocs_table_index { 703318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris /* 713318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * Not cached anywhere, coherency between CPU and GPU accesses is 723318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * guaranteed. 733318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris */ 743318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris I915_MOCS_UNCACHED, 753318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris /* 763318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * Cacheability and coherency controlled by the kernel automatically 773318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current 783318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * usage of the surface (used for display scanout or not). 793318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris */ 803318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris I915_MOCS_PTE, 813318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris /* 823318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * Cached in all GPU caches available on the platform. 833318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * Coherency between CPU and GPU accesses to the surface is not 843318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * guaranteed without extra synchronization. 853318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris */ 863318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris I915_MOCS_CACHED, 873318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris}; 883318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris 89224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Each region is a minimum of 16k, and there are at most 255 of them. 90224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 91224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 92224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * of chars for next/prev indices */ 93224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_LOG_MIN_TEX_REGION_SIZE 14 94224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 95224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct _drm_i915_init { 96224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng enum { 97224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng I915_INIT_DMA = 0x01, 98224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng I915_CLEANUP_DMA = 0x02, 99224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng I915_RESUME_DMA = 0x03 100224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } func; 101224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int mmio_offset; 102224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int sarea_priv_offset; 103224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int ring_start; 104224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int ring_end; 105224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int ring_size; 106224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int front_offset; 107224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int back_offset; 108224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int depth_offset; 109224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int w; 110224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int h; 111224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pitch; 112224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pitch_bits; 113224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int back_pitch; 114224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int depth_pitch; 115224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int cpp; 116224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int chipset; 117224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_init_t; 118224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 119224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct _drm_i915_sarea { 120224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 121224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int last_upload; /* last time texture was uploaded */ 122224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int last_enqueue; /* last time a buffer was enqueued */ 123224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int last_dispatch; /* age of the most recently dispatched buffer */ 124224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int ctxOwner; /* last context to upload state */ 125224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int texAge; 126224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pf_enabled; /* is pageflipping allowed? */ 127224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pf_active; 128224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pf_current_page; /* which buffer is being displayed? */ 129224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int perf_boxes; /* performance boxes to be displayed */ 130224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int width, height; /* screen size in pixels */ 131224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 132224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_handle_t front_handle; 133224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int front_offset; 134224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int front_size; 135224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 136224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_handle_t back_handle; 137224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int back_offset; 138224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int back_size; 139224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 140224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_handle_t depth_handle; 141224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int depth_offset; 142224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int depth_size; 143224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 144224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_handle_t tex_handle; 145224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int tex_offset; 146224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int tex_size; 147224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int log_tex_granularity; 148224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pitch; 149224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int rotation; /* 0, 90, 180 or 270 */ 150224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int rotated_offset; 151224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int rotated_size; 152224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int rotated_pitch; 153224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int virtualX, virtualY; 154224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 155224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int front_tiled; 156224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int back_tiled; 157224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int depth_tiled; 158224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rotated_tiled; 159224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rotated2_tiled; 160224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 161224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeA_x; 162224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeA_y; 163224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeA_w; 164224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeA_h; 165224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeB_x; 166224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeB_y; 167224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeB_w; 168224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeB_h; 169224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 170224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* fill out some space for old userspace triple buffer */ 171224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_handle_t unused_handle; 172224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 unused1, unused2, unused3; 173224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 174224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* buffer object handles for static buffers. May change 175224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * over the lifetime of the client. 176224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 177224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 front_bo_handle; 178224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 back_bo_handle; 179224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 unused_bo_handle; 180224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 depth_bo_handle; 181224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 182224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_sarea_t; 183224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 184224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* due to userspace building against these headers we need some compat here */ 185224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeA_x pipeA_x 186224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeA_y pipeA_y 187224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeA_w pipeA_w 188224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeA_h pipeA_h 189224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeB_x pipeB_x 190224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeB_y pipeB_y 191224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeB_w pipeB_w 192224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeB_h pipeB_h 193224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 194224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Flags for perf_boxes 195224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 196224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BOX_RING_EMPTY 0x1 197224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BOX_FLIP 0x2 198224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BOX_WAIT 0x4 199224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BOX_TEXTURE_LOAD 0x8 200224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BOX_LOST_CONTEXT 0x10 201224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 20212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* 20312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * i915 specific ioctls. 20412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 20512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 20612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 20712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 208224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 209224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_INIT 0x00 210224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_FLUSH 0x01 211224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_FLIP 0x02 212224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_BATCHBUFFER 0x03 213224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_IRQ_EMIT 0x04 214224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_IRQ_WAIT 0x05 215224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GETPARAM 0x06 216224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_SETPARAM 0x07 217224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_ALLOC 0x08 218224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_FREE 0x09 219224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_INIT_HEAP 0x0a 220224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_CMDBUFFER 0x0b 221224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_DESTROY_HEAP 0x0c 222224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_SET_VBLANK_PIPE 0x0d 223224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GET_VBLANK_PIPE 0x0e 224224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_VBLANK_SWAP 0x0f 225224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_HWS_ADDR 0x11 226224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_INIT 0x13 227224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_EXECBUFFER 0x14 228224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_PIN 0x15 229224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_UNPIN 0x16 230224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_BUSY 0x17 231224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_THROTTLE 0x18 232224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_ENTERVT 0x19 233224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_LEAVEVT 0x1a 234224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_CREATE 0x1b 235224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_PREAD 0x1c 236224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_PWRITE 0x1d 237224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_MMAP 0x1e 238224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_SET_DOMAIN 0x1f 239224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_SW_FINISH 0x20 240224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_SET_TILING 0x21 241224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_GET_TILING 0x22 242224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_GET_APERTURE 0x23 243224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_MMAP_GTT 0x24 244224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 245224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_MADVISE 0x26 246224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 247224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_OVERLAY_ATTRS 0x28 248224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_EXECBUFFER2 0x29 2490543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 250224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 251224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 252224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_WAIT 0x2c 253224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 254224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 255224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_SET_CACHING 0x2f 256224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_GET_CACHING 0x30 257224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_REG_READ 0x31 258e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define DRM_I915_GET_RESET_STATS 0x32 259314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris#define DRM_I915_GEM_USERPTR 0x33 26012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 26112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 2620543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define DRM_I915_PERF_OPEN 0x36 26325981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define DRM_I915_PERF_ADD_CONFIG 0x37 26425981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define DRM_I915_PERF_REMOVE_CONFIG 0x38 265224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 266224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 267224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 268224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 269224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 270224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 271224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 272224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 273224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 274224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 275224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 276224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 277224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 278224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 279224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 280224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 281224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 282224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 283224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 284224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 285224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 2860543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 287224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 288224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 289224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 290224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 291224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 292224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 293224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 294224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 295224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 296224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 297224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 298224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 299224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 300224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 301224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 302224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 303224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 304224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 305224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 306224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 307224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 308224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 309224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 31012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 311224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 312224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 313224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 314224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 315e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 316314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 31712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 31812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 3190543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 32025981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) 32125981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) 322224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 323224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Allow drivers to submit batchbuffers directly to hardware, relying 324224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * on the security mechanisms provided by hardware. 325224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 326224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_batchbuffer { 327224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int start; /* agp offset */ 328224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int used; /* nr bytes in use */ 329224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 330224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 331224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int num_cliprects; /* mulitpass with multiple cliprects? */ 332224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 333224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_batchbuffer_t; 334224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 335224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* As above, but pass a pointer to userspace buffer which can be 336224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * validated by the kernel prior to sending to hardware. 337224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 338224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct _drm_i915_cmdbuffer { 339224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng char __user *buf; /* pointer to userspace command buffer */ 340224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int sz; /* nr bytes in buf */ 341224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 342224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 343224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int num_cliprects; /* mulitpass with multiple cliprects? */ 344224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 345224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_cmdbuffer_t; 346224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 347224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Userspace can request & wait on irq's: 348224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 349224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_irq_emit { 350224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int __user *irq_seq; 351224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_irq_emit_t; 352224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 353224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_irq_wait { 354224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int irq_seq; 355224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_irq_wait_t; 356224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 357224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Ioctl to query kernel params: 358224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 359224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_IRQ_ACTIVE 1 360224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_ALLOW_BATCHBUFFER 2 361224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_LAST_DISPATCH 3 362224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_CHIPSET_ID 4 363224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_GEM 5 364224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_NUM_FENCES_AVAIL 6 365224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_OVERLAY 7 366224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_PAGEFLIPPING 8 367224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_EXECBUF2 9 368224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_BSD 10 369224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_BLT 11 370224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_RELAXED_FENCING 12 371224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_COHERENT_RINGS 13 372224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_EXEC_CONSTANTS 14 373224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_RELAXED_DELTA 15 374224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_GEN7_SOL_RESET 16 375224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_LLC 17 376224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_ALIASING_PPGTT 18 377224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_WAIT_TIMEOUT 19 378224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_SEMAPHORES 20 379224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 380e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_PARAM_HAS_VEBOX 22 381224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_SECURE_BATCHES 23 382224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_PINNED_BATCHES 24 383224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_EXEC_NO_RELOC 25 384224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 385e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_PARAM_HAS_WT 27 386314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris#define I915_PARAM_CMD_PARSER_VERSION 28 38712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 38812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_MMAP_VERSION 30 38912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_HAS_BSD2 31 39012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_REVISION 32 39112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_SUBSLICE_TOTAL 33 39212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_EU_TOTAL 34 39312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_HAS_GPU_RESET 35 39412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_HAS_RESOURCE_STREAMER 36 395ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_PARAM_HAS_EXEC_SOFTPIN 37 3966e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris#define I915_PARAM_HAS_POOLED_EU 38 3976e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris#define I915_PARAM_MIN_EU_IN_POOL 39 3983318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define I915_PARAM_MMAP_GTT_VERSION 40 399224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 400a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris/* 401a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution 4022fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris * priorities and the driver will attempt to execute batches in priority order. 403a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris * The param returns a capability bitmask, nonzero implies that the scheduler 404a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris * is enabled, with different features present according to the mask. 405a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris * 406a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris * The initial priority for each batch is supplied by the context and is 407a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris * controlled via I915_CONTEXT_PARAM_PRIORITY. 4082fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris */ 4092fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris#define I915_PARAM_HAS_SCHEDULER 41 410a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris#define I915_SCHEDULER_CAP_ENABLED (1ul << 0) 411a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) 412a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) 413a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris 4140543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PARAM_HUC_STATUS 42 4150543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 4160543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of 4170543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * synchronisation with implicit fencing on individual objects. 4180543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * See EXEC_OBJECT_ASYNC. 4190543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 4200543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PARAM_HAS_EXEC_ASYNC 43 4210543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 4220543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support - 4230543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * both being able to pass in a sync_file fd to wait upon before executing, 4240543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * and being able to return a new sync_file fd that is signaled when the 4250543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT. 4260543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 4270543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PARAM_HAS_EXEC_FENCE 44 4282fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris 42925981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture 43025981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * user specified bufffers for post-mortem debugging of GPU hangs. See 43125981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * EXEC_OBJECT_CAPTURE. 43225981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris */ 43325981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define I915_PARAM_HAS_EXEC_CAPTURE 45 43425981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris 43525981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define I915_PARAM_SLICE_MASK 46 43625981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris 43725981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris/* Assuming it's uniform for each slice, this queries the mask of subslices 43825981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * per-slice for this system. 43925981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris */ 44025981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define I915_PARAM_SUBSLICE_MASK 47 44125981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris 44225981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris/* 44325981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer 44425981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST. 44525981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris */ 44625981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 44725981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris 44825981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of 44925981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY. 45025981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris */ 45125981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 45225981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris 453224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_getparam { 45412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris __s32 param; 45512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* 45612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * WARNING: Using pointers instead of fixed-size u64 means we need to write 45712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * compat32 code. Don't repeat this mistake. 45812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 459224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int __user *value; 460224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_getparam_t; 461224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 462224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Ioctl to set kernel params: 463224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 464224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 465224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 466224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 467224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SETPARAM_NUM_USED_FENCES 4 468224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 469224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_setparam { 470224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int param; 471224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int value; 472224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_setparam_t; 473224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 474224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* A memory manager for regions of shared memory: 475224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 476224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_MEM_REGION_AGP 1 477224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 478224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_mem_alloc { 479224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region; 480224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int alignment; 481224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int size; 482224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int __user *region_offset; /* offset from start of fb or agp */ 483224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_mem_alloc_t; 484224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 485224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_mem_free { 486224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region; 487224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region_offset; 488224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_mem_free_t; 489224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 490224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_mem_init_heap { 491224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region; 492224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int size; 493224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int start; 494224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_mem_init_heap_t; 495224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 496224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Allow memory manager to be torn down and re-initialized (eg on 497224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * rotate): 498224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 499224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_mem_destroy_heap { 500224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region; 501224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_mem_destroy_heap_t; 502224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 503224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Allow X server to configure which pipes to monitor for vblank signals 504224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 505224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_VBLANK_PIPE_A 1 506224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_VBLANK_PIPE_B 2 507224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 508224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_vblank_pipe { 509224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipe; 510224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_vblank_pipe_t; 511224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 512224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Schedule buffer swap at given vertical blank: 513224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 514224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_vblank_swap { 515224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_drawable_t drawable; 516224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng enum drm_vblank_seq_type seqtype; 517224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int sequence; 518224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_vblank_swap_t; 519224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 520224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_hws_addr { 521224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 addr; 522224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_hws_addr_t; 523224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 524224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_init { 525224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 526224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Beginning offset in the GTT to be managed by the DRM memory 527224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * manager. 528224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 529224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 gtt_start; 530224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 531224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Ending offset in the GTT to be managed by the DRM memory 532224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * manager. 533224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 534224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 gtt_end; 535224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 536224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 537224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_create { 538224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 539224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Requested size for the object. 540224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 541224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The (page-aligned) allocated size for the object will be returned. 542224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 543224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 size; 544224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 545224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned handle for the object. 546224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 547224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Object handles are nonzero. 548224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 549224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 550224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 551224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 552224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 553224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_pread { 554224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object being read. */ 555224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 556224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 557224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset into the object to read from */ 558224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 559224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Length of data to read */ 560224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 size; 561224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 562224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Pointer to write the data into. 563224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 564224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This is a fixed-size type for 32/64 compatibility. 565224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 566224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 data_ptr; 567224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 568224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 569224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_pwrite { 570224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object being written to. */ 571224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 572224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 573224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset into the object to write to */ 574224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 575224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Length of data to write */ 576224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 size; 577224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 578224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Pointer to read the data from. 579224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 580224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This is a fixed-size type for 32/64 compatibility. 581224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 582224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 data_ptr; 583224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 584224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 585224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_mmap { 586224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object being mapped. */ 587224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 588224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 589224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset in the object to map. */ 590224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 591224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 592224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Length of data to map. 593224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 594224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The value will be page-aligned. 595224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 596224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 size; 597224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 598224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned pointer the data was mapped at. 599224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 600224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This is a fixed-size type for 32/64 compatibility. 601224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 602224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 addr_ptr; 60312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 60412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** 60512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Flags for extended behaviour. 60612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 60712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Added in version 2. 60812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 60912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris __u64 flags; 61012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_MMAP_WC 0x1 611224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 612224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 613224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_mmap_gtt { 614224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object being mapped. */ 615224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 616224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 617224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 618224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Fake offset to use for subsequent mmap call 619224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 620224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This is a fixed-size type for 32/64 compatibility. 621224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 622224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 623224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 624224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 625224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_set_domain { 626224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object */ 627224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 628224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 629224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** New read domains */ 630224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 read_domains; 631224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 632224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** New write domain */ 633224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 write_domain; 634224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 635224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 636224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_sw_finish { 637224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object */ 638224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 639224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 640224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 641224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_relocation_entry { 642224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 643224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Handle of the buffer being pointed to by this relocation entry. 644224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 645224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * It's appealing to make this be an index into the mm_validate_entry 646224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * list to refer to the buffer, but this allows the driver to create 647224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * a relocation list for state buffers and not re-write it per 648224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * exec using the buffer. 649224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 650224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 target_handle; 651224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 652224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 653224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Value to be added to the offset of the target buffer to make up 654224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the relocation entry. 655224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 656224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 delta; 657224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 658224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset in the buffer the relocation entry will be written into */ 659224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 660224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 661224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 662224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Offset value of the target buffer that the relocation entry was last 663224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * written as. 664224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 665224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * If the buffer has the same offset as last time, we can skip syncing 666224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * and writing the relocation. This value is written back out by 667224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the execbuffer ioctl when the relocation is written. 668224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 669224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 presumed_offset; 670224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 671224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 672224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Target memory domains read by this operation. 673224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 674224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 read_domains; 675224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 676224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 677224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Target memory domains written by this operation. 678224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 679224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Note that only one domain may be written by the whole 680224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * execbuffer operation, so that where there are conflicts, 681224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the application will get -EINVAL back. 682224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 683224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 write_domain; 684224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 685224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 686224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** @{ 687224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Intel memory domains 688224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 689224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Most of these just align with the various caches in 690224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the system and are used to flush and invalidate as 691224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * objects end up cached in different domains. 692224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 693224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** CPU cache */ 694224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_CPU 0x00000001 695224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Render cache, used by 2D and 3D drawing */ 696224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_RENDER 0x00000002 697224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Sampler cache, used by texture engine */ 698224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_SAMPLER 0x00000004 699224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Command queue, used to load batch buffers */ 700224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_COMMAND 0x00000008 701224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Instruction cache, used by shader programs */ 702224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 703224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Vertex address cache */ 704224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_VERTEX 0x00000020 705224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** GTT domain - aperture and scanout */ 706224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_GTT 0x00000040 70725981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris/** WC domain - uncached access */ 70825981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define I915_GEM_DOMAIN_WC 0x00000080 709224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** @} */ 710224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 711224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_exec_object { 712224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 713224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * User's handle for a buffer to be bound into the GTT for this 714224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * operation. 715224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 716224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 717224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 718224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Number of relocations to be performed on this buffer */ 719224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 relocation_count; 720224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 721224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Pointer to array of struct drm_i915_gem_relocation_entry containing 722224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the relocations to be performed in this buffer. 723224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 724224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 relocs_ptr; 725224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 726224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Required alignment in graphics aperture */ 727224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 alignment; 728224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 729224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 730224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned value of the updated offset of the object, for future 731224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * presumed_offset writes. 732224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 733224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 734224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 735224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 736224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_execbuffer { 737224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 738224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * List of buffers to be validated with their relocations to be 739224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * performend on them. 740224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 741224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This is a pointer to an array of struct drm_i915_gem_validate_entry. 742224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 743224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * These buffers must be listed in an order such that all relocations 744224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * a buffer is performing refer to buffers that have already appeared 745224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * in the validate list. 746224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 747224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 buffers_ptr; 748224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 buffer_count; 749224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 750224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset in the batchbuffer to start execution from. */ 751224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 batch_start_offset; 752224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Bytes used in batchbuffer from batch_start_offset */ 753224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 batch_len; 754224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 DR1; 755224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 DR4; 756224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 num_cliprects; 757224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** This is a struct drm_clip_rect *cliprects */ 758224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 cliprects_ptr; 759224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 760224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 761224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_exec_object2 { 762224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 763224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * User's handle for a buffer to be bound into the GTT for this 764224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * operation. 765224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 766224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 767224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 768224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Number of relocations to be performed on this buffer */ 769224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 relocation_count; 770224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 771224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Pointer to array of struct drm_i915_gem_relocation_entry containing 772224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the relocations to be performed in this buffer. 773224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 774224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 relocs_ptr; 775224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 776224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Required alignment in graphics aperture */ 777224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 alignment; 778224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 779224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 780ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * When the EXEC_OBJECT_PINNED flag is specified this is populated by 781ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * the user with the GTT offset at which this object will be pinned. 782ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * When the I915_EXEC_NO_RELOC flag is specified this must contain the 783ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * presumed_offset of the object. 784ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * During execbuffer2 the kernel populates it with the value of the 785ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * current GTT offset of the object, for future presumed_offset writes. 786224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 787224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 788224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 7893318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define EXEC_OBJECT_NEEDS_FENCE (1<<0) 7903318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define EXEC_OBJECT_NEEDS_GTT (1<<1) 7913318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define EXEC_OBJECT_WRITE (1<<2) 79212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 7933318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define EXEC_OBJECT_PINNED (1<<4) 7943318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define EXEC_OBJECT_PAD_TO_SIZE (1<<5) 7950543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/* The kernel implicitly tracks GPU activity on all GEM objects, and 7960543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * synchronises operations with outstanding rendering. This includes 7970543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * rendering on other devices if exported via dma-buf. However, sometimes 7980543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * this tracking is too coarse and the user knows better. For example, 7990543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * if the object is split into non-overlapping ranges shared between different 8000543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * clients or engines (i.e. suballocating objects), the implicit tracking 8010543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * by kernel assumes that each operation affects the whole object rather 8020543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * than an individual range, causing needless synchronisation between clients. 8030543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * The kernel will also forgo any CPU cache flushes prior to rendering from 8040543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * the object as the client is expected to be also handling such domain 8050543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * tracking. 8060543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 8070543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * The kernel maintains the implicit tracking in order to manage resources 8080543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * used by the GPU - this flag only disables the synchronisation prior to 8090543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * rendering with this object in this execbuf. 8100543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 8110543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Opting out of implicit synhronisation requires the user to do its own 8120543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * explicit tracking to avoid rendering corruption. See, for example, 8130543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. 8140543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 8150543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define EXEC_OBJECT_ASYNC (1<<6) 81625981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris/* Request that the contents of this execobject be copied into the error 81725981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * state upon a GPU hang involving this batch for post-mortem debugging. 81825981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * These buffers are recorded in no particular order as "user" in 81925981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see 82025981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * if the kernel supports this flag. 82125981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris */ 82225981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define EXEC_OBJECT_CAPTURE (1<<7) 8233318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ 82425981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1) 825224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 flags; 826224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 8273318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris union { 8283318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris __u64 rsvd1; 8293318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris __u64 pad_to_size; 8303318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris }; 831224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 rsvd2; 832224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 833224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 83425981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferrisstruct drm_i915_gem_exec_fence { 83525981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris /** 83625981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * User's handle for a drm_syncobj to wait on or signal. 83725981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris */ 83825981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris __u32 handle; 83925981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris 84025981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define I915_EXEC_FENCE_WAIT (1<<0) 84125981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define I915_EXEC_FENCE_SIGNAL (1<<1) 84225981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)) 84325981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris __u32 flags; 84425981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris}; 84525981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris 846224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_execbuffer2 { 847224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 848224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * List of gem_exec_object2 structs 849224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 850224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 buffers_ptr; 851224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 buffer_count; 852224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 853224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset in the batchbuffer to start execution from. */ 854224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 batch_start_offset; 855224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Bytes used in batchbuffer from batch_start_offset */ 856224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 batch_len; 857224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 DR1; 858224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 DR4; 859224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 num_cliprects; 86025981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris /** 86125981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY 86225981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a 86325981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * struct drm_i915_gem_exec_fence *fences. 86425981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris */ 865224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 cliprects_ptr; 866224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_RING_MASK (7<<0) 867224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_DEFAULT (0<<0) 868224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_RENDER (1<<0) 869224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_BSD (2<<0) 870224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_BLT (3<<0) 871e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_EXEC_VEBOX (4<<0) 872224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 873224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Used for switching the constants addressing mode on gen4+ RENDER ring. 874224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Gen6+ only supports relative addressing to dynamic state (default) and 875224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * absolute addressing. 876224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 877224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * These flags are ignored for the BSD and BLT rings. 878224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 879224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_CONSTANTS_MASK (3<<6) 880224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 881224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 882224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 883224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 flags; 884224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 rsvd1; /* now used for context info */ 885224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 rsvd2; 886224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 887224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 888224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Resets the SO write offset registers for transform feedback on gen7. */ 889224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_GEN7_SOL_RESET (1<<8) 890224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 891224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Request a privileged ("secure") batch buffer. Note only available for 892224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * DRM_ROOT_ONLY | DRM_MASTER processes. 893224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 894224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_SECURE (1<<9) 895224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 896224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Inform the kernel that the batch is and will always be pinned. This 897224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * negates the requirement for a workaround to be performed to avoid 898224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * an incoherent CS (such as can be found on 830/845). If this flag is 899224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * not passed, the kernel will endeavour to make sure the batch is 900224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * coherent with the CS before execution. If this flag is passed, 901224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * userspace assumes the responsibility for ensuring the same. 902224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 903224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_IS_PINNED (1<<10) 904224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 905e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris/** Provide a hint to the kernel that the command stream and auxiliary 906224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * state buffers already holds the correct presumed addresses and so the 907224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * relocation process may be skipped if no buffers need to be moved in 908224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * preparation for the execbuffer. 909224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 910224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_NO_RELOC (1<<11) 911224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 912224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Use the reloc.handle as an index into the exec object array rather 913224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * than as the per-file handle. 914224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 915224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_HANDLE_LUT (1<<12) 916224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 91712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/** Used for switching BSD rings on the platforms with two BSD rings */ 918ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_EXEC_BSD_SHIFT (13) 919ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 920ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris/* default ping-pong mode */ 921ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 922ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 923ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 92412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 92512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/** Tell the kernel that the batchbuffer is processed by 92612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * the resource streamer. 92712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 92812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_EXEC_RESOURCE_STREAMER (1<<15) 92912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 9300543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent 9310543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * a sync_file fd to wait upon (in a nonblocking manner) prior to executing 9320543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * the batch. 9330543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 9340543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Returns -EINVAL if the sync_file fd cannot be found. 9350543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 9360543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_EXEC_FENCE_IN (1<<16) 9370543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 9380543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd 9390543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given 9400543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * to the caller, and it should be close() after use. (The fd is a regular 9410543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * file descriptor and will be cleaned up on process termination. It holds 9420543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * a reference to the request, but nothing else.) 9430543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 9440543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * The sync_file fd can be combined with other sync_file and passed either 9450543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip 9460543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * will only occur after this request completes), or to other devices. 9470543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 9480543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Using I915_EXEC_FENCE_OUT requires use of 9490543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written 9500543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * back to userspace. Failure to do so will cause the out-fence to always 9510543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * be reported as zero, and the real fence fd to be leaked. 9520543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 9530543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_EXEC_FENCE_OUT (1<<17) 9540543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 95525981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris/* 95625981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * Traditionally the execbuf ioctl has only considered the final element in 95725981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * the execobject[] to be the executable batch. Often though, the client 95825981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * will known the batch object prior to construction and being able to place 95925981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * it into the execobject[] array first can simplify the relocation tracking. 96025981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the 96125981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * execobject[] as the * batch instead (the default is to use the last 96225981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * element). 96325981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris */ 96425981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define I915_EXEC_BATCH_FIRST (1<<18) 96525981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris 96625981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris/* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr 96725981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * define an array of i915_gem_exec_fence structures which specify a set of 96825981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * dma fences to wait upon or signal. 96925981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris */ 97025981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define I915_EXEC_FENCE_ARRAY (1<<19) 97125981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris 97225981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1)) 973224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 974224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 975224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define i915_execbuffer2_set_context_id(eb2, context) \ 976224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 977224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define i915_execbuffer2_get_context_id(eb2) \ 978224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 979224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 980224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_pin { 981224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to be pinned. */ 982224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 983224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 984224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 985224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** alignment required within the aperture */ 986224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 alignment; 987224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 988224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Returned GTT offset of the buffer. */ 989224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 990224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 991224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 992224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_unpin { 993224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to be unpinned. */ 994224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 995224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 996224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 997224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 998224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_busy { 999224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to check for busy */ 1000224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 1001224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1002ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris /** Return busy status 1003ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * 1004ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * A return of 0 implies that the object is idle (after 1005ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * having flushed any pending activity), and a non-zero return that 1006ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * the object is still in-flight on the GPU. (The GPU has not yet 1007ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * signaled completion for all pending requests that reference the 10083318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * object.) An object is guaranteed to become idle eventually (so 10093318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * long as no new GPU commands are executed upon it). Due to the 10103318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * asynchronous nature of the hardware, an object reported 10113318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * as busy may become idle before the ioctl is completed. 10123318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * 10133318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * Furthermore, if the object is busy, which engine is busy is only 10143318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * provided as a guide. There are race conditions which prevent the 10153318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * report of which engines are busy from being always accurate. 10163318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * However, the converse is not true. If the object is idle, the 10173318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * result of the ioctl, that all engines are idle, is accurate. 1018ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * 1019ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * The returned dword is split into two fields to indicate both 1020ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * the engines on which the object is being read, and the 1021ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * engine on which it is currently being written (if any). 1022ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * 1023ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * The low word (bits 0:15) indicate if the object is being written 1024ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * to by any engine (there can only be one, as the GEM implicit 1025ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * synchronisation rules force writes to be serialised). Only the 1026ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * engine for the last write is reported. 1027ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * 1028ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * The high word (bits 16:31) are a bitmask of which engines are 1029ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * currently reading from the object. Multiple engines may be 1030ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * reading from the object simultaneously. 1031ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * 1032ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * The value of each engine is the same as specified in the 1033ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc. 1034ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to 1035ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * the I915_EXEC_RENDER engine for execution, and so it is never 1036ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * reported as active itself. Some hardware may have parallel 1037ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * execution engines, e.g. multiple media engines, which are 1038ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * mapped to the same identifier in the EXECBUFFER2 ioctl and 1039ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * so are not separately reported for busyness. 10403318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * 10413318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * Caveat emptor: 10423318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * Only the boolean result of this query is reliable; that is whether 10433318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * the object is idle or busy. The report of which engines are busy 10443318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * should be only used as a heuristic. 1045224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1046224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 busy; 1047224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1048224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1049e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris/** 1050e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_CACHING_NONE 1051e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 1052e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * GPU access is not coherent with cpu caches. Default for machines without an 1053e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * LLC. 1054e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris */ 1055224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_CACHING_NONE 0 1056e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris/** 1057e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_CACHING_CACHED 1058e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 1059e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * GPU access is coherent with cpu caches and furthermore the data is cached in 1060e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * last-level caches shared between cpu cores and the gpu GT. Default on 1061e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * machines with HAS_LLC. 1062e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris */ 1063224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_CACHING_CACHED 1 1064e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris/** 1065e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_CACHING_DISPLAY 1066e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 1067e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * Special GPU caching mode which is coherent with the scanout engines. 1068e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * Transparently falls back to I915_CACHING_NONE on platforms where no special 1069e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * cache mode (like write-through or gfdt flushing) is available. The kernel 1070e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * automatically sets this mode when using a buffer as a scanout target. 1071e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * Userspace can manually set this mode to avoid a costly stall and clflush in 1072e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * the hotpath of drawing the first frame. 1073e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris */ 1074e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_CACHING_DISPLAY 2 1075224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1076224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_caching { 1077224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 1078224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Handle of the buffer to set/get the caching level of. */ 1079224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 1080224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1081224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 1082224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Cacheing level to apply or return value 1083224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1084224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * bits0-15 are for generic caching control (i.e. the above defined 1085224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * values). bits16-31 are reserved for platform-specific variations 1086224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * (e.g. l3$ caching on gen7). */ 1087224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 caching; 1088224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1089224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1090224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_TILING_NONE 0 1091224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_TILING_X 1 1092224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_TILING_Y 2 10933318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define I915_TILING_LAST I915_TILING_Y 1094224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1095224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_NONE 0 1096224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9 1 1097224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9_10 2 1098224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9_11 3 1099224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9_10_11 4 1100224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Not seen by userland */ 1101224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_UNKNOWN 5 1102224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Seen by userland. */ 1103224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9_17 6 1104224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9_10_17 7 1105224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1106224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_set_tiling { 1107224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to have its tiling state updated */ 1108224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 1109224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1110224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 1111224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1112224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * I915_TILING_Y). 1113224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1114224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This value is to be set on request, and will be updated by the 1115224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * kernel on successful return with the actual chosen tiling layout. 1116224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1117224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The tiling mode may be demoted to I915_TILING_NONE when the system 1118224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * has bit 6 swizzling that can't be managed correctly by GEM. 1119224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1120224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Buffer contents become undefined when changing tiling_mode. 1121224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1122224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 tiling_mode; 1123224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1124224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 1125224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Stride in bytes for the object when in I915_TILING_X or 1126224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * I915_TILING_Y. 1127224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1128224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 stride; 1129224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1130224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 1131224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned address bit 6 swizzling required for CPU access through 1132224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * mmap mapping. 1133224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1134224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 swizzle_mode; 1135224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1136224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1137224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_get_tiling { 1138224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to get tiling state for. */ 1139224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 1140224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1141224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 1142224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1143224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * I915_TILING_Y). 1144224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1145224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 tiling_mode; 1146224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1147224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 1148224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned address bit 6 swizzling required for CPU access through 1149224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * mmap mapping. 1150224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1151224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 swizzle_mode; 115212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 115312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** 115412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Returned address bit 6 swizzling required for CPU access through 115512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * mmap mapping whilst bound. 115612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 115712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris __u32 phys_swizzle_mode; 1158224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1159224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1160224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_get_aperture { 1161224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 1162224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 aper_size; 1163224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1164224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 1165224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Available space in the aperture used by i915_gem_execbuffer, in 1166224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * bytes 1167224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1168224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 aper_available_size; 1169224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1170224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1171224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_get_pipe_from_crtc_id { 1172224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** ID of CRTC being requested **/ 1173224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 crtc_id; 1174224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1175224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** pipe of requested CRTC **/ 1176224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pipe; 1177224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1178224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1179224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_MADV_WILLNEED 0 1180224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_MADV_DONTNEED 1 1181224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define __I915_MADV_PURGED 2 /* internal state */ 1182224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1183224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_madvise { 1184224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to change the backing store advice */ 1185224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 1186224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1187224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Advice: either the buffer will be needed again in the near future, 1188224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * or wont be and could be discarded under memory pressure. 1189224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1190224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 madv; 1191224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1192224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Whether the backing store still exists. */ 1193224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 retained; 1194224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1195224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1196224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* flags */ 1197224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_TYPE_MASK 0xff 1198224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV_PLANAR 0x01 1199224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV_PACKED 0x02 1200224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_RGB 0x03 1201224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1202224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_DEPTH_MASK 0xff00 1203224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_RGB24 0x1000 1204224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_RGB16 0x2000 1205224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_RGB15 0x3000 1206224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV422 0x0100 1207224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV411 0x0200 1208224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV420 0x0300 1209224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV410 0x0400 1210224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1211224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_SWAP_MASK 0xff0000 1212224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_NO_SWAP 0x000000 1213224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_UV_SWAP 0x010000 1214224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_Y_SWAP 0x020000 1215224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 1216224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1217224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_FLAGS_MASK 0xff000000 1218224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_ENABLE 0x01000000 1219224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1220224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_intel_overlay_put_image { 1221224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* various flags and src format description */ 1222224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 flags; 1223224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* source picture description */ 1224224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 bo_handle; 1225224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* stride values and offsets are in bytes, buffer relative */ 1226224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 stride_Y; /* stride for packed formats */ 1227224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 stride_UV; 1228224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 offset_Y; /* offset for packet formats */ 1229224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 offset_U; 1230224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 offset_V; 1231224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* in pixels */ 1232224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 src_width; 1233224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 src_height; 1234224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* to compensate the scaling factors for partially covered surfaces */ 1235224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 src_scan_width; 1236224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 src_scan_height; 1237224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* output crtc description */ 1238224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 crtc_id; 1239224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 dst_x; 1240224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 dst_y; 1241224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 dst_width; 1242224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 dst_height; 1243224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1244224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1245224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* flags */ 1246224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_UPDATE_ATTRS (1<<0) 1247224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_UPDATE_GAMMA (1<<1) 124812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) 1249224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_intel_overlay_attrs { 1250224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 flags; 1251224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 color_key; 1252224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __s32 brightness; 1253224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 contrast; 1254224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 saturation; 1255224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma0; 1256224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma1; 1257224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma2; 1258224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma3; 1259224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma4; 1260224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma5; 1261224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1262224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1263224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 1264224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Intel sprite handling 1265224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1266224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Color keying works with a min/mask/max tuple. Both source and destination 1267224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * color keying is allowed. 1268224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1269224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Source keying: 1270224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Sprite pixels within the min & max values, masked against the color channels 1271224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * specified in the mask field, will be transparent. All other pixels will 1272224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * be displayed on top of the primary plane. For RGB surfaces, only the min 1273224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * and mask fields will be used; ranged compares are not allowed. 1274224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1275224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Destination keying: 1276224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Primary plane pixels that match the min value, masked against the color 1277224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * channels specified in the mask field, will be replaced by corresponding 1278224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * pixels from the sprite plane. 1279224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1280224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Note that source & destination keying are exclusive; only one can be 1281224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * active on a given plane. 1282224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1283224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1284224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 1285224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SET_COLORKEY_DESTINATION (1<<1) 1286224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SET_COLORKEY_SOURCE (1<<2) 1287224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_intel_sprite_colorkey { 1288224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 plane_id; 1289224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 min_value; 1290224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 channel_mask; 1291224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 max_value; 1292224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 flags; 1293224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1294224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1295224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_wait { 1296224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of BO we shall wait on */ 1297224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 bo_handle; 1298224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 flags; 1299224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Number of nanoseconds to wait, Returns time remaining. */ 1300224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __s64 timeout_ns; 1301224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1302224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1303224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_context_create { 1304224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* output: id of new context*/ 1305224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 ctx_id; 1306224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 1307224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1308224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1309224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_context_destroy { 1310224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 ctx_id; 1311224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 1312224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1313224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1314224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_reg_read { 1315ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris /* 1316ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * Register offset. 1317ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * For 64bit wide registers where the upper 32bits don't immediately 1318ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * follow the lower 32bits, the offset of the lower 32bits must 1319ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * be specified 1320ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris */ 1321224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 1322a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris#define I915_REG_READ_8B_WA (1ul << 0) 1323a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris 1324224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 val; /* Return value */ 1325224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 132612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Known registers: 132712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 132812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Render engine timestamp - 0x2358 + 64bit - gen7+ 132912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * - Note this register returns an invalid value if using the default 1330a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris * single instruction 8byte read, in order to workaround that pass 1331a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris * flag I915_REG_READ_8B_WA in offset field. 133212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 133312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 1334e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1335e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferrisstruct drm_i915_reset_stats { 1336e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 ctx_id; 1337e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 flags; 1338e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1339e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris /* All resets since boot/module reload, for all contexts */ 1340e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 reset_count; 1341e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1342e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris /* Number of batches lost when active in GPU, for this context */ 1343e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 batch_active; 1344e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1345e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris /* Number of batches lost pending for execution, for this context */ 1346e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 batch_pending; 1347e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1348e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 pad; 1349e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris}; 1350e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1351314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferrisstruct drm_i915_gem_userptr { 1352314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris __u64 user_ptr; 1353314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris __u64 user_size; 1354314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris __u32 flags; 1355314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris#define I915_USERPTR_READ_ONLY 0x1 1356314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris#define I915_USERPTR_UNSYNCHRONIZED 0x80000000 1357314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris /** 1358314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris * Returned handle for the object. 1359314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris * 1360314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris * Object handles are nonzero. 1361314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris */ 1362314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris __u32 handle; 1363314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris}; 1364314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris 136512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_i915_gem_context_param { 136612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris __u32 ctx_id; 136712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris __u32 size; 136812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris __u64 param; 1369ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 1370ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 1371ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_CONTEXT_PARAM_GTT_SIZE 0x3 13726e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 13730543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_CONTEXT_PARAM_BANNABLE 0x5 1374a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris#define I915_CONTEXT_PARAM_PRIORITY 0x6 1375a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ 1376a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris#define I915_CONTEXT_DEFAULT_PRIORITY 0 1377a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ 137812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris __u64 value; 137912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 138012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 13810543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferrisenum drm_i915_oa_format { 138225981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris I915_OA_FORMAT_A13 = 1, /* HSW only */ 138325981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris I915_OA_FORMAT_A29, /* HSW only */ 138425981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris I915_OA_FORMAT_A13_B8_C8, /* HSW only */ 138525981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris I915_OA_FORMAT_B4_C8, /* HSW only */ 138625981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris I915_OA_FORMAT_A45_B8_C8, /* HSW only */ 138725981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris I915_OA_FORMAT_B4_C8_A16, /* HSW only */ 138825981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris I915_OA_FORMAT_C4_B8, /* HSW+ */ 138925981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris 139025981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris /* Gen8+ */ 139125981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris I915_OA_FORMAT_A12, 139225981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris I915_OA_FORMAT_A12_B8_C8, 139325981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris I915_OA_FORMAT_A32u40_A4u32_B8_C8, 13940543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13950543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris I915_OA_FORMAT_MAX /* non-ABI */ 13960543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris}; 13970543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13980543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferrisenum drm_i915_perf_property_id { 13990543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 14000543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Open the stream for a specific context handle (as used with 14010543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * execbuffer2). A stream opened for a specific context this way 14020543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * won't typically require root privileges. 14030543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 14040543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_PROP_CTX_HANDLE = 1, 14050543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14060543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 14070543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * A value of 1 requests the inclusion of raw OA unit reports as 14080543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * part of stream samples. 14090543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 14100543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_PROP_SAMPLE_OA, 14110543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14120543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 14130543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * The value specifies which set of OA unit metrics should be 14140543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * be configured, defining the contents of any OA unit reports. 14150543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 14160543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_PROP_OA_METRICS_SET, 14170543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14180543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 14190543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * The value specifies the size and layout of OA unit reports. 14200543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 14210543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_PROP_OA_FORMAT, 14220543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14230543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 14240543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Specifying this property implicitly requests periodic OA unit 14250543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * sampling and (at least on Haswell) the sampling frequency is derived 14260543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * from this exponent as follows: 14270543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 14280543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 80ns * 2^(period_exponent + 1) 14290543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 14300543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_PROP_OA_EXPONENT, 14310543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14320543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_PROP_MAX /* non-ABI */ 14330543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris}; 14340543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14350543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferrisstruct drm_i915_perf_open_param { 14360543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris __u32 flags; 14370543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PERF_FLAG_FD_CLOEXEC (1<<0) 14380543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PERF_FLAG_FD_NONBLOCK (1<<1) 14390543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PERF_FLAG_DISABLED (1<<2) 14400543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14410543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** The number of u64 (id, value) pairs */ 14420543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris __u32 num_properties; 14430543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14440543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 14450543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Pointer to array of u64 (id, value) pairs configuring the stream 14460543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * to open. 14470543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 14480543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris __u64 properties_ptr; 14490543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris}; 14500543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14510543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/** 14520543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Enable data capture for a stream that was either opened in a disabled state 14530543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * via I915_PERF_FLAG_DISABLED or was later disabled via 14540543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * I915_PERF_IOCTL_DISABLE. 14550543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 14560543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * It is intended to be cheaper to disable and enable a stream than it may be 14570543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * to close and re-open a stream with the same configuration. 14580543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 14590543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * It's undefined whether any pending data for the stream will be lost. 14600543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 14610543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 14620543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14630543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/** 14640543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Disable data capture for a stream. 14650543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 14660543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * It is an error to try and read a stream that is disabled. 14670543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 14680543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 14690543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14700543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/** 14710543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Common to all i915 perf records 14720543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 14730543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferrisstruct drm_i915_perf_record_header { 14740543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris __u32 type; 14750543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris __u16 pad; 14760543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris __u16 size; 14770543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris}; 14780543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14790543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferrisenum drm_i915_perf_record_type { 14800543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14810543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 14820543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Samples are the work horse record type whose contents are extensible 14830543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * and defined when opening an i915 perf stream based on the given 14840543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * properties. 14850543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 14860543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Boolean properties following the naming convention 14870543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in 14880543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * every sample. 14890543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 14900543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * The order of these sample properties given by userspace has no 14910543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * affect on the ordering of data within a sample. The order is 14920543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * documented here. 14930543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 14940543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * struct { 14950543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * struct drm_i915_perf_record_header header; 14960543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 14970543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA 14980543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * }; 14990543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 15000543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_RECORD_SAMPLE = 1, 15010543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 15020543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /* 15030543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Indicates that one or more OA reports were not written by the 15040543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * hardware. This can happen for example if an MI_REPORT_PERF_COUNT 15050543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * command collides with periodic sampling - which would be more likely 15060543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * at higher sampling frequencies. 15070543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 15080543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 15090543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 15100543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 15110543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * An error occurred that resulted in all pending OA reports being lost. 15120543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 15130543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 15140543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 15150543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_RECORD_MAX /* non-ABI */ 15160543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris}; 15170543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 151825981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris/** 151925981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris * Structure to upload perf dynamic configuration into the kernel. 152025981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris */ 152125981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferrisstruct drm_i915_perf_oa_config { 152225981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris /** String formatted like "%08x-%04x-%04x-%04x-%012x" */ 152325981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris char uuid[36]; 152425981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris 152525981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris __u32 n_mux_regs; 152625981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris __u32 n_boolean_regs; 152725981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris __u32 n_flex_regs; 152825981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris 1529a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris /* 1530a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris * These fields are pointers to tuples of u32 values (register 1531a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris * address, value). For example the expected length of the buffer 1532a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris * pointed by mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs). 1533a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris */ 1534a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris __u64 mux_regs_ptr; 1535a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris __u64 boolean_regs_ptr; 1536a1a109eed086336ef38a07b9f90e3d7c786f850eChristopher Ferris __u64 flex_regs_ptr; 153725981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris}; 153825981136fb13bcacf5f475f3e0ec750341e1e671Christopher Ferris 1539ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#if defined(__cplusplus) 1540ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris} 1541ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#endif 1542ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris 1543224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#endif /* _UAPI_I915_DRM_H_ */ 1544