i915_drm.h revision 0543f743b6f5bc5c0652568c763e6dfb9ddce647
1224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 2224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * All Rights Reserved. 4224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 5224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Permission is hereby granted, free of charge, to any person obtaining a 6224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * copy of this software and associated documentation files (the 7224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * "Software"), to deal in the Software without restriction, including 8224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * without limitation the rights to use, copy, modify, merge, publish, 9224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * distribute, sub license, and/or sell copies of the Software, and to 10224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * permit persons to whom the Software is furnished to do so, subject to 11224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the following conditions: 12224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 13224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The above copyright notice and this permission notice (including the 14224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * next paragraph) shall be included in all copies or substantial portions 15224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * of the Software. 16224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 17224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 25224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 26224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 27224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#ifndef _UAPI_I915_DRM_H_ 28224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define _UAPI_I915_DRM_H_ 29224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 30ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#include "drm.h" 31ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris 32ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#if defined(__cplusplus) 33ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferrisextern "C" { 34ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#endif 35224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 36224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Please note that modifications to all structs defined here are 37224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * subject to backwards-compatibility constraints. 38224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 39224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 40e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris/** 41e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * DOC: uevents generated by i915 on it's device node 42e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 43e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 44e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * event from the gpu l3 cache. Additional information supplied is ROW, 45e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 46e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * track of these events and if a specific cache-line seems to have a 47e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * persistent error remap it with the l3 remapping tool supplied in 48e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * intel-gpu-tools. The value supplied with the event is always 1. 49e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 50e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_ERROR_UEVENT - Generated upon error detection, currently only via 51e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * hangcheck. The error detection event is a good indicator of when things 52e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * began to go badly. The value supplied with the event is a 1 upon error 53e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * detection, and a 0 upon reset completion, signifying no more error 54e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * exists. NOTE: Disabling hangcheck or reset via module parameter will 55e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * cause the related events to not be seen. 56e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 57e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 58e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * the GPU. The value supplied with the event is always 1. NOTE: Disable 59e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * reset via module parameter will cause this event to not be seen. 60e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris */ 61e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 62e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_ERROR_UEVENT "ERROR" 63e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_RESET_UEVENT "RESET" 64224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 653318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris/* 663318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * MOCS indexes used for GPU surfaces, defining the cacheability of the 673318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * surface data and the coherency for this data wrt. CPU vs. GPU accesses. 683318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris */ 693318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferrisenum i915_mocs_table_index { 703318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris /* 713318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * Not cached anywhere, coherency between CPU and GPU accesses is 723318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * guaranteed. 733318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris */ 743318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris I915_MOCS_UNCACHED, 753318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris /* 763318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * Cacheability and coherency controlled by the kernel automatically 773318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current 783318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * usage of the surface (used for display scanout or not). 793318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris */ 803318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris I915_MOCS_PTE, 813318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris /* 823318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * Cached in all GPU caches available on the platform. 833318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * Coherency between CPU and GPU accesses to the surface is not 843318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * guaranteed without extra synchronization. 853318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris */ 863318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris I915_MOCS_CACHED, 873318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris}; 883318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris 89224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Each region is a minimum of 16k, and there are at most 255 of them. 90224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 91224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 92224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * of chars for next/prev indices */ 93224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_LOG_MIN_TEX_REGION_SIZE 14 94224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 95224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct _drm_i915_init { 96224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng enum { 97224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng I915_INIT_DMA = 0x01, 98224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng I915_CLEANUP_DMA = 0x02, 99224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng I915_RESUME_DMA = 0x03 100224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } func; 101224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int mmio_offset; 102224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int sarea_priv_offset; 103224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int ring_start; 104224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int ring_end; 105224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int ring_size; 106224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int front_offset; 107224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int back_offset; 108224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int depth_offset; 109224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int w; 110224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int h; 111224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pitch; 112224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pitch_bits; 113224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int back_pitch; 114224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int depth_pitch; 115224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int cpp; 116224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int chipset; 117224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_init_t; 118224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 119224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct _drm_i915_sarea { 120224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 121224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int last_upload; /* last time texture was uploaded */ 122224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int last_enqueue; /* last time a buffer was enqueued */ 123224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int last_dispatch; /* age of the most recently dispatched buffer */ 124224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int ctxOwner; /* last context to upload state */ 125224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int texAge; 126224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pf_enabled; /* is pageflipping allowed? */ 127224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pf_active; 128224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pf_current_page; /* which buffer is being displayed? */ 129224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int perf_boxes; /* performance boxes to be displayed */ 130224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int width, height; /* screen size in pixels */ 131224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 132224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_handle_t front_handle; 133224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int front_offset; 134224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int front_size; 135224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 136224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_handle_t back_handle; 137224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int back_offset; 138224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int back_size; 139224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 140224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_handle_t depth_handle; 141224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int depth_offset; 142224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int depth_size; 143224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 144224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_handle_t tex_handle; 145224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int tex_offset; 146224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int tex_size; 147224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int log_tex_granularity; 148224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pitch; 149224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int rotation; /* 0, 90, 180 or 270 */ 150224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int rotated_offset; 151224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int rotated_size; 152224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int rotated_pitch; 153224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int virtualX, virtualY; 154224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 155224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int front_tiled; 156224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int back_tiled; 157224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int depth_tiled; 158224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rotated_tiled; 159224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rotated2_tiled; 160224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 161224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeA_x; 162224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeA_y; 163224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeA_w; 164224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeA_h; 165224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeB_x; 166224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeB_y; 167224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeB_w; 168224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeB_h; 169224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 170224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* fill out some space for old userspace triple buffer */ 171224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_handle_t unused_handle; 172224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 unused1, unused2, unused3; 173224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 174224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* buffer object handles for static buffers. May change 175224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * over the lifetime of the client. 176224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 177224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 front_bo_handle; 178224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 back_bo_handle; 179224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 unused_bo_handle; 180224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 depth_bo_handle; 181224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 182224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_sarea_t; 183224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 184224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* due to userspace building against these headers we need some compat here */ 185224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeA_x pipeA_x 186224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeA_y pipeA_y 187224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeA_w pipeA_w 188224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeA_h pipeA_h 189224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeB_x pipeB_x 190224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeB_y pipeB_y 191224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeB_w pipeB_w 192224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeB_h pipeB_h 193224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 194224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Flags for perf_boxes 195224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 196224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BOX_RING_EMPTY 0x1 197224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BOX_FLIP 0x2 198224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BOX_WAIT 0x4 199224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BOX_TEXTURE_LOAD 0x8 200224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BOX_LOST_CONTEXT 0x10 201224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 20212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* 20312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * i915 specific ioctls. 20412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 20512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 20612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 20712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 208224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 209224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_INIT 0x00 210224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_FLUSH 0x01 211224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_FLIP 0x02 212224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_BATCHBUFFER 0x03 213224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_IRQ_EMIT 0x04 214224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_IRQ_WAIT 0x05 215224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GETPARAM 0x06 216224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_SETPARAM 0x07 217224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_ALLOC 0x08 218224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_FREE 0x09 219224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_INIT_HEAP 0x0a 220224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_CMDBUFFER 0x0b 221224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_DESTROY_HEAP 0x0c 222224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_SET_VBLANK_PIPE 0x0d 223224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GET_VBLANK_PIPE 0x0e 224224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_VBLANK_SWAP 0x0f 225224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_HWS_ADDR 0x11 226224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_INIT 0x13 227224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_EXECBUFFER 0x14 228224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_PIN 0x15 229224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_UNPIN 0x16 230224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_BUSY 0x17 231224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_THROTTLE 0x18 232224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_ENTERVT 0x19 233224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_LEAVEVT 0x1a 234224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_CREATE 0x1b 235224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_PREAD 0x1c 236224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_PWRITE 0x1d 237224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_MMAP 0x1e 238224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_SET_DOMAIN 0x1f 239224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_SW_FINISH 0x20 240224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_SET_TILING 0x21 241224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_GET_TILING 0x22 242224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_GET_APERTURE 0x23 243224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_MMAP_GTT 0x24 244224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 245224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_MADVISE 0x26 246224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 247224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_OVERLAY_ATTRS 0x28 248224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_EXECBUFFER2 0x29 2490543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 250224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 251224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 252224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_WAIT 0x2c 253224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 254224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 255224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_SET_CACHING 0x2f 256224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_GET_CACHING 0x30 257224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_REG_READ 0x31 258e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define DRM_I915_GET_RESET_STATS 0x32 259314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris#define DRM_I915_GEM_USERPTR 0x33 26012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 26112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 2620543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define DRM_I915_PERF_OPEN 0x36 263224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 264224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 265224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 266224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 267224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 268224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 269224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 270224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 271224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 272224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 273224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 274224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 275224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 276224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 277224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 278224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 279224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 280224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 281224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 282224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 283224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 2840543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 285224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 286224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 287224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 288224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 289224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 290224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 291224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 292224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 293224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 294224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 295224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 296224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 297224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 298224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 299224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 300224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 301224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 302224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 303224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 304224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 305224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 306224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 307224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 30812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 309224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 310224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 311224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 312224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 313e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 314314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 31512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 31612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 3170543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 318224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 319224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Allow drivers to submit batchbuffers directly to hardware, relying 320224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * on the security mechanisms provided by hardware. 321224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 322224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_batchbuffer { 323224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int start; /* agp offset */ 324224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int used; /* nr bytes in use */ 325224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 326224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 327224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int num_cliprects; /* mulitpass with multiple cliprects? */ 328224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 329224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_batchbuffer_t; 330224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 331224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* As above, but pass a pointer to userspace buffer which can be 332224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * validated by the kernel prior to sending to hardware. 333224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 334224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct _drm_i915_cmdbuffer { 335224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng char __user *buf; /* pointer to userspace command buffer */ 336224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int sz; /* nr bytes in buf */ 337224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 338224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 339224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int num_cliprects; /* mulitpass with multiple cliprects? */ 340224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 341224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_cmdbuffer_t; 342224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 343224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Userspace can request & wait on irq's: 344224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 345224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_irq_emit { 346224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int __user *irq_seq; 347224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_irq_emit_t; 348224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 349224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_irq_wait { 350224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int irq_seq; 351224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_irq_wait_t; 352224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 353224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Ioctl to query kernel params: 354224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 355224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_IRQ_ACTIVE 1 356224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_ALLOW_BATCHBUFFER 2 357224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_LAST_DISPATCH 3 358224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_CHIPSET_ID 4 359224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_GEM 5 360224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_NUM_FENCES_AVAIL 6 361224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_OVERLAY 7 362224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_PAGEFLIPPING 8 363224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_EXECBUF2 9 364224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_BSD 10 365224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_BLT 11 366224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_RELAXED_FENCING 12 367224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_COHERENT_RINGS 13 368224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_EXEC_CONSTANTS 14 369224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_RELAXED_DELTA 15 370224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_GEN7_SOL_RESET 16 371224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_LLC 17 372224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_ALIASING_PPGTT 18 373224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_WAIT_TIMEOUT 19 374224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_SEMAPHORES 20 375224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 376e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_PARAM_HAS_VEBOX 22 377224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_SECURE_BATCHES 23 378224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_PINNED_BATCHES 24 379224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_EXEC_NO_RELOC 25 380224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 381e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_PARAM_HAS_WT 27 382314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris#define I915_PARAM_CMD_PARSER_VERSION 28 38312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 38412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_MMAP_VERSION 30 38512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_HAS_BSD2 31 38612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_REVISION 32 38712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_SUBSLICE_TOTAL 33 38812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_EU_TOTAL 34 38912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_HAS_GPU_RESET 35 39012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_PARAM_HAS_RESOURCE_STREAMER 36 391ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_PARAM_HAS_EXEC_SOFTPIN 37 3926e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris#define I915_PARAM_HAS_POOLED_EU 38 3936e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris#define I915_PARAM_MIN_EU_IN_POOL 39 3943318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define I915_PARAM_MMAP_GTT_VERSION 40 395224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 3962fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution 3972fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris * priorities and the driver will attempt to execute batches in priority order. 3982fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris */ 3992fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris#define I915_PARAM_HAS_SCHEDULER 41 4000543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PARAM_HUC_STATUS 42 4010543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 4020543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of 4030543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * synchronisation with implicit fencing on individual objects. 4040543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * See EXEC_OBJECT_ASYNC. 4050543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 4060543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PARAM_HAS_EXEC_ASYNC 43 4070543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 4080543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support - 4090543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * both being able to pass in a sync_file fd to wait upon before executing, 4100543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * and being able to return a new sync_file fd that is signaled when the 4110543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT. 4120543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 4130543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PARAM_HAS_EXEC_FENCE 44 4142fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris 415224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_getparam { 41612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris __s32 param; 41712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* 41812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * WARNING: Using pointers instead of fixed-size u64 means we need to write 41912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * compat32 code. Don't repeat this mistake. 42012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 421224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int __user *value; 422224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_getparam_t; 423224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 424224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Ioctl to set kernel params: 425224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 426224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 427224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 428224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 429224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SETPARAM_NUM_USED_FENCES 4 430224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 431224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_setparam { 432224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int param; 433224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int value; 434224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_setparam_t; 435224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 436224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* A memory manager for regions of shared memory: 437224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 438224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_MEM_REGION_AGP 1 439224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 440224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_mem_alloc { 441224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region; 442224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int alignment; 443224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int size; 444224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int __user *region_offset; /* offset from start of fb or agp */ 445224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_mem_alloc_t; 446224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 447224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_mem_free { 448224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region; 449224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region_offset; 450224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_mem_free_t; 451224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 452224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_mem_init_heap { 453224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region; 454224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int size; 455224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int start; 456224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_mem_init_heap_t; 457224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 458224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Allow memory manager to be torn down and re-initialized (eg on 459224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * rotate): 460224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 461224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_mem_destroy_heap { 462224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region; 463224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_mem_destroy_heap_t; 464224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 465224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Allow X server to configure which pipes to monitor for vblank signals 466224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 467224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_VBLANK_PIPE_A 1 468224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_VBLANK_PIPE_B 2 469224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 470224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_vblank_pipe { 471224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipe; 472224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_vblank_pipe_t; 473224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 474224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Schedule buffer swap at given vertical blank: 475224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 476224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_vblank_swap { 477224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_drawable_t drawable; 478224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng enum drm_vblank_seq_type seqtype; 479224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int sequence; 480224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_vblank_swap_t; 481224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 482224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_hws_addr { 483224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 addr; 484224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_hws_addr_t; 485224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 486224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_init { 487224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 488224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Beginning offset in the GTT to be managed by the DRM memory 489224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * manager. 490224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 491224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 gtt_start; 492224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 493224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Ending offset in the GTT to be managed by the DRM memory 494224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * manager. 495224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 496224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 gtt_end; 497224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 498224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 499224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_create { 500224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 501224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Requested size for the object. 502224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 503224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The (page-aligned) allocated size for the object will be returned. 504224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 505224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 size; 506224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 507224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned handle for the object. 508224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 509224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Object handles are nonzero. 510224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 511224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 512224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 513224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 514224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 515224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_pread { 516224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object being read. */ 517224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 518224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 519224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset into the object to read from */ 520224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 521224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Length of data to read */ 522224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 size; 523224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 524224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Pointer to write the data into. 525224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 526224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This is a fixed-size type for 32/64 compatibility. 527224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 528224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 data_ptr; 529224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 530224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 531224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_pwrite { 532224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object being written to. */ 533224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 534224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 535224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset into the object to write to */ 536224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 537224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Length of data to write */ 538224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 size; 539224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 540224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Pointer to read the data from. 541224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 542224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This is a fixed-size type for 32/64 compatibility. 543224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 544224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 data_ptr; 545224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 546224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 547224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_mmap { 548224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object being mapped. */ 549224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 550224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 551224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset in the object to map. */ 552224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 553224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 554224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Length of data to map. 555224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 556224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The value will be page-aligned. 557224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 558224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 size; 559224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 560224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned pointer the data was mapped at. 561224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 562224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This is a fixed-size type for 32/64 compatibility. 563224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 564224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 addr_ptr; 56512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 56612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** 56712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Flags for extended behaviour. 56812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 56912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Added in version 2. 57012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 57112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris __u64 flags; 57212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_MMAP_WC 0x1 573224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 574224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 575224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_mmap_gtt { 576224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object being mapped. */ 577224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 578224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 579224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 580224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Fake offset to use for subsequent mmap call 581224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 582224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This is a fixed-size type for 32/64 compatibility. 583224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 584224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 585224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 586224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 587224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_set_domain { 588224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object */ 589224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 590224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 591224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** New read domains */ 592224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 read_domains; 593224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 594224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** New write domain */ 595224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 write_domain; 596224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 597224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 598224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_sw_finish { 599224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object */ 600224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 601224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 602224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 603224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_relocation_entry { 604224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 605224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Handle of the buffer being pointed to by this relocation entry. 606224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 607224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * It's appealing to make this be an index into the mm_validate_entry 608224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * list to refer to the buffer, but this allows the driver to create 609224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * a relocation list for state buffers and not re-write it per 610224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * exec using the buffer. 611224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 612224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 target_handle; 613224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 614224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 615224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Value to be added to the offset of the target buffer to make up 616224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the relocation entry. 617224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 618224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 delta; 619224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 620224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset in the buffer the relocation entry will be written into */ 621224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 622224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 623224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 624224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Offset value of the target buffer that the relocation entry was last 625224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * written as. 626224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 627224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * If the buffer has the same offset as last time, we can skip syncing 628224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * and writing the relocation. This value is written back out by 629224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the execbuffer ioctl when the relocation is written. 630224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 631224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 presumed_offset; 632224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 633224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 634224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Target memory domains read by this operation. 635224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 636224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 read_domains; 637224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 638224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 639224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Target memory domains written by this operation. 640224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 641224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Note that only one domain may be written by the whole 642224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * execbuffer operation, so that where there are conflicts, 643224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the application will get -EINVAL back. 644224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 645224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 write_domain; 646224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 647224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 648224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** @{ 649224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Intel memory domains 650224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 651224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Most of these just align with the various caches in 652224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the system and are used to flush and invalidate as 653224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * objects end up cached in different domains. 654224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 655224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** CPU cache */ 656224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_CPU 0x00000001 657224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Render cache, used by 2D and 3D drawing */ 658224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_RENDER 0x00000002 659224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Sampler cache, used by texture engine */ 660224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_SAMPLER 0x00000004 661224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Command queue, used to load batch buffers */ 662224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_COMMAND 0x00000008 663224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Instruction cache, used by shader programs */ 664224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 665224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Vertex address cache */ 666224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_VERTEX 0x00000020 667224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** GTT domain - aperture and scanout */ 668224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_GTT 0x00000040 669224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** @} */ 670224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 671224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_exec_object { 672224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 673224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * User's handle for a buffer to be bound into the GTT for this 674224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * operation. 675224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 676224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 677224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 678224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Number of relocations to be performed on this buffer */ 679224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 relocation_count; 680224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 681224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Pointer to array of struct drm_i915_gem_relocation_entry containing 682224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the relocations to be performed in this buffer. 683224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 684224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 relocs_ptr; 685224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 686224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Required alignment in graphics aperture */ 687224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 alignment; 688224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 689224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 690224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned value of the updated offset of the object, for future 691224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * presumed_offset writes. 692224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 693224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 694224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 695224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 696224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_execbuffer { 697224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 698224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * List of buffers to be validated with their relocations to be 699224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * performend on them. 700224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 701224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This is a pointer to an array of struct drm_i915_gem_validate_entry. 702224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 703224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * These buffers must be listed in an order such that all relocations 704224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * a buffer is performing refer to buffers that have already appeared 705224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * in the validate list. 706224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 707224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 buffers_ptr; 708224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 buffer_count; 709224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 710224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset in the batchbuffer to start execution from. */ 711224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 batch_start_offset; 712224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Bytes used in batchbuffer from batch_start_offset */ 713224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 batch_len; 714224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 DR1; 715224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 DR4; 716224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 num_cliprects; 717224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** This is a struct drm_clip_rect *cliprects */ 718224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 cliprects_ptr; 719224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 720224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 721224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_exec_object2 { 722224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 723224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * User's handle for a buffer to be bound into the GTT for this 724224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * operation. 725224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 726224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 727224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 728224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Number of relocations to be performed on this buffer */ 729224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 relocation_count; 730224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 731224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Pointer to array of struct drm_i915_gem_relocation_entry containing 732224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the relocations to be performed in this buffer. 733224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 734224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 relocs_ptr; 735224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 736224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Required alignment in graphics aperture */ 737224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 alignment; 738224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 739224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 740ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * When the EXEC_OBJECT_PINNED flag is specified this is populated by 741ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * the user with the GTT offset at which this object will be pinned. 742ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * When the I915_EXEC_NO_RELOC flag is specified this must contain the 743ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * presumed_offset of the object. 744ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * During execbuffer2 the kernel populates it with the value of the 745ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * current GTT offset of the object, for future presumed_offset writes. 746224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 747224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 748224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 7493318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define EXEC_OBJECT_NEEDS_FENCE (1<<0) 7503318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define EXEC_OBJECT_NEEDS_GTT (1<<1) 7513318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define EXEC_OBJECT_WRITE (1<<2) 75212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 7533318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define EXEC_OBJECT_PINNED (1<<4) 7543318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define EXEC_OBJECT_PAD_TO_SIZE (1<<5) 7550543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/* The kernel implicitly tracks GPU activity on all GEM objects, and 7560543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * synchronises operations with outstanding rendering. This includes 7570543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * rendering on other devices if exported via dma-buf. However, sometimes 7580543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * this tracking is too coarse and the user knows better. For example, 7590543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * if the object is split into non-overlapping ranges shared between different 7600543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * clients or engines (i.e. suballocating objects), the implicit tracking 7610543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * by kernel assumes that each operation affects the whole object rather 7620543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * than an individual range, causing needless synchronisation between clients. 7630543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * The kernel will also forgo any CPU cache flushes prior to rendering from 7640543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * the object as the client is expected to be also handling such domain 7650543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * tracking. 7660543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 7670543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * The kernel maintains the implicit tracking in order to manage resources 7680543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * used by the GPU - this flag only disables the synchronisation prior to 7690543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * rendering with this object in this execbuf. 7700543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 7710543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Opting out of implicit synhronisation requires the user to do its own 7720543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * explicit tracking to avoid rendering corruption. See, for example, 7730543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. 7740543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 7750543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define EXEC_OBJECT_ASYNC (1<<6) 7763318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ 7770543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_ASYNC<<1) 778224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 flags; 779224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 7803318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris union { 7813318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris __u64 rsvd1; 7823318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris __u64 pad_to_size; 7833318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris }; 784224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 rsvd2; 785224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 786224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 787224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_execbuffer2 { 788224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 789224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * List of gem_exec_object2 structs 790224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 791224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 buffers_ptr; 792224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 buffer_count; 793224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 794224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset in the batchbuffer to start execution from. */ 795224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 batch_start_offset; 796224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Bytes used in batchbuffer from batch_start_offset */ 797224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 batch_len; 798224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 DR1; 799224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 DR4; 800224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 num_cliprects; 801224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** This is a struct drm_clip_rect *cliprects */ 802224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 cliprects_ptr; 803224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_RING_MASK (7<<0) 804224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_DEFAULT (0<<0) 805224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_RENDER (1<<0) 806224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_BSD (2<<0) 807224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_BLT (3<<0) 808e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_EXEC_VEBOX (4<<0) 809224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 810224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Used for switching the constants addressing mode on gen4+ RENDER ring. 811224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Gen6+ only supports relative addressing to dynamic state (default) and 812224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * absolute addressing. 813224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 814224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * These flags are ignored for the BSD and BLT rings. 815224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 816224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_CONSTANTS_MASK (3<<6) 817224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 818224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 819224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 820224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 flags; 821224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 rsvd1; /* now used for context info */ 822224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 rsvd2; 823224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 824224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 825224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Resets the SO write offset registers for transform feedback on gen7. */ 826224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_GEN7_SOL_RESET (1<<8) 827224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 828224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Request a privileged ("secure") batch buffer. Note only available for 829224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * DRM_ROOT_ONLY | DRM_MASTER processes. 830224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 831224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_SECURE (1<<9) 832224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 833224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Inform the kernel that the batch is and will always be pinned. This 834224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * negates the requirement for a workaround to be performed to avoid 835224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * an incoherent CS (such as can be found on 830/845). If this flag is 836224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * not passed, the kernel will endeavour to make sure the batch is 837224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * coherent with the CS before execution. If this flag is passed, 838224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * userspace assumes the responsibility for ensuring the same. 839224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 840224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_IS_PINNED (1<<10) 841224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 842e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris/** Provide a hint to the kernel that the command stream and auxiliary 843224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * state buffers already holds the correct presumed addresses and so the 844224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * relocation process may be skipped if no buffers need to be moved in 845224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * preparation for the execbuffer. 846224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 847224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_NO_RELOC (1<<11) 848224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 849224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Use the reloc.handle as an index into the exec object array rather 850224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * than as the per-file handle. 851224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 852224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_HANDLE_LUT (1<<12) 853224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 85412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/** Used for switching BSD rings on the platforms with two BSD rings */ 855ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_EXEC_BSD_SHIFT (13) 856ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 857ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris/* default ping-pong mode */ 858ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 859ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 860ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 86112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 86212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/** Tell the kernel that the batchbuffer is processed by 86312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * the resource streamer. 86412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 86512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_EXEC_RESOURCE_STREAMER (1<<15) 86612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 8670543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent 8680543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * a sync_file fd to wait upon (in a nonblocking manner) prior to executing 8690543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * the batch. 8700543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 8710543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Returns -EINVAL if the sync_file fd cannot be found. 8720543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 8730543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_EXEC_FENCE_IN (1<<16) 8740543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 8750543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd 8760543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given 8770543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * to the caller, and it should be close() after use. (The fd is a regular 8780543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * file descriptor and will be cleaned up on process termination. It holds 8790543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * a reference to the request, but nothing else.) 8800543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 8810543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * The sync_file fd can be combined with other sync_file and passed either 8820543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip 8830543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * will only occur after this request completes), or to other devices. 8840543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 8850543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Using I915_EXEC_FENCE_OUT requires use of 8860543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written 8870543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * back to userspace. Failure to do so will cause the out-fence to always 8880543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * be reported as zero, and the real fence fd to be leaked. 8890543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 8900543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_EXEC_FENCE_OUT (1<<17) 8910543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 8920543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_OUT<<1)) 893224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 894224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 895224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define i915_execbuffer2_set_context_id(eb2, context) \ 896224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 897224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define i915_execbuffer2_get_context_id(eb2) \ 898224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 899224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 900224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_pin { 901224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to be pinned. */ 902224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 903224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 904224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 905224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** alignment required within the aperture */ 906224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 alignment; 907224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 908224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Returned GTT offset of the buffer. */ 909224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 910224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 911224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 912224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_unpin { 913224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to be unpinned. */ 914224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 915224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 916224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 917224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 918224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_busy { 919224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to check for busy */ 920224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 921224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 922ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris /** Return busy status 923ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * 924ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * A return of 0 implies that the object is idle (after 925ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * having flushed any pending activity), and a non-zero return that 926ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * the object is still in-flight on the GPU. (The GPU has not yet 927ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * signaled completion for all pending requests that reference the 9283318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * object.) An object is guaranteed to become idle eventually (so 9293318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * long as no new GPU commands are executed upon it). Due to the 9303318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * asynchronous nature of the hardware, an object reported 9313318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * as busy may become idle before the ioctl is completed. 9323318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * 9333318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * Furthermore, if the object is busy, which engine is busy is only 9343318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * provided as a guide. There are race conditions which prevent the 9353318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * report of which engines are busy from being always accurate. 9363318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * However, the converse is not true. If the object is idle, the 9373318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * result of the ioctl, that all engines are idle, is accurate. 938ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * 939ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * The returned dword is split into two fields to indicate both 940ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * the engines on which the object is being read, and the 941ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * engine on which it is currently being written (if any). 942ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * 943ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * The low word (bits 0:15) indicate if the object is being written 944ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * to by any engine (there can only be one, as the GEM implicit 945ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * synchronisation rules force writes to be serialised). Only the 946ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * engine for the last write is reported. 947ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * 948ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * The high word (bits 16:31) are a bitmask of which engines are 949ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * currently reading from the object. Multiple engines may be 950ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * reading from the object simultaneously. 951ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * 952ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * The value of each engine is the same as specified in the 953ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc. 954ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to 955ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * the I915_EXEC_RENDER engine for execution, and so it is never 956ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * reported as active itself. Some hardware may have parallel 957ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * execution engines, e.g. multiple media engines, which are 958ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * mapped to the same identifier in the EXECBUFFER2 ioctl and 959ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * so are not separately reported for busyness. 9603318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * 9613318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * Caveat emptor: 9623318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * Only the boolean result of this query is reliable; that is whether 9633318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * the object is idle or busy. The report of which engines are busy 9643318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris * should be only used as a heuristic. 965224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 966224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 busy; 967224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 968224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 969e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris/** 970e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_CACHING_NONE 971e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 972e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * GPU access is not coherent with cpu caches. Default for machines without an 973e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * LLC. 974e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris */ 975224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_CACHING_NONE 0 976e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris/** 977e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_CACHING_CACHED 978e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 979e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * GPU access is coherent with cpu caches and furthermore the data is cached in 980e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * last-level caches shared between cpu cores and the gpu GT. Default on 981e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * machines with HAS_LLC. 982e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris */ 983224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_CACHING_CACHED 1 984e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris/** 985e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_CACHING_DISPLAY 986e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 987e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * Special GPU caching mode which is coherent with the scanout engines. 988e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * Transparently falls back to I915_CACHING_NONE on platforms where no special 989e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * cache mode (like write-through or gfdt flushing) is available. The kernel 990e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * automatically sets this mode when using a buffer as a scanout target. 991e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * Userspace can manually set this mode to avoid a costly stall and clflush in 992e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * the hotpath of drawing the first frame. 993e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris */ 994e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_CACHING_DISPLAY 2 995224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 996224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_caching { 997224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 998224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Handle of the buffer to set/get the caching level of. */ 999224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 1000224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1001224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 1002224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Cacheing level to apply or return value 1003224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1004224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * bits0-15 are for generic caching control (i.e. the above defined 1005224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * values). bits16-31 are reserved for platform-specific variations 1006224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * (e.g. l3$ caching on gen7). */ 1007224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 caching; 1008224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1009224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1010224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_TILING_NONE 0 1011224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_TILING_X 1 1012224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_TILING_Y 2 10133318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define I915_TILING_LAST I915_TILING_Y 1014224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1015224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_NONE 0 1016224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9 1 1017224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9_10 2 1018224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9_11 3 1019224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9_10_11 4 1020224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Not seen by userland */ 1021224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_UNKNOWN 5 1022224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Seen by userland. */ 1023224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9_17 6 1024224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9_10_17 7 1025224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1026224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_set_tiling { 1027224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to have its tiling state updated */ 1028224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 1029224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1030224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 1031224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1032224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * I915_TILING_Y). 1033224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1034224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This value is to be set on request, and will be updated by the 1035224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * kernel on successful return with the actual chosen tiling layout. 1036224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1037224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The tiling mode may be demoted to I915_TILING_NONE when the system 1038224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * has bit 6 swizzling that can't be managed correctly by GEM. 1039224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1040224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Buffer contents become undefined when changing tiling_mode. 1041224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1042224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 tiling_mode; 1043224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1044224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 1045224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Stride in bytes for the object when in I915_TILING_X or 1046224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * I915_TILING_Y. 1047224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1048224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 stride; 1049224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1050224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 1051224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned address bit 6 swizzling required for CPU access through 1052224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * mmap mapping. 1053224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1054224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 swizzle_mode; 1055224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1056224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1057224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_get_tiling { 1058224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to get tiling state for. */ 1059224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 1060224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1061224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 1062224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1063224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * I915_TILING_Y). 1064224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1065224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 tiling_mode; 1066224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1067224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 1068224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned address bit 6 swizzling required for CPU access through 1069224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * mmap mapping. 1070224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1071224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 swizzle_mode; 107212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 107312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** 107412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Returned address bit 6 swizzling required for CPU access through 107512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * mmap mapping whilst bound. 107612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 107712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris __u32 phys_swizzle_mode; 1078224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1079224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1080224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_get_aperture { 1081224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 1082224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 aper_size; 1083224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1084224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 1085224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Available space in the aperture used by i915_gem_execbuffer, in 1086224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * bytes 1087224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1088224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 aper_available_size; 1089224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1090224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1091224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_get_pipe_from_crtc_id { 1092224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** ID of CRTC being requested **/ 1093224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 crtc_id; 1094224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1095224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** pipe of requested CRTC **/ 1096224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pipe; 1097224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1098224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1099224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_MADV_WILLNEED 0 1100224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_MADV_DONTNEED 1 1101224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define __I915_MADV_PURGED 2 /* internal state */ 1102224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1103224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_madvise { 1104224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to change the backing store advice */ 1105224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 1106224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1107224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Advice: either the buffer will be needed again in the near future, 1108224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * or wont be and could be discarded under memory pressure. 1109224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1110224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 madv; 1111224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1112224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Whether the backing store still exists. */ 1113224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 retained; 1114224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1115224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1116224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* flags */ 1117224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_TYPE_MASK 0xff 1118224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV_PLANAR 0x01 1119224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV_PACKED 0x02 1120224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_RGB 0x03 1121224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1122224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_DEPTH_MASK 0xff00 1123224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_RGB24 0x1000 1124224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_RGB16 0x2000 1125224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_RGB15 0x3000 1126224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV422 0x0100 1127224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV411 0x0200 1128224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV420 0x0300 1129224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV410 0x0400 1130224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1131224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_SWAP_MASK 0xff0000 1132224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_NO_SWAP 0x000000 1133224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_UV_SWAP 0x010000 1134224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_Y_SWAP 0x020000 1135224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 1136224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1137224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_FLAGS_MASK 0xff000000 1138224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_ENABLE 0x01000000 1139224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1140224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_intel_overlay_put_image { 1141224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* various flags and src format description */ 1142224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 flags; 1143224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* source picture description */ 1144224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 bo_handle; 1145224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* stride values and offsets are in bytes, buffer relative */ 1146224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 stride_Y; /* stride for packed formats */ 1147224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 stride_UV; 1148224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 offset_Y; /* offset for packet formats */ 1149224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 offset_U; 1150224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 offset_V; 1151224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* in pixels */ 1152224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 src_width; 1153224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 src_height; 1154224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* to compensate the scaling factors for partially covered surfaces */ 1155224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 src_scan_width; 1156224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 src_scan_height; 1157224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* output crtc description */ 1158224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 crtc_id; 1159224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 dst_x; 1160224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 dst_y; 1161224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 dst_width; 1162224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 dst_height; 1163224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1164224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1165224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* flags */ 1166224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_UPDATE_ATTRS (1<<0) 1167224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_UPDATE_GAMMA (1<<1) 116812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) 1169224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_intel_overlay_attrs { 1170224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 flags; 1171224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 color_key; 1172224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __s32 brightness; 1173224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 contrast; 1174224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 saturation; 1175224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma0; 1176224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma1; 1177224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma2; 1178224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma3; 1179224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma4; 1180224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma5; 1181224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1182224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1183224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 1184224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Intel sprite handling 1185224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1186224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Color keying works with a min/mask/max tuple. Both source and destination 1187224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * color keying is allowed. 1188224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1189224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Source keying: 1190224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Sprite pixels within the min & max values, masked against the color channels 1191224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * specified in the mask field, will be transparent. All other pixels will 1192224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * be displayed on top of the primary plane. For RGB surfaces, only the min 1193224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * and mask fields will be used; ranged compares are not allowed. 1194224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1195224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Destination keying: 1196224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Primary plane pixels that match the min value, masked against the color 1197224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * channels specified in the mask field, will be replaced by corresponding 1198224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * pixels from the sprite plane. 1199224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1200224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Note that source & destination keying are exclusive; only one can be 1201224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * active on a given plane. 1202224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1203224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1204224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 1205224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SET_COLORKEY_DESTINATION (1<<1) 1206224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SET_COLORKEY_SOURCE (1<<2) 1207224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_intel_sprite_colorkey { 1208224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 plane_id; 1209224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 min_value; 1210224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 channel_mask; 1211224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 max_value; 1212224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 flags; 1213224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1214224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1215224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_wait { 1216224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of BO we shall wait on */ 1217224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 bo_handle; 1218224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 flags; 1219224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Number of nanoseconds to wait, Returns time remaining. */ 1220224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __s64 timeout_ns; 1221224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1222224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1223224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_context_create { 1224224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* output: id of new context*/ 1225224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 ctx_id; 1226224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 1227224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1228224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1229224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_context_destroy { 1230224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 ctx_id; 1231224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 1232224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1233224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1234224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_reg_read { 1235ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris /* 1236ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * Register offset. 1237ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * For 64bit wide registers where the upper 32bits don't immediately 1238ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * follow the lower 32bits, the offset of the lower 32bits must 1239ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris * be specified 1240ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris */ 1241224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 1242224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 val; /* Return value */ 1243224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 124412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Known registers: 124512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 124612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Render engine timestamp - 0x2358 + 64bit - gen7+ 124712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * - Note this register returns an invalid value if using the default 124812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * single instruction 8byte read, in order to workaround that use 124912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * offset (0x2538 | 1) instead. 125012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 125112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 1252e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1253e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferrisstruct drm_i915_reset_stats { 1254e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 ctx_id; 1255e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 flags; 1256e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1257e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris /* All resets since boot/module reload, for all contexts */ 1258e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 reset_count; 1259e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1260e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris /* Number of batches lost when active in GPU, for this context */ 1261e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 batch_active; 1262e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1263e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris /* Number of batches lost pending for execution, for this context */ 1264e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 batch_pending; 1265e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1266e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 pad; 1267e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris}; 1268e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1269314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferrisstruct drm_i915_gem_userptr { 1270314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris __u64 user_ptr; 1271314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris __u64 user_size; 1272314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris __u32 flags; 1273314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris#define I915_USERPTR_READ_ONLY 0x1 1274314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris#define I915_USERPTR_UNSYNCHRONIZED 0x80000000 1275314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris /** 1276314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris * Returned handle for the object. 1277314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris * 1278314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris * Object handles are nonzero. 1279314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris */ 1280314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris __u32 handle; 1281314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris}; 1282314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris 128312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_i915_gem_context_param { 128412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris __u32 ctx_id; 128512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris __u32 size; 128612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris __u64 param; 1287ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 1288ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 1289ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#define I915_CONTEXT_PARAM_GTT_SIZE 0x3 12906e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 12910543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_CONTEXT_PARAM_BANNABLE 0x5 129212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris __u64 value; 129312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 129412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 12950543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferrisenum drm_i915_oa_format { 12960543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris I915_OA_FORMAT_A13 = 1, 12970543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris I915_OA_FORMAT_A29, 12980543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris I915_OA_FORMAT_A13_B8_C8, 12990543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris I915_OA_FORMAT_B4_C8, 13000543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris I915_OA_FORMAT_A45_B8_C8, 13010543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris I915_OA_FORMAT_B4_C8_A16, 13020543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris I915_OA_FORMAT_C4_B8, 13030543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13040543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris I915_OA_FORMAT_MAX /* non-ABI */ 13050543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris}; 13060543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13070543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferrisenum drm_i915_perf_property_id { 13080543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 13090543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Open the stream for a specific context handle (as used with 13100543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * execbuffer2). A stream opened for a specific context this way 13110543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * won't typically require root privileges. 13120543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 13130543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_PROP_CTX_HANDLE = 1, 13140543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13150543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 13160543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * A value of 1 requests the inclusion of raw OA unit reports as 13170543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * part of stream samples. 13180543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 13190543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_PROP_SAMPLE_OA, 13200543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13210543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 13220543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * The value specifies which set of OA unit metrics should be 13230543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * be configured, defining the contents of any OA unit reports. 13240543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 13250543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_PROP_OA_METRICS_SET, 13260543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13270543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 13280543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * The value specifies the size and layout of OA unit reports. 13290543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 13300543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_PROP_OA_FORMAT, 13310543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13320543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 13330543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Specifying this property implicitly requests periodic OA unit 13340543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * sampling and (at least on Haswell) the sampling frequency is derived 13350543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * from this exponent as follows: 13360543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 13370543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 80ns * 2^(period_exponent + 1) 13380543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 13390543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_PROP_OA_EXPONENT, 13400543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13410543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_PROP_MAX /* non-ABI */ 13420543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris}; 13430543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13440543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferrisstruct drm_i915_perf_open_param { 13450543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris __u32 flags; 13460543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PERF_FLAG_FD_CLOEXEC (1<<0) 13470543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PERF_FLAG_FD_NONBLOCK (1<<1) 13480543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PERF_FLAG_DISABLED (1<<2) 13490543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13500543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** The number of u64 (id, value) pairs */ 13510543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris __u32 num_properties; 13520543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13530543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 13540543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Pointer to array of u64 (id, value) pairs configuring the stream 13550543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * to open. 13560543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 13570543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris __u64 properties_ptr; 13580543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris}; 13590543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13600543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/** 13610543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Enable data capture for a stream that was either opened in a disabled state 13620543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * via I915_PERF_FLAG_DISABLED or was later disabled via 13630543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * I915_PERF_IOCTL_DISABLE. 13640543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 13650543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * It is intended to be cheaper to disable and enable a stream than it may be 13660543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * to close and re-open a stream with the same configuration. 13670543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 13680543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * It's undefined whether any pending data for the stream will be lost. 13690543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 13700543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 13710543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13720543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/** 13730543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Disable data capture for a stream. 13740543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 13750543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * It is an error to try and read a stream that is disabled. 13760543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 13770543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 13780543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13790543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris/** 13800543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Common to all i915 perf records 13810543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 13820543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferrisstruct drm_i915_perf_record_header { 13830543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris __u32 type; 13840543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris __u16 pad; 13850543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris __u16 size; 13860543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris}; 13870543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13880543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferrisenum drm_i915_perf_record_type { 13890543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 13900543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 13910543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Samples are the work horse record type whose contents are extensible 13920543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * and defined when opening an i915 perf stream based on the given 13930543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * properties. 13940543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 13950543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Boolean properties following the naming convention 13960543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in 13970543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * every sample. 13980543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 13990543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * The order of these sample properties given by userspace has no 14000543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * affect on the ordering of data within a sample. The order is 14010543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * documented here. 14020543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 14030543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * struct { 14040543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * struct drm_i915_perf_record_header header; 14050543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * 14060543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA 14070543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * }; 14080543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 14090543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_RECORD_SAMPLE = 1, 14100543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14110543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /* 14120543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * Indicates that one or more OA reports were not written by the 14130543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * hardware. This can happen for example if an MI_REPORT_PERF_COUNT 14140543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * command collides with periodic sampling - which would be more likely 14150543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * at higher sampling frequencies. 14160543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 14170543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 14180543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14190543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris /** 14200543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris * An error occurred that resulted in all pending OA reports being lost. 14210543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris */ 14220543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 14230543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 14240543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris DRM_I915_PERF_RECORD_MAX /* non-ABI */ 14250543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris}; 14260543f743b6f5bc5c0652568c763e6dfb9ddce647Christopher Ferris 1427ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#if defined(__cplusplus) 1428ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris} 1429ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#endif 1430ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris 1431224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#endif /* _UAPI_I915_DRM_H_ */ 1432