i915_drm.h revision 314752488cb92b9f86028836d0b8eabd8acb6a7c
1224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 2224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * All Rights Reserved. 4224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 5224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Permission is hereby granted, free of charge, to any person obtaining a 6224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * copy of this software and associated documentation files (the 7224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * "Software"), to deal in the Software without restriction, including 8224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * without limitation the rights to use, copy, modify, merge, publish, 9224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * distribute, sub license, and/or sell copies of the Software, and to 10224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * permit persons to whom the Software is furnished to do so, subject to 11224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the following conditions: 12224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 13224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The above copyright notice and this permission notice (including the 14224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * next paragraph) shall be included in all copies or substantial portions 15224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * of the Software. 16224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 17224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 25224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 26224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 27224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#ifndef _UAPI_I915_DRM_H_ 28224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define _UAPI_I915_DRM_H_ 29224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 30224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#include <drm/drm.h> 31224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 32224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Please note that modifications to all structs defined here are 33224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * subject to backwards-compatibility constraints. 34224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 35224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 36e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris/** 37e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * DOC: uevents generated by i915 on it's device node 38e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 39e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 40e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * event from the gpu l3 cache. Additional information supplied is ROW, 41e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 42e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * track of these events and if a specific cache-line seems to have a 43e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * persistent error remap it with the l3 remapping tool supplied in 44e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * intel-gpu-tools. The value supplied with the event is always 1. 45e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 46e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_ERROR_UEVENT - Generated upon error detection, currently only via 47e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * hangcheck. The error detection event is a good indicator of when things 48e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * began to go badly. The value supplied with the event is a 1 upon error 49e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * detection, and a 0 upon reset completion, signifying no more error 50e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * exists. NOTE: Disabling hangcheck or reset via module parameter will 51e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * cause the related events to not be seen. 52e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 53e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 54e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * the GPU. The value supplied with the event is always 1. NOTE: Disable 55e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * reset via module parameter will cause this event to not be seen. 56e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris */ 57e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 58e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_ERROR_UEVENT "ERROR" 59e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_RESET_UEVENT "RESET" 60224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 61224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Each region is a minimum of 16k, and there are at most 255 of them. 62224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 63224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 64224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * of chars for next/prev indices */ 65224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_LOG_MIN_TEX_REGION_SIZE 14 66224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 67224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct _drm_i915_init { 68224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng enum { 69224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng I915_INIT_DMA = 0x01, 70224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng I915_CLEANUP_DMA = 0x02, 71224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng I915_RESUME_DMA = 0x03 72224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } func; 73224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int mmio_offset; 74224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int sarea_priv_offset; 75224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int ring_start; 76224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int ring_end; 77224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int ring_size; 78224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int front_offset; 79224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int back_offset; 80224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int depth_offset; 81224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int w; 82224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int h; 83224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pitch; 84224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pitch_bits; 85224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int back_pitch; 86224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int depth_pitch; 87224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int cpp; 88224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int chipset; 89224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_init_t; 90224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 91224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct _drm_i915_sarea { 92224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 93224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int last_upload; /* last time texture was uploaded */ 94224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int last_enqueue; /* last time a buffer was enqueued */ 95224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int last_dispatch; /* age of the most recently dispatched buffer */ 96224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int ctxOwner; /* last context to upload state */ 97224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int texAge; 98224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pf_enabled; /* is pageflipping allowed? */ 99224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pf_active; 100224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pf_current_page; /* which buffer is being displayed? */ 101224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int perf_boxes; /* performance boxes to be displayed */ 102224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int width, height; /* screen size in pixels */ 103224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 104224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_handle_t front_handle; 105224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int front_offset; 106224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int front_size; 107224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 108224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_handle_t back_handle; 109224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int back_offset; 110224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int back_size; 111224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 112224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_handle_t depth_handle; 113224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int depth_offset; 114224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int depth_size; 115224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 116224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_handle_t tex_handle; 117224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int tex_offset; 118224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int tex_size; 119224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int log_tex_granularity; 120224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pitch; 121224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int rotation; /* 0, 90, 180 or 270 */ 122224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int rotated_offset; 123224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int rotated_size; 124224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int rotated_pitch; 125224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int virtualX, virtualY; 126224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 127224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int front_tiled; 128224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int back_tiled; 129224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int depth_tiled; 130224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rotated_tiled; 131224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rotated2_tiled; 132224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 133224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeA_x; 134224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeA_y; 135224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeA_w; 136224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeA_h; 137224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeB_x; 138224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeB_y; 139224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeB_w; 140224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipeB_h; 141224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 142224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* fill out some space for old userspace triple buffer */ 143224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_handle_t unused_handle; 144224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 unused1, unused2, unused3; 145224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 146224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* buffer object handles for static buffers. May change 147224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * over the lifetime of the client. 148224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 149224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 front_bo_handle; 150224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 back_bo_handle; 151224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 unused_bo_handle; 152224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 depth_bo_handle; 153224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 154224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_sarea_t; 155224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 156224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* due to userspace building against these headers we need some compat here */ 157224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeA_x pipeA_x 158224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeA_y pipeA_y 159224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeA_w pipeA_w 160224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeA_h pipeA_h 161224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeB_x pipeB_x 162224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeB_y pipeB_y 163224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeB_w pipeB_w 164224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define planeB_h pipeB_h 165224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 166224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Flags for perf_boxes 167224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 168224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BOX_RING_EMPTY 0x1 169224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BOX_FLIP 0x2 170224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BOX_WAIT 0x4 171224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BOX_TEXTURE_LOAD 0x8 172224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BOX_LOST_CONTEXT 0x10 173224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 174224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* I915 specific ioctls 175224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The device specific ioctl range is 0x40 to 0x79. 176224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 177224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_INIT 0x00 178224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_FLUSH 0x01 179224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_FLIP 0x02 180224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_BATCHBUFFER 0x03 181224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_IRQ_EMIT 0x04 182224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_IRQ_WAIT 0x05 183224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GETPARAM 0x06 184224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_SETPARAM 0x07 185224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_ALLOC 0x08 186224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_FREE 0x09 187224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_INIT_HEAP 0x0a 188224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_CMDBUFFER 0x0b 189224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_DESTROY_HEAP 0x0c 190224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_SET_VBLANK_PIPE 0x0d 191224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GET_VBLANK_PIPE 0x0e 192224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_VBLANK_SWAP 0x0f 193224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_HWS_ADDR 0x11 194224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_INIT 0x13 195224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_EXECBUFFER 0x14 196224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_PIN 0x15 197224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_UNPIN 0x16 198224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_BUSY 0x17 199224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_THROTTLE 0x18 200224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_ENTERVT 0x19 201224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_LEAVEVT 0x1a 202224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_CREATE 0x1b 203224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_PREAD 0x1c 204224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_PWRITE 0x1d 205224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_MMAP 0x1e 206224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_SET_DOMAIN 0x1f 207224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_SW_FINISH 0x20 208224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_SET_TILING 0x21 209224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_GET_TILING 0x22 210224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_GET_APERTURE 0x23 211224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_MMAP_GTT 0x24 212224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 213224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_MADVISE 0x26 214224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 215224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_OVERLAY_ATTRS 0x28 216224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_EXECBUFFER2 0x29 217224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 218224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 219224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_WAIT 0x2c 220224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 221224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 222224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_SET_CACHING 0x2f 223224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_GEM_GET_CACHING 0x30 224224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_REG_READ 0x31 225e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define DRM_I915_GET_RESET_STATS 0x32 226314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris#define DRM_I915_GEM_USERPTR 0x33 227224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 228224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 229224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 230224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 231224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 232224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 233224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 234224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 235224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 236224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 237224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 238224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 239224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 240224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 241224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 242224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 243224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 244224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 245224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 246224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 247224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 248224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 249224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 250224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 251224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 252224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 253224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 254224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 255224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 256224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 257224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 258224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 259224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 260224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 261224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 262224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 263224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 264224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 265224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 266224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 267224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 268224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 269224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 270224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 271224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 272224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 273224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 274224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 275224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 276e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 277314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 278224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 279224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Allow drivers to submit batchbuffers directly to hardware, relying 280224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * on the security mechanisms provided by hardware. 281224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 282224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_batchbuffer { 283224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int start; /* agp offset */ 284224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int used; /* nr bytes in use */ 285224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 286224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 287224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int num_cliprects; /* mulitpass with multiple cliprects? */ 288224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 289224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_batchbuffer_t; 290224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 291224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* As above, but pass a pointer to userspace buffer which can be 292224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * validated by the kernel prior to sending to hardware. 293224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 294224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct _drm_i915_cmdbuffer { 295224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng char __user *buf; /* pointer to userspace command buffer */ 296224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int sz; /* nr bytes in buf */ 297224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 298224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 299224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int num_cliprects; /* mulitpass with multiple cliprects? */ 300224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 301224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_cmdbuffer_t; 302224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 303224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Userspace can request & wait on irq's: 304224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 305224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_irq_emit { 306224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int __user *irq_seq; 307224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_irq_emit_t; 308224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 309224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_irq_wait { 310224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int irq_seq; 311224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_irq_wait_t; 312224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 313224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Ioctl to query kernel params: 314224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 315224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_IRQ_ACTIVE 1 316224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_ALLOW_BATCHBUFFER 2 317224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_LAST_DISPATCH 3 318224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_CHIPSET_ID 4 319224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_GEM 5 320224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_NUM_FENCES_AVAIL 6 321224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_OVERLAY 7 322224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_PAGEFLIPPING 8 323224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_EXECBUF2 9 324224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_BSD 10 325224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_BLT 11 326224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_RELAXED_FENCING 12 327224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_COHERENT_RINGS 13 328224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_EXEC_CONSTANTS 14 329224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_RELAXED_DELTA 15 330224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_GEN7_SOL_RESET 16 331224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_LLC 17 332224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_ALIASING_PPGTT 18 333224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_WAIT_TIMEOUT 19 334224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_SEMAPHORES 20 335224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 336e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_PARAM_HAS_VEBOX 22 337224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_SECURE_BATCHES 23 338224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_PINNED_BATCHES 24 339224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_EXEC_NO_RELOC 25 340224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 341e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_PARAM_HAS_WT 27 342314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris#define I915_PARAM_CMD_PARSER_VERSION 28 343224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 344224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_getparam { 345224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int param; 346224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int __user *value; 347224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_getparam_t; 348224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 349224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Ioctl to set kernel params: 350224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 351224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 352224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 353224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 354224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SETPARAM_NUM_USED_FENCES 4 355224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 356224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_setparam { 357224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int param; 358224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int value; 359224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_setparam_t; 360224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 361224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* A memory manager for regions of shared memory: 362224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 363224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_MEM_REGION_AGP 1 364224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 365224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_mem_alloc { 366224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region; 367224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int alignment; 368224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int size; 369224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int __user *region_offset; /* offset from start of fb or agp */ 370224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_mem_alloc_t; 371224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 372224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_mem_free { 373224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region; 374224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region_offset; 375224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_mem_free_t; 376224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 377224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_mem_init_heap { 378224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region; 379224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int size; 380224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int start; 381224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_mem_init_heap_t; 382224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 383224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Allow memory manager to be torn down and re-initialized (eg on 384224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * rotate): 385224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 386224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_mem_destroy_heap { 387224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region; 388224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_mem_destroy_heap_t; 389224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 390224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Allow X server to configure which pipes to monitor for vblank signals 391224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 392224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_VBLANK_PIPE_A 1 393224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_I915_VBLANK_PIPE_B 2 394224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 395224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_vblank_pipe { 396224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pipe; 397224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_vblank_pipe_t; 398224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 399224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Schedule buffer swap at given vertical blank: 400224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 401224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_vblank_swap { 402224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_drawable_t drawable; 403224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng enum drm_vblank_seq_type seqtype; 404224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int sequence; 405224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_vblank_swap_t; 406224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 407224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_i915_hws_addr { 408224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 addr; 409224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_i915_hws_addr_t; 410224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 411224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_init { 412224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 413224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Beginning offset in the GTT to be managed by the DRM memory 414224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * manager. 415224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 416224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 gtt_start; 417224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 418224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Ending offset in the GTT to be managed by the DRM memory 419224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * manager. 420224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 421224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 gtt_end; 422224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 423224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 424224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_create { 425224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 426224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Requested size for the object. 427224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 428224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The (page-aligned) allocated size for the object will be returned. 429224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 430224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 size; 431224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 432224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned handle for the object. 433224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 434224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Object handles are nonzero. 435224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 436224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 437224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 438224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 439224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 440224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_pread { 441224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object being read. */ 442224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 443224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 444224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset into the object to read from */ 445224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 446224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Length of data to read */ 447224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 size; 448224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 449224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Pointer to write the data into. 450224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 451224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This is a fixed-size type for 32/64 compatibility. 452224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 453224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 data_ptr; 454224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 455224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 456224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_pwrite { 457224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object being written to. */ 458224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 459224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 460224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset into the object to write to */ 461224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 462224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Length of data to write */ 463224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 size; 464224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 465224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Pointer to read the data from. 466224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 467224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This is a fixed-size type for 32/64 compatibility. 468224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 469224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 data_ptr; 470224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 471224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 472224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_mmap { 473224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object being mapped. */ 474224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 475224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 476224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset in the object to map. */ 477224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 478224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 479224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Length of data to map. 480224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 481224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The value will be page-aligned. 482224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 483224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 size; 484224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 485224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned pointer the data was mapped at. 486224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 487224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This is a fixed-size type for 32/64 compatibility. 488224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 489224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 addr_ptr; 490224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 491224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 492224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_mmap_gtt { 493224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object being mapped. */ 494224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 495224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 496224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 497224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Fake offset to use for subsequent mmap call 498224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 499224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This is a fixed-size type for 32/64 compatibility. 500224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 501224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 502224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 503224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 504224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_set_domain { 505224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object */ 506224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 507224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 508224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** New read domains */ 509224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 read_domains; 510224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 511224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** New write domain */ 512224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 write_domain; 513224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 514224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 515224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_sw_finish { 516224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object */ 517224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 518224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 519224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 520224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_relocation_entry { 521224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 522224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Handle of the buffer being pointed to by this relocation entry. 523224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 524224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * It's appealing to make this be an index into the mm_validate_entry 525224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * list to refer to the buffer, but this allows the driver to create 526224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * a relocation list for state buffers and not re-write it per 527224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * exec using the buffer. 528224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 529224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 target_handle; 530224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 531224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 532224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Value to be added to the offset of the target buffer to make up 533224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the relocation entry. 534224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 535224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 delta; 536224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 537224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset in the buffer the relocation entry will be written into */ 538224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 539224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 540224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 541224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Offset value of the target buffer that the relocation entry was last 542224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * written as. 543224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 544224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * If the buffer has the same offset as last time, we can skip syncing 545224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * and writing the relocation. This value is written back out by 546224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the execbuffer ioctl when the relocation is written. 547224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 548224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 presumed_offset; 549224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 550224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 551224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Target memory domains read by this operation. 552224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 553224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 read_domains; 554224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 555224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 556224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Target memory domains written by this operation. 557224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 558224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Note that only one domain may be written by the whole 559224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * execbuffer operation, so that where there are conflicts, 560224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the application will get -EINVAL back. 561224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 562224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 write_domain; 563224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 564224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 565224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** @{ 566224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Intel memory domains 567224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 568224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Most of these just align with the various caches in 569224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the system and are used to flush and invalidate as 570224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * objects end up cached in different domains. 571224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 572224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** CPU cache */ 573224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_CPU 0x00000001 574224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Render cache, used by 2D and 3D drawing */ 575224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_RENDER 0x00000002 576224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Sampler cache, used by texture engine */ 577224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_SAMPLER 0x00000004 578224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Command queue, used to load batch buffers */ 579224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_COMMAND 0x00000008 580224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Instruction cache, used by shader programs */ 581224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 582224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Vertex address cache */ 583224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_VERTEX 0x00000020 584224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** GTT domain - aperture and scanout */ 585224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_GEM_DOMAIN_GTT 0x00000040 586224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** @} */ 587224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 588224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_exec_object { 589224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 590224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * User's handle for a buffer to be bound into the GTT for this 591224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * operation. 592224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 593224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 594224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 595224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Number of relocations to be performed on this buffer */ 596224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 relocation_count; 597224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 598224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Pointer to array of struct drm_i915_gem_relocation_entry containing 599224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the relocations to be performed in this buffer. 600224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 601224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 relocs_ptr; 602224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 603224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Required alignment in graphics aperture */ 604224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 alignment; 605224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 606224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 607224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned value of the updated offset of the object, for future 608224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * presumed_offset writes. 609224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 610224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 611224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 612224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 613224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_execbuffer { 614224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 615224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * List of buffers to be validated with their relocations to be 616224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * performend on them. 617224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 618224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This is a pointer to an array of struct drm_i915_gem_validate_entry. 619224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 620224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * These buffers must be listed in an order such that all relocations 621224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * a buffer is performing refer to buffers that have already appeared 622224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * in the validate list. 623224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 624224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 buffers_ptr; 625224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 buffer_count; 626224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 627224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset in the batchbuffer to start execution from. */ 628224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 batch_start_offset; 629224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Bytes used in batchbuffer from batch_start_offset */ 630224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 batch_len; 631224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 DR1; 632224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 DR4; 633224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 num_cliprects; 634224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** This is a struct drm_clip_rect *cliprects */ 635224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 cliprects_ptr; 636224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 637224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 638224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_exec_object2 { 639224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 640224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * User's handle for a buffer to be bound into the GTT for this 641224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * operation. 642224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 643224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 644224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 645224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Number of relocations to be performed on this buffer */ 646224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 relocation_count; 647224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 648224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Pointer to array of struct drm_i915_gem_relocation_entry containing 649224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the relocations to be performed in this buffer. 650224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 651224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 relocs_ptr; 652224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 653224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Required alignment in graphics aperture */ 654224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 alignment; 655224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 656224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 657224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned value of the updated offset of the object, for future 658224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * presumed_offset writes. 659224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 660224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 661224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 662224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define EXEC_OBJECT_NEEDS_FENCE (1<<0) 663224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define EXEC_OBJECT_NEEDS_GTT (1<<1) 664224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define EXEC_OBJECT_WRITE (1<<2) 665224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) 666224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 flags; 667224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 668224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 rsvd1; 669224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 rsvd2; 670224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 671224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 672224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_execbuffer2 { 673224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 674224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * List of gem_exec_object2 structs 675224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 676224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 buffers_ptr; 677224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 buffer_count; 678224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 679224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset in the batchbuffer to start execution from. */ 680224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 batch_start_offset; 681224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Bytes used in batchbuffer from batch_start_offset */ 682224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 batch_len; 683224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 DR1; 684224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 DR4; 685224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 num_cliprects; 686224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** This is a struct drm_clip_rect *cliprects */ 687224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 cliprects_ptr; 688224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_RING_MASK (7<<0) 689224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_DEFAULT (0<<0) 690224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_RENDER (1<<0) 691224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_BSD (2<<0) 692224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_BLT (3<<0) 693e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_EXEC_VEBOX (4<<0) 694224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 695224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Used for switching the constants addressing mode on gen4+ RENDER ring. 696224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Gen6+ only supports relative addressing to dynamic state (default) and 697224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * absolute addressing. 698224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 699224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * These flags are ignored for the BSD and BLT rings. 700224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 701224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_CONSTANTS_MASK (3<<6) 702224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 703224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 704224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 705224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 flags; 706224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 rsvd1; /* now used for context info */ 707224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 rsvd2; 708224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 709224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 710224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Resets the SO write offset registers for transform feedback on gen7. */ 711224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_GEN7_SOL_RESET (1<<8) 712224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 713224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Request a privileged ("secure") batch buffer. Note only available for 714224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * DRM_ROOT_ONLY | DRM_MASTER processes. 715224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 716224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_SECURE (1<<9) 717224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 718224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Inform the kernel that the batch is and will always be pinned. This 719224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * negates the requirement for a workaround to be performed to avoid 720224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * an incoherent CS (such as can be found on 830/845). If this flag is 721224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * not passed, the kernel will endeavour to make sure the batch is 722224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * coherent with the CS before execution. If this flag is passed, 723224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * userspace assumes the responsibility for ensuring the same. 724224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 725224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_IS_PINNED (1<<10) 726224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 727e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris/** Provide a hint to the kernel that the command stream and auxiliary 728224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * state buffers already holds the correct presumed addresses and so the 729224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * relocation process may be skipped if no buffers need to be moved in 730224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * preparation for the execbuffer. 731224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 732224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_NO_RELOC (1<<11) 733224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 734224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/** Use the reloc.handle as an index into the exec object array rather 735224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * than as the per-file handle. 736224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 737224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_HANDLE_LUT (1<<12) 738224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 739224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1) 740224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 741224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 742224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define i915_execbuffer2_set_context_id(eb2, context) \ 743224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 744224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define i915_execbuffer2_get_context_id(eb2) \ 745224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 746224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 747224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_pin { 748224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to be pinned. */ 749224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 750224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 751224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 752224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** alignment required within the aperture */ 753224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 alignment; 754224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 755224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Returned GTT offset of the buffer. */ 756224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 757224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 758224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 759224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_unpin { 760224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to be unpinned. */ 761224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 762224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 763224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 764224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 765224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_busy { 766224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to check for busy */ 767224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 768224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 769224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Return busy status (1 if busy, 0 if idle). 770224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The high word is used to indicate on which rings the object 771224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * currently resides: 772224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) 773224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 774224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 busy; 775224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 776224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 777e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris/** 778e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_CACHING_NONE 779e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 780e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * GPU access is not coherent with cpu caches. Default for machines without an 781e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * LLC. 782e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris */ 783224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_CACHING_NONE 0 784e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris/** 785e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_CACHING_CACHED 786e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 787e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * GPU access is coherent with cpu caches and furthermore the data is cached in 788e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * last-level caches shared between cpu cores and the gpu GT. Default on 789e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * machines with HAS_LLC. 790e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris */ 791224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_CACHING_CACHED 1 792e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris/** 793e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * I915_CACHING_DISPLAY 794e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * 795e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * Special GPU caching mode which is coherent with the scanout engines. 796e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * Transparently falls back to I915_CACHING_NONE on platforms where no special 797e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * cache mode (like write-through or gfdt flushing) is available. The kernel 798e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * automatically sets this mode when using a buffer as a scanout target. 799e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * Userspace can manually set this mode to avoid a costly stall and clflush in 800e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris * the hotpath of drawing the first frame. 801e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris */ 802e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris#define I915_CACHING_DISPLAY 2 803224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 804224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_caching { 805224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 806224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Handle of the buffer to set/get the caching level of. */ 807224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 808224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 809224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 810224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Cacheing level to apply or return value 811224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 812224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * bits0-15 are for generic caching control (i.e. the above defined 813224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * values). bits16-31 are reserved for platform-specific variations 814224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * (e.g. l3$ caching on gen7). */ 815224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 caching; 816224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 817224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 818224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_TILING_NONE 0 819224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_TILING_X 1 820224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_TILING_Y 2 821224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 822224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_NONE 0 823224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9 1 824224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9_10 2 825224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9_11 3 826224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9_10_11 4 827224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Not seen by userland */ 828224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_UNKNOWN 5 829224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Seen by userland. */ 830224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9_17 6 831224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_BIT_6_SWIZZLE_9_10_17 7 832224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 833224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_set_tiling { 834224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to have its tiling state updated */ 835224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 836224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 837224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 838224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 839224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * I915_TILING_Y). 840224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 841224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * This value is to be set on request, and will be updated by the 842224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * kernel on successful return with the actual chosen tiling layout. 843224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 844224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The tiling mode may be demoted to I915_TILING_NONE when the system 845224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * has bit 6 swizzling that can't be managed correctly by GEM. 846224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 847224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Buffer contents become undefined when changing tiling_mode. 848224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 849224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 tiling_mode; 850224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 851224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 852224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Stride in bytes for the object when in I915_TILING_X or 853224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * I915_TILING_Y. 854224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 855224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 stride; 856224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 857224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 858224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned address bit 6 swizzling required for CPU access through 859224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * mmap mapping. 860224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 861224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 swizzle_mode; 862224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 863224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 864224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_get_tiling { 865224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to get tiling state for. */ 866224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 867224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 868224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 869224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 870224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * I915_TILING_Y). 871224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 872224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 tiling_mode; 873224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 874224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 875224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Returned address bit 6 swizzling required for CPU access through 876224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * mmap mapping. 877224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 878224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 swizzle_mode; 879224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 880224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 881224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_get_aperture { 882224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 883224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 aper_size; 884224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 885224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** 886224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Available space in the aperture used by i915_gem_execbuffer, in 887224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * bytes 888224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 889224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 aper_available_size; 890224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 891224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 892224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_get_pipe_from_crtc_id { 893224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** ID of CRTC being requested **/ 894224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 crtc_id; 895224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 896224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** pipe of requested CRTC **/ 897224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pipe; 898224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 899224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 900224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_MADV_WILLNEED 0 901224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_MADV_DONTNEED 1 902224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define __I915_MADV_PURGED 2 /* internal state */ 903224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 904224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_madvise { 905224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of the buffer to change the backing store advice */ 906224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 handle; 907224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 908224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Advice: either the buffer will be needed again in the near future, 909224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * or wont be and could be discarded under memory pressure. 910224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 911224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 madv; 912224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 913224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Whether the backing store still exists. */ 914224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 retained; 915224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 916224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 917224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* flags */ 918224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_TYPE_MASK 0xff 919224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV_PLANAR 0x01 920224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV_PACKED 0x02 921224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_RGB 0x03 922224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 923224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_DEPTH_MASK 0xff00 924224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_RGB24 0x1000 925224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_RGB16 0x2000 926224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_RGB15 0x3000 927224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV422 0x0100 928224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV411 0x0200 929224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV420 0x0300 930224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_YUV410 0x0400 931224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 932224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_SWAP_MASK 0xff0000 933224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_NO_SWAP 0x000000 934224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_UV_SWAP 0x010000 935224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_Y_SWAP 0x020000 936224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 937224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 938224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_FLAGS_MASK 0xff000000 939224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_ENABLE 0x01000000 940224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 941224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_intel_overlay_put_image { 942224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* various flags and src format description */ 943224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 flags; 944224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* source picture description */ 945224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 bo_handle; 946224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* stride values and offsets are in bytes, buffer relative */ 947224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 stride_Y; /* stride for packed formats */ 948224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 stride_UV; 949224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 offset_Y; /* offset for packet formats */ 950224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 offset_U; 951224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 offset_V; 952224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* in pixels */ 953224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 src_width; 954224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 src_height; 955224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* to compensate the scaling factors for partially covered surfaces */ 956224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 src_scan_width; 957224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 src_scan_height; 958224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* output crtc description */ 959224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 crtc_id; 960224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 dst_x; 961224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 dst_y; 962224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 dst_width; 963224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u16 dst_height; 964224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 965224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 966224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* flags */ 967224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_UPDATE_ATTRS (1<<0) 968224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_OVERLAY_UPDATE_GAMMA (1<<1) 969224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_intel_overlay_attrs { 970224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 flags; 971224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 color_key; 972224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __s32 brightness; 973224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 contrast; 974224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 saturation; 975224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma0; 976224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma1; 977224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma2; 978224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma3; 979224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma4; 980224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 gamma5; 981224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 982224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 983224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 984224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Intel sprite handling 985224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 986224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Color keying works with a min/mask/max tuple. Both source and destination 987224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * color keying is allowed. 988224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 989224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Source keying: 990224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Sprite pixels within the min & max values, masked against the color channels 991224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * specified in the mask field, will be transparent. All other pixels will 992224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * be displayed on top of the primary plane. For RGB surfaces, only the min 993224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * and mask fields will be used; ranged compares are not allowed. 994224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 995224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Destination keying: 996224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Primary plane pixels that match the min value, masked against the color 997224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * channels specified in the mask field, will be replaced by corresponding 998224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * pixels from the sprite plane. 999224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1000224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Note that source & destination keying are exclusive; only one can be 1001224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * active on a given plane. 1002224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1003224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1004224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 1005224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SET_COLORKEY_DESTINATION (1<<1) 1006224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define I915_SET_COLORKEY_SOURCE (1<<2) 1007224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_intel_sprite_colorkey { 1008224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 plane_id; 1009224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 min_value; 1010224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 channel_mask; 1011224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 max_value; 1012224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 flags; 1013224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1014224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1015224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_wait { 1016224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle of BO we shall wait on */ 1017224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 bo_handle; 1018224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 flags; 1019224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Number of nanoseconds to wait, Returns time remaining. */ 1020224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __s64 timeout_ns; 1021224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1022224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1023224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_context_create { 1024224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* output: id of new context*/ 1025224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 ctx_id; 1026224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 1027224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1028224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1029224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_gem_context_destroy { 1030224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 ctx_id; 1031224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u32 pad; 1032224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1033224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1034224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_i915_reg_read { 1035224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 offset; 1036224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __u64 val; /* Return value */ 1037224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 1038e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1039e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferrisstruct drm_i915_reset_stats { 1040e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 ctx_id; 1041e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 flags; 1042e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1043e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris /* All resets since boot/module reload, for all contexts */ 1044e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 reset_count; 1045e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1046e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris /* Number of batches lost when active in GPU, for this context */ 1047e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 batch_active; 1048e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1049e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris /* Number of batches lost pending for execution, for this context */ 1050e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 batch_pending; 1051e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1052e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris __u32 pad; 1053e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris}; 1054e084501669a4e4931c9d648351ecd7d595b81b79Christopher Ferris 1055314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferrisstruct drm_i915_gem_userptr { 1056314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris __u64 user_ptr; 1057314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris __u64 user_size; 1058314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris __u32 flags; 1059314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris#define I915_USERPTR_READ_ONLY 0x1 1060314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris#define I915_USERPTR_UNSYNCHRONIZED 0x80000000 1061314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris /** 1062314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris * Returned handle for the object. 1063314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris * 1064314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris * Object handles are nonzero. 1065314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris */ 1066314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris __u32 handle; 1067314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris}; 1068314752488cb92b9f86028836d0b8eabd8acb6a7cChristopher Ferris 1069224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#endif /* _UAPI_I915_DRM_H_ */ 1070