ih264d_api.c revision 370bd8625d9167dc05a07bf4d02ab931d940e23a
1/****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19*/ 20 21/*****************************************************************************/ 22/* */ 23/* File Name : ih264d_api.c */ 24/* */ 25/* Description : Has all API related functions */ 26/* */ 27/* */ 28/* List of Functions : api_check_struct_sanity */ 29/* ih264d_set_processor */ 30/* ih264d_create */ 31/* ih264d_delete */ 32/* ih264d_init */ 33/* ih264d_map_error */ 34/* ih264d_video_decode */ 35/* ih264d_get_version */ 36/* ih264d_get_display_frame */ 37/* ih264d_set_display_frame */ 38/* ih264d_set_flush_mode */ 39/* ih264d_get_status */ 40/* ih264d_get_buf_info */ 41/* ih264d_set_params */ 42/* ih264d_set_default_params */ 43/* ih264d_reset */ 44/* ih264d_ctl */ 45/* ih264d_rel_display_frame */ 46/* ih264d_set_degrade */ 47/* ih264d_get_frame_dimensions */ 48/* ih264d_set_num_cores */ 49/* ih264d_fill_output_struct_from_context */ 50/* ih264d_api_function */ 51/* */ 52/* Issues / Problems : None */ 53/* */ 54/* Revision History : */ 55/* */ 56/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 57/* 14 10 2008 100356(SKV) Draft */ 58/* */ 59/*****************************************************************************/ 60#include "ih264_typedefs.h" 61#include "ih264_macros.h" 62#include "ih264_platform_macros.h" 63#include "ih264d_tables.h" 64#include "iv.h" 65#include "ivd.h" 66#include "ih264d.h" 67#include "ih264d_defs.h" 68 69#include <string.h> 70#include <limits.h> 71#include <stddef.h> 72 73#include "ih264d_inter_pred.h" 74 75#include "ih264d_structs.h" 76#include "ih264d_nal.h" 77#include "ih264d_error_handler.h" 78 79#include "ih264d_defs.h" 80 81#include "ithread.h" 82#include "ih264d_parse_slice.h" 83#include "ih264d_function_selector.h" 84#include "ih264_error.h" 85#include "ih264_disp_mgr.h" 86#include "ih264_buf_mgr.h" 87#include "ih264d_deblocking.h" 88#include "ih264d_parse_cavlc.h" 89#include "ih264d_parse_cabac.h" 90#include "ih264d_utils.h" 91#include "ih264d_format_conv.h" 92#include "ih264d_parse_headers.h" 93#include "ih264d_thread_compute_bs.h" 94#include <assert.h> 95 96 97/*********************/ 98/* Codec Versioning */ 99/*********************/ 100//Move this to where it is used 101#define CODEC_NAME "H264VDEC" 102#define CODEC_RELEASE_TYPE "production" 103#define CODEC_RELEASE_VER "05.00" 104#define CODEC_VENDOR "ITTIAM" 105#define MAXVERSION_STRLEN 511 106#ifdef __ANDROID__ 107#define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \ 108 snprintf(version_string, MAXVERSION_STRLEN, \ 109 "@(#)Id:%s_%s Ver:%s Released by %s", \ 110 codec_name, codec_release_type, codec_release_ver, codec_vendor) 111#else 112#define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \ 113 snprintf(version_string, MAXVERSION_STRLEN, \ 114 "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s", \ 115 codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__) 116#endif 117 118 119#define MIN_IN_BUFS 1 120#define MIN_OUT_BUFS_420 3 121#define MIN_OUT_BUFS_422ILE 1 122#define MIN_OUT_BUFS_RGB565 1 123#define MIN_OUT_BUFS_420SP 2 124 125#define NUM_FRAMES_LIMIT_ENABLED 0 126 127#if NUM_FRAMES_LIMIT_ENABLED 128#define NUM_FRAMES_LIMIT 10000 129#else 130#define NUM_FRAMES_LIMIT 0x7FFFFFFF 131#endif 132 133 134UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height); 135WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl, 136 void *pv_api_ip, 137 void *pv_api_op); 138WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op); 139 140WORD32 ih264d_deblock_display(dec_struct_t *ps_dec); 141 142void ih264d_signal_decode_thread(dec_struct_t *ps_dec); 143 144void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec); 145void ih264d_decode_picture_thread(dec_struct_t *ps_dec); 146 147WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj, 148 void *pv_api_ip, 149 void *pv_api_op); 150 151void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec, 152 ivd_video_decode_op_t *ps_dec_op); 153 154static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle, 155 void *pv_api_ip, 156 void *pv_api_op) 157{ 158 IVD_API_COMMAND_TYPE_T e_cmd; 159 UWORD32 *pu4_api_ip; 160 UWORD32 *pu4_api_op; 161 UWORD32 i, j; 162 163 if(NULL == pv_api_op) 164 return (IV_FAIL); 165 166 if(NULL == pv_api_ip) 167 return (IV_FAIL); 168 169 pu4_api_ip = (UWORD32 *)pv_api_ip; 170 pu4_api_op = (UWORD32 *)pv_api_op; 171 e_cmd = *(pu4_api_ip + 1); 172 173 /* error checks on handle */ 174 switch((WORD32)e_cmd) 175 { 176 case IVD_CMD_CREATE: 177 break; 178 179 case IVD_CMD_REL_DISPLAY_FRAME: 180 case IVD_CMD_SET_DISPLAY_FRAME: 181 case IVD_CMD_GET_DISPLAY_FRAME: 182 case IVD_CMD_VIDEO_DECODE: 183 case IVD_CMD_DELETE: 184 case IVD_CMD_VIDEO_CTL: 185 if(ps_handle == NULL) 186 { 187 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 188 *(pu4_api_op + 1) |= IVD_HANDLE_NULL; 189 return IV_FAIL; 190 } 191 192 if(ps_handle->u4_size != sizeof(iv_obj_t)) 193 { 194 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 195 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT; 196 return IV_FAIL; 197 } 198 199 if(ps_handle->pv_fxns != ih264d_api_function) 200 { 201 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 202 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 203 return IV_FAIL; 204 } 205 206 if(ps_handle->pv_codec_handle == NULL) 207 { 208 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 209 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 210 return IV_FAIL; 211 } 212 break; 213 default: 214 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 215 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD; 216 return IV_FAIL; 217 } 218 219 switch((WORD32)e_cmd) 220 { 221 case IVD_CMD_CREATE: 222 { 223 ih264d_create_ip_t *ps_ip = (ih264d_create_ip_t *)pv_api_ip; 224 ih264d_create_op_t *ps_op = (ih264d_create_op_t *)pv_api_op; 225 226 227 ps_op->s_ivd_create_op_t.u4_error_code = 0; 228 229 if((ps_ip->s_ivd_create_ip_t.u4_size > sizeof(ih264d_create_ip_t)) 230 || (ps_ip->s_ivd_create_ip_t.u4_size 231 < sizeof(ivd_create_ip_t))) 232 { 233 ps_op->s_ivd_create_op_t.u4_error_code |= 1 234 << IVD_UNSUPPORTEDPARAM; 235 ps_op->s_ivd_create_op_t.u4_error_code |= 236 IVD_IP_API_STRUCT_SIZE_INCORRECT; 237 H264_DEC_DEBUG_PRINT("\n"); 238 return (IV_FAIL); 239 } 240 241 if((ps_op->s_ivd_create_op_t.u4_size != sizeof(ih264d_create_op_t)) 242 && (ps_op->s_ivd_create_op_t.u4_size 243 != sizeof(ivd_create_op_t))) 244 { 245 ps_op->s_ivd_create_op_t.u4_error_code |= 1 246 << IVD_UNSUPPORTEDPARAM; 247 ps_op->s_ivd_create_op_t.u4_error_code |= 248 IVD_OP_API_STRUCT_SIZE_INCORRECT; 249 H264_DEC_DEBUG_PRINT("\n"); 250 return (IV_FAIL); 251 } 252 253 254 if((ps_ip->s_ivd_create_ip_t.e_output_format != IV_YUV_420P) 255 && (ps_ip->s_ivd_create_ip_t.e_output_format 256 != IV_YUV_422ILE) 257 && (ps_ip->s_ivd_create_ip_t.e_output_format 258 != IV_RGB_565) 259 && (ps_ip->s_ivd_create_ip_t.e_output_format 260 != IV_YUV_420SP_UV) 261 && (ps_ip->s_ivd_create_ip_t.e_output_format 262 != IV_YUV_420SP_VU)) 263 { 264 ps_op->s_ivd_create_op_t.u4_error_code |= 1 265 << IVD_UNSUPPORTEDPARAM; 266 ps_op->s_ivd_create_op_t.u4_error_code |= 267 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED; 268 H264_DEC_DEBUG_PRINT("\n"); 269 return (IV_FAIL); 270 } 271 272 } 273 break; 274 275 case IVD_CMD_GET_DISPLAY_FRAME: 276 { 277 ih264d_get_display_frame_ip_t *ps_ip = 278 (ih264d_get_display_frame_ip_t *)pv_api_ip; 279 ih264d_get_display_frame_op_t *ps_op = 280 (ih264d_get_display_frame_op_t *)pv_api_op; 281 282 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0; 283 284 if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size 285 != sizeof(ih264d_get_display_frame_ip_t)) 286 && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size 287 != sizeof(ivd_get_display_frame_ip_t))) 288 { 289 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 290 << IVD_UNSUPPORTEDPARAM; 291 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 292 IVD_IP_API_STRUCT_SIZE_INCORRECT; 293 return (IV_FAIL); 294 } 295 296 if((ps_op->s_ivd_get_display_frame_op_t.u4_size 297 != sizeof(ih264d_get_display_frame_op_t)) 298 && (ps_op->s_ivd_get_display_frame_op_t.u4_size 299 != sizeof(ivd_get_display_frame_op_t))) 300 { 301 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 302 << IVD_UNSUPPORTEDPARAM; 303 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 304 IVD_OP_API_STRUCT_SIZE_INCORRECT; 305 return (IV_FAIL); 306 } 307 } 308 break; 309 310 case IVD_CMD_REL_DISPLAY_FRAME: 311 { 312 ih264d_rel_display_frame_ip_t *ps_ip = 313 (ih264d_rel_display_frame_ip_t *)pv_api_ip; 314 ih264d_rel_display_frame_op_t *ps_op = 315 (ih264d_rel_display_frame_op_t *)pv_api_op; 316 317 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0; 318 319 if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size 320 != sizeof(ih264d_rel_display_frame_ip_t)) 321 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size 322 != sizeof(ivd_rel_display_frame_ip_t))) 323 { 324 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 325 << IVD_UNSUPPORTEDPARAM; 326 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 327 IVD_IP_API_STRUCT_SIZE_INCORRECT; 328 return (IV_FAIL); 329 } 330 331 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size 332 != sizeof(ih264d_rel_display_frame_op_t)) 333 && (ps_op->s_ivd_rel_display_frame_op_t.u4_size 334 != sizeof(ivd_rel_display_frame_op_t))) 335 { 336 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 337 << IVD_UNSUPPORTEDPARAM; 338 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 339 IVD_OP_API_STRUCT_SIZE_INCORRECT; 340 return (IV_FAIL); 341 } 342 343 } 344 break; 345 346 case IVD_CMD_SET_DISPLAY_FRAME: 347 { 348 ih264d_set_display_frame_ip_t *ps_ip = 349 (ih264d_set_display_frame_ip_t *)pv_api_ip; 350 ih264d_set_display_frame_op_t *ps_op = 351 (ih264d_set_display_frame_op_t *)pv_api_op; 352 UWORD32 j; 353 354 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0; 355 356 if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size 357 != sizeof(ih264d_set_display_frame_ip_t)) 358 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size 359 != sizeof(ivd_set_display_frame_ip_t))) 360 { 361 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 362 << IVD_UNSUPPORTEDPARAM; 363 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 364 IVD_IP_API_STRUCT_SIZE_INCORRECT; 365 return (IV_FAIL); 366 } 367 368 if((ps_op->s_ivd_set_display_frame_op_t.u4_size 369 != sizeof(ih264d_set_display_frame_op_t)) 370 && (ps_op->s_ivd_set_display_frame_op_t.u4_size 371 != sizeof(ivd_set_display_frame_op_t))) 372 { 373 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 374 << IVD_UNSUPPORTEDPARAM; 375 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 376 IVD_OP_API_STRUCT_SIZE_INCORRECT; 377 return (IV_FAIL); 378 } 379 380 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0) 381 { 382 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 383 << IVD_UNSUPPORTEDPARAM; 384 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 385 IVD_DISP_FRM_ZERO_OP_BUFS; 386 return IV_FAIL; 387 } 388 389 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; 390 j++) 391 { 392 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs 393 == 0) 394 { 395 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 396 << IVD_UNSUPPORTEDPARAM; 397 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 398 IVD_DISP_FRM_ZERO_OP_BUFS; 399 return IV_FAIL; 400 } 401 402 for(i = 0; 403 i 404 < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs; 405 i++) 406 { 407 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] 408 == NULL) 409 { 410 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 411 << IVD_UNSUPPORTEDPARAM; 412 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 413 IVD_DISP_FRM_OP_BUF_NULL; 414 return IV_FAIL; 415 } 416 417 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] 418 == 0) 419 { 420 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 421 << IVD_UNSUPPORTEDPARAM; 422 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 423 IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 424 return IV_FAIL; 425 } 426 } 427 } 428 } 429 break; 430 431 case IVD_CMD_VIDEO_DECODE: 432 { 433 ih264d_video_decode_ip_t *ps_ip = 434 (ih264d_video_decode_ip_t *)pv_api_ip; 435 ih264d_video_decode_op_t *ps_op = 436 (ih264d_video_decode_op_t *)pv_api_op; 437 438 H264_DEC_DEBUG_PRINT("The input bytes is: %d", 439 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes); 440 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0; 441 442 if(ps_ip->s_ivd_video_decode_ip_t.u4_size 443 != sizeof(ih264d_video_decode_ip_t)&& 444 ps_ip->s_ivd_video_decode_ip_t.u4_size != offsetof(ivd_video_decode_ip_t, s_out_buffer)) 445 { 446 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 447 << IVD_UNSUPPORTEDPARAM; 448 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 449 IVD_IP_API_STRUCT_SIZE_INCORRECT; 450 return (IV_FAIL); 451 } 452 453 if(ps_op->s_ivd_video_decode_op_t.u4_size 454 != sizeof(ih264d_video_decode_op_t)&& 455 ps_op->s_ivd_video_decode_op_t.u4_size != offsetof(ivd_video_decode_op_t, u4_output_present)) 456 { 457 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 458 << IVD_UNSUPPORTEDPARAM; 459 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 460 IVD_OP_API_STRUCT_SIZE_INCORRECT; 461 return (IV_FAIL); 462 } 463 464 } 465 break; 466 467 case IVD_CMD_DELETE: 468 { 469 ih264d_delete_ip_t *ps_ip = 470 (ih264d_delete_ip_t *)pv_api_ip; 471 ih264d_delete_op_t *ps_op = 472 (ih264d_delete_op_t *)pv_api_op; 473 474 ps_op->s_ivd_delete_op_t.u4_error_code = 0; 475 476 if(ps_ip->s_ivd_delete_ip_t.u4_size 477 != sizeof(ih264d_delete_ip_t)) 478 { 479 ps_op->s_ivd_delete_op_t.u4_error_code |= 1 480 << IVD_UNSUPPORTEDPARAM; 481 ps_op->s_ivd_delete_op_t.u4_error_code |= 482 IVD_IP_API_STRUCT_SIZE_INCORRECT; 483 return (IV_FAIL); 484 } 485 486 if(ps_op->s_ivd_delete_op_t.u4_size 487 != sizeof(ih264d_delete_op_t)) 488 { 489 ps_op->s_ivd_delete_op_t.u4_error_code |= 1 490 << IVD_UNSUPPORTEDPARAM; 491 ps_op->s_ivd_delete_op_t.u4_error_code |= 492 IVD_OP_API_STRUCT_SIZE_INCORRECT; 493 return (IV_FAIL); 494 } 495 496 } 497 break; 498 499 case IVD_CMD_VIDEO_CTL: 500 { 501 UWORD32 *pu4_ptr_cmd; 502 UWORD32 sub_command; 503 504 pu4_ptr_cmd = (UWORD32 *)pv_api_ip; 505 pu4_ptr_cmd += 2; 506 sub_command = *pu4_ptr_cmd; 507 508 switch(sub_command) 509 { 510 case IVD_CMD_CTL_SETPARAMS: 511 { 512 ih264d_ctl_set_config_ip_t *ps_ip; 513 ih264d_ctl_set_config_op_t *ps_op; 514 ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip; 515 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op; 516 517 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size 518 != sizeof(ih264d_ctl_set_config_ip_t)) 519 { 520 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 521 << IVD_UNSUPPORTEDPARAM; 522 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 523 IVD_IP_API_STRUCT_SIZE_INCORRECT; 524 return IV_FAIL; 525 } 526 } 527 //no break; is needed here 528 case IVD_CMD_CTL_SETDEFAULT: 529 { 530 ih264d_ctl_set_config_op_t *ps_op; 531 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op; 532 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size 533 != sizeof(ih264d_ctl_set_config_op_t)) 534 { 535 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 536 << IVD_UNSUPPORTEDPARAM; 537 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 538 IVD_OP_API_STRUCT_SIZE_INCORRECT; 539 return IV_FAIL; 540 } 541 } 542 break; 543 544 case IVD_CMD_CTL_GETPARAMS: 545 { 546 ih264d_ctl_getstatus_ip_t *ps_ip; 547 ih264d_ctl_getstatus_op_t *ps_op; 548 549 ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip; 550 ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op; 551 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size 552 != sizeof(ih264d_ctl_getstatus_ip_t)) 553 { 554 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 555 << IVD_UNSUPPORTEDPARAM; 556 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 557 IVD_IP_API_STRUCT_SIZE_INCORRECT; 558 return IV_FAIL; 559 } 560 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size 561 != sizeof(ih264d_ctl_getstatus_op_t)) 562 { 563 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 564 << IVD_UNSUPPORTEDPARAM; 565 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 566 IVD_OP_API_STRUCT_SIZE_INCORRECT; 567 return IV_FAIL; 568 } 569 } 570 break; 571 572 case IVD_CMD_CTL_GETBUFINFO: 573 { 574 ih264d_ctl_getbufinfo_ip_t *ps_ip; 575 ih264d_ctl_getbufinfo_op_t *ps_op; 576 ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip; 577 ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op; 578 579 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size 580 != sizeof(ih264d_ctl_getbufinfo_ip_t)) 581 { 582 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 583 << IVD_UNSUPPORTEDPARAM; 584 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 585 IVD_IP_API_STRUCT_SIZE_INCORRECT; 586 return IV_FAIL; 587 } 588 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size 589 != sizeof(ih264d_ctl_getbufinfo_op_t)) 590 { 591 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 592 << IVD_UNSUPPORTEDPARAM; 593 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 594 IVD_OP_API_STRUCT_SIZE_INCORRECT; 595 return IV_FAIL; 596 } 597 } 598 break; 599 600 case IVD_CMD_CTL_GETVERSION: 601 { 602 ih264d_ctl_getversioninfo_ip_t *ps_ip; 603 ih264d_ctl_getversioninfo_op_t *ps_op; 604 ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip; 605 ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op; 606 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size 607 != sizeof(ih264d_ctl_getversioninfo_ip_t)) 608 { 609 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 610 << IVD_UNSUPPORTEDPARAM; 611 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 612 IVD_IP_API_STRUCT_SIZE_INCORRECT; 613 return IV_FAIL; 614 } 615 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size 616 != sizeof(ih264d_ctl_getversioninfo_op_t)) 617 { 618 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 619 << IVD_UNSUPPORTEDPARAM; 620 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 621 IVD_OP_API_STRUCT_SIZE_INCORRECT; 622 return IV_FAIL; 623 } 624 } 625 break; 626 627 case IVD_CMD_CTL_FLUSH: 628 { 629 ih264d_ctl_flush_ip_t *ps_ip; 630 ih264d_ctl_flush_op_t *ps_op; 631 ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip; 632 ps_op = (ih264d_ctl_flush_op_t *)pv_api_op; 633 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size 634 != sizeof(ih264d_ctl_flush_ip_t)) 635 { 636 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 637 << IVD_UNSUPPORTEDPARAM; 638 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 639 IVD_IP_API_STRUCT_SIZE_INCORRECT; 640 return IV_FAIL; 641 } 642 if(ps_op->s_ivd_ctl_flush_op_t.u4_size 643 != sizeof(ih264d_ctl_flush_op_t)) 644 { 645 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 646 << IVD_UNSUPPORTEDPARAM; 647 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 648 IVD_OP_API_STRUCT_SIZE_INCORRECT; 649 return IV_FAIL; 650 } 651 } 652 break; 653 654 case IVD_CMD_CTL_RESET: 655 { 656 ih264d_ctl_reset_ip_t *ps_ip; 657 ih264d_ctl_reset_op_t *ps_op; 658 ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip; 659 ps_op = (ih264d_ctl_reset_op_t *)pv_api_op; 660 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size 661 != sizeof(ih264d_ctl_reset_ip_t)) 662 { 663 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 664 << IVD_UNSUPPORTEDPARAM; 665 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 666 IVD_IP_API_STRUCT_SIZE_INCORRECT; 667 return IV_FAIL; 668 } 669 if(ps_op->s_ivd_ctl_reset_op_t.u4_size 670 != sizeof(ih264d_ctl_reset_op_t)) 671 { 672 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 673 << IVD_UNSUPPORTEDPARAM; 674 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 675 IVD_OP_API_STRUCT_SIZE_INCORRECT; 676 return IV_FAIL; 677 } 678 } 679 break; 680 681 case IH264D_CMD_CTL_DEGRADE: 682 { 683 ih264d_ctl_degrade_ip_t *ps_ip; 684 ih264d_ctl_degrade_op_t *ps_op; 685 686 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip; 687 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op; 688 689 if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t)) 690 { 691 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 692 ps_op->u4_error_code |= 693 IVD_IP_API_STRUCT_SIZE_INCORRECT; 694 return IV_FAIL; 695 } 696 697 if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t)) 698 { 699 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 700 ps_op->u4_error_code |= 701 IVD_OP_API_STRUCT_SIZE_INCORRECT; 702 return IV_FAIL; 703 } 704 705 if((ps_ip->i4_degrade_pics < 0) 706 || (ps_ip->i4_degrade_pics > 4) 707 || (ps_ip->i4_nondegrade_interval < 0) 708 || (ps_ip->i4_degrade_type < 0) 709 || (ps_ip->i4_degrade_type > 15)) 710 { 711 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 712 return IV_FAIL; 713 } 714 715 break; 716 } 717 718 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS: 719 { 720 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip; 721 ih264d_ctl_get_frame_dimensions_op_t *ps_op; 722 723 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 724 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op; 725 726 if(ps_ip->u4_size 727 != sizeof(ih264d_ctl_get_frame_dimensions_ip_t)) 728 { 729 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 730 ps_op->u4_error_code |= 731 IVD_IP_API_STRUCT_SIZE_INCORRECT; 732 return IV_FAIL; 733 } 734 735 if(ps_op->u4_size 736 != sizeof(ih264d_ctl_get_frame_dimensions_op_t)) 737 { 738 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 739 ps_op->u4_error_code |= 740 IVD_OP_API_STRUCT_SIZE_INCORRECT; 741 return IV_FAIL; 742 } 743 744 break; 745 } 746 747 case IH264D_CMD_CTL_SET_NUM_CORES: 748 { 749 ih264d_ctl_set_num_cores_ip_t *ps_ip; 750 ih264d_ctl_set_num_cores_op_t *ps_op; 751 752 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip; 753 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op; 754 755 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t)) 756 { 757 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 758 ps_op->u4_error_code |= 759 IVD_IP_API_STRUCT_SIZE_INCORRECT; 760 return IV_FAIL; 761 } 762 763 if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t)) 764 { 765 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 766 ps_op->u4_error_code |= 767 IVD_OP_API_STRUCT_SIZE_INCORRECT; 768 return IV_FAIL; 769 } 770 771 if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2) 772 && (ps_ip->u4_num_cores != 3) 773 && (ps_ip->u4_num_cores != 4)) 774 { 775 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 776 return IV_FAIL; 777 } 778 break; 779 } 780 case IH264D_CMD_CTL_SET_PROCESSOR: 781 { 782 ih264d_ctl_set_processor_ip_t *ps_ip; 783 ih264d_ctl_set_processor_op_t *ps_op; 784 785 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip; 786 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op; 787 788 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t)) 789 { 790 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 791 ps_op->u4_error_code |= 792 IVD_IP_API_STRUCT_SIZE_INCORRECT; 793 return IV_FAIL; 794 } 795 796 if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t)) 797 { 798 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 799 ps_op->u4_error_code |= 800 IVD_OP_API_STRUCT_SIZE_INCORRECT; 801 return IV_FAIL; 802 } 803 804 break; 805 } 806 default: 807 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 808 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD; 809 return IV_FAIL; 810 break; 811 } 812 } 813 break; 814 } 815 816 return IV_SUCCESS; 817} 818 819 820/** 821 ******************************************************************************* 822 * 823 * @brief 824 * Sets Processor type 825 * 826 * @par Description: 827 * Sets Processor type 828 * 829 * @param[in] ps_codec_obj 830 * Pointer to codec object at API level 831 * 832 * @param[in] pv_api_ip 833 * Pointer to input argument structure 834 * 835 * @param[out] pv_api_op 836 * Pointer to output argument structure 837 * 838 * @returns Status 839 * 840 * @remarks 841 * 842 * 843 ******************************************************************************* 844 */ 845 846WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 847{ 848 ih264d_ctl_set_processor_ip_t *ps_ip; 849 ih264d_ctl_set_processor_op_t *ps_op; 850 dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle; 851 852 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip; 853 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op; 854 855 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch; 856 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc; 857 858 ih264d_init_function_ptr(ps_codec); 859 860 ps_op->u4_error_code = 0; 861 return IV_SUCCESS; 862} 863 864 865/************************************************************************** 866 * \if Function name : ih264d_init_decoder \endif 867 * 868 * 869 * \brief 870 * Initializes the decoder 871 * 872 * \param apiVersion : Version of the api being used. 873 * \param errorHandlingMechanism : Mechanism to be used for errror handling. 874 * \param postFilteringType: Type of post filtering operation to be used. 875 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0]. 876 * \param uc_dispBufs: Number of Display Buffers. 877 * \param p_NALBufAPI: Pointer to NAL Buffer API. 878 * \param p_DispBufAPI: Pointer to Display Buffer API. 879 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder 880 * for memory allocation and freeing. 881 * 882 * \return 883 * 0 on Success and -1 on error 884 * 885 ************************************************************************** 886 */ 887void ih264d_init_decoder(void * ps_dec_params) 888{ 889 dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params; 890 dec_slice_params_t *ps_cur_slice; 891 pocstruct_t *ps_prev_poc, *ps_cur_poc; 892 WORD32 size; 893 894 size = sizeof(pred_info_t) * 2 * 32; 895 memset(ps_dec->ps_pred, 0 , size); 896 897 size = sizeof(disp_mgr_t); 898 memset(ps_dec->pv_disp_buf_mgr, 0 , size); 899 900 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 901 memset(ps_dec->pv_pic_buf_mgr, 0, size); 902 903 size = sizeof(dec_err_status_t); 904 memset(ps_dec->ps_dec_err_status, 0, size); 905 906 size = sizeof(sei); 907 memset(ps_dec->ps_sei, 0, size); 908 909 size = sizeof(dpb_commands_t); 910 memset(ps_dec->ps_dpb_cmds, 0, size); 911 912 size = sizeof(dec_bit_stream_t); 913 memset(ps_dec->ps_bitstrm, 0, size); 914 915 size = sizeof(dec_slice_params_t); 916 memset(ps_dec->ps_cur_slice, 0, size); 917 918 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t)); 919 memset(ps_dec->pv_scratch_sps_pps, 0, size); 920 921 size = sizeof(ctxt_inc_mb_info_t); 922 memset(ps_dec->ps_left_mb_ctxt_info, 0, size); 923 924 size = (sizeof(neighbouradd_t) << 2); 925 memset(ps_dec->ps_left_mvpred_addr, 0 ,size); 926 927 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 928 memset(ps_dec->pv_mv_buf_mgr, 0, size); 929 930 /* Free any dynamic buffers that are allocated */ 931 ih264d_free_dynamic_bufs(ps_dec); 932 933 ps_cur_slice = ps_dec->ps_cur_slice; 934 ps_dec->init_done = 0; 935 936 ps_dec->u4_num_cores = 1; 937 938 ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0; 939 940 ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE; 941 ps_dec->u4_app_disable_deblk_frm = 0; 942 ps_dec->i4_degrade_type = 0; 943 ps_dec->i4_degrade_pics = 0; 944 945 ps_dec->i4_app_skip_mode = IVD_SKIP_NONE; 946 ps_dec->i4_dec_skip_mode = IVD_SKIP_NONE; 947 948 memset(ps_dec->ps_pps, 0, 949 ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS)); 950 memset(ps_dec->ps_sps, 0, 951 ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS)); 952 953 /* Initialization of function pointers ih264d_deblock_picture function*/ 954 955 ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff; 956 ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff; 957 958 ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec; 959 960 ps_dec->u4_num_fld_in_frm = 0; 961 962 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec; 963 964 /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/ 965 ps_dec->ps_sei->u1_is_valid = 0; 966 967 /* decParams Initializations */ 968 ps_dec->ps_cur_pps = NULL; 969 ps_dec->ps_cur_sps = NULL; 970 ps_dec->u1_init_dec_flag = 0; 971 ps_dec->u1_first_slice_in_stream = 1; 972 ps_dec->u1_first_pb_nal_in_pic = 1; 973 ps_dec->u1_last_pic_not_decoded = 0; 974 ps_dec->u4_app_disp_width = 0; 975 ps_dec->i4_header_decoded = 0; 976 ps_dec->u4_total_frames_decoded = 0; 977 978 ps_dec->i4_error_code = 0; 979 ps_dec->i4_content_type = -1; 980 ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0; 981 982 ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS; 983 ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN; 984 ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT; 985 ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME; 986 ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN; 987 988 ps_dec->u1_pr_sl_type = 0xFF; 989 ps_dec->u2_mbx = 0xffff; 990 ps_dec->u2_mby = 0; 991 ps_dec->u2_total_mbs_coded = 0; 992 993 /* POC initializations */ 994 ps_prev_poc = &ps_dec->s_prev_pic_poc; 995 ps_cur_poc = &ps_dec->s_cur_pic_poc; 996 ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0; 997 ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0; 998 ps_prev_poc->i4_delta_pic_order_cnt_bottom = 999 ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0; 1000 ps_prev_poc->i4_delta_pic_order_cnt[0] = 1001 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0; 1002 ps_prev_poc->i4_delta_pic_order_cnt[1] = 1003 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0; 1004 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0; 1005 ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count = 1006 0; 1007 ps_prev_poc->i4_bottom_field_order_count = 1008 ps_cur_poc->i4_bottom_field_order_count = 0; 1009 ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0; 1010 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0; 1011 ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0; 1012 ps_cur_slice->u1_mmco_equalto5 = 0; 1013 ps_cur_slice->u2_frame_num = 0; 1014 1015 ps_dec->i4_max_poc = 0; 1016 ps_dec->i4_prev_max_display_seq = 0; 1017 ps_dec->u1_recon_mb_grp = 4; 1018 1019 /* Field PIC initializations */ 1020 ps_dec->u1_second_field = 0; 1021 ps_dec->s_prev_seq_params.u1_eoseq_pending = 0; 1022 1023 /* Set the cropping parameters as zero */ 1024 ps_dec->u2_crop_offset_y = 0; 1025 ps_dec->u2_crop_offset_uv = 0; 1026 1027 /* The Initial Frame Rate Info is not Present */ 1028 ps_dec->i4_vui_frame_rate = -1; 1029 ps_dec->i4_pic_type = -1; 1030 ps_dec->i4_frametype = -1; 1031 ps_dec->i4_content_type = -1; 1032 1033 ps_dec->u1_res_changed = 0; 1034 1035 1036 ps_dec->u1_frame_decoded_flag = 0; 1037 1038 /* Set the default frame seek mask mode */ 1039 ps_dec->u4_skip_frm_mask = SKIP_NONE; 1040 1041 /********************************************************/ 1042 /* Initialize CAVLC residual decoding function pointers */ 1043 /********************************************************/ 1044 ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1; 1045 ps_dec->pf_cavlc_4x4res_block[1] = 1046 ih264d_cavlc_4x4res_block_totalcoeff_2to10; 1047 ps_dec->pf_cavlc_4x4res_block[2] = 1048 ih264d_cavlc_4x4res_block_totalcoeff_11to16; 1049 1050 ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7; 1051 ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8; 1052 1053 ps_dec->pf_cavlc_parse_8x8block[0] = 1054 ih264d_cavlc_parse_8x8block_none_available; 1055 ps_dec->pf_cavlc_parse_8x8block[1] = 1056 ih264d_cavlc_parse_8x8block_left_available; 1057 ps_dec->pf_cavlc_parse_8x8block[2] = 1058 ih264d_cavlc_parse_8x8block_top_available; 1059 ps_dec->pf_cavlc_parse_8x8block[3] = 1060 ih264d_cavlc_parse_8x8block_both_available; 1061 1062 /***************************************************************************/ 1063 /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */ 1064 /***************************************************************************/ 1065 ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice; 1066 ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice; 1067 1068 ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice; 1069 ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice; 1070 1071 ps_dec->pf_fill_bs_xtra_left_edge[0] = 1072 ih264d_fill_bs_xtra_left_edge_cur_frm; 1073 ps_dec->pf_fill_bs_xtra_left_edge[1] = 1074 ih264d_fill_bs_xtra_left_edge_cur_fld; 1075 1076 /* Initialize Reference Pic Buffers */ 1077 ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr); 1078 1079 ps_dec->u2_prv_frame_num = 0; 1080 ps_dec->u1_top_bottom_decoded = 0; 1081 ps_dec->u1_dangling_field = 0; 1082 1083 ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table; 1084 1085 ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0]; 1086 ps_dec->pi1_left_ref_idx_ctxt_inc = 1087 &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0]; 1088 ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb; 1089 1090 /* ! */ 1091 /* Initializing flush frame u4_flag */ 1092 ps_dec->u1_flushfrm = 0; 1093 1094 { 1095 ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec; 1096 ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec; 1097 ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec; 1098 ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec; 1099 } 1100 1101 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t)); 1102 memset(ps_dec->u4_disp_buf_mapping, 0, 1103 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1104 memset(ps_dec->u4_disp_buf_to_be_freed, 0, 1105 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1106 1107 ih264d_init_arch(ps_dec); 1108 ih264d_init_function_ptr(ps_dec); 1109 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT; 1110 ps_dec->init_done = 1; 1111 1112} 1113WORD32 ih264d_free_static_bufs(iv_obj_t *dec_hdl) 1114{ 1115 dec_struct_t *ps_dec; 1116 1117 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf); 1118 void *pv_mem_ctxt; 1119 1120 ps_dec = (dec_struct_t *)dec_hdl->pv_codec_handle; 1121 pf_aligned_free = ps_dec->pf_aligned_free; 1122 pv_mem_ctxt = ps_dec->pv_mem_ctxt; 1123 1124 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sps); 1125 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pps); 1126 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_dec_thread_handle); 1127 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_bs_deblk_thread_handle); 1128 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_mgr); 1129 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred); 1130 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_disp_buf_mgr); 1131 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_pic_buf_mgr); 1132 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pic_buf_base); 1133 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_err_status); 1134 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei); 1135 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_cmds); 1136 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_bitstrm); 1137 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_cur_slice); 1138 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_scratch_sps_pps); 1139 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_static); 1140 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ppv_map_ref_idx_to_poc_base); 1141 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_cabac_ctxt_table_t); 1142 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mb_ctxt_info); 1143 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_ref_buff_base); 1144 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_pred1); 1145 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_temp_mc_buffer); 1146 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_init_dpb_base); 1147 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_mbaff_wt_mat); 1148 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_wts_ofsts_mat); 1149 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mvpred_addr); 1150 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_mv_buf_mgr); 1151 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_col_mv_base); 1152 PS_DEC_ALIGNED_FREE(ps_dec, dec_hdl->pv_codec_handle); 1153 1154 if(dec_hdl) 1155 { 1156 pf_aligned_free(pv_mem_ctxt, dec_hdl); 1157 } 1158 return IV_SUCCESS; 1159} 1160/*****************************************************************************/ 1161/* */ 1162/* Function Name : ih264d_create */ 1163/* */ 1164/* Description : creates decoder */ 1165/* */ 1166/* Inputs :iv_obj_t decoder handle */ 1167/* :pv_api_ip pointer to input structure */ 1168/* :pv_api_op pointer to output structure */ 1169/* Outputs : */ 1170/* Returns : void */ 1171/* */ 1172/* Issues : none */ 1173/* */ 1174/* Revision History: */ 1175/* */ 1176/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1177/* 22 10 2008 100356 Draft */ 1178/* */ 1179/*****************************************************************************/ 1180WORD32 ih264d_allocate_static_bufs(iv_obj_t **dec_hdl, void *pv_api_ip, void *pv_api_op) 1181{ 1182 ih264d_create_ip_t *ps_create_ip; 1183 ih264d_create_op_t *ps_create_op; 1184 void *pv_buf; 1185 UWORD8 *pu1_buf; 1186 dec_struct_t *ps_dec; 1187 void *(*pf_aligned_alloc)(void *pv_mem_ctxt, WORD32 alignment, WORD32 size); 1188 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf); 1189 void *pv_mem_ctxt; 1190 WORD32 size; 1191 1192 ps_create_ip = (ih264d_create_ip_t *)pv_api_ip; 1193 ps_create_op = (ih264d_create_op_t *)pv_api_op; 1194 1195 ps_create_op->s_ivd_create_op_t.u4_error_code = 0; 1196 1197 pf_aligned_alloc = ps_create_ip->s_ivd_create_ip_t.pf_aligned_alloc; 1198 pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free; 1199 pv_mem_ctxt = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt; 1200 1201 /* Initialize return handle to NULL */ 1202 ps_create_op->s_ivd_create_op_t.pv_handle = NULL; 1203 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(iv_obj_t)); 1204 RETURN_IF((NULL == pv_buf), IV_FAIL); 1205 *dec_hdl = (iv_obj_t *)pv_buf; 1206 ps_create_op->s_ivd_create_op_t.pv_handle = *dec_hdl; 1207 1208 (*dec_hdl)->pv_codec_handle = NULL; 1209 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(dec_struct_t)); 1210 RETURN_IF((NULL == pv_buf), IV_FAIL); 1211 (*dec_hdl)->pv_codec_handle = (dec_struct_t *)pv_buf; 1212 ps_dec = (dec_struct_t *)pv_buf; 1213 1214 memset(ps_dec, 0, sizeof(dec_struct_t)); 1215 1216#ifndef LOGO_EN 1217 ps_dec->u4_share_disp_buf = ps_create_ip->s_ivd_create_ip_t.u4_share_disp_buf; 1218#else 1219 ps_dec->u4_share_disp_buf = 0; 1220#endif 1221 1222 ps_dec->u1_chroma_format = 1223 (UWORD8)(ps_create_ip->s_ivd_create_ip_t.e_output_format); 1224 1225 if((ps_dec->u1_chroma_format != IV_YUV_420P) 1226 && (ps_dec->u1_chroma_format 1227 != IV_YUV_420SP_UV) 1228 && (ps_dec->u1_chroma_format 1229 != IV_YUV_420SP_VU)) 1230 { 1231 ps_dec->u4_share_disp_buf = 0; 1232 } 1233 1234 ps_dec->pf_aligned_alloc = pf_aligned_alloc; 1235 ps_dec->pf_aligned_free = pf_aligned_free; 1236 ps_dec->pv_mem_ctxt = pv_mem_ctxt; 1237 1238 1239 size = ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS); 1240 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1241 RETURN_IF((NULL == pv_buf), IV_FAIL); 1242 ps_dec->ps_sps = pv_buf; 1243 1244 size = (sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS; 1245 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1246 RETURN_IF((NULL == pv_buf), IV_FAIL); 1247 ps_dec->ps_pps = pv_buf; 1248 1249 size = ithread_get_handle_size(); 1250 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1251 RETURN_IF((NULL == pv_buf), IV_FAIL); 1252 ps_dec->pv_dec_thread_handle = pv_buf; 1253 1254 size = ithread_get_handle_size(); 1255 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1256 RETURN_IF((NULL == pv_buf), IV_FAIL); 1257 ps_dec->pv_bs_deblk_thread_handle = pv_buf; 1258 1259 size = sizeof(dpb_manager_t); 1260 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1261 RETURN_IF((NULL == pv_buf), IV_FAIL); 1262 ps_dec->ps_dpb_mgr = pv_buf; 1263 1264 size = sizeof(pred_info_t) * 2 * 32; 1265 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1266 RETURN_IF((NULL == pv_buf), IV_FAIL); 1267 ps_dec->ps_pred = pv_buf; 1268 1269 size = sizeof(disp_mgr_t); 1270 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1271 RETURN_IF((NULL == pv_buf), IV_FAIL); 1272 ps_dec->pv_disp_buf_mgr = pv_buf; 1273 1274 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 1275 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1276 RETURN_IF((NULL == pv_buf), IV_FAIL); 1277 ps_dec->pv_pic_buf_mgr = pv_buf; 1278 1279 size = sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2); 1280 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1281 RETURN_IF((NULL == pv_buf), IV_FAIL); 1282 ps_dec->ps_pic_buf_base = pv_buf; 1283 1284 size = sizeof(dec_err_status_t); 1285 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1286 RETURN_IF((NULL == pv_buf), IV_FAIL); 1287 ps_dec->ps_dec_err_status = (dec_err_status_t *)pv_buf; 1288 1289 size = sizeof(sei); 1290 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1291 RETURN_IF((NULL == pv_buf), IV_FAIL); 1292 ps_dec->ps_sei = (sei *)pv_buf; 1293 1294 size = sizeof(dpb_commands_t); 1295 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1296 RETURN_IF((NULL == pv_buf), IV_FAIL); 1297 ps_dec->ps_dpb_cmds = (dpb_commands_t *)pv_buf; 1298 1299 size = sizeof(dec_bit_stream_t); 1300 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1301 RETURN_IF((NULL == pv_buf), IV_FAIL); 1302 ps_dec->ps_bitstrm = (dec_bit_stream_t *)pv_buf; 1303 1304 size = sizeof(dec_slice_params_t); 1305 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1306 RETURN_IF((NULL == pv_buf), IV_FAIL); 1307 ps_dec->ps_cur_slice = (dec_slice_params_t *)pv_buf; 1308 1309 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t)); 1310 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1311 RETURN_IF((NULL == pv_buf), IV_FAIL); 1312 ps_dec->pv_scratch_sps_pps = pv_buf; 1313 1314 1315 ps_dec->u4_static_bits_buf_size = 256000; 1316 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, ps_dec->u4_static_bits_buf_size); 1317 RETURN_IF((NULL == pv_buf), IV_FAIL); 1318 ps_dec->pu1_bits_buf_static = pv_buf; 1319 1320 1321 size = ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC) 1322 * sizeof(void *)); 1323 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1324 RETURN_IF((NULL == pv_buf), IV_FAIL); 1325 ps_dec->ppv_map_ref_idx_to_poc_base = pv_buf; 1326 memset(ps_dec->ppv_map_ref_idx_to_poc_base, 0, size); 1327 1328 ps_dec->ppv_map_ref_idx_to_poc = ps_dec->ppv_map_ref_idx_to_poc_base + OFFSET_MAP_IDX_POC; 1329 1330 1331 size = (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS); 1332 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1333 RETURN_IF((NULL == pv_buf), IV_FAIL); 1334 ps_dec->p_cabac_ctxt_table_t = pv_buf; 1335 1336 1337 1338 size = sizeof(ctxt_inc_mb_info_t); 1339 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1340 RETURN_IF((NULL == pv_buf), IV_FAIL); 1341 ps_dec->ps_left_mb_ctxt_info = pv_buf; 1342 1343 1344 1345 size = MAX_REF_BUF_SIZE * 2; 1346 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1347 RETURN_IF((NULL == pv_buf), IV_FAIL); 1348 ps_dec->pu1_ref_buff_base = pv_buf; 1349 ps_dec->pu1_ref_buff = ps_dec->pu1_ref_buff_base + MAX_REF_BUF_SIZE; 1350 1351 1352 size = ((sizeof(WORD16)) * PRED_BUFFER_WIDTH 1353 * PRED_BUFFER_HEIGHT * 2); 1354 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1355 RETURN_IF((NULL == pv_buf), IV_FAIL); 1356 ps_dec->pi2_pred1 = pv_buf; 1357 1358 1359 size = sizeof(UWORD8) * (MB_LUM_SIZE); 1360 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1361 RETURN_IF((NULL == pv_buf), IV_FAIL); 1362 ps_dec->pu1_temp_mc_buffer = pv_buf; 1363 1364 1365 1366 1367 size = 8 * MAX_REF_BUFS * sizeof(struct pic_buffer_t); 1368 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1369 RETURN_IF((NULL == pv_buf), IV_FAIL); 1370 1371 ps_dec->pu1_init_dpb_base = pv_buf; 1372 pu1_buf = pv_buf; 1373 ps_dec->ps_dpb_mgr->ps_init_dpb[0][0] = (struct pic_buffer_t *)pu1_buf; 1374 1375 pu1_buf += size / 2; 1376 ps_dec->ps_dpb_mgr->ps_init_dpb[1][0] = (struct pic_buffer_t *)pu1_buf; 1377 1378 size = (sizeof(UWORD32) * 3 1379 * (MAX_FRAMES * MAX_FRAMES)) 1380 << 3; 1381 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1382 RETURN_IF((NULL == pv_buf), IV_FAIL); 1383 ps_dec->pu4_mbaff_wt_mat = pv_buf; 1384 1385 size = sizeof(UWORD32) * 2 * 3 1386 * (MAX_FRAMES * MAX_FRAMES); 1387 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1388 RETURN_IF((NULL == pv_buf), IV_FAIL); 1389 ps_dec->pu4_wts_ofsts_mat = pv_buf; 1390 1391 1392 size = (sizeof(neighbouradd_t) << 2); 1393 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1394 RETURN_IF((NULL == pv_buf), IV_FAIL); 1395 ps_dec->ps_left_mvpred_addr = pv_buf; 1396 1397 1398 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 1399 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1400 RETURN_IF((NULL == pv_buf), IV_FAIL); 1401 ps_dec->pv_mv_buf_mgr = pv_buf; 1402 1403 1404 size = sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2); 1405 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1406 RETURN_IF((NULL == pv_buf), IV_FAIL); 1407 ps_dec->ps_col_mv_base = pv_buf; 1408 memset(ps_dec->ps_col_mv_base, 0, size); 1409 1410 { 1411 UWORD8 i; 1412 struct pic_buffer_t *ps_init_dpb; 1413 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[0][0]; 1414 for(i = 0; i < 2 * MAX_REF_BUFS; i++) 1415 { 1416 ps_init_dpb->pu1_buf1 = NULL; 1417 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1; 1418 ps_dec->ps_dpb_mgr->ps_init_dpb[0][i] = ps_init_dpb; 1419 ps_dec->ps_dpb_mgr->ps_mod_dpb[0][i] = ps_init_dpb; 1420 ps_init_dpb++; 1421 } 1422 1423 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[1][0]; 1424 for(i = 0; i < 2 * MAX_REF_BUFS; i++) 1425 { 1426 ps_init_dpb->pu1_buf1 = NULL; 1427 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1; 1428 ps_dec->ps_dpb_mgr->ps_init_dpb[1][i] = ps_init_dpb; 1429 ps_dec->ps_dpb_mgr->ps_mod_dpb[1][i] = ps_init_dpb; 1430 ps_init_dpb++; 1431 } 1432 } 1433 ih264d_init_decoder(ps_dec); 1434 1435 return IV_SUCCESS; 1436} 1437 1438 1439/*****************************************************************************/ 1440/* */ 1441/* Function Name : ih264d_create */ 1442/* */ 1443/* Description : creates decoder */ 1444/* */ 1445/* Inputs :iv_obj_t decoder handle */ 1446/* :pv_api_ip pointer to input structure */ 1447/* :pv_api_op pointer to output structure */ 1448/* Outputs : */ 1449/* Returns : void */ 1450/* */ 1451/* Issues : none */ 1452/* */ 1453/* Revision History: */ 1454/* */ 1455/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1456/* 22 10 2008 100356 Draft */ 1457/* */ 1458/*****************************************************************************/ 1459WORD32 ih264d_create(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 1460{ 1461 ih264d_create_op_t *ps_create_op; 1462 1463 WORD32 ret; 1464 1465 ps_create_op = (ih264d_create_op_t *)pv_api_op; 1466 1467 ps_create_op->s_ivd_create_op_t.u4_error_code = 0; 1468 1469 ret = ih264d_allocate_static_bufs(&dec_hdl, pv_api_ip, pv_api_op); 1470 1471 /* If allocation of some buffer fails, then free buffers allocated till then */ 1472 if((IV_FAIL == ret) && (NULL != dec_hdl)) 1473 { 1474 ih264d_free_static_bufs(dec_hdl); 1475 ps_create_op->s_ivd_create_op_t.u4_error_code = IVD_MEM_ALLOC_FAILED; 1476 ps_create_op->s_ivd_create_op_t.u4_error_code = 1 << IVD_FATALERROR; 1477 1478 return IV_FAIL; 1479 } 1480 1481 return IV_SUCCESS; 1482} 1483 1484/*****************************************************************************/ 1485/* */ 1486/* Function Name : ih264d_map_error */ 1487/* */ 1488/* Description : Maps error codes to IVD error groups */ 1489/* */ 1490/* Inputs : */ 1491/* Globals : <Does it use any global variables?> */ 1492/* Outputs : */ 1493/* Returns : void */ 1494/* */ 1495/* Issues : none */ 1496/* */ 1497/* Revision History: */ 1498/* */ 1499/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1500/* 22 10 2008 100356 Draft */ 1501/* */ 1502/*****************************************************************************/ 1503UWORD32 ih264d_map_error(UWORD32 i4_err_status) 1504{ 1505 UWORD32 temp = 0; 1506 1507 switch(i4_err_status) 1508 { 1509 case ERROR_MEM_ALLOC_ISRAM_T: 1510 case ERROR_MEM_ALLOC_SDRAM_T: 1511 case ERROR_BUF_MGR: 1512 case ERROR_MB_GROUP_ASSGN_T: 1513 case ERROR_FRAME_LIMIT_OVER: 1514 case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT: 1515 case ERROR_PROFILE_NOT_SUPPORTED: 1516 case ERROR_INIT_NOT_DONE: 1517 case IVD_MEM_ALLOC_FAILED: 1518 temp = 1 << IVD_FATALERROR; 1519 H264_DEC_DEBUG_PRINT("\nFatal Error\n"); 1520 break; 1521 1522 case ERROR_DBP_MANAGER_T: 1523 case ERROR_GAPS_IN_FRM_NUM: 1524 case ERROR_UNKNOWN_NAL: 1525 case ERROR_INV_MB_SLC_GRP_T: 1526 case ERROR_MULTIPLE_SLC_GRP_T: 1527 case ERROR_UNKNOWN_LEVEL: 1528 case ERROR_UNAVAIL_PICBUF_T: 1529 case ERROR_UNAVAIL_MVBUF_T: 1530 case ERROR_UNAVAIL_DISPBUF_T: 1531 case ERROR_NUM_REF: 1532 case ERROR_REFIDX_ORDER_T: 1533 case ERROR_PIC0_NOT_FOUND_T: 1534 case ERROR_MB_TYPE: 1535 case ERROR_SUB_MB_TYPE: 1536 case ERROR_CBP: 1537 case ERROR_REF_IDX: 1538 case ERROR_NUM_MV: 1539 case ERROR_CHROMA_PRED_MODE: 1540 case ERROR_INTRAPRED: 1541 case ERROR_NEXT_MB_ADDRESS_T: 1542 case ERROR_MB_ADDRESS_T: 1543 case ERROR_PIC1_NOT_FOUND_T: 1544 case ERROR_CAVLC_NUM_COEFF_T: 1545 case ERROR_CAVLC_SCAN_POS_T: 1546 case ERROR_PRED_WEIGHT_TABLE_T: 1547 case ERROR_CORRUPTED_SLICE: 1548 temp = 1 << IVD_CORRUPTEDDATA; 1549 break; 1550 1551 case ERROR_NOT_SUPP_RESOLUTION: 1552 case ERROR_FEATURE_UNAVAIL: 1553 case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT: 1554 temp = 1 << IVD_UNSUPPORTEDINPUT; 1555 break; 1556 1557 case ERROR_INVALID_PIC_PARAM: 1558 case ERROR_INVALID_SEQ_PARAM: 1559 case ERROR_EGC_EXCEED_32_1_T: 1560 case ERROR_EGC_EXCEED_32_2_T: 1561 case ERROR_INV_RANGE_TEV_T: 1562 case ERROR_INV_SLC_TYPE_T: 1563 case ERROR_INV_POC_TYPE_T: 1564 case ERROR_INV_RANGE_QP_T: 1565 case ERROR_INV_SPS_PPS_T: 1566 case ERROR_INV_SLICE_HDR_T: 1567 temp = 1 << IVD_CORRUPTEDHEADER; 1568 break; 1569 1570 case ERROR_EOB_FLUSHBITS_T: 1571 case ERROR_EOB_GETBITS_T: 1572 case ERROR_EOB_GETBIT_T: 1573 case ERROR_EOB_BYPASS_T: 1574 case ERROR_EOB_DECISION_T: 1575 case ERROR_EOB_TERMINATE_T: 1576 case ERROR_EOB_READCOEFF4X4CAB_T: 1577 temp = 1 << IVD_INSUFFICIENTDATA; 1578 break; 1579 case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED: 1580 case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH: 1581 temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR; 1582 break; 1583 1584 case ERROR_DANGLING_FIELD_IN_PIC: 1585 temp = 1 << IVD_APPLIEDCONCEALMENT; 1586 break; 1587 1588 } 1589 1590 return temp; 1591 1592} 1593 1594/*****************************************************************************/ 1595/* */ 1596/* Function Name : ih264d_video_decode */ 1597/* */ 1598/* Description : handle video decode API command */ 1599/* */ 1600/* Inputs :iv_obj_t decoder handle */ 1601/* :pv_api_ip pointer to input structure */ 1602/* :pv_api_op pointer to output structure */ 1603/* Outputs : */ 1604/* Returns : void */ 1605/* */ 1606/* Issues : none */ 1607/* */ 1608/* Revision History: */ 1609/* */ 1610/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1611/* 22 10 2008 100356 Draft */ 1612/* */ 1613/*****************************************************************************/ 1614 1615WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 1616{ 1617 /* ! */ 1618 1619 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 1620 1621 WORD32 i4_err_status = 0; 1622 UWORD8 *pu1_buf = NULL; 1623 WORD32 buflen; 1624 UWORD32 u4_max_ofst, u4_length_of_start_code = 0; 1625 1626 UWORD32 bytes_consumed = 0; 1627 UWORD32 cur_slice_is_nonref = 0; 1628 UWORD32 u4_next_is_aud; 1629 UWORD32 u4_first_start_code_found = 0; 1630 WORD32 ret = 0,api_ret_value = IV_SUCCESS; 1631 WORD32 header_data_left = 0,frame_data_left = 0; 1632 UWORD8 *pu1_bitstrm_buf; 1633 ivd_video_decode_ip_t *ps_dec_ip; 1634 ivd_video_decode_op_t *ps_dec_op; 1635 1636 ithread_set_name((void*)"Parse_thread"); 1637 1638 ps_dec_ip = (ivd_video_decode_ip_t *)pv_api_ip; 1639 ps_dec_op = (ivd_video_decode_op_t *)pv_api_op; 1640 ps_dec->pv_dec_out = ps_dec_op; 1641 if(ps_dec->init_done != 1) 1642 { 1643 return IV_FAIL; 1644 } 1645 1646 /*Data memory barries instruction,so that bitstream write by the application is complete*/ 1647 DATA_SYNC(); 1648 1649 if(0 == ps_dec->u1_flushfrm) 1650 { 1651 if(ps_dec_ip->pv_stream_buffer == NULL) 1652 { 1653 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1654 ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL; 1655 return IV_FAIL; 1656 } 1657 if(ps_dec_ip->u4_num_Bytes <= 0) 1658 { 1659 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1660 ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV; 1661 return IV_FAIL; 1662 1663 } 1664 } 1665 ps_dec->u1_pic_decode_done = 0; 1666 1667 ps_dec_op->u4_num_bytes_consumed = 0; 1668 1669 ps_dec->ps_out_buffer = NULL; 1670 1671 if(ps_dec_ip->u4_size 1672 >= offsetof(ivd_video_decode_ip_t, s_out_buffer)) 1673 ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer; 1674 1675 ps_dec->u4_fmt_conv_cur_row = 0; 1676 1677 ps_dec->u4_output_present = 0; 1678 ps_dec->s_disp_op.u4_error_code = 1; 1679 ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS; 1680 if(0 == ps_dec->u4_share_disp_buf 1681 && ps_dec->i4_decode_header == 0) 1682 { 1683 UWORD32 i; 1684 if(ps_dec->ps_out_buffer->u4_num_bufs == 0) 1685 { 1686 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1687 ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS; 1688 return IV_FAIL; 1689 } 1690 1691 for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++) 1692 { 1693 if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL) 1694 { 1695 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1696 ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL; 1697 return IV_FAIL; 1698 } 1699 1700 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0) 1701 { 1702 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1703 ps_dec_op->u4_error_code |= 1704 IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 1705 return IV_FAIL; 1706 } 1707 } 1708 } 1709 1710 if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT) 1711 { 1712 ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER; 1713 return IV_FAIL; 1714 } 1715 1716 /* ! */ 1717 ps_dec->u4_ts = ps_dec_ip->u4_ts; 1718 1719 ps_dec_op->u4_error_code = 0; 1720 ps_dec_op->e_pic_type = -1; 1721 ps_dec_op->u4_output_present = 0; 1722 ps_dec_op->u4_frame_decoded_flag = 0; 1723 1724 ps_dec->i4_frametype = -1; 1725 ps_dec->i4_content_type = -1; 1726 /* 1727 * For field pictures, set the bottom and top picture decoded u4_flag correctly. 1728 */ 1729 { 1730 if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded) 1731 { 1732 ps_dec->u1_top_bottom_decoded = 0; 1733 } 1734 } 1735 ps_dec->u4_slice_start_code_found = 0; 1736 1737 /* In case the deocder is not in flush mode(in shared mode), 1738 then decoder has to pick up a buffer to write current frame. 1739 Check if a frame is available in such cases */ 1740 1741 if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1 1742 && ps_dec->u1_flushfrm == 0) 1743 { 1744 UWORD32 i; 1745 1746 WORD32 disp_avail = 0, free_id; 1747 1748 /* Check if at least one buffer is available with the codec */ 1749 /* If not then return to application with error */ 1750 for(i = 0; i < ps_dec->u1_pic_bufs; i++) 1751 { 1752 if(0 == ps_dec->u4_disp_buf_mapping[i] 1753 || 1 == ps_dec->u4_disp_buf_to_be_freed[i]) 1754 { 1755 disp_avail = 1; 1756 break; 1757 } 1758 1759 } 1760 1761 if(0 == disp_avail) 1762 { 1763 /* If something is queued for display wait for that buffer to be returned */ 1764 1765 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL; 1766 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 1767 return (IV_FAIL); 1768 } 1769 1770 while(1) 1771 { 1772 pic_buffer_t *ps_pic_buf; 1773 ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free( 1774 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id); 1775 1776 if(ps_pic_buf == NULL) 1777 { 1778 UWORD32 i, display_queued = 0; 1779 1780 /* check if any buffer was given for display which is not returned yet */ 1781 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++) 1782 { 1783 if(0 != ps_dec->u4_disp_buf_mapping[i]) 1784 { 1785 display_queued = 1; 1786 break; 1787 } 1788 } 1789 /* If some buffer is queued for display, then codec has to singal an error and wait 1790 for that buffer to be returned. 1791 If nothing is queued for display then codec has ownership of all display buffers 1792 and it can reuse any of the existing buffers and continue decoding */ 1793 1794 if(1 == display_queued) 1795 { 1796 /* If something is queued for display wait for that buffer to be returned */ 1797 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL; 1798 ps_dec_op->u4_error_code |= (1 1799 << IVD_UNSUPPORTEDPARAM); 1800 return (IV_FAIL); 1801 } 1802 } 1803 else 1804 { 1805 /* If the buffer is with display, then mark it as in use and then look for a buffer again */ 1806 if(1 == ps_dec->u4_disp_buf_mapping[free_id]) 1807 { 1808 ih264_buf_mgr_set_status( 1809 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 1810 free_id, 1811 BUF_MGR_IO); 1812 } 1813 else 1814 { 1815 /** 1816 * Found a free buffer for present call. Release it now. 1817 * Will be again obtained later. 1818 */ 1819 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 1820 free_id, 1821 BUF_MGR_IO); 1822 break; 1823 } 1824 } 1825 } 1826 1827 } 1828 1829 if(ps_dec->u1_flushfrm && ps_dec->u1_init_dec_flag) 1830 { 1831 1832 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer, 1833 &(ps_dec->s_disp_op)); 1834 if(0 == ps_dec->s_disp_op.u4_error_code) 1835 { 1836 ps_dec->u4_fmt_conv_cur_row = 0; 1837 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht; 1838 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 1839 ps_dec->u4_fmt_conv_cur_row, 1840 ps_dec->u4_fmt_conv_num_rows); 1841 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 1842 ps_dec->u4_output_present = 1; 1843 1844 } 1845 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op)); 1846 1847 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 1848 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 1849 1850 ps_dec_op->u4_new_seq = 0; 1851 1852 ps_dec_op->u4_output_present = ps_dec->u4_output_present; 1853 ps_dec_op->u4_progressive_frame_flag = 1854 ps_dec->s_disp_op.u4_progressive_frame_flag; 1855 ps_dec_op->e_output_format = 1856 ps_dec->s_disp_op.e_output_format; 1857 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf; 1858 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type; 1859 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts; 1860 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id; 1861 1862 /*In the case of flush ,since no frame is decoded set pic type as invalid*/ 1863 ps_dec_op->u4_is_ref_flag = -1; 1864 ps_dec_op->e_pic_type = IV_NA_FRAME; 1865 ps_dec_op->u4_frame_decoded_flag = 0; 1866 1867 if(0 == ps_dec->s_disp_op.u4_error_code) 1868 { 1869 return (IV_SUCCESS); 1870 } 1871 else 1872 return (IV_FAIL); 1873 1874 } 1875 if(ps_dec->u1_res_changed == 1) 1876 { 1877 /*if resolution has changed and all buffers have been flushed, reset decoder*/ 1878 ih264d_init_decoder(ps_dec); 1879 } 1880 1881 ps_dec->u4_prev_nal_skipped = 0; 1882 1883 ps_dec->u2_cur_mb_addr = 0; 1884 ps_dec->u2_total_mbs_coded = 0; 1885 ps_dec->u2_cur_slice_num = 0; 1886 ps_dec->cur_dec_mb_num = 0; 1887 ps_dec->cur_recon_mb_num = 0; 1888 ps_dec->u4_first_slice_in_pic = 2; 1889 ps_dec->u1_slice_header_done = 0; 1890 ps_dec->u1_dangling_field = 0; 1891 1892 ps_dec->u4_dec_thread_created = 0; 1893 ps_dec->u4_bs_deblk_thread_created = 0; 1894 ps_dec->u4_cur_bs_mb_num = 0; 1895 1896 DEBUG_THREADS_PRINTF(" Starting process call\n"); 1897 1898 1899 ps_dec->u4_pic_buf_got = 0; 1900 1901 do 1902 { 1903 WORD32 buf_size; 1904 1905 pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer 1906 + ps_dec_op->u4_num_bytes_consumed; 1907 1908 u4_max_ofst = ps_dec_ip->u4_num_Bytes 1909 - ps_dec_op->u4_num_bytes_consumed; 1910 1911 /* If dynamic bitstream buffer is not allocated and 1912 * header decode is done, then allocate dynamic bitstream buffer 1913 */ 1914 if((NULL == ps_dec->pu1_bits_buf_dynamic) && 1915 (ps_dec->i4_header_decoded & 1)) 1916 { 1917 WORD32 size; 1918 1919 void *pv_buf; 1920 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt; 1921 size = MAX(256000, ps_dec->u2_pic_wd * ps_dec->u2_pic_ht * 3 / 2); 1922 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1923 RETURN_IF((NULL == pv_buf), IV_FAIL); 1924 ps_dec->pu1_bits_buf_dynamic = pv_buf; 1925 ps_dec->u4_dynamic_bits_buf_size = size; 1926 } 1927 1928 if(ps_dec->pu1_bits_buf_dynamic) 1929 { 1930 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_dynamic; 1931 buf_size = ps_dec->u4_dynamic_bits_buf_size; 1932 } 1933 else 1934 { 1935 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_static; 1936 buf_size = ps_dec->u4_static_bits_buf_size; 1937 } 1938 1939 u4_next_is_aud = 0; 1940 1941 buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst, 1942 &u4_length_of_start_code, 1943 &u4_next_is_aud); 1944 1945 if(buflen == -1) 1946 buflen = 0; 1947 /* Ignore bytes beyond the allocated size of intermediate buffer */ 1948 buflen = MIN(buflen, buf_size); 1949 1950 bytes_consumed = buflen + u4_length_of_start_code; 1951 ps_dec_op->u4_num_bytes_consumed += bytes_consumed; 1952 1953 { 1954 UWORD8 u1_firstbyte, u1_nal_ref_idc; 1955 1956 if(ps_dec->i4_app_skip_mode == IVD_SKIP_B) 1957 { 1958 u1_firstbyte = *(pu1_buf + u4_length_of_start_code); 1959 u1_nal_ref_idc = (UWORD8)(NAL_REF_IDC(u1_firstbyte)); 1960 if(u1_nal_ref_idc == 0) 1961 { 1962 /*skip non reference frames*/ 1963 cur_slice_is_nonref = 1; 1964 continue; 1965 } 1966 else 1967 { 1968 if(1 == cur_slice_is_nonref) 1969 { 1970 /*We have encountered a referenced frame,return to app*/ 1971 ps_dec_op->u4_num_bytes_consumed -= 1972 bytes_consumed; 1973 ps_dec_op->e_pic_type = IV_B_FRAME; 1974 ps_dec_op->u4_error_code = 1975 IVD_DEC_FRM_SKIPPED; 1976 ps_dec_op->u4_error_code |= (1 1977 << IVD_UNSUPPORTEDPARAM); 1978 ps_dec_op->u4_frame_decoded_flag = 0; 1979 ps_dec_op->u4_size = 1980 sizeof(ivd_video_decode_op_t); 1981 /*signal the decode thread*/ 1982 ih264d_signal_decode_thread(ps_dec); 1983 /* close deblock thread if it is not closed yet*/ 1984 if(ps_dec->u4_num_cores == 3) 1985 { 1986 ih264d_signal_bs_deblk_thread(ps_dec); 1987 } 1988 1989 return (IV_FAIL); 1990 } 1991 } 1992 1993 } 1994 1995 } 1996 1997 1998 if(buflen) 1999 { 2000 memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code, 2001 buflen); 2002 /* Decoder may read extra 8 bytes near end of the frame */ 2003 if((buflen + 8) < buf_size) 2004 { 2005 memset(pu1_bitstrm_buf + buflen, 0, 8); 2006 } 2007 u4_first_start_code_found = 1; 2008 2009 } 2010 else 2011 { 2012 /*start code not found*/ 2013 2014 if(u4_first_start_code_found == 0) 2015 { 2016 /*no start codes found in current process call*/ 2017 2018 ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND; 2019 ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA; 2020 2021 if(ps_dec->u4_pic_buf_got == 0) 2022 { 2023 2024 ih264d_fill_output_struct_from_context(ps_dec, 2025 ps_dec_op); 2026 2027 ps_dec_op->u4_error_code = ps_dec->i4_error_code; 2028 ps_dec_op->u4_frame_decoded_flag = 0; 2029 2030 return (IV_FAIL); 2031 } 2032 else 2033 { 2034 ps_dec->u1_pic_decode_done = 1; 2035 continue; 2036 } 2037 } 2038 else 2039 { 2040 /* a start code has already been found earlier in the same process call*/ 2041 frame_data_left = 0; 2042 continue; 2043 } 2044 2045 } 2046 2047 ps_dec->u4_return_to_app = 0; 2048 ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op, 2049 pu1_bitstrm_buf, buflen); 2050 if(ret != OK) 2051 { 2052 UWORD32 error = ih264d_map_error(ret); 2053 ps_dec_op->u4_error_code = error | ret; 2054 api_ret_value = IV_FAIL; 2055 2056 if((ret == IVD_RES_CHANGED) 2057 || (ret == IVD_MEM_ALLOC_FAILED) 2058 || (ret == ERROR_UNAVAIL_PICBUF_T) 2059 || (ret == ERROR_UNAVAIL_MVBUF_T)) 2060 { 2061 break; 2062 } 2063 2064 if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC)) 2065 { 2066 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 2067 api_ret_value = IV_FAIL; 2068 break; 2069 } 2070 2071 if(ret == ERROR_IN_LAST_SLICE_OF_PIC) 2072 { 2073 api_ret_value = IV_FAIL; 2074 break; 2075 } 2076 2077 } 2078 2079 if(ps_dec->u4_return_to_app) 2080 { 2081 /*We have encountered a referenced frame,return to app*/ 2082 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 2083 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED; 2084 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 2085 ps_dec_op->u4_frame_decoded_flag = 0; 2086 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t); 2087 /*signal the decode thread*/ 2088 ih264d_signal_decode_thread(ps_dec); 2089 /* close deblock thread if it is not closed yet*/ 2090 if(ps_dec->u4_num_cores == 3) 2091 { 2092 ih264d_signal_bs_deblk_thread(ps_dec); 2093 } 2094 return (IV_FAIL); 2095 2096 } 2097 2098 2099 2100 header_data_left = ((ps_dec->i4_decode_header == 1) 2101 && (ps_dec->i4_header_decoded != 3) 2102 && (ps_dec_op->u4_num_bytes_consumed 2103 < ps_dec_ip->u4_num_Bytes)); 2104 frame_data_left = (((ps_dec->i4_decode_header == 0) 2105 && ((ps_dec->u1_pic_decode_done == 0) 2106 || (u4_next_is_aud == 1))) 2107 && (ps_dec_op->u4_num_bytes_consumed 2108 < ps_dec_ip->u4_num_Bytes)); 2109 } 2110 while(( header_data_left == 1)||(frame_data_left == 1)); 2111 2112 if((ps_dec->u4_slice_start_code_found == 1) 2113 && (ret != IVD_MEM_ALLOC_FAILED) 2114 && ps_dec->u2_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs) 2115 { 2116 // last slice - missing/corruption 2117 WORD32 num_mb_skipped; 2118 WORD32 prev_slice_err; 2119 pocstruct_t temp_poc; 2120 WORD32 ret1; 2121 2122 num_mb_skipped = (ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs) 2123 - ps_dec->u2_total_mbs_coded; 2124 2125 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0)) 2126 prev_slice_err = 1; 2127 else 2128 prev_slice_err = 2; 2129 2130 ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num, 2131 &temp_poc, prev_slice_err); 2132 2133 if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T)) 2134 { 2135 return IV_FAIL; 2136 } 2137 } 2138 2139 if((ret == IVD_RES_CHANGED) 2140 || (ret == IVD_MEM_ALLOC_FAILED) 2141 || (ret == ERROR_UNAVAIL_PICBUF_T) 2142 || (ret == ERROR_UNAVAIL_MVBUF_T)) 2143 { 2144 2145 /* signal the decode thread */ 2146 ih264d_signal_decode_thread(ps_dec); 2147 /* close deblock thread if it is not closed yet */ 2148 if(ps_dec->u4_num_cores == 3) 2149 { 2150 ih264d_signal_bs_deblk_thread(ps_dec); 2151 } 2152 /* dont consume bitstream for change in resolution case */ 2153 if(ret == IVD_RES_CHANGED) 2154 { 2155 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 2156 } 2157 return IV_FAIL; 2158 } 2159 2160 2161 if(ps_dec->u1_separate_parse) 2162 { 2163 /* If Format conversion is not complete, 2164 complete it here */ 2165 if(ps_dec->u4_num_cores == 2) 2166 { 2167 2168 /*do deblocking of all mbs*/ 2169 if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0)) 2170 { 2171 UWORD32 u4_num_mbs,u4_max_addr; 2172 tfr_ctxt_t s_tfr_ctxt; 2173 tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt; 2174 pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr; 2175 2176 /*BS is done for all mbs while parsing*/ 2177 u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1; 2178 ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1; 2179 2180 2181 ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt, 2182 ps_dec->u2_frm_wd_in_mbs, 0); 2183 2184 2185 u4_num_mbs = u4_max_addr 2186 - ps_dec->u4_cur_deblk_mb_num + 1; 2187 2188 DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs); 2189 2190 if(u4_num_mbs != 0) 2191 ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs, 2192 ps_tfr_cxt,1); 2193 2194 ps_dec->u4_start_recon_deblk = 0; 2195 2196 } 2197 2198 } 2199 2200 /*signal the decode thread*/ 2201 ih264d_signal_decode_thread(ps_dec); 2202 /* close deblock thread if it is not closed yet*/ 2203 if(ps_dec->u4_num_cores == 3) 2204 { 2205 ih264d_signal_bs_deblk_thread(ps_dec); 2206 } 2207 } 2208 2209 2210 DATA_SYNC(); 2211 2212 2213 if((ps_dec_op->u4_error_code & 0xff) 2214 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED) 2215 { 2216 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 2217 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 2218 } 2219 2220//Report if header (sps and pps) has not been decoded yet 2221 if(ps_dec->i4_header_decoded != 3) 2222 { 2223 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA); 2224 2225 } 2226 2227 if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3) 2228 { 2229 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA); 2230 2231 } 2232 if(ps_dec->u4_prev_nal_skipped) 2233 { 2234 /*We have encountered a referenced frame,return to app*/ 2235 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED; 2236 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 2237 ps_dec_op->u4_frame_decoded_flag = 0; 2238 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t); 2239 /* close deblock thread if it is not closed yet*/ 2240 if(ps_dec->u4_num_cores == 3) 2241 { 2242 ih264d_signal_bs_deblk_thread(ps_dec); 2243 } 2244 return (IV_FAIL); 2245 2246 } 2247 2248 if((ps_dec->u4_slice_start_code_found == 1) 2249 && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status)) 2250 { 2251 /* 2252 * For field pictures, set the bottom and top picture decoded u4_flag correctly. 2253 */ 2254 2255 if(ps_dec->ps_cur_slice->u1_field_pic_flag) 2256 { 2257 if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag) 2258 { 2259 ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY; 2260 } 2261 else 2262 { 2263 ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY; 2264 } 2265 } 2266 2267 /* if new frame in not found (if we are still getting slices from previous frame) 2268 * ih264d_deblock_display is not called. Such frames will not be added to reference /display 2269 */ 2270 if((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0) 2271 { 2272 /* Calling Function to deblock Picture and Display */ 2273 ret = ih264d_deblock_display(ps_dec); 2274 if(ret != 0) 2275 { 2276 return IV_FAIL; 2277 } 2278 } 2279 2280 2281 /*set to complete ,as we dont support partial frame decode*/ 2282 if(ps_dec->i4_header_decoded == 3) 2283 { 2284 ps_dec->u2_total_mbs_coded = ps_dec->ps_cur_sps->u2_max_mb_addr + 1; 2285 } 2286 2287 /*Update the i4_frametype at the end of picture*/ 2288 if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL) 2289 { 2290 ps_dec->i4_frametype = IV_IDR_FRAME; 2291 } 2292 else if(ps_dec->i4_pic_type == B_SLICE) 2293 { 2294 ps_dec->i4_frametype = IV_B_FRAME; 2295 } 2296 else if(ps_dec->i4_pic_type == P_SLICE) 2297 { 2298 ps_dec->i4_frametype = IV_P_FRAME; 2299 } 2300 else if(ps_dec->i4_pic_type == I_SLICE) 2301 { 2302 ps_dec->i4_frametype = IV_I_FRAME; 2303 } 2304 else 2305 { 2306 H264_DEC_DEBUG_PRINT("Shouldn't come here\n"); 2307 } 2308 2309 //Update the content type 2310 ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag; 2311 2312 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2; 2313 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded 2314 - ps_dec->ps_cur_slice->u1_field_pic_flag; 2315 2316 } 2317 2318 /* close deblock thread if it is not closed yet*/ 2319 if(ps_dec->u4_num_cores == 3) 2320 { 2321 ih264d_signal_bs_deblk_thread(ps_dec); 2322 } 2323 2324 2325 { 2326 /* In case the decoder is configured to run in low delay mode, 2327 * then get display buffer and then format convert. 2328 * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles 2329 */ 2330 2331 if((IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode) 2332 && ps_dec->u1_init_dec_flag) 2333 { 2334 2335 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer, 2336 &(ps_dec->s_disp_op)); 2337 if(0 == ps_dec->s_disp_op.u4_error_code) 2338 { 2339 ps_dec->u4_fmt_conv_cur_row = 0; 2340 ps_dec->u4_output_present = 1; 2341 } 2342 } 2343 2344 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op); 2345 2346 /* If Format conversion is not complete, 2347 complete it here */ 2348 if(ps_dec->u4_output_present && 2349 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht)) 2350 { 2351 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht 2352 - ps_dec->u4_fmt_conv_cur_row; 2353 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 2354 ps_dec->u4_fmt_conv_cur_row, 2355 ps_dec->u4_fmt_conv_num_rows); 2356 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 2357 } 2358 2359 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op)); 2360 } 2361 2362 if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1) 2363 { 2364 ps_dec_op->u4_progressive_frame_flag = 1; 2365 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 2366 { 2367 if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag) 2368 && (0 == ps_dec->ps_sps->u1_mb_aff_flag)) 2369 ps_dec_op->u4_progressive_frame_flag = 0; 2370 2371 } 2372 } 2373 2374 /*Data memory barrier instruction,so that yuv write by the library is complete*/ 2375 DATA_SYNC(); 2376 2377 H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n", 2378 ps_dec_op->u4_num_bytes_consumed); 2379 return api_ret_value; 2380} 2381 2382WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2383{ 2384 char version_string[MAXVERSION_STRLEN + 1]; 2385 UWORD32 version_string_len; 2386 2387 ivd_ctl_getversioninfo_ip_t *ps_ip; 2388 ivd_ctl_getversioninfo_op_t *ps_op; 2389 2390 ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip; 2391 ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op; 2392 UNUSED(dec_hdl); 2393 ps_op->u4_error_code = IV_SUCCESS; 2394 2395 VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER, 2396 CODEC_VENDOR); 2397 2398 if((WORD32)ps_ip->u4_version_buffer_size <= 0) 2399 { 2400 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT; 2401 return (IV_FAIL); 2402 } 2403 2404 version_string_len = strnlen(version_string, MAXVERSION_STRLEN) + 1; 2405 2406 if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string))) 2407 { 2408 memcpy(ps_ip->pv_version_buffer, version_string, version_string_len); 2409 ps_op->u4_error_code = IV_SUCCESS; 2410 } 2411 else 2412 { 2413 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT; 2414 return IV_FAIL; 2415 } 2416 return (IV_SUCCESS); 2417} 2418 2419/*****************************************************************************/ 2420/* */ 2421/* Function Name : ih264d_get_display_frame */ 2422/* */ 2423/* Description : */ 2424/* Inputs :iv_obj_t decoder handle */ 2425/* :pv_api_ip pointer to input structure */ 2426/* :pv_api_op pointer to output structure */ 2427/* Outputs : */ 2428/* Returns : void */ 2429/* */ 2430/* Issues : none */ 2431/* */ 2432/* Revision History: */ 2433/* */ 2434/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2435/* 22 10 2008 100356 Draft */ 2436/* */ 2437/*****************************************************************************/ 2438WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl, 2439 void *pv_api_ip, 2440 void *pv_api_op) 2441{ 2442 2443 UNUSED(dec_hdl); 2444 UNUSED(pv_api_ip); 2445 UNUSED(pv_api_op); 2446 // This function is no longer needed, output is returned in the process() 2447 return IV_FAIL; 2448} 2449 2450/*****************************************************************************/ 2451/* */ 2452/* Function Name : ih264d_set_display_frame */ 2453/* */ 2454/* Description : */ 2455/* */ 2456/* Inputs :iv_obj_t decoder handle */ 2457/* :pv_api_ip pointer to input structure */ 2458/* :pv_api_op pointer to output structure */ 2459/* Outputs : */ 2460/* Returns : void */ 2461/* */ 2462/* Issues : none */ 2463/* */ 2464/* Revision History: */ 2465/* */ 2466/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2467/* 22 10 2008 100356 Draft */ 2468/* */ 2469/*****************************************************************************/ 2470WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl, 2471 void *pv_api_ip, 2472 void *pv_api_op) 2473{ 2474 2475 ivd_set_display_frame_ip_t *dec_disp_ip; 2476 ivd_set_display_frame_op_t *dec_disp_op; 2477 2478 UWORD32 i; 2479 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2480 2481 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip; 2482 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op; 2483 dec_disp_op->u4_error_code = 0; 2484 2485 2486 ps_dec->u4_num_disp_bufs = 0; 2487 if(ps_dec->u4_share_disp_buf) 2488 { 2489 UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs; 2490 2491 u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW); 2492 2493 ps_dec->u4_num_disp_bufs = u4_num_bufs; 2494 for(i = 0; i < u4_num_bufs; i++) 2495 { 2496 ps_dec->disp_bufs[i].u4_num_bufs = 2497 dec_disp_ip->s_disp_buffer[i].u4_num_bufs; 2498 2499 ps_dec->disp_bufs[i].buf[0] = 2500 dec_disp_ip->s_disp_buffer[i].pu1_bufs[0]; 2501 ps_dec->disp_bufs[i].buf[1] = 2502 dec_disp_ip->s_disp_buffer[i].pu1_bufs[1]; 2503 ps_dec->disp_bufs[i].buf[2] = 2504 dec_disp_ip->s_disp_buffer[i].pu1_bufs[2]; 2505 2506 ps_dec->disp_bufs[i].u4_bufsize[0] = 2507 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]; 2508 ps_dec->disp_bufs[i].u4_bufsize[1] = 2509 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]; 2510 ps_dec->disp_bufs[i].u4_bufsize[2] = 2511 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]; 2512 2513 } 2514 } 2515 return IV_SUCCESS; 2516 2517} 2518 2519/*****************************************************************************/ 2520/* */ 2521/* Function Name : ih264d_set_flush_mode */ 2522/* */ 2523/* Description : */ 2524/* */ 2525/* Inputs :iv_obj_t decoder handle */ 2526/* :pv_api_ip pointer to input structure */ 2527/* :pv_api_op pointer to output structure */ 2528/* Globals : <Does it use any global variables?> */ 2529/* Outputs : */ 2530/* Returns : void */ 2531/* */ 2532/* Issues : none */ 2533/* */ 2534/* Revision History: */ 2535/* */ 2536/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2537/* 22 10 2008 100356 Draft */ 2538/* */ 2539/*****************************************************************************/ 2540WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2541{ 2542 dec_struct_t * ps_dec; 2543 ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op; 2544 ps_ctl_op->u4_error_code = 0; 2545 2546 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2547 UNUSED(pv_api_ip); 2548 /* ! */ 2549 /* Signal flush frame control call */ 2550 ps_dec->u1_flushfrm = 1; 2551 2552 if(ps_dec->u1_init_dec_flag == 1) 2553 { 2554 ih264d_release_pics_in_dpb((void *)ps_dec, ps_dec->u1_pic_bufs); 2555 ih264d_release_display_bufs(ps_dec); 2556 } 2557 2558 ps_ctl_op->u4_error_code = 0; 2559 2560 return IV_SUCCESS; 2561} 2562 2563/*****************************************************************************/ 2564/* */ 2565/* Function Name : ih264d_get_status */ 2566/* */ 2567/* Description : */ 2568/* */ 2569/* Inputs :iv_obj_t decoder handle */ 2570/* :pv_api_ip pointer to input structure */ 2571/* :pv_api_op pointer to output structure */ 2572/* Globals : <Does it use any global variables?> */ 2573/* Outputs : */ 2574/* Returns : void */ 2575/* */ 2576/* Issues : none */ 2577/* */ 2578/* Revision History: */ 2579/* */ 2580/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2581/* 22 10 2008 100356 Draft */ 2582/* */ 2583/*****************************************************************************/ 2584 2585WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2586{ 2587 2588 UWORD32 i; 2589 dec_struct_t * ps_dec; 2590 UWORD32 pic_wd, pic_ht; 2591 ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op; 2592 UNUSED(pv_api_ip); 2593 ps_ctl_op->u4_error_code = 0; 2594 2595 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2596 2597 2598 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 2599 { 2600 ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height; 2601 ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width; 2602 2603 if(0 == ps_dec->u4_share_disp_buf) 2604 { 2605 pic_wd = ps_dec->u2_disp_width; 2606 pic_ht = ps_dec->u2_disp_height; 2607 2608 } 2609 else 2610 { 2611 pic_wd = ps_dec->u2_frm_wd_y; 2612 pic_ht = ps_dec->u2_frm_ht_y; 2613 } 2614 } 2615 else 2616 { 2617 pic_wd = 0; 2618 pic_ht = 0; 2619 2620 ps_ctl_op->u4_pic_ht = pic_wd; 2621 ps_ctl_op->u4_pic_wd = pic_ht; 2622 2623 if(1 == ps_dec->u4_share_disp_buf) 2624 { 2625 pic_wd += (PAD_LEN_Y_H << 1); 2626 pic_ht += (PAD_LEN_Y_V << 2); 2627 2628 } 2629 2630 } 2631 2632 if(ps_dec->u4_app_disp_width > pic_wd) 2633 pic_wd = ps_dec->u4_app_disp_width; 2634 if(0 == ps_dec->u4_share_disp_buf) 2635 ps_ctl_op->u4_num_disp_bufs = 1; 2636 else 2637 { 2638 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 2639 { 2640 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) && 2641 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag)) 2642 { 2643 ps_ctl_op->u4_num_disp_bufs = 2644 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1; 2645 } 2646 else 2647 { 2648 /*if VUI is not present assume maximum possible refrence frames for the level, 2649 * as max reorder frames*/ 2650 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps); 2651 } 2652 2653 ps_ctl_op->u4_num_disp_bufs += 2654 ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 2655 } 2656 else 2657 { 2658 ps_ctl_op->u4_num_disp_bufs = 32; 2659 } 2660 ps_ctl_op->u4_num_disp_bufs = MAX( 2661 ps_ctl_op->u4_num_disp_bufs, 6); 2662 ps_ctl_op->u4_num_disp_bufs = MIN( 2663 ps_ctl_op->u4_num_disp_bufs, 32); 2664 } 2665 2666 ps_ctl_op->u4_error_code = ps_dec->i4_error_code; 2667 2668 ps_ctl_op->u4_frame_rate = 0; //make it proper 2669 ps_ctl_op->u4_bit_rate = 0; //make it proper 2670 ps_ctl_op->e_content_type = ps_dec->i4_content_type; 2671 ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format; 2672 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS; 2673 2674 if(ps_dec->u1_chroma_format == IV_YUV_420P) 2675 { 2676 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420; 2677 } 2678 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 2679 { 2680 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 2681 } 2682 else if(ps_dec->u1_chroma_format == IV_RGB_565) 2683 { 2684 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 2685 } 2686 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2687 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 2688 { 2689 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP; 2690 } 2691 2692 else 2693 { 2694 //Invalid chroma format; Error code may be updated, verify in testing if needed 2695 ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL; 2696 return IV_FAIL; 2697 } 2698 2699 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++) 2700 { 2701 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2); 2702 } 2703 2704 /*!*/ 2705 if(ps_dec->u1_chroma_format == IV_YUV_420P) 2706 { 2707 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 2708 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 2709 >> 2; 2710 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht) 2711 >> 2; 2712 } 2713 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 2714 { 2715 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 2716 * 2; 2717 ps_ctl_op->u4_min_out_buf_size[1] = 2718 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2719 } 2720 else if(ps_dec->u1_chroma_format == IV_RGB_565) 2721 { 2722 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 2723 * 2; 2724 ps_ctl_op->u4_min_out_buf_size[1] = 2725 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2726 } 2727 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2728 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 2729 { 2730 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 2731 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 2732 >> 1; 2733 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2734 } 2735 2736 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs; 2737 return IV_SUCCESS; 2738} 2739 2740/*****************************************************************************/ 2741/* */ 2742/* Function Name : ih264d_get_buf_info */ 2743/* */ 2744/* Description : */ 2745/* */ 2746/* Inputs :iv_obj_t decoder handle */ 2747/* :pv_api_ip pointer to input structure */ 2748/* :pv_api_op pointer to output structure */ 2749/* Globals : <Does it use any global variables?> */ 2750/* Outputs : */ 2751/* Returns : void */ 2752/* */ 2753/* Issues : none */ 2754/* */ 2755/* Revision History: */ 2756/* */ 2757/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2758/* 22 10 2008 100356 Draft */ 2759/* */ 2760/*****************************************************************************/ 2761WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2762{ 2763 2764 dec_struct_t * ps_dec; 2765 UWORD8 i = 0; // Default for 420P format 2766 UWORD16 pic_wd, pic_ht; 2767 ivd_ctl_getbufinfo_op_t *ps_ctl_op = 2768 (ivd_ctl_getbufinfo_op_t*)pv_api_op; 2769 UNUSED(pv_api_ip); 2770 ps_ctl_op->u4_error_code = 0; 2771 2772 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2773 2774 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS; 2775 if(ps_dec->u1_chroma_format == IV_YUV_420P) 2776 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420; 2777 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 2778 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 2779 else if(ps_dec->u1_chroma_format == IV_RGB_565) 2780 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 2781 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2782 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 2783 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP; 2784 2785 else 2786 { 2787 //Invalid chroma format; Error code may be updated, verify in testing if needed 2788 return IV_FAIL; 2789 } 2790 2791 ps_ctl_op->u4_num_disp_bufs = 1; 2792 2793 2794 pic_wd = 0; 2795 pic_ht = 0; 2796 2797 if(ps_dec->i4_header_decoded == 3) 2798 { 2799 2800 if(0 == ps_dec->u4_share_disp_buf) 2801 { 2802 pic_wd = ps_dec->u2_disp_width; 2803 pic_ht = ps_dec->u2_disp_height; 2804 2805 } 2806 else 2807 { 2808 pic_wd = ps_dec->u2_frm_wd_y; 2809 pic_ht = ps_dec->u2_frm_ht_y; 2810 } 2811 2812 } 2813 2814 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++) 2815 { 2816 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2); 2817 } 2818 if((WORD32)ps_dec->u4_app_disp_width > pic_wd) 2819 pic_wd = ps_dec->u4_app_disp_width; 2820 2821 if(0 == ps_dec->u4_share_disp_buf) 2822 ps_ctl_op->u4_num_disp_bufs = 1; 2823 else 2824 { 2825 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 2826 { 2827 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) && 2828 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag)) 2829 { 2830 ps_ctl_op->u4_num_disp_bufs = 2831 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1; 2832 } 2833 else 2834 { 2835 /*if VUI is not present assume maximum possible refrence frames for the level, 2836 * as max reorder frames*/ 2837 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps); 2838 } 2839 2840 ps_ctl_op->u4_num_disp_bufs += 2841 ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 2842 2843 } 2844 else 2845 { 2846 ps_ctl_op->u4_num_disp_bufs = 32; 2847 2848 } 2849 2850 ps_ctl_op->u4_num_disp_bufs = MAX( 2851 ps_ctl_op->u4_num_disp_bufs, 6); 2852 ps_ctl_op->u4_num_disp_bufs = MIN( 2853 ps_ctl_op->u4_num_disp_bufs, 32); 2854 } 2855 2856 /*!*/ 2857 if(ps_dec->u1_chroma_format == IV_YUV_420P) 2858 { 2859 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 2860 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 2861 >> 2; 2862 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht) 2863 >> 2; 2864 } 2865 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 2866 { 2867 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 2868 * 2; 2869 ps_ctl_op->u4_min_out_buf_size[1] = 2870 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2871 } 2872 else if(ps_dec->u1_chroma_format == IV_RGB_565) 2873 { 2874 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 2875 * 2; 2876 ps_ctl_op->u4_min_out_buf_size[1] = 2877 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2878 } 2879 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2880 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 2881 { 2882 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 2883 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 2884 >> 1; 2885 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2886 } 2887 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs; 2888 2889 return IV_SUCCESS; 2890} 2891 2892/*****************************************************************************/ 2893/* */ 2894/* Function Name : ih264d_set_params */ 2895/* */ 2896/* Description : */ 2897/* */ 2898/* Inputs :iv_obj_t decoder handle */ 2899/* :pv_api_ip pointer to input structure */ 2900/* :pv_api_op pointer to output structure */ 2901/* Outputs : */ 2902/* Returns : void */ 2903/* */ 2904/* Issues : none */ 2905/* */ 2906/* Revision History: */ 2907/* */ 2908/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2909/* 22 10 2008 100356 Draft */ 2910/* */ 2911/*****************************************************************************/ 2912WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2913{ 2914 2915 dec_struct_t * ps_dec; 2916 WORD32 ret = IV_SUCCESS; 2917 2918 ivd_ctl_set_config_ip_t *ps_ctl_ip = 2919 (ivd_ctl_set_config_ip_t *)pv_api_ip; 2920 ivd_ctl_set_config_op_t *ps_ctl_op = 2921 (ivd_ctl_set_config_op_t *)pv_api_op; 2922 2923 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2924 2925 ps_dec->u4_skip_frm_mask = 0; 2926 2927 ps_ctl_op->u4_error_code = 0; 2928 2929 ps_dec->i4_app_skip_mode = ps_ctl_ip->e_frm_skip_mode; 2930 2931 /*Is it really supported test it when you so the corner testing using test app*/ 2932 2933 if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE) 2934 { 2935 2936 if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_P) 2937 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT; 2938 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_B) 2939 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT; 2940 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_PB) 2941 { 2942 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT; 2943 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT; 2944 } 2945 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_I) 2946 ps_dec->u4_skip_frm_mask |= 1 << I_SLC_BIT; 2947 else 2948 { 2949 //dynamic parameter not supported 2950 //Put an appropriate error code to return the error.. 2951 //when you do the error code tests and after that remove this comment 2952 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 2953 ret = IV_FAIL; 2954 } 2955 } 2956 2957 if((0 != ps_dec->u4_app_disp_width) 2958 && (ps_ctl_ip->u4_disp_wd 2959 != ps_dec->u4_app_disp_width)) 2960 { 2961 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 2962 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID; 2963 ret = IV_FAIL; 2964 } 2965 else 2966 { 2967 if(ps_ctl_ip->u4_disp_wd >= ps_dec->u2_pic_wd) 2968 { 2969 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd; 2970 } 2971 else if(0 == ps_dec->i4_header_decoded) 2972 { 2973 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd; 2974 } 2975 else if(ps_ctl_ip->u4_disp_wd == 0) 2976 { 2977 ps_dec->u4_app_disp_width = 0; 2978 } 2979 else 2980 { 2981 /* 2982 * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF) 2983 * does not propogate. 2984 */ 2985 ps_dec->u4_app_disp_width = 0; 2986 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 2987 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID; 2988 ret = IV_FAIL; 2989 } 2990 } 2991 if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME) 2992 ps_dec->i4_decode_header = 0; 2993 else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER) 2994 ps_dec->i4_decode_header = 1; 2995 else 2996 { 2997 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 2998 ps_dec->i4_decode_header = 1; 2999 ret = IV_FAIL; 3000 } 3001 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT; 3002 3003 if((ps_ctl_ip->e_frm_out_mode != IVD_DECODE_FRAME_OUT) && 3004 (ps_ctl_ip->e_frm_out_mode != IVD_DISPLAY_FRAME_OUT)) 3005 { 3006 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 3007 ret = IV_FAIL; 3008 } 3009 ps_dec->e_frm_out_mode = ps_ctl_ip->e_frm_out_mode; 3010 return ret; 3011 3012} 3013 3014/*****************************************************************************/ 3015/* */ 3016/* Function Name : ih264d_set_default_params */ 3017/* */ 3018/* Description : */ 3019/* */ 3020/* Inputs :iv_obj_t decoder handle */ 3021/* :pv_api_ip pointer to input structure */ 3022/* :pv_api_op pointer to output structure */ 3023/* Outputs : */ 3024/* Returns : void */ 3025/* */ 3026/* Issues : none */ 3027/* */ 3028/* Revision History: */ 3029/* */ 3030/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3031/* 08 08 2011 100421 Copied from set_params */ 3032/* */ 3033/*****************************************************************************/ 3034WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl, 3035 void *pv_api_ip, 3036 void *pv_api_op) 3037{ 3038 3039 dec_struct_t * ps_dec; 3040 WORD32 ret = IV_SUCCESS; 3041 3042 ivd_ctl_set_config_op_t *ps_ctl_op = 3043 (ivd_ctl_set_config_op_t *)pv_api_op; 3044 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3045 UNUSED(pv_api_ip); 3046 3047 3048 { 3049 ps_dec->u4_app_disp_width = 0; 3050 ps_dec->u4_skip_frm_mask = 0; 3051 ps_dec->i4_decode_header = 1; 3052 3053 ps_ctl_op->u4_error_code = 0; 3054 } 3055 3056 3057 return ret; 3058} 3059/*****************************************************************************/ 3060/* */ 3061/* Function Name : ih264d_reset */ 3062/* */ 3063/* Description : */ 3064/* */ 3065/* Inputs :iv_obj_t decoder handle */ 3066/* :pv_api_ip pointer to input structure */ 3067/* :pv_api_op pointer to output structure */ 3068/* Globals : <Does it use any global variables?> */ 3069/* Outputs : */ 3070/* Returns : void */ 3071/* */ 3072/* Issues : none */ 3073/* */ 3074/* Revision History: */ 3075/* */ 3076/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3077/* 22 10 2008 100356 Draft */ 3078/* */ 3079/*****************************************************************************/ 3080WORD32 ih264d_delete(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3081{ 3082 dec_struct_t *ps_dec; 3083 ih264d_delete_ip_t *ps_ip = (ih264d_delete_ip_t *)pv_api_ip; 3084 ih264d_delete_op_t *ps_op = (ih264d_delete_op_t *)pv_api_op; 3085 3086 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3087 UNUSED(ps_ip); 3088 ps_op->s_ivd_delete_op_t.u4_error_code = 0; 3089 ih264d_free_dynamic_bufs(ps_dec); 3090 ih264d_free_static_bufs(dec_hdl); 3091 return IV_SUCCESS; 3092} 3093/*****************************************************************************/ 3094/* */ 3095/* Function Name : ih264d_reset */ 3096/* */ 3097/* Description : */ 3098/* */ 3099/* Inputs :iv_obj_t decoder handle */ 3100/* :pv_api_ip pointer to input structure */ 3101/* :pv_api_op pointer to output structure */ 3102/* Globals : <Does it use any global variables?> */ 3103/* Outputs : */ 3104/* Returns : void */ 3105/* */ 3106/* Issues : none */ 3107/* */ 3108/* Revision History: */ 3109/* */ 3110/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3111/* 22 10 2008 100356 Draft */ 3112/* */ 3113/*****************************************************************************/ 3114WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3115{ 3116 dec_struct_t * ps_dec; 3117 ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op; 3118 UNUSED(pv_api_ip); 3119 ps_ctl_op->u4_error_code = 0; 3120 3121 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3122 3123 if(ps_dec != NULL) 3124 { 3125 ih264d_init_decoder(ps_dec); 3126 } 3127 else 3128 { 3129 H264_DEC_DEBUG_PRINT( 3130 "\nReset called without Initializing the decoder\n"); 3131 ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE; 3132 } 3133 3134 return IV_SUCCESS; 3135} 3136 3137/*****************************************************************************/ 3138/* */ 3139/* Function Name : ih264d_ctl */ 3140/* */ 3141/* Description : */ 3142/* */ 3143/* Inputs :iv_obj_t decoder handle */ 3144/* :pv_api_ip pointer to input structure */ 3145/* :pv_api_op pointer to output structure */ 3146/* Outputs : */ 3147/* Returns : void */ 3148/* */ 3149/* Issues : none */ 3150/* */ 3151/* Revision History: */ 3152/* */ 3153/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3154/* 22 10 2008 100356 Draft */ 3155/* */ 3156/*****************************************************************************/ 3157WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3158{ 3159 ivd_ctl_set_config_ip_t *ps_ctl_ip; 3160 ivd_ctl_set_config_op_t *ps_ctl_op; 3161 WORD32 ret = IV_SUCCESS; 3162 UWORD32 subcommand; 3163 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3164 3165 if(ps_dec->init_done != 1) 3166 { 3167 //Return proper Error Code 3168 return IV_FAIL; 3169 } 3170 ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip; 3171 ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op; 3172 ps_ctl_op->u4_error_code = 0; 3173 subcommand = ps_ctl_ip->e_sub_cmd; 3174 3175 switch(subcommand) 3176 { 3177 case IVD_CMD_CTL_GETPARAMS: 3178 ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip, 3179 (void *)pv_api_op); 3180 break; 3181 case IVD_CMD_CTL_SETPARAMS: 3182 ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip, 3183 (void *)pv_api_op); 3184 break; 3185 case IVD_CMD_CTL_RESET: 3186 ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op); 3187 break; 3188 case IVD_CMD_CTL_SETDEFAULT: 3189 ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip, 3190 (void *)pv_api_op); 3191 break; 3192 case IVD_CMD_CTL_FLUSH: 3193 ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip, 3194 (void *)pv_api_op); 3195 break; 3196 case IVD_CMD_CTL_GETBUFINFO: 3197 ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip, 3198 (void *)pv_api_op); 3199 break; 3200 case IVD_CMD_CTL_GETVERSION: 3201 ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip, 3202 (void *)pv_api_op); 3203 break; 3204 case IH264D_CMD_CTL_DEGRADE: 3205 ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip, 3206 (void *)pv_api_op); 3207 break; 3208 3209 case IH264D_CMD_CTL_SET_NUM_CORES: 3210 ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip, 3211 (void *)pv_api_op); 3212 break; 3213 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS: 3214 ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip, 3215 (void *)pv_api_op); 3216 break; 3217 case IH264D_CMD_CTL_SET_PROCESSOR: 3218 ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip, 3219 (void *)pv_api_op); 3220 break; 3221 default: 3222 H264_DEC_DEBUG_PRINT("\ndo nothing\n") 3223 ; 3224 break; 3225 } 3226 3227 return ret; 3228} 3229/*****************************************************************************/ 3230/* */ 3231/* Function Name : ih264d_rel_display_frame */ 3232/* */ 3233/* Description : */ 3234/* */ 3235/* Inputs :iv_obj_t decoder handle */ 3236/* :pv_api_ip pointer to input structure */ 3237/* :pv_api_op pointer to output structure */ 3238/* Outputs : */ 3239/* Returns : void */ 3240/* */ 3241/* Issues : none */ 3242/* */ 3243/* Revision History: */ 3244/* */ 3245/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3246/* 22 10 2008 100356 Draft */ 3247/* */ 3248/*****************************************************************************/ 3249WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl, 3250 void *pv_api_ip, 3251 void *pv_api_op) 3252{ 3253 3254 ivd_rel_display_frame_ip_t *ps_rel_ip; 3255 ivd_rel_display_frame_op_t *ps_rel_op; 3256 UWORD32 buf_released = 0; 3257 3258 UWORD32 u4_ts = -1; 3259 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3260 3261 ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip; 3262 ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op; 3263 ps_rel_op->u4_error_code = 0; 3264 u4_ts = ps_rel_ip->u4_disp_buf_id; 3265 3266 if(0 == ps_dec->u4_share_disp_buf) 3267 { 3268 ps_dec->u4_disp_buf_mapping[u4_ts] = 0; 3269 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0; 3270 return IV_SUCCESS; 3271 } 3272 3273 if(ps_dec->pv_pic_buf_mgr != NULL) 3274 { 3275 if(1 == ps_dec->u4_disp_buf_mapping[u4_ts]) 3276 { 3277 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 3278 ps_rel_ip->u4_disp_buf_id, 3279 BUF_MGR_IO); 3280 ps_dec->u4_disp_buf_mapping[u4_ts] = 0; 3281 buf_released = 1; 3282 } 3283 } 3284 3285 if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released)) 3286 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1; 3287 3288 return IV_SUCCESS; 3289} 3290 3291/** 3292 ******************************************************************************* 3293 * 3294 * @brief 3295 * Sets degrade params 3296 * 3297 * @par Description: 3298 * Sets degrade params. 3299 * Refer to ih264d_ctl_degrade_ip_t definition for details 3300 * 3301 * @param[in] ps_codec_obj 3302 * Pointer to codec object at API level 3303 * 3304 * @param[in] pv_api_ip 3305 * Pointer to input argument structure 3306 * 3307 * @param[out] pv_api_op 3308 * Pointer to output argument structure 3309 * 3310 * @returns Status 3311 * 3312 * @remarks 3313 * 3314 * 3315 ******************************************************************************* 3316 */ 3317 3318WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj, 3319 void *pv_api_ip, 3320 void *pv_api_op) 3321{ 3322 ih264d_ctl_degrade_ip_t *ps_ip; 3323 ih264d_ctl_degrade_op_t *ps_op; 3324 dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle; 3325 3326 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip; 3327 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op; 3328 3329 ps_codec->i4_degrade_type = ps_ip->i4_degrade_type; 3330 ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval; 3331 ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics; 3332 3333 ps_op->u4_error_code = 0; 3334 ps_codec->i4_degrade_pic_cnt = 0; 3335 3336 return IV_SUCCESS; 3337} 3338 3339WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl, 3340 void *pv_api_ip, 3341 void *pv_api_op) 3342{ 3343 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip; 3344 ih264d_ctl_get_frame_dimensions_op_t *ps_op; 3345 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3346 UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset; 3347 3348 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 3349 3350 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op; 3351 UNUSED(ps_ip); 3352 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3353 { 3354 disp_wd = ps_dec->u2_disp_width; 3355 disp_ht = ps_dec->u2_disp_height; 3356 3357 if(0 == ps_dec->u4_share_disp_buf) 3358 { 3359 buffer_wd = disp_wd; 3360 buffer_ht = disp_ht; 3361 } 3362 else 3363 { 3364 buffer_wd = ps_dec->u2_frm_wd_y; 3365 buffer_ht = ps_dec->u2_frm_ht_y; 3366 } 3367 } 3368 else 3369 { 3370 disp_wd = 0; 3371 disp_ht = 0; 3372 3373 if(0 == ps_dec->u4_share_disp_buf) 3374 { 3375 buffer_wd = disp_wd; 3376 buffer_ht = disp_ht; 3377 } 3378 else 3379 { 3380 buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1); 3381 buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2); 3382 } 3383 } 3384 if(ps_dec->u4_app_disp_width > buffer_wd) 3385 buffer_wd = ps_dec->u4_app_disp_width; 3386 3387 if(0 == ps_dec->u4_share_disp_buf) 3388 { 3389 x_offset = 0; 3390 y_offset = 0; 3391 } 3392 else 3393 { 3394 y_offset = (PAD_LEN_Y_V << 1); 3395 x_offset = PAD_LEN_Y_H; 3396 3397 if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid)) 3398 && (0 != ps_dec->u2_crop_offset_y)) 3399 { 3400 y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y; 3401 x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y; 3402 } 3403 } 3404 3405 ps_op->u4_disp_wd[0] = disp_wd; 3406 ps_op->u4_disp_ht[0] = disp_ht; 3407 ps_op->u4_buffer_wd[0] = buffer_wd; 3408 ps_op->u4_buffer_ht[0] = buffer_ht; 3409 ps_op->u4_x_offset[0] = x_offset; 3410 ps_op->u4_y_offset[0] = y_offset; 3411 3412 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1) 3413 >> 1); 3414 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1) 3415 >> 1); 3416 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0] 3417 >> 1); 3418 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0] 3419 >> 1); 3420 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = 3421 (ps_op->u4_x_offset[0] >> 1); 3422 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = 3423 (ps_op->u4_y_offset[0] >> 1); 3424 3425 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 3426 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 3427 { 3428 ps_op->u4_disp_wd[2] = 0; 3429 ps_op->u4_disp_ht[2] = 0; 3430 ps_op->u4_buffer_wd[2] = 0; 3431 ps_op->u4_buffer_ht[2] = 0; 3432 ps_op->u4_x_offset[2] = 0; 3433 ps_op->u4_y_offset[2] = 0; 3434 3435 ps_op->u4_disp_wd[1] <<= 1; 3436 ps_op->u4_buffer_wd[1] <<= 1; 3437 ps_op->u4_x_offset[1] <<= 1; 3438 } 3439 3440 return IV_SUCCESS; 3441 3442} 3443 3444WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3445{ 3446 ih264d_ctl_set_num_cores_ip_t *ps_ip; 3447 ih264d_ctl_set_num_cores_op_t *ps_op; 3448 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3449 3450 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip; 3451 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op; 3452 ps_op->u4_error_code = 0; 3453 ps_dec->u4_num_cores = ps_ip->u4_num_cores; 3454 if(ps_dec->u4_num_cores == 1) 3455 { 3456 ps_dec->u1_separate_parse = 0; 3457 } 3458 else 3459 { 3460 ps_dec->u1_separate_parse = 1; 3461 } 3462 3463 /*using only upto three threads currently*/ 3464 if(ps_dec->u4_num_cores > 3) 3465 ps_dec->u4_num_cores = 3; 3466 3467 return IV_SUCCESS; 3468} 3469 3470void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec, 3471 ivd_video_decode_op_t *ps_dec_op) 3472{ 3473 if((ps_dec_op->u4_error_code & 0xff) 3474 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED) 3475 { 3476 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 3477 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 3478 } 3479 ps_dec_op->e_pic_type = ps_dec->i4_frametype; 3480 3481 ps_dec_op->u4_new_seq = 0; 3482 ps_dec_op->u4_output_present = ps_dec->u4_output_present; 3483 ps_dec_op->u4_progressive_frame_flag = 3484 ps_dec->s_disp_op.u4_progressive_frame_flag; 3485 3486 ps_dec_op->u4_is_ref_flag = 1; 3487 if(ps_dec_op->u4_frame_decoded_flag) 3488 { 3489 if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0) 3490 ps_dec_op->u4_is_ref_flag = 0; 3491 } 3492 3493 ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format; 3494 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf; 3495 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type; 3496 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts; 3497 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id; 3498} 3499 3500/*****************************************************************************/ 3501/* */ 3502/* Function Name : ih264d_api_function */ 3503/* */ 3504/* Description : */ 3505/* */ 3506/* Inputs :iv_obj_t decoder handle */ 3507/* :pv_api_ip pointer to input structure */ 3508/* :pv_api_op pointer to output structure */ 3509/* Outputs : */ 3510/* Returns : void */ 3511/* */ 3512/* Issues : none */ 3513/* */ 3514/* Revision History: */ 3515/* */ 3516/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3517/* 22 10 2008 100356 Draft */ 3518/* */ 3519/*****************************************************************************/ 3520IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl, 3521 void *pv_api_ip, 3522 void *pv_api_op) 3523{ 3524 UWORD32 command; 3525 UWORD32 *pu2_ptr_cmd; 3526 UWORD32 u4_api_ret; 3527 IV_API_CALL_STATUS_T e_status; 3528 e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op); 3529 3530 if(e_status != IV_SUCCESS) 3531 { 3532 UWORD32 *ptr_err; 3533 3534 ptr_err = (UWORD32 *)pv_api_op; 3535 UNUSED(ptr_err); 3536 H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1)); 3537 return IV_FAIL; 3538 } 3539 3540 pu2_ptr_cmd = (UWORD32 *)pv_api_ip; 3541 pu2_ptr_cmd++; 3542 3543 command = *pu2_ptr_cmd; 3544// H264_DEC_DEBUG_PRINT("inside lib = %d\n",command); 3545 switch(command) 3546 { 3547 3548 case IVD_CMD_CREATE: 3549 u4_api_ret = ih264d_create(dec_hdl, (void *)pv_api_ip, 3550 (void *)pv_api_op); 3551 break; 3552 case IVD_CMD_DELETE: 3553 u4_api_ret = ih264d_delete(dec_hdl, (void *)pv_api_ip, 3554 (void *)pv_api_op); 3555 break; 3556 3557 case IVD_CMD_VIDEO_DECODE: 3558 u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip, 3559 (void *)pv_api_op); 3560 break; 3561 3562 case IVD_CMD_GET_DISPLAY_FRAME: 3563 u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip, 3564 (void *)pv_api_op); 3565 3566 break; 3567 3568 case IVD_CMD_SET_DISPLAY_FRAME: 3569 u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip, 3570 (void *)pv_api_op); 3571 3572 break; 3573 3574 case IVD_CMD_REL_DISPLAY_FRAME: 3575 u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip, 3576 (void *)pv_api_op); 3577 break; 3578 3579 case IVD_CMD_VIDEO_CTL: 3580 u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip, 3581 (void *)pv_api_op); 3582 break; 3583 default: 3584 u4_api_ret = IV_FAIL; 3585 break; 3586 } 3587 3588 return u4_api_ret; 3589} 3590