ih264d_api.c revision 494561291a503840f385fbcd11d9bc5f4dc502b8
1/****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19*/ 20 21/*****************************************************************************/ 22/* */ 23/* File Name : ih264d_api.c */ 24/* */ 25/* Description : Has all API related functions */ 26/* */ 27/* */ 28/* List of Functions : api_check_struct_sanity */ 29/* ih264d_set_processor */ 30/* ih264d_get_num_rec */ 31/* ih264d_init_decoder */ 32/* ih264d_init_video_decoder */ 33/* ih264d_fill_num_mem_rec */ 34/* ih264d_clr */ 35/* ih264d_init */ 36/* ih264d_map_error */ 37/* ih264d_video_decode */ 38/* ih264d_get_version */ 39/* ih264d_get_display_frame */ 40/* ih264d_set_display_frame */ 41/* ih264d_set_flush_mode */ 42/* ih264d_get_status */ 43/* ih264d_get_buf_info */ 44/* ih264d_set_params */ 45/* ih264d_set_default_params */ 46/* ih264d_reset */ 47/* ih264d_ctl */ 48/* ih264d_rel_display_frame */ 49/* ih264d_set_degrade */ 50/* ih264d_get_frame_dimensions */ 51/* ih264d_set_num_cores */ 52/* ih264d_fill_output_struct_from_context */ 53/* ih264d_api_function */ 54/* */ 55/* Issues / Problems : None */ 56/* */ 57/* Revision History : */ 58/* */ 59/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 60/* 14 10 2008 100356(SKV) Draft */ 61/* */ 62/*****************************************************************************/ 63#include "ih264_typedefs.h" 64#include "ih264_macros.h" 65#include "ih264_platform_macros.h" 66#include "ih264d_tables.h" 67#include "iv.h" 68#include "ivd.h" 69#include "ih264d.h" 70#include "ih264d_defs.h" 71 72#include <string.h> 73#include <limits.h> 74#include <stddef.h> 75 76#include "ih264d_inter_pred.h" 77 78#include "ih264d_structs.h" 79#include "ih264d_nal.h" 80#include "ih264d_error_handler.h" 81 82#include "ih264d_defs.h" 83 84#include "ithread.h" 85#include "ih264d_parse_slice.h" 86#include "ih264d_function_selector.h" 87#include "ih264_error.h" 88#include "ih264_disp_mgr.h" 89#include "ih264_buf_mgr.h" 90#include "ih264d_deblocking.h" 91#include "ih264d_parse_cavlc.h" 92#include "ih264d_parse_cabac.h" 93#include "ih264d_utils.h" 94#include "ih264d_format_conv.h" 95#include "ih264d_parse_headers.h" 96#include "ih264d_thread_compute_bs.h" 97#include <assert.h> 98 99 100/*********************/ 101/* Codec Versioning */ 102/*********************/ 103//Move this to where it is used 104#define CODEC_NAME "H264VDEC" 105#define CODEC_RELEASE_TYPE "production" 106#define CODEC_RELEASE_VER "04.00" 107#define CODEC_VENDOR "ITTIAM" 108#define MAXVERSION_STRLEN 511 109#define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \ 110 snprintf(version_string, MAXVERSION_STRLEN, \ 111 "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s", \ 112 codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__) 113 114#define MAX_NAL_UNIT_SIZE MAX((H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_HEIGHT),MIN_NALUNIT_SIZE) 115#define MIN_NALUNIT_SIZE 200000 116 117 118#define MIN_IN_BUFS 1 119#define MIN_OUT_BUFS_420 3 120#define MIN_OUT_BUFS_422ILE 1 121#define MIN_OUT_BUFS_RGB565 1 122#define MIN_OUT_BUFS_420SP 2 123#define MIN_IN_BUF_SIZE (2*1024*1024) // Currently, i4_size set to 500kb, CHECK LATER 124 125#define NUM_FRAMES_LIMIT_ENABLED 0 126 127#if NUM_FRAMES_LIMIT_ENABLED 128#define NUM_FRAMES_LIMIT 10000 129#else 130#define NUM_FRAMES_LIMIT 0x7FFFFFFF 131#endif 132 133 134UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height); 135WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl, 136 void *pv_api_ip, 137 void *pv_api_op); 138WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op); 139 140WORD32 ih264d_deblock_display(dec_struct_t *ps_dec); 141 142void ih264d_signal_decode_thread(dec_struct_t *ps_dec); 143 144void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec); 145void ih264d_decode_picture_thread(dec_struct_t *ps_dec); 146 147WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj, 148 void *pv_api_ip, 149 void *pv_api_op); 150 151void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec, 152 ivd_video_decode_op_t *ps_dec_op); 153 154static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle, 155 void *pv_api_ip, 156 void *pv_api_op) 157{ 158 IVD_API_COMMAND_TYPE_T e_cmd; 159 UWORD32 *pu4_api_ip; 160 UWORD32 *pu4_api_op; 161 UWORD32 i, j; 162 163 if(NULL == pv_api_op) 164 return (IV_FAIL); 165 166 if(NULL == pv_api_ip) 167 return (IV_FAIL); 168 169 pu4_api_ip = (UWORD32 *)pv_api_ip; 170 pu4_api_op = (UWORD32 *)pv_api_op; 171 e_cmd = *(pu4_api_ip + 1); 172 173 /* error checks on handle */ 174 switch((WORD32)e_cmd) 175 { 176 case IV_CMD_GET_NUM_MEM_REC: 177 case IV_CMD_FILL_NUM_MEM_REC: 178 break; 179 case IV_CMD_INIT: 180 if(ps_handle == NULL) 181 { 182 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 183 *(pu4_api_op + 1) |= IVD_HANDLE_NULL; 184 return IV_FAIL; 185 } 186 187 if(ps_handle->u4_size != sizeof(iv_obj_t)) 188 { 189 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 190 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT; 191 H264_DEC_DEBUG_PRINT( 192 "Sizes do not match. Expected: %d, Got: %d", 193 sizeof(iv_obj_t), ps_handle->u4_size); 194 return IV_FAIL; 195 } 196 break; 197 case IVD_CMD_REL_DISPLAY_FRAME: 198 case IVD_CMD_SET_DISPLAY_FRAME: 199 case IVD_CMD_GET_DISPLAY_FRAME: 200 case IVD_CMD_VIDEO_DECODE: 201 case IV_CMD_RETRIEVE_MEMREC: 202 case IVD_CMD_VIDEO_CTL: 203 if(ps_handle == NULL) 204 { 205 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 206 *(pu4_api_op + 1) |= IVD_HANDLE_NULL; 207 return IV_FAIL; 208 } 209 210 if(ps_handle->u4_size != sizeof(iv_obj_t)) 211 { 212 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 213 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT; 214 return IV_FAIL; 215 } 216 217 if(ps_handle->pv_fxns != ih264d_api_function) 218 { 219 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 220 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 221 return IV_FAIL; 222 } 223 224 if(ps_handle->pv_codec_handle == NULL) 225 { 226 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 227 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 228 return IV_FAIL; 229 } 230 break; 231 default: 232 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 233 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD; 234 return IV_FAIL; 235 } 236 237 switch((WORD32)e_cmd) 238 { 239 case IV_CMD_GET_NUM_MEM_REC: 240 { 241 ih264d_num_mem_rec_ip_t *ps_ip = 242 (ih264d_num_mem_rec_ip_t *)pv_api_ip; 243 ih264d_num_mem_rec_op_t *ps_op = 244 (ih264d_num_mem_rec_op_t *)pv_api_op; 245 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0; 246 247 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size 248 != sizeof(ih264d_num_mem_rec_ip_t)) 249 { 250 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 251 << IVD_UNSUPPORTEDPARAM; 252 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 253 IVD_IP_API_STRUCT_SIZE_INCORRECT; 254 return (IV_FAIL); 255 } 256 257 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size 258 != sizeof(ih264d_num_mem_rec_op_t)) 259 { 260 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 261 << IVD_UNSUPPORTEDPARAM; 262 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 263 IVD_OP_API_STRUCT_SIZE_INCORRECT; 264 return (IV_FAIL); 265 } 266 } 267 break; 268 case IV_CMD_FILL_NUM_MEM_REC: 269 { 270 ih264d_fill_mem_rec_ip_t *ps_ip = 271 (ih264d_fill_mem_rec_ip_t *)pv_api_ip; 272 ih264d_fill_mem_rec_op_t *ps_op = 273 (ih264d_fill_mem_rec_op_t *)pv_api_op; 274 iv_mem_rec_t *ps_mem_rec; 275 WORD32 max_wd = ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd; 276 WORD32 max_ht = ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht; 277 278 max_wd = ALIGN16(max_wd); 279 max_ht = ALIGN32(max_ht); 280 281 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0; 282 283 if((ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size 284 > sizeof(ih264d_fill_mem_rec_ip_t)) 285 || (ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size 286 < sizeof(iv_fill_mem_rec_ip_t))) 287 { 288 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 289 << IVD_UNSUPPORTEDPARAM; 290 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 291 IVD_IP_API_STRUCT_SIZE_INCORRECT; 292 return (IV_FAIL); 293 } 294 295 if((ps_op->s_ivd_fill_mem_rec_op_t.u4_size 296 != sizeof(ih264d_fill_mem_rec_op_t)) 297 && (ps_op->s_ivd_fill_mem_rec_op_t.u4_size 298 != sizeof(iv_fill_mem_rec_op_t))) 299 { 300 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 301 << IVD_UNSUPPORTEDPARAM; 302 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 303 IVD_OP_API_STRUCT_SIZE_INCORRECT; 304 return (IV_FAIL); 305 } 306 307 if(max_wd < H264_MIN_FRAME_WIDTH) 308 { 309 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 310 << IVD_UNSUPPORTEDPARAM; 311 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 312 IVD_REQUESTED_WIDTH_NOT_SUPPPORTED; 313 return (IV_FAIL); 314 } 315 316 if(max_wd > H264_MAX_FRAME_WIDTH) 317 { 318 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 319 << IVD_UNSUPPORTEDPARAM; 320 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 321 IVD_REQUESTED_WIDTH_NOT_SUPPPORTED; 322 return (IV_FAIL); 323 } 324 325 if(max_ht < H264_MIN_FRAME_HEIGHT) 326 { 327 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 328 << IVD_UNSUPPORTEDPARAM; 329 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 330 IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED; 331 return (IV_FAIL); 332 } 333 334 if((max_ht * max_wd) 335 > (H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_WIDTH)) 336 337 { 338 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 339 << IVD_UNSUPPORTEDPARAM; 340 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 341 IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED; 342 return (IV_FAIL); 343 } 344 345 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location) 346 { 347 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 348 << IVD_UNSUPPORTEDPARAM; 349 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 350 IVD_NUM_REC_NOT_SUFFICIENT; 351 return (IV_FAIL); 352 } 353 354 /* check memrecords sizes are correct */ 355 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location; 356 for(i = 0; i < MEM_REC_CNT; i++) 357 { 358 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 359 { 360 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 361 << IVD_UNSUPPORTEDPARAM; 362 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 363 IVD_MEM_REC_STRUCT_SIZE_INCORRECT; 364 return IV_FAIL; 365 } 366 } 367 } 368 break; 369 370 case IV_CMD_INIT: 371 { 372 ih264d_init_ip_t *ps_ip = (ih264d_init_ip_t *)pv_api_ip; 373 ih264d_init_op_t *ps_op = (ih264d_init_op_t *)pv_api_op; 374 iv_mem_rec_t *ps_mem_rec; 375 WORD32 max_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd; 376 WORD32 max_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht; 377 378 max_wd = ALIGN16(max_wd); 379 max_ht = ALIGN32(max_ht); 380 381 ps_op->s_ivd_init_op_t.u4_error_code = 0; 382 383 if((ps_ip->s_ivd_init_ip_t.u4_size > sizeof(ih264d_init_ip_t)) 384 || (ps_ip->s_ivd_init_ip_t.u4_size 385 < sizeof(ivd_init_ip_t))) 386 { 387 ps_op->s_ivd_init_op_t.u4_error_code |= 1 388 << IVD_UNSUPPORTEDPARAM; 389 ps_op->s_ivd_init_op_t.u4_error_code |= 390 IVD_IP_API_STRUCT_SIZE_INCORRECT; 391 H264_DEC_DEBUG_PRINT("\n"); 392 return (IV_FAIL); 393 } 394 395 if((ps_op->s_ivd_init_op_t.u4_size != sizeof(ih264d_init_op_t)) 396 && (ps_op->s_ivd_init_op_t.u4_size 397 != sizeof(ivd_init_op_t))) 398 { 399 ps_op->s_ivd_init_op_t.u4_error_code |= 1 400 << IVD_UNSUPPORTEDPARAM; 401 ps_op->s_ivd_init_op_t.u4_error_code |= 402 IVD_OP_API_STRUCT_SIZE_INCORRECT; 403 H264_DEC_DEBUG_PRINT("\n"); 404 return (IV_FAIL); 405 } 406 407 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec != MEM_REC_CNT) 408 { 409 ps_op->s_ivd_init_op_t.u4_error_code |= 1 410 << IVD_UNSUPPORTEDPARAM; 411 ps_op->s_ivd_init_op_t.u4_error_code |= 412 IVD_INIT_DEC_NOT_SUFFICIENT; 413 H264_DEC_DEBUG_PRINT("\n"); 414 return (IV_FAIL); 415 } 416 417 if(max_wd < H264_MIN_FRAME_WIDTH) 418 { 419 ps_op->s_ivd_init_op_t.u4_error_code |= 1 420 << IVD_UNSUPPORTEDPARAM; 421 ps_op->s_ivd_init_op_t.u4_error_code |= 422 IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED; 423 H264_DEC_DEBUG_PRINT("\n"); 424 return (IV_FAIL); 425 } 426 427 if(max_wd > H264_MAX_FRAME_WIDTH) 428 { 429 ps_op->s_ivd_init_op_t.u4_error_code |= 1 430 << IVD_UNSUPPORTEDPARAM; 431 ps_op->s_ivd_init_op_t.u4_error_code |= 432 IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED; 433 H264_DEC_DEBUG_PRINT("\n"); 434 return (IV_FAIL); 435 } 436 437 if(max_ht < H264_MIN_FRAME_HEIGHT) 438 { 439 ps_op->s_ivd_init_op_t.u4_error_code |= 1 440 << IVD_UNSUPPORTEDPARAM; 441 ps_op->s_ivd_init_op_t.u4_error_code |= 442 IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED; 443 H264_DEC_DEBUG_PRINT("\n"); 444 return (IV_FAIL); 445 } 446 447 if((max_ht * max_wd) 448 > (H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_WIDTH)) 449 450 { 451 ps_op->s_ivd_init_op_t.u4_error_code |= 1 452 << IVD_UNSUPPORTEDPARAM; 453 ps_op->s_ivd_init_op_t.u4_error_code |= 454 IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED; 455 H264_DEC_DEBUG_PRINT("\n"); 456 return (IV_FAIL); 457 } 458 459 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location) 460 { 461 ps_op->s_ivd_init_op_t.u4_error_code |= 1 462 << IVD_UNSUPPORTEDPARAM; 463 ps_op->s_ivd_init_op_t.u4_error_code |= 464 IVD_NUM_REC_NOT_SUFFICIENT; 465 H264_DEC_DEBUG_PRINT("\n"); 466 return (IV_FAIL); 467 } 468 469 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) 470 && (ps_ip->s_ivd_init_ip_t.e_output_format 471 != IV_YUV_422ILE) 472 && (ps_ip->s_ivd_init_ip_t.e_output_format 473 != IV_RGB_565) 474 && (ps_ip->s_ivd_init_ip_t.e_output_format 475 != IV_YUV_420SP_UV) 476 && (ps_ip->s_ivd_init_ip_t.e_output_format 477 != IV_YUV_420SP_VU)) 478 { 479 ps_op->s_ivd_init_op_t.u4_error_code |= 1 480 << IVD_UNSUPPORTEDPARAM; 481 ps_op->s_ivd_init_op_t.u4_error_code |= 482 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED; 483 H264_DEC_DEBUG_PRINT("\n"); 484 return (IV_FAIL); 485 } 486 487 /* verify number of mem records */ 488 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < MEM_REC_CNT) 489 { 490 ps_op->s_ivd_init_op_t.u4_error_code |= 1 491 << IVD_UNSUPPORTEDPARAM; 492 ps_op->s_ivd_init_op_t.u4_error_code |= 493 IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT; 494 H264_DEC_DEBUG_PRINT("\n"); 495 return IV_FAIL; 496 } 497 498 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location; 499 /* check memrecords sizes are correct */ 500 for(i = 0; i < ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++) 501 { 502 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 503 { 504 ps_op->s_ivd_init_op_t.u4_error_code |= 1 505 << IVD_UNSUPPORTEDPARAM; 506 ps_op->s_ivd_init_op_t.u4_error_code |= 507 IVD_MEM_REC_STRUCT_SIZE_INCORRECT; 508 H264_DEC_DEBUG_PRINT("i: %d\n", i); 509 return IV_FAIL; 510 } 511 /* check memrecords pointers are not NULL */ 512 513 if(ps_mem_rec[i].pv_base == NULL) 514 { 515 516 ps_op->s_ivd_init_op_t.u4_error_code |= 1 517 << IVD_UNSUPPORTEDPARAM; 518 ps_op->s_ivd_init_op_t.u4_error_code |= 519 IVD_INIT_DEC_MEM_REC_BASE_NULL; 520 H264_DEC_DEBUG_PRINT("i: %d\n", i); 521 return IV_FAIL; 522 523 } 524 525 } 526 527 /* verify memtabs for overlapping regions */ 528 { 529 void *start[MEM_REC_CNT]; 530 void *end[MEM_REC_CNT]; 531 532 start[0] = (void *)(ps_mem_rec[0].pv_base); 533 end[0] = (void *)((UWORD8 *)ps_mem_rec[0].pv_base 534 + ps_mem_rec[0].u4_mem_size - 1); 535 for(i = 1; i < MEM_REC_CNT; i++) 536 { 537 /* This array is populated to check memtab overlapp */ 538 start[i] = (void *)(ps_mem_rec[i].pv_base); 539 end[i] = (void *)((UWORD8 *)ps_mem_rec[i].pv_base 540 + ps_mem_rec[i].u4_mem_size - 1); 541 542 for(j = 0; j < i; j++) 543 { 544 if((start[i] >= start[j]) && (start[i] <= end[j])) 545 { 546 ps_op->s_ivd_init_op_t.u4_error_code |= 1 547 << IVD_UNSUPPORTEDPARAM; 548 ps_op->s_ivd_init_op_t.u4_error_code |= 549 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR; 550 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j); 551 return IV_FAIL; 552 } 553 554 if((end[i] >= start[j]) && (end[i] <= end[j])) 555 { 556 ps_op->s_ivd_init_op_t.u4_error_code |= 1 557 << IVD_UNSUPPORTEDPARAM; 558 ps_op->s_ivd_init_op_t.u4_error_code |= 559 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR; 560 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j); 561 return IV_FAIL; 562 } 563 564 if((start[i] < start[j]) && (end[i] > end[j])) 565 { 566 ps_op->s_ivd_init_op_t.u4_error_code |= 1 567 << IVD_UNSUPPORTEDPARAM; 568 ps_op->s_ivd_init_op_t.u4_error_code |= 569 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR; 570 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j); 571 return IV_FAIL; 572 } 573 } 574 575 } 576 } 577 578 { 579 iv_mem_rec_t mem_rec_ittiam_api[MEM_REC_CNT]; 580 ih264d_fill_mem_rec_ip_t s_fill_mem_rec_ip; 581 ih264d_fill_mem_rec_op_t s_fill_mem_rec_op; 582 IV_API_CALL_STATUS_T e_status; 583 584 UWORD32 i; 585 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd = 586 IV_CMD_FILL_NUM_MEM_REC; 587 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location = 588 mem_rec_ittiam_api; 589 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd = 590 max_wd; 591 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht = 592 max_ht; 593 594 if(ps_ip->s_ivd_init_ip_t.u4_size 595 > offsetof(ih264d_init_ip_t, i4_level)) 596 { 597 s_fill_mem_rec_ip.i4_level = ps_ip->i4_level; 598 } 599 else 600 { 601 s_fill_mem_rec_ip.i4_level = H264_LEVEL_3_1; 602 } 603 604 if(ps_ip->s_ivd_init_ip_t.u4_size 605 > offsetof(ih264d_init_ip_t, u4_num_ref_frames)) 606 { 607 s_fill_mem_rec_ip.u4_num_ref_frames = 608 ps_ip->u4_num_ref_frames; 609 } 610 else 611 { 612 s_fill_mem_rec_ip.u4_num_ref_frames = 613 (H264_MAX_REF_PICS + 1); 614 } 615 616 if(ps_ip->s_ivd_init_ip_t.u4_size 617 > offsetof(ih264d_init_ip_t, 618 u4_num_reorder_frames)) 619 { 620 s_fill_mem_rec_ip.u4_num_reorder_frames = 621 ps_ip->u4_num_reorder_frames; 622 } 623 else 624 { 625 s_fill_mem_rec_ip.u4_num_reorder_frames = (H264_MAX_REF_PICS 626 + 1); 627 } 628 629 if(ps_ip->s_ivd_init_ip_t.u4_size 630 > offsetof(ih264d_init_ip_t, 631 u4_num_extra_disp_buf)) 632 { 633 s_fill_mem_rec_ip.u4_num_extra_disp_buf = 634 ps_ip->u4_num_extra_disp_buf; 635 } 636 else 637 { 638 s_fill_mem_rec_ip.u4_num_extra_disp_buf = 0; 639 } 640 641 if(ps_ip->s_ivd_init_ip_t.u4_size 642 > offsetof(ih264d_init_ip_t, u4_share_disp_buf)) 643 { 644#ifndef LOGO_EN 645 s_fill_mem_rec_ip.u4_share_disp_buf = 646 ps_ip->u4_share_disp_buf; 647#else 648 s_fill_mem_rec_ip.u4_share_disp_buf = 0; 649#endif 650 } 651 else 652 { 653 s_fill_mem_rec_ip.u4_share_disp_buf = 0; 654 } 655 656 s_fill_mem_rec_ip.e_output_format = 657 ps_ip->s_ivd_init_ip_t.e_output_format; 658 659 if((s_fill_mem_rec_ip.e_output_format != IV_YUV_420P) 660 && (s_fill_mem_rec_ip.e_output_format 661 != IV_YUV_420SP_UV) 662 && (s_fill_mem_rec_ip.e_output_format 663 != IV_YUV_420SP_VU)) 664 { 665 s_fill_mem_rec_ip.u4_share_disp_buf = 0; 666 } 667 668 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size = 669 sizeof(ih264d_fill_mem_rec_ip_t); 670 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size = 671 sizeof(ih264d_fill_mem_rec_op_t); 672 673 for(i = 0; i < MEM_REC_CNT; i++) 674 mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t); 675 676 e_status = ih264d_api_function(NULL, 677 (void *)&s_fill_mem_rec_ip, 678 (void *)&s_fill_mem_rec_op); 679 if(IV_FAIL == e_status) 680 { 681 ps_op->s_ivd_init_op_t.u4_error_code = 682 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code; 683 H264_DEC_DEBUG_PRINT("Fail\n"); 684 return (IV_FAIL); 685 } 686 687 for(i = 0; i < MEM_REC_CNT; i++) 688 { 689 if(ps_mem_rec[i].u4_mem_size 690 < mem_rec_ittiam_api[i].u4_mem_size) 691 { 692 ps_op->s_ivd_init_op_t.u4_error_code |= 1 693 << IVD_UNSUPPORTEDPARAM; 694 ps_op->s_ivd_init_op_t.u4_error_code |= 695 IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE; 696 H264_DEC_DEBUG_PRINT("i: %d \n", i); 697 return IV_FAIL; 698 } 699 if(ps_mem_rec[i].u4_mem_alignment 700 != mem_rec_ittiam_api[i].u4_mem_alignment) 701 { 702 ps_op->s_ivd_init_op_t.u4_error_code |= 1 703 << IVD_UNSUPPORTEDPARAM; 704 ps_op->s_ivd_init_op_t.u4_error_code |= 705 IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR; 706 H264_DEC_DEBUG_PRINT("i: %d \n", i); 707 return IV_FAIL; 708 } 709 if(ps_mem_rec[i].e_mem_type 710 != mem_rec_ittiam_api[i].e_mem_type) 711 { 712 UWORD32 check = IV_SUCCESS; 713 UWORD32 diff = mem_rec_ittiam_api[i].e_mem_type 714 - ps_mem_rec[i].e_mem_type; 715 716 if((ps_mem_rec[i].e_mem_type 717 <= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM) 718 && (mem_rec_ittiam_api[i].e_mem_type 719 >= IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM)) 720 { 721 check = IV_FAIL; 722 } 723 if(3 != MOD(mem_rec_ittiam_api[i].e_mem_type, 4)) 724 { 725 /* 726 * It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM 727 */ 728 if((diff < 1) || (diff > 3)) 729 { 730 // Difference between 1 and 3 is okay for all cases other than the two filtered 731 // with the MOD condition above 732 check = IV_FAIL; 733 } 734 } 735 else 736 { 737 if(diff == 1) 738 { 739 /* 740 * This particular case is when codec asked for External Persistent, but got 741 * Internal Scratch. 742 */ 743 check = IV_FAIL; 744 } 745 if((diff != 2) && (diff != 3)) 746 { 747 check = IV_FAIL; 748 } 749 } 750 if(check == IV_FAIL) 751 { 752 ps_op->s_ivd_init_op_t.u4_error_code |= 1 753 << IVD_UNSUPPORTEDPARAM; 754 ps_op->s_ivd_init_op_t.u4_error_code |= 755 IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE; 756 H264_DEC_DEBUG_PRINT("i: %d \n", i); 757 return IV_FAIL; 758 } 759 } 760 } 761 } 762 763 } 764 break; 765 766 case IVD_CMD_GET_DISPLAY_FRAME: 767 { 768 ih264d_get_display_frame_ip_t *ps_ip = 769 (ih264d_get_display_frame_ip_t *)pv_api_ip; 770 ih264d_get_display_frame_op_t *ps_op = 771 (ih264d_get_display_frame_op_t *)pv_api_op; 772 773 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0; 774 775 if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size 776 != sizeof(ih264d_get_display_frame_ip_t)) 777 && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size 778 != sizeof(ivd_get_display_frame_ip_t))) 779 { 780 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 781 << IVD_UNSUPPORTEDPARAM; 782 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 783 IVD_IP_API_STRUCT_SIZE_INCORRECT; 784 return (IV_FAIL); 785 } 786 787 if((ps_op->s_ivd_get_display_frame_op_t.u4_size 788 != sizeof(ih264d_get_display_frame_op_t)) 789 && (ps_op->s_ivd_get_display_frame_op_t.u4_size 790 != sizeof(ivd_get_display_frame_op_t))) 791 { 792 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 793 << IVD_UNSUPPORTEDPARAM; 794 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 795 IVD_OP_API_STRUCT_SIZE_INCORRECT; 796 return (IV_FAIL); 797 } 798 } 799 break; 800 801 case IVD_CMD_REL_DISPLAY_FRAME: 802 { 803 ih264d_rel_display_frame_ip_t *ps_ip = 804 (ih264d_rel_display_frame_ip_t *)pv_api_ip; 805 ih264d_rel_display_frame_op_t *ps_op = 806 (ih264d_rel_display_frame_op_t *)pv_api_op; 807 808 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0; 809 810 if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size 811 != sizeof(ih264d_rel_display_frame_ip_t)) 812 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size 813 != sizeof(ivd_rel_display_frame_ip_t))) 814 { 815 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 816 << IVD_UNSUPPORTEDPARAM; 817 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 818 IVD_IP_API_STRUCT_SIZE_INCORRECT; 819 return (IV_FAIL); 820 } 821 822 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size 823 != sizeof(ih264d_rel_display_frame_op_t)) 824 && (ps_op->s_ivd_rel_display_frame_op_t.u4_size 825 != sizeof(ivd_rel_display_frame_op_t))) 826 { 827 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 828 << IVD_UNSUPPORTEDPARAM; 829 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 830 IVD_OP_API_STRUCT_SIZE_INCORRECT; 831 return (IV_FAIL); 832 } 833 834 } 835 break; 836 837 case IVD_CMD_SET_DISPLAY_FRAME: 838 { 839 ih264d_set_display_frame_ip_t *ps_ip = 840 (ih264d_set_display_frame_ip_t *)pv_api_ip; 841 ih264d_set_display_frame_op_t *ps_op = 842 (ih264d_set_display_frame_op_t *)pv_api_op; 843 UWORD32 j; 844 845 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0; 846 847 if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size 848 != sizeof(ih264d_set_display_frame_ip_t)) 849 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size 850 != sizeof(ivd_set_display_frame_ip_t))) 851 { 852 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 853 << IVD_UNSUPPORTEDPARAM; 854 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 855 IVD_IP_API_STRUCT_SIZE_INCORRECT; 856 return (IV_FAIL); 857 } 858 859 if((ps_op->s_ivd_set_display_frame_op_t.u4_size 860 != sizeof(ih264d_set_display_frame_op_t)) 861 && (ps_op->s_ivd_set_display_frame_op_t.u4_size 862 != sizeof(ivd_set_display_frame_op_t))) 863 { 864 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 865 << IVD_UNSUPPORTEDPARAM; 866 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 867 IVD_OP_API_STRUCT_SIZE_INCORRECT; 868 return (IV_FAIL); 869 } 870 871 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0) 872 { 873 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 874 << IVD_UNSUPPORTEDPARAM; 875 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 876 IVD_DISP_FRM_ZERO_OP_BUFS; 877 return IV_FAIL; 878 } 879 880 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; 881 j++) 882 { 883 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs 884 == 0) 885 { 886 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 887 << IVD_UNSUPPORTEDPARAM; 888 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 889 IVD_DISP_FRM_ZERO_OP_BUFS; 890 return IV_FAIL; 891 } 892 893 for(i = 0; 894 i 895 < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs; 896 i++) 897 { 898 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] 899 == NULL) 900 { 901 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 902 << IVD_UNSUPPORTEDPARAM; 903 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 904 IVD_DISP_FRM_OP_BUF_NULL; 905 return IV_FAIL; 906 } 907 908 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] 909 == 0) 910 { 911 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 912 << IVD_UNSUPPORTEDPARAM; 913 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 914 IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 915 return IV_FAIL; 916 } 917 } 918 } 919 } 920 break; 921 922 case IVD_CMD_VIDEO_DECODE: 923 { 924 ih264d_video_decode_ip_t *ps_ip = 925 (ih264d_video_decode_ip_t *)pv_api_ip; 926 ih264d_video_decode_op_t *ps_op = 927 (ih264d_video_decode_op_t *)pv_api_op; 928 929 H264_DEC_DEBUG_PRINT("The input bytes is: %d", 930 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes); 931 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0; 932 933 if(ps_ip->s_ivd_video_decode_ip_t.u4_size 934 != sizeof(ih264d_video_decode_ip_t)&& 935 ps_ip->s_ivd_video_decode_ip_t.u4_size != offsetof(ivd_video_decode_ip_t, s_out_buffer)) 936 { 937 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 938 << IVD_UNSUPPORTEDPARAM; 939 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 940 IVD_IP_API_STRUCT_SIZE_INCORRECT; 941 return (IV_FAIL); 942 } 943 944 if(ps_op->s_ivd_video_decode_op_t.u4_size 945 != sizeof(ih264d_video_decode_op_t)&& 946 ps_op->s_ivd_video_decode_op_t.u4_size != offsetof(ivd_video_decode_op_t, u4_output_present)) 947 { 948 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 949 << IVD_UNSUPPORTEDPARAM; 950 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 951 IVD_OP_API_STRUCT_SIZE_INCORRECT; 952 return (IV_FAIL); 953 } 954 955 } 956 break; 957 958 case IV_CMD_RETRIEVE_MEMREC: 959 { 960 ih264d_retrieve_mem_rec_ip_t *ps_ip = 961 (ih264d_retrieve_mem_rec_ip_t *)pv_api_ip; 962 ih264d_retrieve_mem_rec_op_t *ps_op = 963 (ih264d_retrieve_mem_rec_op_t *)pv_api_op; 964 iv_mem_rec_t *ps_mem_rec; 965 966 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0; 967 968 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size 969 != sizeof(ih264d_retrieve_mem_rec_ip_t)) 970 { 971 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 972 << IVD_UNSUPPORTEDPARAM; 973 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 974 IVD_IP_API_STRUCT_SIZE_INCORRECT; 975 return (IV_FAIL); 976 } 977 978 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size 979 != sizeof(ih264d_retrieve_mem_rec_op_t)) 980 { 981 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 982 << IVD_UNSUPPORTEDPARAM; 983 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 984 IVD_OP_API_STRUCT_SIZE_INCORRECT; 985 return (IV_FAIL); 986 } 987 988 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location; 989 /* check memrecords sizes are correct */ 990 for(i = 0; i < MEM_REC_CNT; i++) 991 { 992 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 993 { 994 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 995 << IVD_UNSUPPORTEDPARAM; 996 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 997 IVD_MEM_REC_STRUCT_SIZE_INCORRECT; 998 return IV_FAIL; 999 } 1000 } 1001 } 1002 break; 1003 1004 case IVD_CMD_VIDEO_CTL: 1005 { 1006 UWORD32 *pu4_ptr_cmd; 1007 UWORD32 sub_command; 1008 1009 pu4_ptr_cmd = (UWORD32 *)pv_api_ip; 1010 pu4_ptr_cmd += 2; 1011 sub_command = *pu4_ptr_cmd; 1012 1013 switch(sub_command) 1014 { 1015 case IVD_CMD_CTL_SETPARAMS: 1016 { 1017 ih264d_ctl_set_config_ip_t *ps_ip; 1018 ih264d_ctl_set_config_op_t *ps_op; 1019 ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip; 1020 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op; 1021 1022 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size 1023 != sizeof(ih264d_ctl_set_config_ip_t)) 1024 { 1025 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 1026 << IVD_UNSUPPORTEDPARAM; 1027 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1028 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1029 return IV_FAIL; 1030 } 1031 } 1032 //no break; is needed here 1033 case IVD_CMD_CTL_SETDEFAULT: 1034 { 1035 ih264d_ctl_set_config_op_t *ps_op; 1036 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op; 1037 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size 1038 != sizeof(ih264d_ctl_set_config_op_t)) 1039 { 1040 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 1041 << IVD_UNSUPPORTEDPARAM; 1042 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1043 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1044 return IV_FAIL; 1045 } 1046 } 1047 break; 1048 1049 case IVD_CMD_CTL_GETPARAMS: 1050 { 1051 ih264d_ctl_getstatus_ip_t *ps_ip; 1052 ih264d_ctl_getstatus_op_t *ps_op; 1053 1054 ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip; 1055 ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op; 1056 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size 1057 != sizeof(ih264d_ctl_getstatus_ip_t)) 1058 { 1059 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 1060 << IVD_UNSUPPORTEDPARAM; 1061 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1062 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1063 return IV_FAIL; 1064 } 1065 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size 1066 != sizeof(ih264d_ctl_getstatus_op_t)) 1067 { 1068 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 1069 << IVD_UNSUPPORTEDPARAM; 1070 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1071 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1072 return IV_FAIL; 1073 } 1074 } 1075 break; 1076 1077 case IVD_CMD_CTL_GETBUFINFO: 1078 { 1079 ih264d_ctl_getbufinfo_ip_t *ps_ip; 1080 ih264d_ctl_getbufinfo_op_t *ps_op; 1081 ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip; 1082 ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op; 1083 1084 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size 1085 != sizeof(ih264d_ctl_getbufinfo_ip_t)) 1086 { 1087 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 1088 << IVD_UNSUPPORTEDPARAM; 1089 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1090 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1091 return IV_FAIL; 1092 } 1093 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size 1094 != sizeof(ih264d_ctl_getbufinfo_op_t)) 1095 { 1096 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 1097 << IVD_UNSUPPORTEDPARAM; 1098 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1099 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1100 return IV_FAIL; 1101 } 1102 } 1103 break; 1104 1105 case IVD_CMD_CTL_GETVERSION: 1106 { 1107 ih264d_ctl_getversioninfo_ip_t *ps_ip; 1108 ih264d_ctl_getversioninfo_op_t *ps_op; 1109 ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip; 1110 ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op; 1111 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size 1112 != sizeof(ih264d_ctl_getversioninfo_ip_t)) 1113 { 1114 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 1115 << IVD_UNSUPPORTEDPARAM; 1116 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1117 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1118 return IV_FAIL; 1119 } 1120 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size 1121 != sizeof(ih264d_ctl_getversioninfo_op_t)) 1122 { 1123 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 1124 << IVD_UNSUPPORTEDPARAM; 1125 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1126 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1127 return IV_FAIL; 1128 } 1129 } 1130 break; 1131 1132 case IVD_CMD_CTL_FLUSH: 1133 { 1134 ih264d_ctl_flush_ip_t *ps_ip; 1135 ih264d_ctl_flush_op_t *ps_op; 1136 ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip; 1137 ps_op = (ih264d_ctl_flush_op_t *)pv_api_op; 1138 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size 1139 != sizeof(ih264d_ctl_flush_ip_t)) 1140 { 1141 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 1142 << IVD_UNSUPPORTEDPARAM; 1143 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1144 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1145 return IV_FAIL; 1146 } 1147 if(ps_op->s_ivd_ctl_flush_op_t.u4_size 1148 != sizeof(ih264d_ctl_flush_op_t)) 1149 { 1150 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 1151 << IVD_UNSUPPORTEDPARAM; 1152 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1153 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1154 return IV_FAIL; 1155 } 1156 } 1157 break; 1158 1159 case IVD_CMD_CTL_RESET: 1160 { 1161 ih264d_ctl_reset_ip_t *ps_ip; 1162 ih264d_ctl_reset_op_t *ps_op; 1163 ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip; 1164 ps_op = (ih264d_ctl_reset_op_t *)pv_api_op; 1165 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size 1166 != sizeof(ih264d_ctl_reset_ip_t)) 1167 { 1168 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 1169 << IVD_UNSUPPORTEDPARAM; 1170 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1171 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1172 return IV_FAIL; 1173 } 1174 if(ps_op->s_ivd_ctl_reset_op_t.u4_size 1175 != sizeof(ih264d_ctl_reset_op_t)) 1176 { 1177 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 1178 << IVD_UNSUPPORTEDPARAM; 1179 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1180 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1181 return IV_FAIL; 1182 } 1183 } 1184 break; 1185 1186 case IH264D_CMD_CTL_DEGRADE: 1187 { 1188 ih264d_ctl_degrade_ip_t *ps_ip; 1189 ih264d_ctl_degrade_op_t *ps_op; 1190 1191 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip; 1192 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op; 1193 1194 if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t)) 1195 { 1196 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1197 ps_op->u4_error_code |= 1198 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1199 return IV_FAIL; 1200 } 1201 1202 if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t)) 1203 { 1204 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1205 ps_op->u4_error_code |= 1206 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1207 return IV_FAIL; 1208 } 1209 1210 if((ps_ip->i4_degrade_pics < 0) 1211 || (ps_ip->i4_degrade_pics > 4) 1212 || (ps_ip->i4_nondegrade_interval < 0) 1213 || (ps_ip->i4_degrade_type < 0) 1214 || (ps_ip->i4_degrade_type > 15)) 1215 { 1216 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1217 return IV_FAIL; 1218 } 1219 1220 break; 1221 } 1222 1223 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS: 1224 { 1225 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip; 1226 ih264d_ctl_get_frame_dimensions_op_t *ps_op; 1227 1228 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 1229 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op; 1230 1231 if(ps_ip->u4_size 1232 != sizeof(ih264d_ctl_get_frame_dimensions_ip_t)) 1233 { 1234 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1235 ps_op->u4_error_code |= 1236 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1237 return IV_FAIL; 1238 } 1239 1240 if(ps_op->u4_size 1241 != sizeof(ih264d_ctl_get_frame_dimensions_op_t)) 1242 { 1243 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1244 ps_op->u4_error_code |= 1245 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1246 return IV_FAIL; 1247 } 1248 1249 break; 1250 } 1251 1252 case IH264D_CMD_CTL_SET_NUM_CORES: 1253 { 1254 ih264d_ctl_set_num_cores_ip_t *ps_ip; 1255 ih264d_ctl_set_num_cores_op_t *ps_op; 1256 1257 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip; 1258 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op; 1259 1260 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t)) 1261 { 1262 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1263 ps_op->u4_error_code |= 1264 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1265 return IV_FAIL; 1266 } 1267 1268 if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t)) 1269 { 1270 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1271 ps_op->u4_error_code |= 1272 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1273 return IV_FAIL; 1274 } 1275 1276 if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2) 1277 && (ps_ip->u4_num_cores != 3) 1278 && (ps_ip->u4_num_cores != 4)) 1279 { 1280 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1281 return IV_FAIL; 1282 } 1283 break; 1284 } 1285 case IH264D_CMD_CTL_SET_PROCESSOR: 1286 { 1287 ih264d_ctl_set_processor_ip_t *ps_ip; 1288 ih264d_ctl_set_processor_op_t *ps_op; 1289 1290 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip; 1291 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op; 1292 1293 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t)) 1294 { 1295 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1296 ps_op->u4_error_code |= 1297 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1298 return IV_FAIL; 1299 } 1300 1301 if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t)) 1302 { 1303 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1304 ps_op->u4_error_code |= 1305 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1306 return IV_FAIL; 1307 } 1308 1309 break; 1310 } 1311 default: 1312 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 1313 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD; 1314 return IV_FAIL; 1315 break; 1316 } 1317 } 1318 break; 1319 } 1320 1321 return IV_SUCCESS; 1322} 1323 1324 1325/** 1326 ******************************************************************************* 1327 * 1328 * @brief 1329 * Sets Processor type 1330 * 1331 * @par Description: 1332 * Sets Processor type 1333 * 1334 * @param[in] ps_codec_obj 1335 * Pointer to codec object at API level 1336 * 1337 * @param[in] pv_api_ip 1338 * Pointer to input argument structure 1339 * 1340 * @param[out] pv_api_op 1341 * Pointer to output argument structure 1342 * 1343 * @returns Status 1344 * 1345 * @remarks 1346 * 1347 * 1348 ******************************************************************************* 1349 */ 1350 1351WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 1352{ 1353 ih264d_ctl_set_processor_ip_t *ps_ip; 1354 ih264d_ctl_set_processor_op_t *ps_op; 1355 dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle; 1356 1357 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip; 1358 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op; 1359 1360 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch; 1361 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc; 1362 1363 ih264d_init_function_ptr(ps_codec); 1364 1365 ps_op->u4_error_code = 0; 1366 return IV_SUCCESS; 1367} 1368/*****************************************************************************/ 1369/* */ 1370/* Function Name : ih264d_get_num_rec */ 1371/* */ 1372/* Description : returns number of mem records required */ 1373/* */ 1374/* Inputs : pv_api_ip input api structure */ 1375/* : pv_api_op output api structure */ 1376/* Outputs : */ 1377/* Outputs : */ 1378/* Returns : void */ 1379/* */ 1380/* Issues : none */ 1381/* */ 1382/* Revision History: */ 1383/* */ 1384/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1385/* 22 10 2008 100356 Draft */ 1386/* */ 1387/*****************************************************************************/ 1388WORD32 ih264d_get_num_rec(void *pv_api_ip, void *pv_api_op) 1389{ 1390 iv_num_mem_rec_ip_t *ps_mem_q_ip; 1391 iv_num_mem_rec_op_t *ps_mem_q_op; 1392 ps_mem_q_ip = (iv_num_mem_rec_ip_t *)pv_api_ip; 1393 ps_mem_q_op = (iv_num_mem_rec_op_t *)pv_api_op; 1394 UNUSED(ps_mem_q_ip); 1395 ps_mem_q_op->u4_num_mem_rec = MEM_REC_CNT; 1396 1397 return IV_SUCCESS; 1398 1399} 1400 1401 1402/************************************************************************** 1403 * \if Function name : ih264d_init_decoder \endif 1404 * 1405 * 1406 * \brief 1407 * Initializes the decoder 1408 * 1409 * \param apiVersion : Version of the api being used. 1410 * \param errorHandlingMechanism : Mechanism to be used for errror handling. 1411 * \param postFilteringType: Type of post filtering operation to be used. 1412 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0]. 1413 * \param uc_dispBufs: Number of Display Buffers. 1414 * \param p_NALBufAPI: Pointer to NAL Buffer API. 1415 * \param p_DispBufAPI: Pointer to Display Buffer API. 1416 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder 1417 * for memory allocation and freeing. 1418 * 1419 * \return 1420 * 0 on Success and -1 on error 1421 * 1422 ************************************************************************** 1423 */ 1424void ih264d_init_decoder(void * ps_dec_params) 1425{ 1426 dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params; 1427 dec_slice_params_t *ps_cur_slice; 1428 pocstruct_t *ps_prev_poc, *ps_cur_poc; 1429 WORD32 size; 1430 1431 size = sizeof(dec_err_status_t); 1432 memset(ps_dec->ps_dec_err_status, 0, size); 1433 1434 size = sizeof(sei); 1435 memset(ps_dec->ps_sei, 0, size); 1436 1437 size = sizeof(dpb_commands_t); 1438 memset(ps_dec->ps_dpb_cmds, 0, size); 1439 1440 size = sizeof(dec_bit_stream_t); 1441 memset(ps_dec->ps_bitstrm, 0, size); 1442 1443 size = sizeof(dec_slice_params_t); 1444 memset(ps_dec->ps_cur_slice, 0, size); 1445 1446 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t)); 1447 memset(ps_dec->pv_scratch_sps_pps, 0, size); 1448 1449 1450 1451 /* Set pic_parameter_set_id to -1 */ 1452 1453 1454 1455 ps_cur_slice = ps_dec->ps_cur_slice; 1456 ps_dec->init_done = 0; 1457 1458 ps_dec->u4_num_cores = 1; 1459 1460 ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0; 1461 1462 ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE; 1463 ps_dec->u4_app_disable_deblk_frm = 0; 1464 ps_dec->i4_degrade_type = 0; 1465 ps_dec->i4_degrade_pics = 0; 1466 1467 ps_dec->i4_app_skip_mode = IVD_SKIP_NONE; 1468 ps_dec->i4_dec_skip_mode = IVD_SKIP_NONE; 1469 1470 memset(ps_dec->ps_pps, 0, 1471 ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS)); 1472 memset(ps_dec->ps_sps, 0, 1473 ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS)); 1474 1475 /* Initialization of function pointers ih264d_deblock_picture function*/ 1476 1477 ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff; 1478 ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff; 1479 1480 ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec; 1481 1482 ps_dec->u4_num_fld_in_frm = 0; 1483 1484 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec; 1485 1486 /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/ 1487 ps_dec->ps_sei->u1_is_valid = 0; 1488 1489 /* decParams Initializations */ 1490 ps_dec->ps_cur_pps = NULL; 1491 ps_dec->ps_cur_sps = NULL; 1492 ps_dec->u1_init_dec_flag = 0; 1493 ps_dec->u1_first_slice_in_stream = 1; 1494 ps_dec->u1_first_pb_nal_in_pic = 1; 1495 ps_dec->u1_last_pic_not_decoded = 0; 1496 ps_dec->u4_app_disp_width = 0; 1497 ps_dec->i4_header_decoded = 0; 1498 ps_dec->u4_total_frames_decoded = 0; 1499 1500 ps_dec->i4_error_code = 0; 1501 ps_dec->i4_content_type = -1; 1502 ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0; 1503 1504 ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS; 1505 ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN; 1506 ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT; 1507 ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME; 1508 ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN; 1509 1510 ps_dec->u1_pr_sl_type = 0xFF; 1511 ps_dec->u2_mbx = 0xffff; 1512 ps_dec->u2_mby = 0; 1513 ps_dec->u2_total_mbs_coded = 0; 1514 1515 /* POC initializations */ 1516 ps_prev_poc = &ps_dec->s_prev_pic_poc; 1517 ps_cur_poc = &ps_dec->s_cur_pic_poc; 1518 ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0; 1519 ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0; 1520 ps_prev_poc->i4_delta_pic_order_cnt_bottom = 1521 ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0; 1522 ps_prev_poc->i4_delta_pic_order_cnt[0] = 1523 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0; 1524 ps_prev_poc->i4_delta_pic_order_cnt[1] = 1525 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0; 1526 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0; 1527 ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count = 1528 0; 1529 ps_prev_poc->i4_bottom_field_order_count = 1530 ps_cur_poc->i4_bottom_field_order_count = 0; 1531 ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0; 1532 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0; 1533 ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0; 1534 ps_cur_slice->u1_mmco_equalto5 = 0; 1535 ps_cur_slice->u2_frame_num = 0; 1536 1537 ps_dec->i4_max_poc = 0; 1538 ps_dec->i4_prev_max_display_seq = 0; 1539 ps_dec->u1_recon_mb_grp = 4; 1540 1541 /* Field PIC initializations */ 1542 ps_dec->u1_second_field = 0; 1543 ps_dec->s_prev_seq_params.u1_eoseq_pending = 0; 1544 1545 /* Set the cropping parameters as zero */ 1546 ps_dec->u2_crop_offset_y = 0; 1547 ps_dec->u2_crop_offset_uv = 0; 1548 1549 /* The Initial Frame Rate Info is not Present */ 1550 ps_dec->i4_vui_frame_rate = -1; 1551 ps_dec->i4_pic_type = -1; 1552 ps_dec->i4_frametype = -1; 1553 ps_dec->i4_content_type = -1; 1554 1555 ps_dec->u1_res_changed = 0; 1556 1557 1558 ps_dec->u1_frame_decoded_flag = 0; 1559 1560 /* Set the default frame seek mask mode */ 1561 ps_dec->u4_skip_frm_mask = SKIP_NONE; 1562 1563 /********************************************************/ 1564 /* Initialize CAVLC residual decoding function pointers */ 1565 /********************************************************/ 1566 ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1; 1567 ps_dec->pf_cavlc_4x4res_block[1] = 1568 ih264d_cavlc_4x4res_block_totalcoeff_2to10; 1569 ps_dec->pf_cavlc_4x4res_block[2] = 1570 ih264d_cavlc_4x4res_block_totalcoeff_11to16; 1571 1572 ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7; 1573 ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8; 1574 1575 ps_dec->pf_cavlc_parse_8x8block[0] = 1576 ih264d_cavlc_parse_8x8block_none_available; 1577 ps_dec->pf_cavlc_parse_8x8block[1] = 1578 ih264d_cavlc_parse_8x8block_left_available; 1579 ps_dec->pf_cavlc_parse_8x8block[2] = 1580 ih264d_cavlc_parse_8x8block_top_available; 1581 ps_dec->pf_cavlc_parse_8x8block[3] = 1582 ih264d_cavlc_parse_8x8block_both_available; 1583 1584 /***************************************************************************/ 1585 /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */ 1586 /***************************************************************************/ 1587 ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice; 1588 ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice; 1589 1590 ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice; 1591 ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice; 1592 1593 ps_dec->pf_fill_bs_xtra_left_edge[0] = 1594 ih264d_fill_bs_xtra_left_edge_cur_frm; 1595 ps_dec->pf_fill_bs_xtra_left_edge[1] = 1596 ih264d_fill_bs_xtra_left_edge_cur_fld; 1597 1598 /* Initialize Reference Pic Buffers */ 1599 ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr); 1600 1601#if VERT_SCALE_UP_AND_422 1602 ps_dec->u1_vert_up_scale_flag = 1; 1603#else 1604 ps_dec->u1_vert_up_scale_flag = 0; 1605#endif 1606 1607 ps_dec->u2_prv_frame_num = 0; 1608 ps_dec->u1_top_bottom_decoded = 0; 1609 ps_dec->u1_dangling_field = 0; 1610 1611 ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table; 1612 1613 ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0]; 1614 ps_dec->pi1_left_ref_idx_ctxt_inc = 1615 &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0]; 1616 ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb; 1617 1618 /* ! */ 1619 /* Initializing flush frame u4_flag */ 1620 ps_dec->u1_flushfrm = 0; 1621 1622 { 1623 ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec; 1624 ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec; 1625 ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec; 1626 ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec; 1627 } 1628 1629 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t)); 1630 memset(ps_dec->u4_disp_buf_mapping, 0, 1631 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1632 memset(ps_dec->u4_disp_buf_to_be_freed, 0, 1633 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1634 memset(ps_dec->ps_cur_slice, 0, sizeof(dec_slice_params_t)); 1635 1636 ih264d_init_arch(ps_dec); 1637 ih264d_init_function_ptr(ps_dec); 1638 1639 ps_dec->init_done = 1; 1640 ps_dec->process_called = 1; 1641 1642 ps_dec->pv_pic_buf_mgr = NULL; 1643 ps_dec->pv_mv_buf_mgr = NULL; 1644} 1645 1646/************************************************************************** 1647 * \if Function name : ih264d_init_video_decoder \endif 1648 * 1649 * \brief 1650 * Wrapper for the decoder init 1651 * 1652 * \param p_NALBufAPI: Pointer to NAL Buffer API. 1653 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder 1654 * for memory allocation and freeing. 1655 * 1656 * \return 1657 * pointer to the decparams 1658 * 1659 ************************************************************************** 1660 */ 1661 1662WORD32 ih264d_init_video_decoder(iv_obj_t *dec_hdl, 1663 ih264d_init_ip_t *ps_init_ip, 1664 ih264d_init_op_t *ps_init_op) 1665{ 1666 dec_struct_t * ps_dec; 1667 iv_mem_rec_t *memtab; 1668 UWORD8 *pu1_extra_mem_base,*pu1_mem_base; 1669 1670 memtab = ps_init_ip->s_ivd_init_ip_t.pv_mem_rec_location; 1671 1672 dec_hdl->pv_codec_handle = memtab[MEM_REC_CODEC].pv_base; 1673 ps_dec = dec_hdl->pv_codec_handle; 1674 1675 memset(ps_dec, 0, sizeof(dec_struct_t)); 1676 1677 if(ps_init_ip->s_ivd_init_ip_t.u4_size 1678 > offsetof(ih264d_init_ip_t, i4_level)) 1679 { 1680 ps_dec->u4_level_at_init = ps_init_ip->i4_level; 1681 } 1682 else 1683 { 1684 ps_dec->u4_level_at_init = H264_LEVEL_3_1; 1685 } 1686 1687 if(ps_init_ip->s_ivd_init_ip_t.u4_size 1688 > offsetof(ih264d_init_ip_t, u4_num_ref_frames)) 1689 { 1690 ps_dec->u4_num_ref_frames_at_init = ps_init_ip->u4_num_ref_frames; 1691 } 1692 else 1693 { 1694 ps_dec->u4_num_ref_frames_at_init = H264_MAX_REF_PICS; 1695 } 1696 1697 if(ps_init_ip->s_ivd_init_ip_t.u4_size 1698 > offsetof(ih264d_init_ip_t, u4_num_reorder_frames)) 1699 { 1700 ps_dec->u4_num_reorder_frames_at_init = 1701 ps_init_ip->u4_num_reorder_frames; 1702 } 1703 else 1704 { 1705 ps_dec->u4_num_reorder_frames_at_init = H264_MAX_REF_PICS; 1706 } 1707 1708 if(ps_init_ip->s_ivd_init_ip_t.u4_size 1709 > offsetof(ih264d_init_ip_t, u4_num_extra_disp_buf)) 1710 { 1711 ps_dec->u4_num_extra_disp_bufs_at_init = 1712 ps_init_ip->u4_num_extra_disp_buf; 1713 } 1714 else 1715 { 1716 ps_dec->u4_num_extra_disp_bufs_at_init = 0; 1717 } 1718 1719 if(ps_init_ip->s_ivd_init_ip_t.u4_size 1720 > offsetof(ih264d_init_ip_t, u4_share_disp_buf)) 1721 { 1722#ifndef LOGO_EN 1723 ps_dec->u4_share_disp_buf = ps_init_ip->u4_share_disp_buf; 1724#else 1725 ps_dec->u4_share_disp_buf = 0; 1726#endif 1727 } 1728 else 1729 { 1730 ps_dec->u4_share_disp_buf = 0; 1731 } 1732 1733 if((ps_init_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) 1734 && (ps_init_ip->s_ivd_init_ip_t.e_output_format 1735 != IV_YUV_420SP_UV) 1736 && (ps_init_ip->s_ivd_init_ip_t.e_output_format 1737 != IV_YUV_420SP_VU)) 1738 { 1739 ps_dec->u4_share_disp_buf = 0; 1740 } 1741 1742 if((ps_dec->u4_level_at_init < MIN_LEVEL_SUPPORTED) 1743 || (ps_dec->u4_level_at_init > MAX_LEVEL_SUPPORTED)) 1744 { 1745 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_LEVEL_UNSUPPORTED; 1746 return (IV_FAIL); 1747 } 1748 1749 if(ps_dec->u4_num_ref_frames_at_init > H264_MAX_REF_PICS) 1750 { 1751 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF; 1752 ps_dec->u4_num_ref_frames_at_init = H264_MAX_REF_PICS; 1753 } 1754 1755 if(ps_dec->u4_num_reorder_frames_at_init > H264_MAX_REF_PICS) 1756 { 1757 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF; 1758 ps_dec->u4_num_reorder_frames_at_init = H264_MAX_REF_PICS; 1759 } 1760 1761 if(ps_dec->u4_num_extra_disp_bufs_at_init > H264_MAX_REF_PICS) 1762 { 1763 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF; 1764 ps_dec->u4_num_extra_disp_bufs_at_init = 0; 1765 } 1766 1767 if(0 == ps_dec->u4_share_disp_buf) 1768 ps_dec->u4_num_extra_disp_bufs_at_init = 0; 1769 1770 ps_dec->u4_num_disp_bufs_requested = 1; 1771 1772 ps_dec->u4_width_at_init = ps_init_ip->s_ivd_init_ip_t.u4_frm_max_wd; 1773 ps_dec->u4_height_at_init = ps_init_ip->s_ivd_init_ip_t.u4_frm_max_ht; 1774 1775 ps_dec->u4_width_at_init = ALIGN16(ps_dec->u4_width_at_init); 1776 ps_dec->u4_height_at_init = ALIGN32(ps_dec->u4_height_at_init); 1777 1778 ps_dec->pv_dec_thread_handle = memtab[MEM_REC_THREAD_HANDLE].pv_base; 1779 1780 pu1_mem_base = memtab[MEM_REC_THREAD_HANDLE].pv_base; 1781 ps_dec->pv_bs_deblk_thread_handle = pu1_mem_base 1782 + ithread_get_handle_size(); 1783 1784 ps_dec->u4_extra_mem_used = 0; 1785 1786 pu1_extra_mem_base = memtab[MEM_REC_EXTRA_MEM].pv_base; 1787 1788 ps_dec->ps_dec_err_status = (dec_err_status_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1789 ps_dec->u4_extra_mem_used += (((sizeof(dec_err_status_t) + 127) >> 7) << 7); 1790 1791 ps_dec->ps_mem_tab = memtab[MEM_REC_BACKUP].pv_base; 1792 1793 memcpy(ps_dec->ps_mem_tab, memtab, sizeof(iv_mem_rec_t) * MEM_REC_CNT); 1794 1795 ps_dec->ps_pps = memtab[MEM_REC_PPS].pv_base; 1796 1797 ps_dec->ps_sps = memtab[MEM_REC_SPS].pv_base; 1798 1799 ps_dec->ps_sei = (sei *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1800 ps_dec->u4_extra_mem_used += sizeof(sei); 1801 1802 ps_dec->ps_dpb_mgr = memtab[MEM_REC_DPB_MGR].pv_base; 1803 1804 ps_dec->ps_dpb_cmds = (dpb_commands_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1805 ps_dec->u4_extra_mem_used += sizeof(dpb_commands_t); 1806 1807 ps_dec->ps_bitstrm = (dec_bit_stream_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1808 ps_dec->u4_extra_mem_used += sizeof(dec_bit_stream_t); 1809 1810 ps_dec->ps_cur_slice =(dec_slice_params_t *) (pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1811 ps_dec->u4_extra_mem_used += sizeof(dec_slice_params_t); 1812 1813 ps_dec->pv_scratch_sps_pps = (void *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1814 1815 1816 ps_dec->u4_extra_mem_used += MAX(sizeof(dec_seq_params_t), 1817 sizeof(dec_pic_params_t)); 1818 ps_dec->ps_pred_pkd = memtab[MEM_REC_PRED_INFO_PKD].pv_base; 1819 1820 1821 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec; 1822 1823 ps_dec->pv_dec_out = (void *)ps_init_op; 1824 ps_dec->pv_dec_in = (void *)ps_init_ip; 1825 1826 ps_dec->u1_chroma_format = 1827 (UWORD8)(ps_init_ip->s_ivd_init_ip_t.e_output_format); 1828 1829 1830 1831 ih264d_init_decoder(ps_dec); 1832 1833 return (IV_SUCCESS); 1834 1835} 1836 1837 1838/*****************************************************************************/ 1839/* */ 1840/* Function Name : ih264d_fill_num_mem_rec */ 1841/* */ 1842/* Description : fills memory records */ 1843/* */ 1844/* Inputs : pv_api_ip input api structure */ 1845/* : pv_api_op output api structure */ 1846/* Outputs : */ 1847/* Returns : void */ 1848/* */ 1849/* Issues : none */ 1850/* */ 1851/* Revision History: */ 1852/* */ 1853/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1854/* 22 10 2008 100356 Draft */ 1855/* */ 1856/*****************************************************************************/ 1857WORD32 ih264d_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op) 1858{ 1859 1860 ih264d_fill_mem_rec_ip_t *ps_mem_q_ip; 1861 ih264d_fill_mem_rec_op_t *ps_mem_q_op; 1862 WORD32 level; 1863 UWORD32 num_reorder_frames; 1864 UWORD32 num_ref_frames; 1865 UWORD32 num_extra_disp_bufs; 1866 UWORD32 u4_dpb_size_num_frames; 1867 iv_mem_rec_t *memTab; 1868 1869 UWORD32 chroma_format, u4_share_disp_buf; 1870 UWORD32 u4_total_num_mbs; 1871 UWORD32 luma_width, luma_width_in_mbs; 1872 UWORD32 luma_height, luma_height_in_mbs; 1873 UWORD32 max_dpb_size; 1874 1875 ps_mem_q_ip = (ih264d_fill_mem_rec_ip_t *)pv_api_ip; 1876 ps_mem_q_op = (ih264d_fill_mem_rec_op_t *)pv_api_op; 1877 1878 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1879 > offsetof(ih264d_fill_mem_rec_ip_t, i4_level)) 1880 { 1881 level = ps_mem_q_ip->i4_level; 1882 } 1883 else 1884 { 1885 level = H264_LEVEL_3_1; 1886 } 1887 1888 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1889 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_reorder_frames)) 1890 { 1891 num_reorder_frames = ps_mem_q_ip->u4_num_reorder_frames; 1892 } 1893 else 1894 { 1895 num_reorder_frames = H264_MAX_REF_PICS; 1896 } 1897 1898 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1899 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_ref_frames)) 1900 { 1901 num_ref_frames = ps_mem_q_ip->u4_num_ref_frames; 1902 } 1903 else 1904 { 1905 num_ref_frames = H264_MAX_REF_PICS; 1906 } 1907 1908 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1909 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_extra_disp_buf)) 1910 { 1911 num_extra_disp_bufs = ps_mem_q_ip->u4_num_extra_disp_buf; 1912 } 1913 else 1914 { 1915 num_extra_disp_bufs = 0; 1916 } 1917 1918 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1919 > offsetof(ih264d_fill_mem_rec_ip_t, u4_share_disp_buf)) 1920 { 1921#ifndef LOGO_EN 1922 u4_share_disp_buf = ps_mem_q_ip->u4_share_disp_buf; 1923#else 1924 u4_share_disp_buf = 0; 1925#endif 1926 } 1927 else 1928 { 1929 u4_share_disp_buf = 0; 1930 } 1931 1932 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1933 > offsetof(ih264d_fill_mem_rec_ip_t, e_output_format)) 1934 { 1935 chroma_format = ps_mem_q_ip->e_output_format; 1936 } 1937 else 1938 { 1939 chroma_format = -1; 1940 } 1941 1942 if((chroma_format != IV_YUV_420P) && (chroma_format != IV_YUV_420SP_UV) 1943 && (chroma_format != IV_YUV_420SP_VU)) 1944 { 1945 u4_share_disp_buf = 0; 1946 } 1947 if(0 == u4_share_disp_buf) 1948 num_extra_disp_bufs = 0; 1949 1950 { 1951 1952 luma_height = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht; 1953 luma_width = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd; 1954 1955 luma_height = ALIGN32(luma_height); 1956 luma_width = ALIGN16(luma_width); 1957 luma_width_in_mbs = luma_width >> 4; 1958 luma_height_in_mbs = luma_height >> 4; 1959 u4_total_num_mbs = (luma_height * luma_width) >> 8; 1960 } 1961 /* 1962 * If level is lesser than 31 and the resolution required is higher, 1963 * then make the level at least 31. 1964 */ 1965 if(u4_total_num_mbs > MAX_MBS_LEVEL_30 && level < H264_LEVEL_3_1) 1966 { 1967 level = H264_LEVEL_3_1; 1968 } 1969 1970 if((level < MIN_LEVEL_SUPPORTED) || (level > MAX_LEVEL_SUPPORTED)) 1971 { 1972 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1973 ERROR_LEVEL_UNSUPPORTED; 1974 return (IV_FAIL); 1975 } 1976 1977 if(num_ref_frames > H264_MAX_REF_PICS) 1978 { 1979 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= ERROR_NUM_REF; 1980 num_ref_frames = H264_MAX_REF_PICS; 1981 } 1982 1983 if(num_reorder_frames > H264_MAX_REF_PICS) 1984 { 1985 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= ERROR_NUM_REF; 1986 num_reorder_frames = H264_MAX_REF_PICS; 1987 } 1988 memTab = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location; 1989 1990 memTab[MEM_REC_IV_OBJ].u4_mem_size = sizeof(iv_obj_t); 1991 memTab[MEM_REC_IV_OBJ].u4_mem_alignment = (128 * 8) / CHAR_BIT; 1992 memTab[MEM_REC_IV_OBJ].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 1993 H264_DEC_DEBUG_PRINT("MEM_REC_IV_OBJ MEM Size = %d\n", 1994 memTab[MEM_REC_IV_OBJ].u4_mem_size); 1995 1996 memTab[MEM_REC_CODEC].u4_mem_alignment = (128 * 8) / CHAR_BIT; 1997 memTab[MEM_REC_CODEC].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 1998 memTab[MEM_REC_CODEC].u4_mem_size = sizeof(dec_struct_t); 1999 2000 { 2001 UWORD32 mvinfo_size, mv_info_size_pad; 2002 UWORD32 MVbank, MVbank_pad; 2003 UWORD32 Ysize; 2004 UWORD32 UVsize; 2005 UWORD32 one_frm_size; 2006 2007 UWORD32 extra_mem = 0; 2008 2009 UWORD32 pad_len_h, pad_len_v; 2010 2011 /* 2012 * For low_delay, use num_buf as 2 - 2013 * num_buf = (num_buf_ref) + 1; 2014 * where num_buf_ref is 1. 2015 */ 2016 UWORD32 num_buf; 2017 2018 { 2019 UWORD32 num_bufs_app, num_bufs_level; 2020 2021 num_bufs_app = num_ref_frames + num_reorder_frames + 1; 2022 2023 if(num_bufs_app <= 1) 2024 num_bufs_app = 2; 2025 2026 num_bufs_level = ih264d_get_dpb_size_new(level, (luma_width >> 4), 2027 (luma_height >> 4)); 2028 2029 max_dpb_size = num_bufs_level; 2030 2031 num_bufs_level = num_bufs_level * 2 + 1; 2032 2033 num_buf = MIN(num_bufs_level, num_bufs_app); 2034 2035 num_buf += num_extra_disp_bufs; 2036 2037 } 2038 2039 mvinfo_size = ((luma_width * (luma_height)) >> 4); 2040 2041 mv_info_size_pad = ((luma_width * (PAD_MV_BANK_ROW)) >> 4); 2042 2043 Ysize = ALIGN32((luma_width + (PAD_LEN_Y_H << 1))) 2044 * (luma_height + (PAD_LEN_Y_V << 2)); 2045 2046 2047 UVsize = Ysize >> 2; 2048 if(u4_share_disp_buf == 1) 2049 { 2050 /* In case of buffers getting shared between application and library 2051 there is no need of reference memtabs. Instead of setting the i4_size 2052 to zero, it is reduced to a small i4_size to ensure that changes 2053 in the code are minimal */ 2054 2055 if((chroma_format == IV_YUV_420P) 2056 || (chroma_format == IV_YUV_420SP_UV) 2057 || (chroma_format == IV_YUV_420SP_VU)) 2058 { 2059 Ysize = 64; 2060 } 2061 if(chroma_format == IV_YUV_420SP_UV) 2062 { 2063 UVsize = 64; 2064 } 2065 } 2066 2067 one_frm_size = (((Ysize + 127) >> 7) << 7) 2068 + ((((UVsize << 1) + 127) >> 7) << 7); 2069 2070 //Note that for ARM RVDS WS the sizeof(mv_pred_t) is 16 2071 2072 /*Add memory for colocated MB*/ 2073 MVbank = sizeof(mv_pred_t) * mvinfo_size; 2074 MVbank_pad = sizeof(mv_pred_t) * mv_info_size_pad; 2075 2076 MVbank = (((MVbank + 127) >> 7) << 7); 2077 2078 MVbank_pad = (((MVbank_pad + 127) >> 7) << 7); 2079 2080 memTab[MEM_REC_MVBANK].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2081 memTab[MEM_REC_MVBANK].e_mem_type = 2082 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2083 memTab[MEM_REC_MVBANK].u4_mem_size = (MVbank + MVbank_pad) 2084 * (MIN(max_dpb_size, num_ref_frames) + 1); 2085 2086 2087 memTab[MEM_REC_REF_PIC].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2088 memTab[MEM_REC_REF_PIC].e_mem_type = 2089 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2090 memTab[MEM_REC_REF_PIC].u4_mem_size = one_frm_size * num_buf; 2091 2092 } 2093 2094 memTab[MEM_REC_DEBLK_MB_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2095 memTab[MEM_REC_DEBLK_MB_INFO].e_mem_type = 2096 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2097 memTab[MEM_REC_DEBLK_MB_INFO].u4_mem_size = (((((u4_total_num_mbs 2098 + (luma_width >> 4)) * sizeof(deblk_mb_t)) + 127) >> 7) << 7); 2099 2100 memTab[MEM_REC_NEIGHBOR_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2101 memTab[MEM_REC_NEIGHBOR_INFO].e_mem_type = 2102 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2103 memTab[MEM_REC_NEIGHBOR_INFO].u4_mem_size = sizeof(mb_neigbour_params_t) 2104 * ((luma_width + 16) >> 4) * 2 * 2; 2105 { 2106 WORD32 size; 2107 WORD32 num_entries; 2108 2109 num_entries = MIN(MAX_FRAMES, num_ref_frames); 2110 num_entries = 2 * ((2 * num_entries) + 1); 2111 2112 size = num_entries * sizeof(void *); 2113 size += PAD_MAP_IDX_POC * sizeof(void *); 2114 size *= u4_total_num_mbs; 2115 size += sizeof(dec_slice_struct_t) * u4_total_num_mbs; 2116 memTab[MEM_REC_SLICE_HDR].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2117 memTab[MEM_REC_SLICE_HDR].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2118 memTab[MEM_REC_SLICE_HDR].u4_mem_size = size; 2119 } 2120 { 2121 2122 UWORD32 u4_num_entries; 2123 2124 u4_num_entries = u4_total_num_mbs; 2125 2126 memTab[MEM_REC_MB_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2127 memTab[MEM_REC_MB_INFO].e_mem_type = 2128 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2129 memTab[MEM_REC_MB_INFO].u4_mem_size = sizeof(dec_mb_info_t) 2130 * u4_num_entries; 2131 2132 memTab[MEM_REC_PRED_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2133 memTab[MEM_REC_PRED_INFO].e_mem_type = 2134 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2135 2136 memTab[MEM_REC_PRED_INFO].u4_mem_size = sizeof(pred_info_t) * 2*32; 2137 2138 memTab[MEM_REC_COEFF_DATA].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2139 memTab[MEM_REC_COEFF_DATA].e_mem_type = 2140 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2141 memTab[MEM_REC_COEFF_DATA].u4_mem_size = MB_LUM_SIZE * sizeof(WORD16); 2142 /*For I16x16 MBs, 16 4x4 AC coeffs and 1 4x4 DC coeff TU blocks will be sent 2143 For all MBs along with 8 4x4 AC coeffs 2 2x2 DC coeff TU blocks will be sent 2144 So use 17 4x4 TU blocks for luma and 9 4x4 TU blocks for chroma */ 2145 memTab[MEM_REC_COEFF_DATA].u4_mem_size += u4_num_entries 2146 * (MAX(17 * sizeof(tu_sblk4x4_coeff_data_t),4 * sizeof(tu_blk8x8_coeff_data_t)) 2147 + 9 * sizeof(tu_sblk4x4_coeff_data_t)); 2148 //32 bytes for each mb to store u1_prev_intra4x4_pred_mode and u1_rem_intra4x4_pred_mode data 2149 memTab[MEM_REC_COEFF_DATA].u4_mem_size += u4_num_entries * 32; 2150 2151 } 2152 2153 memTab[MEM_REC_SPS].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2154 memTab[MEM_REC_SPS].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2155 memTab[MEM_REC_SPS].u4_mem_size = ((sizeof(dec_seq_params_t)) 2156 * MAX_NUM_SEQ_PARAMS); 2157 2158 memTab[MEM_REC_PPS].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2159 memTab[MEM_REC_PPS].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2160 memTab[MEM_REC_PPS].u4_mem_size = (sizeof(dec_pic_params_t)) 2161 * MAX_NUM_PIC_PARAMS; 2162 2163 { 2164 UWORD32 u4_mem_size; 2165 2166 u4_mem_size = 0; 2167 u4_mem_size += (((sizeof(dec_err_status_t) + 127) >> 7) << 7); 2168 u4_mem_size += sizeof(sei); 2169 u4_mem_size += sizeof(dpb_commands_t); 2170 u4_mem_size += sizeof(dec_bit_stream_t); 2171 u4_mem_size += sizeof(dec_slice_params_t); 2172 u4_mem_size += MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t)); 2173 2174 memTab[MEM_REC_EXTRA_MEM].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2175 memTab[MEM_REC_EXTRA_MEM].e_mem_type = 2176 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2177 memTab[MEM_REC_EXTRA_MEM].u4_mem_size = u4_mem_size; 2178 } 2179 2180 { 2181 2182 UWORD32 u4_mem_size; 2183 2184 u4_mem_size = 0; 2185 u4_mem_size += ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC) * sizeof(void *)); 2186 u4_mem_size = ALIGN64(u4_mem_size); 2187 u4_mem_size += (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS); 2188 u4_mem_size = ALIGN64(u4_mem_size); 2189 u4_mem_size += sizeof(ctxt_inc_mb_info_t); 2190 u4_mem_size = ALIGN64(u4_mem_size); 2191 u4_mem_size += sizeof(UWORD32) * (MAX_REF_BUFS * MAX_REF_BUFS); 2192 u4_mem_size = ALIGN64(u4_mem_size); 2193 2194 u4_mem_size += MAX_REF_BUF_SIZE * 2; 2195 u4_mem_size = ALIGN64(u4_mem_size); 2196 u4_mem_size += ((sizeof(WORD16)) * PRED_BUFFER_WIDTH 2197 * PRED_BUFFER_HEIGHT * 2); 2198 u4_mem_size = ALIGN64(u4_mem_size); 2199 u4_mem_size += sizeof(UWORD8) * (MB_LUM_SIZE); 2200 u4_mem_size = ALIGN64(u4_mem_size); 2201 u4_mem_size += sizeof(parse_pmbarams_t) * luma_width_in_mbs; //Max recon mb group*/ 2202 u4_mem_size = ALIGN64(u4_mem_size); 2203 u4_mem_size += (sizeof(parse_part_params_t) * luma_width_in_mbs) << 4; //Max recon mb group*/ 2204 u4_mem_size = ALIGN64(u4_mem_size); 2205 2206 u4_mem_size += 2 * MAX_REF_BUFS * sizeof(struct pic_buffer_t); 2207 u4_mem_size = ALIGN64(u4_mem_size); 2208 u4_mem_size += 2 * MAX_REF_BUFS * sizeof(struct pic_buffer_t); 2209 u4_mem_size = ALIGN64(u4_mem_size); 2210 u4_mem_size += (sizeof(UWORD32) * 3 * (MAX_REF_BUFS * MAX_REF_BUFS)) << 3; 2211 u4_mem_size = ALIGN64(u4_mem_size); 2212 2213 u4_mem_size += sizeof(UWORD32) * 2 * 3 2214 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1)); 2215 u4_mem_size = ALIGN64(u4_mem_size); 2216 2217 memTab[MEM_REC_INTERNAL_SCRATCH].u4_mem_alignment = 2218 (128 * 8) / CHAR_BIT; 2219 memTab[MEM_REC_INTERNAL_SCRATCH].e_mem_type = 2220 IV_EXTERNAL_CACHEABLE_SCRATCH_MEM; 2221 memTab[MEM_REC_INTERNAL_SCRATCH].u4_mem_size = u4_mem_size; 2222 } 2223 2224 { 2225 2226 UWORD32 u4_mem_used; 2227 UWORD32 u4_numRows = MB_SIZE << 1; 2228 UWORD32 u4_blk_wd = ((luma_width_in_mbs << 4) >> 1) + 8; 2229 2230 u4_mem_used = 0; 2231 u4_mem_used += ((luma_width_in_mbs * sizeof(deblkmb_neighbour_t)) << 1); 2232 u4_mem_used = ALIGN64(u4_mem_used); 2233 u4_mem_used += (sizeof(neighbouradd_t) << 2); 2234 u4_mem_used = ALIGN64(u4_mem_used); 2235 u4_mem_used += ((sizeof(ctxt_inc_mb_info_t)) 2236 * (((luma_width_in_mbs + 1) << 1) + 1)); 2237 u4_mem_used = ALIGN64(u4_mem_used); 2238 2239 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 16); 2240 u4_mem_used = ALIGN64(u4_mem_used); 2241 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 16); 2242 u4_mem_used = ALIGN64(u4_mem_used); 2243 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 4 2244 * MV_SCRATCH_BUFS); 2245 u4_mem_used = ALIGN64(u4_mem_used); 2246 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2247 u4_mem_used = ALIGN64(u4_mem_used); 2248 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2249 u4_mem_used = ALIGN64(u4_mem_used); 2250 u4_numRows = BLK8x8SIZE << 1; 2251 2252 u4_blk_wd = ((luma_width_in_mbs << 3) >> 1) + 8; 2253 2254 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2255 u4_mem_used = ALIGN64(u4_mem_used); 2256 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2257 u4_mem_used = ALIGN64(u4_mem_used); 2258 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2259 u4_mem_used = ALIGN64(u4_mem_used); 2260 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2261 u4_mem_used += 32; 2262 u4_mem_used = ALIGN64(u4_mem_used); 2263 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2; 2264 u4_mem_used = ALIGN64(u4_mem_used); 2265 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2; 2266 u4_mem_used = ALIGN64(u4_mem_used); 2267 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2; 2268 u4_mem_used = ALIGN64(u4_mem_used); 2269 u4_mem_used += sizeof(mb_neigbour_params_t) * (luma_width_in_mbs + 1) 2270 * luma_height_in_mbs; 2271 u4_mem_used += luma_width; 2272 u4_mem_used = ALIGN64(u4_mem_used); 2273 u4_mem_used += luma_width; 2274 u4_mem_used = ALIGN64(u4_mem_used); 2275 u4_mem_used += luma_width; 2276 u4_mem_used = ALIGN64(u4_mem_used); 2277 2278 u4_mem_used += ((MB_SIZE + 4) << 1) * PAD_LEN_Y_H; 2279 u4_mem_used = ALIGN64(u4_mem_used); 2280 u4_mem_used += ((BLK8x8SIZE + 2) << 1) * PAD_LEN_UV_H; 2281 u4_mem_used = ALIGN64(u4_mem_used); 2282 u4_mem_used += ((BLK8x8SIZE + 2) << 1) * PAD_LEN_UV_H; 2283 u4_mem_used = ALIGN64(u4_mem_used); 2284 memTab[MEM_REC_INTERNAL_PERSIST].u4_mem_alignment = 2285 (128 * 8) / CHAR_BIT; 2286 memTab[MEM_REC_INTERNAL_PERSIST].e_mem_type = 2287 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2288 memTab[MEM_REC_INTERNAL_PERSIST].u4_mem_size = u4_mem_used; 2289 } 2290 2291 memTab[MEM_REC_BITSBUF].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2292 memTab[MEM_REC_BITSBUF].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2293 memTab[MEM_REC_BITSBUF].u4_mem_size = MAX(256000, (luma_width * luma_height * 3 / 2)); 2294 2295 { 2296 2297 UWORD32 u4_thread_struct_size = ithread_get_handle_size(); 2298 2299 memTab[MEM_REC_THREAD_HANDLE].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2300 memTab[MEM_REC_THREAD_HANDLE].e_mem_type = 2301 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2302 memTab[MEM_REC_THREAD_HANDLE].u4_mem_size = u4_thread_struct_size * 2; 2303 2304 } 2305 2306 memTab[MEM_REC_PARSE_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2307 memTab[MEM_REC_PARSE_MAP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2308 memTab[MEM_REC_PARSE_MAP].u4_mem_size = u4_total_num_mbs; 2309 2310 memTab[MEM_REC_PROC_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2311 memTab[MEM_REC_PROC_MAP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2312 memTab[MEM_REC_PROC_MAP].u4_mem_size = u4_total_num_mbs; 2313 2314 memTab[MEM_REC_SLICE_NUM_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2315 memTab[MEM_REC_SLICE_NUM_MAP].e_mem_type = 2316 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2317 memTab[MEM_REC_SLICE_NUM_MAP].u4_mem_size = u4_total_num_mbs 2318 * sizeof(UWORD16); 2319 2320 memTab[MEM_REC_DPB_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2321 memTab[MEM_REC_DPB_MGR].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2322 memTab[MEM_REC_DPB_MGR].u4_mem_size = sizeof(dpb_manager_t); 2323 2324 memTab[MEM_REC_BACKUP].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2325 memTab[MEM_REC_BACKUP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2326 memTab[MEM_REC_BACKUP].u4_mem_size = sizeof(iv_mem_rec_t) * MEM_REC_CNT; 2327 2328 { 2329 2330 UWORD32 u4_mem_size; 2331 2332 u4_mem_size = sizeof(disp_mgr_t); 2333 u4_mem_size += sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 2334 u4_mem_size += sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2); 2335 2336 memTab[MEM_REC_PIC_BUF_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2337 memTab[MEM_REC_PIC_BUF_MGR].e_mem_type = 2338 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2339 memTab[MEM_REC_PIC_BUF_MGR].u4_mem_size = u4_mem_size; 2340 } 2341 2342 { 2343 UWORD32 u4_mem_size; 2344 2345 u4_mem_size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 2346 u4_mem_size += sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2); 2347 u4_mem_size = ALIGN128(u4_mem_size); 2348 u4_mem_size += ((luma_width * luma_height) >> 4) 2349 * (MIN(max_dpb_size, num_ref_frames) + 1); 2350 memTab[MEM_REC_MV_BUF_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2351 memTab[MEM_REC_MV_BUF_MGR].e_mem_type = 2352 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2353 memTab[MEM_REC_MV_BUF_MGR].u4_mem_size = u4_mem_size; 2354 } 2355 2356 memTab[MEM_REC_PRED_INFO_PKD].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2357 memTab[MEM_REC_PRED_INFO_PKD].e_mem_type = 2358 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2359 2360 { 2361 UWORD32 u4_num_entries; 2362 u4_num_entries = u4_total_num_mbs; 2363 2364 if(1 == num_ref_frames) 2365 u4_num_entries *= 16; 2366 else 2367 u4_num_entries *= 16 * 2; 2368 2369 memTab[MEM_REC_PRED_INFO_PKD].u4_mem_size = sizeof(pred_info_pkd_t) 2370 * u4_num_entries; 2371 } 2372 2373 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = MEM_REC_CNT; 2374 2375 2376 return IV_SUCCESS; 2377} 2378/*****************************************************************************/ 2379/* */ 2380/* Function Name : ih264d_clr */ 2381/* */ 2382/* Description : returns memory records to app */ 2383/* */ 2384/* Inputs :iv_obj_t decoder handle */ 2385/* :pv_api_ip pointer to input structure */ 2386/* :pv_api_op pointer to output structure */ 2387/* Outputs : */ 2388/* Returns : void */ 2389/* */ 2390/* Issues : none */ 2391/* */ 2392/* Revision History: */ 2393/* */ 2394/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2395/* 22 10 2008 100356 Draft */ 2396/* */ 2397/*****************************************************************************/ 2398WORD32 ih264d_clr(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2399{ 2400 2401 dec_struct_t * ps_dec; 2402 iv_retrieve_mem_rec_ip_t *dec_clr_ip; 2403 iv_retrieve_mem_rec_op_t *dec_clr_op; 2404 2405 dec_clr_ip = (iv_retrieve_mem_rec_ip_t *)pv_api_ip; 2406 dec_clr_op = (iv_retrieve_mem_rec_op_t *)pv_api_op; 2407 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2408 2409 if(ps_dec->init_done != 1) 2410 { 2411 //return a proper Error Code 2412 return IV_FAIL; 2413 } 2414 2415 if(ps_dec->pv_pic_buf_mgr) 2416 ih264_buf_mgr_free((buf_mgr_t *)ps_dec->pv_pic_buf_mgr); 2417 if(ps_dec->pv_mv_buf_mgr) 2418 ih264_buf_mgr_free((buf_mgr_t *)ps_dec->pv_mv_buf_mgr); 2419 2420 memcpy(dec_clr_ip->pv_mem_rec_location, ps_dec->ps_mem_tab, 2421 MEM_REC_CNT * (sizeof(iv_mem_rec_t))); 2422 dec_clr_op->u4_num_mem_rec_filled = MEM_REC_CNT; 2423 2424 H264_DEC_DEBUG_PRINT("The clear non-conceal num mem recs: %d\n", 2425 dec_clr_op->u4_num_mem_rec_filled); 2426 2427 return IV_SUCCESS; 2428 2429} 2430 2431/*****************************************************************************/ 2432/* */ 2433/* Function Name : ih264d_init */ 2434/* */ 2435/* Description : initializes decoder */ 2436/* */ 2437/* Inputs :iv_obj_t decoder handle */ 2438/* :pv_api_ip pointer to input structure */ 2439/* :pv_api_op pointer to output structure */ 2440/* Outputs : */ 2441/* Returns : void */ 2442/* */ 2443/* Issues : none */ 2444/* */ 2445/* Revision History: */ 2446/* */ 2447/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2448/* 22 10 2008 100356 Draft */ 2449/* */ 2450/*****************************************************************************/ 2451WORD32 ih264d_init(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2452{ 2453 ih264d_init_ip_t *ps_init_ip; 2454 ih264d_init_op_t *ps_init_op; 2455 WORD32 init_status = IV_SUCCESS; 2456 ps_init_ip = (ih264d_init_ip_t *)pv_api_ip; 2457 ps_init_op = (ih264d_init_op_t *)pv_api_op; 2458 2459 init_status = ih264d_init_video_decoder(dec_hdl, ps_init_ip, ps_init_op); 2460 2461 if(IV_SUCCESS != init_status) 2462 { 2463 return init_status; 2464 } 2465 2466 return init_status; 2467} 2468/*****************************************************************************/ 2469/* */ 2470/* Function Name : ih264d_map_error */ 2471/* */ 2472/* Description : Maps error codes to IVD error groups */ 2473/* */ 2474/* Inputs : */ 2475/* Globals : <Does it use any global variables?> */ 2476/* Outputs : */ 2477/* Returns : void */ 2478/* */ 2479/* Issues : none */ 2480/* */ 2481/* Revision History: */ 2482/* */ 2483/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2484/* 22 10 2008 100356 Draft */ 2485/* */ 2486/*****************************************************************************/ 2487UWORD32 ih264d_map_error(UWORD32 i4_err_status) 2488{ 2489 UWORD32 temp = 0; 2490 2491 switch(i4_err_status) 2492 { 2493 case ERROR_MEM_ALLOC_ISRAM_T: 2494 case ERROR_MEM_ALLOC_SDRAM_T: 2495 case ERROR_BUF_MGR: 2496 case ERROR_MB_GROUP_ASSGN_T: 2497 case ERROR_FRAME_LIMIT_OVER: 2498 case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT: 2499 case ERROR_PROFILE_NOT_SUPPORTED: 2500 case ERROR_INIT_NOT_DONE: 2501 temp = 1 << IVD_FATALERROR; 2502 H264_DEC_DEBUG_PRINT("\nFatal Error\n"); 2503 break; 2504 2505 case ERROR_DBP_MANAGER_T: 2506 case ERROR_GAPS_IN_FRM_NUM: 2507 case ERROR_UNKNOWN_NAL: 2508 case ERROR_INV_MB_SLC_GRP_T: 2509 case ERROR_MULTIPLE_SLC_GRP_T: 2510 case ERROR_UNKNOWN_LEVEL: 2511 case ERROR_UNAVAIL_PICBUF_T: 2512 case ERROR_UNAVAIL_MVBUF_T: 2513 case ERROR_UNAVAIL_DISPBUF_T: 2514 case ERROR_NUM_REF: 2515 case ERROR_REFIDX_ORDER_T: 2516 case ERROR_PIC0_NOT_FOUND_T: 2517 case ERROR_MB_TYPE: 2518 case ERROR_SUB_MB_TYPE: 2519 case ERROR_CBP: 2520 case ERROR_REF_IDX: 2521 case ERROR_NUM_MV: 2522 case ERROR_CHROMA_PRED_MODE: 2523 case ERROR_INTRAPRED: 2524 case ERROR_NEXT_MB_ADDRESS_T: 2525 case ERROR_MB_ADDRESS_T: 2526 case ERROR_PIC1_NOT_FOUND_T: 2527 case ERROR_CAVLC_NUM_COEFF_T: 2528 case ERROR_CAVLC_SCAN_POS_T: 2529 case ERROR_PRED_WEIGHT_TABLE_T: 2530 case ERROR_CORRUPTED_SLICE: 2531 temp = 1 << IVD_CORRUPTEDDATA; 2532 break; 2533 2534 case ERROR_NOT_SUPP_RESOLUTION: 2535 case ERROR_FEATURE_UNAVAIL: 2536 case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT: 2537 temp = 1 << IVD_UNSUPPORTEDINPUT; 2538 break; 2539 2540 case ERROR_INVALID_PIC_PARAM: 2541 case ERROR_INVALID_SEQ_PARAM: 2542 case ERROR_EGC_EXCEED_32_1_T: 2543 case ERROR_EGC_EXCEED_32_2_T: 2544 case ERROR_INV_RANGE_TEV_T: 2545 case ERROR_INV_SLC_TYPE_T: 2546 case ERROR_INV_POC_TYPE_T: 2547 case ERROR_INV_RANGE_QP_T: 2548 case ERROR_INV_SPS_PPS_T: 2549 case ERROR_INV_SLICE_HDR_T: 2550 temp = 1 << IVD_CORRUPTEDHEADER; 2551 break; 2552 2553 case ERROR_EOB_FLUSHBITS_T: 2554 case ERROR_EOB_GETBITS_T: 2555 case ERROR_EOB_GETBIT_T: 2556 case ERROR_EOB_BYPASS_T: 2557 case ERROR_EOB_DECISION_T: 2558 case ERROR_EOB_TERMINATE_T: 2559 case ERROR_EOB_READCOEFF4X4CAB_T: 2560 temp = 1 << IVD_INSUFFICIENTDATA; 2561 break; 2562 case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED: 2563 case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH: 2564 temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR; 2565 break; 2566 2567 case ERROR_DANGLING_FIELD_IN_PIC: 2568 temp = 1 << IVD_APPLIEDCONCEALMENT; 2569 break; 2570 2571 } 2572 2573 return temp; 2574 2575} 2576 2577/*****************************************************************************/ 2578/* */ 2579/* Function Name : ih264d_video_decode */ 2580/* */ 2581/* Description : handle video decode API command */ 2582/* */ 2583/* Inputs :iv_obj_t decoder handle */ 2584/* :pv_api_ip pointer to input structure */ 2585/* :pv_api_op pointer to output structure */ 2586/* Outputs : */ 2587/* Returns : void */ 2588/* */ 2589/* Issues : none */ 2590/* */ 2591/* Revision History: */ 2592/* */ 2593/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2594/* 22 10 2008 100356 Draft */ 2595/* */ 2596/*****************************************************************************/ 2597 2598WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2599{ 2600 /* ! */ 2601 2602 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2603 2604 WORD32 i4_err_status = 0; 2605 UWORD8 *pu1_buf = NULL; 2606 WORD32 buflen; 2607 UWORD32 u4_max_ofst, u4_length_of_start_code = 0; 2608 2609 UWORD32 bytes_consumed = 0; 2610 UWORD32 cur_slice_is_nonref = 0; 2611 UWORD32 u4_next_is_aud; 2612 UWORD32 u4_first_start_code_found = 0; 2613 WORD32 ret = 0,api_ret_value = IV_SUCCESS; 2614 WORD32 header_data_left = 0,frame_data_left = 0; 2615 UWORD8 *pu1_bitstrm_buf; 2616 ivd_video_decode_ip_t *ps_dec_ip; 2617 ivd_video_decode_op_t *ps_dec_op; 2618 2619 ithread_set_name((void*)"Parse_thread"); 2620 2621 ps_dec_ip = (ivd_video_decode_ip_t *)pv_api_ip; 2622 ps_dec_op = (ivd_video_decode_op_t *)pv_api_op; 2623 2624 { 2625 UWORD32 u4_size; 2626 u4_size = ps_dec_op->u4_size; 2627 memset(ps_dec_op, 0, sizeof(ivd_video_decode_op_t)); 2628 ps_dec_op->u4_size = u4_size; 2629 } 2630 2631 ps_dec->pv_dec_out = ps_dec_op; 2632 ps_dec->process_called = 1; 2633 if(ps_dec->init_done != 1) 2634 { 2635 return IV_FAIL; 2636 } 2637 2638 /*Data memory barries instruction,so that bitstream write by the application is complete*/ 2639 DATA_SYNC(); 2640 2641 if(0 == ps_dec->u1_flushfrm) 2642 { 2643 if(ps_dec_ip->pv_stream_buffer == NULL) 2644 { 2645 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2646 ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL; 2647 return IV_FAIL; 2648 } 2649 if(ps_dec_ip->u4_num_Bytes <= 0) 2650 { 2651 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2652 ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV; 2653 return IV_FAIL; 2654 2655 } 2656 } 2657 ps_dec->u1_pic_decode_done = 0; 2658 2659 ps_dec_op->u4_num_bytes_consumed = 0; 2660 2661 ps_dec->ps_out_buffer = NULL; 2662 2663 if(ps_dec_ip->u4_size 2664 >= offsetof(ivd_video_decode_ip_t, s_out_buffer)) 2665 ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer; 2666 2667 ps_dec->u4_fmt_conv_cur_row = 0; 2668 2669 ps_dec->u4_output_present = 0; 2670 ps_dec->s_disp_op.u4_error_code = 1; 2671 ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS; 2672 ps_dec->u4_stop_threads = 0; 2673 if(0 == ps_dec->u4_share_disp_buf 2674 && ps_dec->i4_decode_header == 0) 2675 { 2676 UWORD32 i; 2677 if(ps_dec->ps_out_buffer->u4_num_bufs == 0) 2678 { 2679 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2680 ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS; 2681 return IV_FAIL; 2682 } 2683 2684 for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++) 2685 { 2686 if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL) 2687 { 2688 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2689 ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL; 2690 return IV_FAIL; 2691 } 2692 2693 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0) 2694 { 2695 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2696 ps_dec_op->u4_error_code |= 2697 IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 2698 return IV_FAIL; 2699 } 2700 } 2701 } 2702 2703 if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT) 2704 { 2705 ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER; 2706 return IV_FAIL; 2707 } 2708 2709 /* ! */ 2710 ps_dec->u4_ts = ps_dec_ip->u4_ts; 2711 2712 ps_dec_op->u4_error_code = 0; 2713 ps_dec_op->e_pic_type = -1; 2714 ps_dec_op->u4_output_present = 0; 2715 ps_dec_op->u4_frame_decoded_flag = 0; 2716 2717 ps_dec->i4_frametype = -1; 2718 ps_dec->i4_content_type = -1; 2719 2720 ps_dec->u4_slice_start_code_found = 0; 2721 2722 /* In case the deocder is not in flush mode(in shared mode), 2723 then decoder has to pick up a buffer to write current frame. 2724 Check if a frame is available in such cases */ 2725 2726 if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1 2727 && ps_dec->u1_flushfrm == 0) 2728 { 2729 UWORD32 i; 2730 2731 WORD32 disp_avail = 0, free_id; 2732 2733 /* Check if at least one buffer is available with the codec */ 2734 /* If not then return to application with error */ 2735 for(i = 0; i < ps_dec->u1_pic_bufs; i++) 2736 { 2737 if(0 == ps_dec->u4_disp_buf_mapping[i] 2738 || 1 == ps_dec->u4_disp_buf_to_be_freed[i]) 2739 { 2740 disp_avail = 1; 2741 break; 2742 } 2743 2744 } 2745 2746 if(0 == disp_avail) 2747 { 2748 /* If something is queued for display wait for that buffer to be returned */ 2749 2750 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL; 2751 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 2752 return (IV_FAIL); 2753 } 2754 2755 while(1) 2756 { 2757 pic_buffer_t *ps_pic_buf; 2758 ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free( 2759 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id); 2760 2761 if(ps_pic_buf == NULL) 2762 { 2763 UWORD32 i, display_queued = 0; 2764 2765 /* check if any buffer was given for display which is not returned yet */ 2766 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++) 2767 { 2768 if(0 != ps_dec->u4_disp_buf_mapping[i]) 2769 { 2770 display_queued = 1; 2771 break; 2772 } 2773 } 2774 /* If some buffer is queued for display, then codec has to singal an error and wait 2775 for that buffer to be returned. 2776 If nothing is queued for display then codec has ownership of all display buffers 2777 and it can reuse any of the existing buffers and continue decoding */ 2778 2779 if(1 == display_queued) 2780 { 2781 /* If something is queued for display wait for that buffer to be returned */ 2782 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL; 2783 ps_dec_op->u4_error_code |= (1 2784 << IVD_UNSUPPORTEDPARAM); 2785 return (IV_FAIL); 2786 } 2787 } 2788 else 2789 { 2790 /* If the buffer is with display, then mark it as in use and then look for a buffer again */ 2791 if(1 == ps_dec->u4_disp_buf_mapping[free_id]) 2792 { 2793 ih264_buf_mgr_set_status( 2794 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 2795 free_id, 2796 BUF_MGR_IO); 2797 } 2798 else 2799 { 2800 /** 2801 * Found a free buffer for present call. Release it now. 2802 * Will be again obtained later. 2803 */ 2804 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 2805 free_id, 2806 BUF_MGR_IO); 2807 break; 2808 } 2809 } 2810 } 2811 2812 } 2813 2814 if(ps_dec->u1_flushfrm && ps_dec->u1_init_dec_flag) 2815 { 2816 2817 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer, 2818 &(ps_dec->s_disp_op)); 2819 if(0 == ps_dec->s_disp_op.u4_error_code) 2820 { 2821 ps_dec->u4_fmt_conv_cur_row = 0; 2822 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht; 2823 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 2824 ps_dec->u4_fmt_conv_cur_row, 2825 ps_dec->u4_fmt_conv_num_rows); 2826 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 2827 ps_dec->u4_output_present = 1; 2828 2829 } 2830 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op)); 2831 2832 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 2833 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 2834 2835 ps_dec_op->u4_new_seq = 0; 2836 2837 ps_dec_op->u4_output_present = ps_dec->u4_output_present; 2838 ps_dec_op->u4_progressive_frame_flag = 2839 ps_dec->s_disp_op.u4_progressive_frame_flag; 2840 ps_dec_op->e_output_format = 2841 ps_dec->s_disp_op.e_output_format; 2842 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf; 2843 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type; 2844 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts; 2845 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id; 2846 2847 /*In the case of flush ,since no frame is decoded set pic type as invalid*/ 2848 ps_dec_op->u4_is_ref_flag = -1; 2849 ps_dec_op->e_pic_type = IV_NA_FRAME; 2850 ps_dec_op->u4_frame_decoded_flag = 0; 2851 2852 if(0 == ps_dec->s_disp_op.u4_error_code) 2853 { 2854 return (IV_SUCCESS); 2855 } 2856 else 2857 return (IV_FAIL); 2858 2859 } 2860 if(ps_dec->u1_res_changed == 1) 2861 { 2862 /*if resolution has changed and all buffers have been flushed, reset decoder*/ 2863 ih264d_init_decoder(ps_dec); 2864 } 2865 2866 ps_dec->u4_prev_nal_skipped = 0; 2867 2868 ps_dec->u2_cur_mb_addr = 0; 2869 ps_dec->u2_total_mbs_coded = 0; 2870 ps_dec->u2_cur_slice_num = 0; 2871 ps_dec->cur_dec_mb_num = 0; 2872 ps_dec->cur_recon_mb_num = 0; 2873 ps_dec->u4_first_slice_in_pic = 2; 2874 ps_dec->u1_first_pb_nal_in_pic = 1; 2875 ps_dec->u1_slice_header_done = 0; 2876 ps_dec->u1_dangling_field = 0; 2877 2878 ps_dec->u4_dec_thread_created = 0; 2879 ps_dec->u4_bs_deblk_thread_created = 0; 2880 ps_dec->u4_cur_bs_mb_num = 0; 2881 ps_dec->u4_start_recon_deblk = 0; 2882 2883 DEBUG_THREADS_PRINTF(" Starting process call\n"); 2884 2885 ps_dec->u4_pic_buf_got = 0; 2886 2887 do 2888 { 2889 2890 pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer 2891 + ps_dec_op->u4_num_bytes_consumed; 2892 2893 u4_max_ofst = ps_dec_ip->u4_num_Bytes 2894 - ps_dec_op->u4_num_bytes_consumed; 2895 pu1_bitstrm_buf = ps_dec->ps_mem_tab[MEM_REC_BITSBUF].pv_base; 2896 2897 u4_next_is_aud = 0; 2898 2899 buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst, 2900 &u4_length_of_start_code, 2901 &u4_next_is_aud); 2902 2903 if(buflen == -1) 2904 buflen = 0; 2905 /* Ignore bytes beyond the allocated size of intermediate buffer */ 2906 /* Since 8 bytes are read ahead, ensure 8 bytes are free at the 2907 end of the buffer, which will be memset to 0 after emulation prevention */ 2908 buflen = MIN(buflen, (WORD32)(ps_dec->ps_mem_tab[MEM_REC_BITSBUF].u4_mem_size - 8)); 2909 2910 bytes_consumed = buflen + u4_length_of_start_code; 2911 ps_dec_op->u4_num_bytes_consumed += bytes_consumed; 2912 2913 if(buflen >= MAX_NAL_UNIT_SIZE) 2914 { 2915 2916 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op); 2917 H264_DEC_DEBUG_PRINT( 2918 "\nNal Size exceeded %d, Processing Stopped..\n", 2919 MAX_NAL_UNIT_SIZE); 2920 ps_dec->i4_error_code = 1 << IVD_CORRUPTEDDATA; 2921 2922 ps_dec_op->e_pic_type = -1; 2923 /*signal the decode thread*/ 2924 ih264d_signal_decode_thread(ps_dec); 2925 /*signal end of frame decode for curren frame*/ 2926 2927 if(ps_dec->u4_pic_buf_got == 0) 2928 { 2929 if(ps_dec->i4_header_decoded == 3) 2930 { 2931 ps_dec->u2_total_mbs_coded = 2932 ps_dec->ps_cur_sps->u2_max_mb_addr + 1; 2933 } 2934 2935 /* close deblock thread if it is not closed yet*/ 2936 if(ps_dec->u4_num_cores == 3) 2937 { 2938 ih264d_signal_bs_deblk_thread(ps_dec); 2939 } 2940 return IV_FAIL; 2941 } 2942 else 2943 { 2944 ps_dec->u1_pic_decode_done = 1; 2945 continue; 2946 } 2947 } 2948 2949 { 2950 UWORD8 u1_firstbyte, u1_nal_ref_idc; 2951 2952 if(ps_dec->i4_app_skip_mode == IVD_SKIP_B) 2953 { 2954 u1_firstbyte = *(pu1_buf + u4_length_of_start_code); 2955 u1_nal_ref_idc = (UWORD8)(NAL_REF_IDC(u1_firstbyte)); 2956 if(u1_nal_ref_idc == 0) 2957 { 2958 /*skip non reference frames*/ 2959 cur_slice_is_nonref = 1; 2960 continue; 2961 } 2962 else 2963 { 2964 if(1 == cur_slice_is_nonref) 2965 { 2966 /*We have encountered a referenced frame,return to app*/ 2967 ps_dec_op->u4_num_bytes_consumed -= 2968 bytes_consumed; 2969 ps_dec_op->e_pic_type = IV_B_FRAME; 2970 ps_dec_op->u4_error_code = 2971 IVD_DEC_FRM_SKIPPED; 2972 ps_dec_op->u4_error_code |= (1 2973 << IVD_UNSUPPORTEDPARAM); 2974 ps_dec_op->u4_frame_decoded_flag = 0; 2975 ps_dec_op->u4_size = 2976 sizeof(ivd_video_decode_op_t); 2977 /*signal the decode thread*/ 2978 ih264d_signal_decode_thread(ps_dec); 2979 /* close deblock thread if it is not closed yet*/ 2980 if(ps_dec->u4_num_cores == 3) 2981 { 2982 ih264d_signal_bs_deblk_thread(ps_dec); 2983 } 2984 2985 return (IV_FAIL); 2986 } 2987 } 2988 2989 } 2990 2991 } 2992 2993 2994 if(buflen) 2995 { 2996 memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code, 2997 buflen); 2998 u4_first_start_code_found = 1; 2999 3000 } 3001 else 3002 { 3003 /*start code not found*/ 3004 3005 if(u4_first_start_code_found == 0) 3006 { 3007 /*no start codes found in current process call*/ 3008 3009 ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND; 3010 ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA; 3011 3012 if(ps_dec->u4_pic_buf_got == 0) 3013 { 3014 3015 ih264d_fill_output_struct_from_context(ps_dec, 3016 ps_dec_op); 3017 3018 ps_dec_op->u4_error_code = ps_dec->i4_error_code; 3019 ps_dec_op->u4_frame_decoded_flag = 0; 3020 3021 return (IV_FAIL); 3022 } 3023 else 3024 { 3025 ps_dec->u1_pic_decode_done = 1; 3026 continue; 3027 } 3028 } 3029 else 3030 { 3031 /* a start code has already been found earlier in the same process call*/ 3032 frame_data_left = 0; 3033 header_data_left = 0; 3034 continue; 3035 } 3036 3037 } 3038 3039 ps_dec->u4_return_to_app = 0; 3040 ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op, 3041 pu1_bitstrm_buf, buflen); 3042 if(ret != OK) 3043 { 3044 UWORD32 error = ih264d_map_error(ret); 3045 ps_dec_op->u4_error_code = error | ret; 3046 api_ret_value = IV_FAIL; 3047 3048 if((ret == IVD_RES_CHANGED) 3049 || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED) 3050 || (ret == ERROR_UNAVAIL_PICBUF_T) 3051 || (ret == ERROR_UNAVAIL_MVBUF_T) 3052 || (ret == ERROR_INV_SPS_PPS_T)) 3053 { 3054 ps_dec->u4_slice_start_code_found = 0; 3055 break; 3056 } 3057 3058 if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC)) 3059 { 3060 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 3061 api_ret_value = IV_FAIL; 3062 break; 3063 } 3064 3065 if(ret == ERROR_IN_LAST_SLICE_OF_PIC) 3066 { 3067 api_ret_value = IV_FAIL; 3068 break; 3069 } 3070 3071 } 3072 3073 if(ps_dec->u4_return_to_app) 3074 { 3075 /*We have encountered a referenced frame,return to app*/ 3076 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 3077 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED; 3078 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 3079 ps_dec_op->u4_frame_decoded_flag = 0; 3080 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t); 3081 /*signal the decode thread*/ 3082 ih264d_signal_decode_thread(ps_dec); 3083 /* close deblock thread if it is not closed yet*/ 3084 if(ps_dec->u4_num_cores == 3) 3085 { 3086 ih264d_signal_bs_deblk_thread(ps_dec); 3087 } 3088 return (IV_FAIL); 3089 3090 } 3091 3092 3093 3094 header_data_left = ((ps_dec->i4_decode_header == 1) 3095 && (ps_dec->i4_header_decoded != 3) 3096 && (ps_dec_op->u4_num_bytes_consumed 3097 < ps_dec_ip->u4_num_Bytes)); 3098 frame_data_left = (((ps_dec->i4_decode_header == 0) 3099 && ((ps_dec->u1_pic_decode_done == 0) 3100 || (u4_next_is_aud == 1))) 3101 && (ps_dec_op->u4_num_bytes_consumed 3102 < ps_dec_ip->u4_num_Bytes)); 3103 } 3104 while(( header_data_left == 1)||(frame_data_left == 1)); 3105 3106 if((ps_dec->u4_slice_start_code_found == 1) 3107 && ps_dec->u2_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs) 3108 { 3109 // last slice - missing/corruption 3110 WORD32 num_mb_skipped; 3111 WORD32 prev_slice_err; 3112 pocstruct_t temp_poc; 3113 WORD32 ret1; 3114 WORD32 ht_in_mbs; 3115 ht_in_mbs = ps_dec->u2_pic_ht >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag); 3116 num_mb_skipped = (ht_in_mbs * ps_dec->u2_frm_wd_in_mbs) 3117 - ps_dec->u2_total_mbs_coded; 3118 3119 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0)) 3120 prev_slice_err = 1; 3121 else 3122 prev_slice_err = 2; 3123 3124 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u2_total_mbs_coded == 0)) 3125 prev_slice_err = 1; 3126 3127 ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num, 3128 &temp_poc, prev_slice_err); 3129 3130 if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T) || 3131 (ret1 == ERROR_INV_SPS_PPS_T)) 3132 { 3133 ret = ret1; 3134 } 3135 } 3136 3137 if((ret == IVD_RES_CHANGED) 3138 || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED) 3139 || (ret == ERROR_UNAVAIL_PICBUF_T) 3140 || (ret == ERROR_UNAVAIL_MVBUF_T) 3141 || (ret == ERROR_INV_SPS_PPS_T)) 3142 { 3143 3144 /* signal the decode thread */ 3145 ih264d_signal_decode_thread(ps_dec); 3146 /* close deblock thread if it is not closed yet */ 3147 if(ps_dec->u4_num_cores == 3) 3148 { 3149 ih264d_signal_bs_deblk_thread(ps_dec); 3150 } 3151 /* dont consume bitstream for change in resolution case */ 3152 if(ret == IVD_RES_CHANGED) 3153 { 3154 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 3155 } 3156 return IV_FAIL; 3157 } 3158 3159 3160 if(ps_dec->u1_separate_parse) 3161 { 3162 /* If Format conversion is not complete, 3163 complete it here */ 3164 if(ps_dec->u4_num_cores == 2) 3165 { 3166 3167 /*do deblocking of all mbs*/ 3168 if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0)) 3169 { 3170 UWORD32 u4_num_mbs,u4_max_addr; 3171 tfr_ctxt_t s_tfr_ctxt; 3172 tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt; 3173 pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr; 3174 3175 /*BS is done for all mbs while parsing*/ 3176 u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1; 3177 ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1; 3178 3179 3180 ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt, 3181 ps_dec->u2_frm_wd_in_mbs, 0); 3182 3183 3184 u4_num_mbs = u4_max_addr 3185 - ps_dec->u4_cur_deblk_mb_num + 1; 3186 3187 DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs); 3188 3189 if(u4_num_mbs != 0) 3190 ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs, 3191 ps_tfr_cxt,1); 3192 3193 ps_dec->u4_start_recon_deblk = 0; 3194 3195 } 3196 3197 } 3198 3199 /*signal the decode thread*/ 3200 ih264d_signal_decode_thread(ps_dec); 3201 /* close deblock thread if it is not closed yet*/ 3202 if(ps_dec->u4_num_cores == 3) 3203 { 3204 ih264d_signal_bs_deblk_thread(ps_dec); 3205 } 3206 } 3207 3208 3209 DATA_SYNC(); 3210 3211 3212 if((ps_dec_op->u4_error_code & 0xff) 3213 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED) 3214 { 3215 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 3216 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 3217 } 3218 3219//Report if header (sps and pps) has not been decoded yet 3220 if(ps_dec->i4_header_decoded != 3) 3221 { 3222 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA); 3223 3224 } 3225 3226 if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3) 3227 { 3228 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA); 3229 3230 } 3231 if(ps_dec->u4_prev_nal_skipped) 3232 { 3233 /*We have encountered a referenced frame,return to app*/ 3234 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED; 3235 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 3236 ps_dec_op->u4_frame_decoded_flag = 0; 3237 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t); 3238 /* close deblock thread if it is not closed yet*/ 3239 if(ps_dec->u4_num_cores == 3) 3240 { 3241 ih264d_signal_bs_deblk_thread(ps_dec); 3242 } 3243 return (IV_FAIL); 3244 3245 } 3246 3247 if((ps_dec->u4_slice_start_code_found == 1) 3248 && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status)) 3249 { 3250 /* 3251 * For field pictures, set the bottom and top picture decoded u4_flag correctly. 3252 */ 3253 3254 if(ps_dec->ps_cur_slice->u1_field_pic_flag) 3255 { 3256 if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag) 3257 { 3258 ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY; 3259 } 3260 else 3261 { 3262 ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY; 3263 } 3264 } 3265 3266 /* if new frame in not found (if we are still getting slices from previous frame) 3267 * ih264d_deblock_display is not called. Such frames will not be added to reference /display 3268 */ 3269 if (((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0) 3270 && (ps_dec->u4_pic_buf_got == 1)) 3271 { 3272 /* Calling Function to deblock Picture and Display */ 3273 ret = ih264d_deblock_display(ps_dec); 3274 } 3275 3276 3277 /*set to complete ,as we dont support partial frame decode*/ 3278 if(ps_dec->i4_header_decoded == 3) 3279 { 3280 ps_dec->u2_total_mbs_coded = ps_dec->ps_cur_sps->u2_max_mb_addr + 1; 3281 } 3282 3283 /*Update the i4_frametype at the end of picture*/ 3284 if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL) 3285 { 3286 ps_dec->i4_frametype = IV_IDR_FRAME; 3287 } 3288 else if(ps_dec->i4_pic_type == B_SLICE) 3289 { 3290 ps_dec->i4_frametype = IV_B_FRAME; 3291 } 3292 else if(ps_dec->i4_pic_type == P_SLICE) 3293 { 3294 ps_dec->i4_frametype = IV_P_FRAME; 3295 } 3296 else if(ps_dec->i4_pic_type == I_SLICE) 3297 { 3298 ps_dec->i4_frametype = IV_I_FRAME; 3299 } 3300 else 3301 { 3302 H264_DEC_DEBUG_PRINT("Shouldn't come here\n"); 3303 } 3304 3305 //Update the content type 3306 ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag; 3307 3308 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2; 3309 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded 3310 - ps_dec->ps_cur_slice->u1_field_pic_flag; 3311 3312 } 3313 3314 /* close deblock thread if it is not closed yet*/ 3315 if(ps_dec->u4_num_cores == 3) 3316 { 3317 ih264d_signal_bs_deblk_thread(ps_dec); 3318 } 3319 3320 3321 { 3322 /* In case the decoder is configured to run in low delay mode, 3323 * then get display buffer and then format convert. 3324 * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles 3325 */ 3326 3327 if((0 == ps_dec->u4_num_reorder_frames_at_init) 3328 && ps_dec->u1_init_dec_flag) 3329 { 3330 3331 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer, 3332 &(ps_dec->s_disp_op)); 3333 if(0 == ps_dec->s_disp_op.u4_error_code) 3334 { 3335 ps_dec->u4_fmt_conv_cur_row = 0; 3336 ps_dec->u4_output_present = 1; 3337 } 3338 } 3339 3340 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op); 3341 3342 /* If Format conversion is not complete, 3343 complete it here */ 3344 if(ps_dec->u4_output_present && 3345 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht)) 3346 { 3347 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht 3348 - ps_dec->u4_fmt_conv_cur_row; 3349 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 3350 ps_dec->u4_fmt_conv_cur_row, 3351 ps_dec->u4_fmt_conv_num_rows); 3352 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 3353 } 3354 3355 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op)); 3356 } 3357 3358 if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1) 3359 { 3360 ps_dec_op->u4_progressive_frame_flag = 1; 3361 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3362 { 3363 if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag) 3364 && (0 == ps_dec->ps_sps->u1_mb_aff_flag)) 3365 ps_dec_op->u4_progressive_frame_flag = 0; 3366 3367 } 3368 } 3369 3370 if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded) 3371 { 3372 ps_dec->u1_top_bottom_decoded = 0; 3373 } 3374 /*--------------------------------------------------------------------*/ 3375 /* Do End of Pic processing. */ 3376 /* Should be called only if frame was decoded in previous process call*/ 3377 /*--------------------------------------------------------------------*/ 3378 if(ps_dec->u4_pic_buf_got == 1) 3379 { 3380 if(1 == ps_dec->u1_last_pic_not_decoded) 3381 { 3382 ret = ih264d_end_of_pic_dispbuf_mgr(ps_dec); 3383 3384 if(ret != OK) 3385 return ret; 3386 3387 ret = ih264d_end_of_pic(ps_dec); 3388 if(ret != OK) 3389 return ret; 3390 } 3391 else 3392 { 3393 ret = ih264d_end_of_pic(ps_dec); 3394 if(ret != OK) 3395 return ret; 3396 } 3397 3398 } 3399 3400 3401 /*Data memory barrier instruction,so that yuv write by the library is complete*/ 3402 DATA_SYNC(); 3403 3404 H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n", 3405 ps_dec_op->u4_num_bytes_consumed); 3406 return api_ret_value; 3407} 3408 3409WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3410{ 3411 char version_string[MAXVERSION_STRLEN + 1]; 3412 UWORD32 version_string_len; 3413 3414 ivd_ctl_getversioninfo_ip_t *ps_ip; 3415 ivd_ctl_getversioninfo_op_t *ps_op; 3416 3417 ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip; 3418 ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op; 3419 UNUSED(dec_hdl); 3420 ps_op->u4_error_code = IV_SUCCESS; 3421 3422 VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER, 3423 CODEC_VENDOR); 3424 3425 if((WORD32)ps_ip->u4_version_buffer_size <= 0) 3426 { 3427 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT; 3428 return (IV_FAIL); 3429 } 3430 3431 version_string_len = strlen(version_string) + 1; 3432 3433 if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string))) 3434 { 3435 memcpy(ps_ip->pv_version_buffer, version_string, version_string_len); 3436 ps_op->u4_error_code = IV_SUCCESS; 3437 } 3438 else 3439 { 3440 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT; 3441 return IV_FAIL; 3442 } 3443 return (IV_SUCCESS); 3444} 3445 3446/*****************************************************************************/ 3447/* */ 3448/* Function Name : ih264d_get_display_frame */ 3449/* */ 3450/* Description : */ 3451/* Inputs :iv_obj_t decoder handle */ 3452/* :pv_api_ip pointer to input structure */ 3453/* :pv_api_op pointer to output structure */ 3454/* Outputs : */ 3455/* Returns : void */ 3456/* */ 3457/* Issues : none */ 3458/* */ 3459/* Revision History: */ 3460/* */ 3461/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3462/* 22 10 2008 100356 Draft */ 3463/* */ 3464/*****************************************************************************/ 3465WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl, 3466 void *pv_api_ip, 3467 void *pv_api_op) 3468{ 3469 3470 UNUSED(dec_hdl); 3471 UNUSED(pv_api_ip); 3472 UNUSED(pv_api_op); 3473 // This function is no longer needed, output is returned in the process() 3474 return IV_FAIL; 3475} 3476 3477/*****************************************************************************/ 3478/* */ 3479/* Function Name : ih264d_set_display_frame */ 3480/* */ 3481/* Description : */ 3482/* */ 3483/* Inputs :iv_obj_t decoder handle */ 3484/* :pv_api_ip pointer to input structure */ 3485/* :pv_api_op pointer to output structure */ 3486/* Outputs : */ 3487/* Returns : void */ 3488/* */ 3489/* Issues : none */ 3490/* */ 3491/* Revision History: */ 3492/* */ 3493/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3494/* 22 10 2008 100356 Draft */ 3495/* */ 3496/*****************************************************************************/ 3497WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl, 3498 void *pv_api_ip, 3499 void *pv_api_op) 3500{ 3501 3502 ivd_set_display_frame_ip_t *dec_disp_ip; 3503 ivd_set_display_frame_op_t *dec_disp_op; 3504 3505 UWORD32 i, num_mvbank_req; 3506 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3507 3508 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip; 3509 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op; 3510 dec_disp_op->u4_error_code = 0; 3511 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3512 { 3513 UWORD32 level, width_mbs, height_mbs; 3514 3515 level = ps_dec->u4_level_at_init; 3516 width_mbs = ps_dec->u2_frm_wd_in_mbs; 3517 height_mbs = ps_dec->u2_frm_ht_in_mbs; 3518 3519 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) 3520 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames != 64)) 3521 { 3522 num_mvbank_req = ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2; 3523 } 3524 else 3525 { 3526 /*if VUI is not present assume maximum possible refrence frames for the level, 3527 * as max reorder frames*/ 3528 num_mvbank_req = ih264d_get_dpb_size_new(level, width_mbs, 3529 height_mbs); 3530 } 3531 3532 num_mvbank_req += ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 3533 } 3534 else 3535 { 3536 UWORD32 num_bufs_app, num_bufs_level; 3537 UWORD32 num_ref_frames, num_reorder_frames, luma_width; 3538 UWORD32 luma_height, level; 3539 3540 num_ref_frames = ps_dec->u4_num_ref_frames_at_init; 3541 num_reorder_frames = ps_dec->u4_num_reorder_frames_at_init; 3542 level = ps_dec->u4_level_at_init; 3543 luma_width = ps_dec->u4_width_at_init; 3544 luma_height = ps_dec->u4_height_at_init; 3545 3546 num_bufs_app = num_ref_frames + num_reorder_frames + 1; 3547 3548 if(num_bufs_app <= 1) 3549 num_bufs_app = 2; 3550 3551 num_bufs_level = ih264d_get_dpb_size_new(level, (luma_width >> 4), 3552 (luma_height >> 4)); 3553 3554 num_bufs_level = num_bufs_level * 2 + 1; 3555 3556 num_mvbank_req = MIN(num_bufs_level, num_bufs_app); 3557 3558 num_mvbank_req += ps_dec->u4_num_extra_disp_bufs_at_init; 3559 3560 } 3561 3562 ps_dec->u4_num_disp_bufs = 0; 3563 if(ps_dec->u4_share_disp_buf) 3564 { 3565 UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs; 3566 if(u4_num_bufs > MAX_DISP_BUFS_NEW) 3567 u4_num_bufs = MAX_DISP_BUFS_NEW; 3568 3569 u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW); 3570 u4_num_bufs = MIN(u4_num_bufs, num_mvbank_req); 3571 3572 ps_dec->u4_num_disp_bufs = u4_num_bufs; 3573 for(i = 0; i < u4_num_bufs; i++) 3574 { 3575 ps_dec->disp_bufs[i].u4_num_bufs = 3576 dec_disp_ip->s_disp_buffer[i].u4_num_bufs; 3577 3578 ps_dec->disp_bufs[i].buf[0] = 3579 dec_disp_ip->s_disp_buffer[i].pu1_bufs[0]; 3580 ps_dec->disp_bufs[i].buf[1] = 3581 dec_disp_ip->s_disp_buffer[i].pu1_bufs[1]; 3582 ps_dec->disp_bufs[i].buf[2] = 3583 dec_disp_ip->s_disp_buffer[i].pu1_bufs[2]; 3584 3585 ps_dec->disp_bufs[i].u4_bufsize[0] = 3586 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]; 3587 ps_dec->disp_bufs[i].u4_bufsize[1] = 3588 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]; 3589 ps_dec->disp_bufs[i].u4_bufsize[2] = 3590 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]; 3591 3592 } 3593 } 3594 return IV_SUCCESS; 3595 3596} 3597 3598/*****************************************************************************/ 3599/* */ 3600/* Function Name : ih264d_set_flush_mode */ 3601/* */ 3602/* Description : */ 3603/* */ 3604/* Inputs :iv_obj_t decoder handle */ 3605/* :pv_api_ip pointer to input structure */ 3606/* :pv_api_op pointer to output structure */ 3607/* Globals : <Does it use any global variables?> */ 3608/* Outputs : */ 3609/* Returns : void */ 3610/* */ 3611/* Issues : none */ 3612/* */ 3613/* Revision History: */ 3614/* */ 3615/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3616/* 22 10 2008 100356 Draft */ 3617/* */ 3618/*****************************************************************************/ 3619WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3620{ 3621 3622 dec_struct_t * ps_dec; 3623 ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op; 3624 ps_ctl_op->u4_error_code = 0; 3625 3626 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3627 UNUSED(pv_api_ip); 3628 /* ! */ 3629 /* Signal flush frame control call */ 3630 ps_dec->u1_flushfrm = 1; 3631 3632 if( ps_dec->u1_init_dec_flag == 1) 3633 { 3634 3635 ih264d_release_pics_in_dpb((void *)ps_dec, 3636 ps_dec->u1_pic_bufs); 3637 ih264d_release_display_bufs(ps_dec); 3638 } 3639 3640 ps_ctl_op->u4_error_code = 3641 ((ivd_ctl_flush_op_t*)ps_dec->pv_dec_out)->u4_error_code; //verify the value 3642 3643 return IV_SUCCESS; 3644 3645} 3646 3647/*****************************************************************************/ 3648/* */ 3649/* Function Name : ih264d_get_status */ 3650/* */ 3651/* Description : */ 3652/* */ 3653/* Inputs :iv_obj_t decoder handle */ 3654/* :pv_api_ip pointer to input structure */ 3655/* :pv_api_op pointer to output structure */ 3656/* Globals : <Does it use any global variables?> */ 3657/* Outputs : */ 3658/* Returns : void */ 3659/* */ 3660/* Issues : none */ 3661/* */ 3662/* Revision History: */ 3663/* */ 3664/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3665/* 22 10 2008 100356 Draft */ 3666/* */ 3667/*****************************************************************************/ 3668 3669WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3670{ 3671 3672 UWORD32 i; 3673 dec_struct_t * ps_dec; 3674 UWORD32 pic_wd, pic_ht; 3675 ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op; 3676 UNUSED(pv_api_ip); 3677 ps_ctl_op->u4_error_code = 0; 3678 3679 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3680 3681 pic_wd = ps_dec->u4_width_at_init; 3682 pic_ht = ps_dec->u4_height_at_init; 3683 3684 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3685 { 3686 ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height; 3687 ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width; 3688 3689 if(0 == ps_dec->u4_share_disp_buf) 3690 { 3691 pic_wd = ps_dec->u2_disp_width; 3692 pic_ht = ps_dec->u2_disp_height; 3693 3694 } 3695 else 3696 { 3697 pic_wd = ps_dec->u2_frm_wd_y; 3698 pic_ht = ps_dec->u2_frm_ht_y; 3699 } 3700 } 3701 else 3702 { 3703 ps_ctl_op->u4_pic_ht = pic_wd; 3704 ps_ctl_op->u4_pic_wd = pic_ht; 3705 3706 if(1 == ps_dec->u4_share_disp_buf) 3707 { 3708 pic_wd += (PAD_LEN_Y_H << 1); 3709 pic_ht += (PAD_LEN_Y_V << 2); 3710 3711 } 3712 3713 } 3714 3715 if(ps_dec->u4_app_disp_width > pic_wd) 3716 pic_wd = ps_dec->u4_app_disp_width; 3717 if(0 == ps_dec->u4_share_disp_buf) 3718 ps_ctl_op->u4_num_disp_bufs = 1; 3719 else 3720 { 3721 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3722 { 3723 UWORD32 level, width_mbs, height_mbs; 3724 3725 level = ps_dec->u4_level_at_init; 3726 width_mbs = ps_dec->u2_frm_wd_in_mbs; 3727 height_mbs = ps_dec->u2_frm_ht_in_mbs; 3728 3729 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) 3730 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames 3731 != 64)) 3732 { 3733 ps_ctl_op->u4_num_disp_bufs = 3734 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2; 3735 } 3736 else 3737 { 3738 /*if VUI is not present assume maximum possible refrence frames for the level, 3739 * as max reorder frames*/ 3740 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new( 3741 level, width_mbs, height_mbs); 3742 } 3743 3744 ps_ctl_op->u4_num_disp_bufs += 3745 ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 3746 } 3747 else 3748 { 3749 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new( 3750 ps_dec->u4_level_at_init, 3751 (ps_dec->u4_width_at_init >> 4), 3752 (ps_dec->u4_height_at_init >> 4)); 3753 3754 ps_ctl_op->u4_num_disp_bufs += 3755 ps_ctl_op->u4_num_disp_bufs; 3756 3757 ps_ctl_op->u4_num_disp_bufs = 3758 MIN(ps_ctl_op->u4_num_disp_bufs, 3759 (ps_dec->u4_num_ref_frames_at_init 3760 + ps_dec->u4_num_reorder_frames_at_init)); 3761 3762 } 3763 3764 ps_ctl_op->u4_num_disp_bufs = MAX( 3765 ps_ctl_op->u4_num_disp_bufs, 6); 3766 ps_ctl_op->u4_num_disp_bufs = MIN( 3767 ps_ctl_op->u4_num_disp_bufs, 32); 3768 } 3769 3770 ps_ctl_op->u4_error_code = ps_dec->i4_error_code; 3771 3772 ps_ctl_op->u4_frame_rate = 0; //make it proper 3773 ps_ctl_op->u4_bit_rate = 0; //make it proper 3774 ps_ctl_op->e_content_type = ps_dec->i4_content_type; 3775 ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format; 3776 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS; 3777 3778 if(ps_dec->u1_chroma_format == IV_YUV_420P) 3779 { 3780 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420; 3781 } 3782 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 3783 { 3784 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 3785 } 3786 else if(ps_dec->u1_chroma_format == IV_RGB_565) 3787 { 3788 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 3789 } 3790 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 3791 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 3792 { 3793 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP; 3794 } 3795 3796 else 3797 { 3798 //Invalid chroma format; Error code may be updated, verify in testing if needed 3799 ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL; 3800 return IV_FAIL; 3801 } 3802 3803 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++) 3804 { 3805 ps_ctl_op->u4_min_in_buf_size[i] = MIN_IN_BUF_SIZE; 3806 } 3807 3808 /*!*/ 3809 if(ps_dec->u1_chroma_format == IV_YUV_420P) 3810 { 3811 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 3812 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 3813 >> 2; 3814 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht) 3815 >> 2; 3816 } 3817 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 3818 { 3819 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 3820 * 2; 3821 ps_ctl_op->u4_min_out_buf_size[1] = 3822 ps_ctl_op->u4_min_out_buf_size[2] = 0; 3823 } 3824 else if(ps_dec->u1_chroma_format == IV_RGB_565) 3825 { 3826 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 3827 * 2; 3828 ps_ctl_op->u4_min_out_buf_size[1] = 3829 ps_ctl_op->u4_min_out_buf_size[2] = 0; 3830 } 3831 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 3832 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 3833 { 3834 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 3835 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 3836 >> 1; 3837 ps_ctl_op->u4_min_out_buf_size[2] = 0; 3838 } 3839 3840 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs; 3841 return IV_SUCCESS; 3842} 3843 3844/*****************************************************************************/ 3845/* */ 3846/* Function Name : ih264d_get_buf_info */ 3847/* */ 3848/* Description : */ 3849/* */ 3850/* Inputs :iv_obj_t decoder handle */ 3851/* :pv_api_ip pointer to input structure */ 3852/* :pv_api_op pointer to output structure */ 3853/* Globals : <Does it use any global variables?> */ 3854/* Outputs : */ 3855/* Returns : void */ 3856/* */ 3857/* Issues : none */ 3858/* */ 3859/* Revision History: */ 3860/* */ 3861/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3862/* 22 10 2008 100356 Draft */ 3863/* */ 3864/*****************************************************************************/ 3865WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3866{ 3867 3868 dec_struct_t * ps_dec; 3869 UWORD8 i = 0; // Default for 420P format 3870 UWORD16 pic_wd, pic_ht; 3871 ivd_ctl_getbufinfo_op_t *ps_ctl_op = 3872 (ivd_ctl_getbufinfo_op_t*)pv_api_op; 3873 UNUSED(pv_api_ip); 3874 ps_ctl_op->u4_error_code = 0; 3875 3876 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3877 3878 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS; 3879 if(ps_dec->u1_chroma_format == IV_YUV_420P) 3880 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420; 3881 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 3882 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 3883 else if(ps_dec->u1_chroma_format == IV_RGB_565) 3884 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 3885 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 3886 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 3887 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP; 3888 3889 else 3890 { 3891 //Invalid chroma format; Error code may be updated, verify in testing if needed 3892 return IV_FAIL; 3893 } 3894 3895 ps_ctl_op->u4_num_disp_bufs = 1; 3896 3897 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++) 3898 { 3899 ps_ctl_op->u4_min_in_buf_size[i] = MIN_IN_BUF_SIZE; 3900 } 3901 3902 pic_wd = ps_dec->u4_width_at_init; 3903 pic_ht = ps_dec->u4_height_at_init; 3904 3905 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3906 { 3907 3908 if(0 == ps_dec->u4_share_disp_buf) 3909 { 3910 pic_wd = ps_dec->u2_disp_width; 3911 pic_ht = ps_dec->u2_disp_height; 3912 3913 } 3914 else 3915 { 3916 pic_wd = ps_dec->u2_frm_wd_y; 3917 pic_ht = ps_dec->u2_frm_ht_y; 3918 } 3919 3920 } 3921 else 3922 { 3923 if(1 == ps_dec->u4_share_disp_buf) 3924 { 3925 pic_wd += (PAD_LEN_Y_H << 1); 3926 pic_ht += (PAD_LEN_Y_V << 2); 3927 3928 } 3929 } 3930 3931 if((WORD32)ps_dec->u4_app_disp_width > pic_wd) 3932 pic_wd = ps_dec->u4_app_disp_width; 3933 3934 if(0 == ps_dec->u4_share_disp_buf) 3935 ps_ctl_op->u4_num_disp_bufs = 1; 3936 else 3937 { 3938 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3939 { 3940 UWORD32 level, width_mbs, height_mbs; 3941 3942 level = ps_dec->u4_level_at_init; 3943 width_mbs = ps_dec->u2_frm_wd_in_mbs; 3944 height_mbs = ps_dec->u2_frm_ht_in_mbs; 3945 3946 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) 3947 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames 3948 != 64)) 3949 { 3950 ps_ctl_op->u4_num_disp_bufs = 3951 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2; 3952 } 3953 else 3954 { 3955 /*if VUI is not present assume maximum possible refrence frames for the level, 3956 * as max reorder frames*/ 3957 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new( 3958 level, width_mbs, height_mbs); 3959 } 3960 3961 ps_ctl_op->u4_num_disp_bufs += 3962 ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 3963 3964 } 3965 else 3966 { 3967 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new( 3968 ps_dec->u4_level_at_init, 3969 (ps_dec->u4_width_at_init >> 4), 3970 (ps_dec->u4_height_at_init >> 4)); 3971 3972 ps_ctl_op->u4_num_disp_bufs += 3973 ps_ctl_op->u4_num_disp_bufs; 3974 3975 ps_ctl_op->u4_num_disp_bufs = 3976 MIN(ps_ctl_op->u4_num_disp_bufs, 3977 (ps_dec->u4_num_ref_frames_at_init 3978 + ps_dec->u4_num_reorder_frames_at_init)); 3979 3980 } 3981 3982 ps_ctl_op->u4_num_disp_bufs = MAX( 3983 ps_ctl_op->u4_num_disp_bufs, 6); 3984 ps_ctl_op->u4_num_disp_bufs = MIN( 3985 ps_ctl_op->u4_num_disp_bufs, 32); 3986 } 3987 3988 /*!*/ 3989 if(ps_dec->u1_chroma_format == IV_YUV_420P) 3990 { 3991 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 3992 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 3993 >> 2; 3994 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht) 3995 >> 2; 3996 } 3997 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 3998 { 3999 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 4000 * 2; 4001 ps_ctl_op->u4_min_out_buf_size[1] = 4002 ps_ctl_op->u4_min_out_buf_size[2] = 0; 4003 } 4004 else if(ps_dec->u1_chroma_format == IV_RGB_565) 4005 { 4006 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 4007 * 2; 4008 ps_ctl_op->u4_min_out_buf_size[1] = 4009 ps_ctl_op->u4_min_out_buf_size[2] = 0; 4010 } 4011 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 4012 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 4013 { 4014 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 4015 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 4016 >> 1; 4017 ps_ctl_op->u4_min_out_buf_size[2] = 0; 4018 } 4019 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs; 4020 4021 return IV_SUCCESS; 4022} 4023 4024/*****************************************************************************/ 4025/* */ 4026/* Function Name : ih264d_set_params */ 4027/* */ 4028/* Description : */ 4029/* */ 4030/* Inputs :iv_obj_t decoder handle */ 4031/* :pv_api_ip pointer to input structure */ 4032/* :pv_api_op pointer to output structure */ 4033/* Outputs : */ 4034/* Returns : void */ 4035/* */ 4036/* Issues : none */ 4037/* */ 4038/* Revision History: */ 4039/* */ 4040/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4041/* 22 10 2008 100356 Draft */ 4042/* */ 4043/*****************************************************************************/ 4044WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 4045{ 4046 4047 dec_struct_t * ps_dec; 4048 WORD32 ret = IV_SUCCESS; 4049 4050 ivd_ctl_set_config_ip_t *ps_ctl_ip = 4051 (ivd_ctl_set_config_ip_t *)pv_api_ip; 4052 ivd_ctl_set_config_op_t *ps_ctl_op = 4053 (ivd_ctl_set_config_op_t *)pv_api_op; 4054 4055 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 4056 4057 ps_dec->u4_skip_frm_mask = 0; 4058 4059 ps_ctl_op->u4_error_code = 0; 4060 4061 ps_dec->i4_app_skip_mode = ps_ctl_ip->e_frm_skip_mode; 4062 4063 /*Is it really supported test it when you so the corner testing using test app*/ 4064 4065 if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE) 4066 { 4067 4068 if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_P) 4069 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT; 4070 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_B) 4071 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT; 4072 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_PB) 4073 { 4074 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT; 4075 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT; 4076 } 4077 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_I) 4078 ps_dec->u4_skip_frm_mask |= 1 << I_SLC_BIT; 4079 else 4080 { 4081 //dynamic parameter not supported 4082 //Put an appropriate error code to return the error.. 4083 //when you do the error code tests and after that remove this comment 4084 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 4085 ret = IV_FAIL; 4086 } 4087 } 4088 4089 if((0 != ps_dec->u4_app_disp_width) 4090 && (ps_ctl_ip->u4_disp_wd 4091 != ps_dec->u4_app_disp_width)) 4092 { 4093 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 4094 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID; 4095 ret = IV_FAIL; 4096 } 4097 else 4098 { 4099 if((ps_ctl_ip->u4_disp_wd >= ps_dec->u2_pic_wd)/* && (ps_ctl_ip->u4_disp_wd <= ps_dec->u4_width_at_init) */) 4100 { 4101 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd; 4102 } 4103 else if((0 == ps_dec->i4_header_decoded) /*&& (ps_ctl_ip->u4_disp_wd <= ps_dec->u4_width_at_init)*/) 4104 { 4105 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd; 4106 } 4107 else if(ps_ctl_ip->u4_disp_wd == 0) 4108 { 4109 ps_dec->u4_app_disp_width = 0; 4110 } 4111 else 4112 { 4113 /* 4114 * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF) 4115 * does not propogate. 4116 */ 4117 ps_dec->u4_app_disp_width = 0; 4118 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 4119 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID; 4120 ret = IV_FAIL; 4121 } 4122 } 4123 if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME) 4124 ps_dec->i4_decode_header = 0; 4125 else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER) 4126 ps_dec->i4_decode_header = 1; 4127 else 4128 { 4129 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 4130 ps_dec->i4_decode_header = 1; 4131 ret = IV_FAIL; 4132 } 4133 4134 return ret; 4135 4136} 4137 4138/*****************************************************************************/ 4139/* */ 4140/* Function Name : ih264d_set_default_params */ 4141/* */ 4142/* Description : */ 4143/* */ 4144/* Inputs :iv_obj_t decoder handle */ 4145/* :pv_api_ip pointer to input structure */ 4146/* :pv_api_op pointer to output structure */ 4147/* Outputs : */ 4148/* Returns : void */ 4149/* */ 4150/* Issues : none */ 4151/* */ 4152/* Revision History: */ 4153/* */ 4154/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4155/* 08 08 2011 100421 Copied from set_params */ 4156/* */ 4157/*****************************************************************************/ 4158WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl, 4159 void *pv_api_ip, 4160 void *pv_api_op) 4161{ 4162 4163 dec_struct_t * ps_dec; 4164 WORD32 ret = IV_SUCCESS; 4165 4166 ivd_ctl_set_config_op_t *ps_ctl_op = 4167 (ivd_ctl_set_config_op_t *)pv_api_op; 4168 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 4169 UNUSED(pv_api_ip); 4170 4171 4172 { 4173 ps_dec->u4_app_disp_width = 0; 4174 ps_dec->u4_skip_frm_mask = 0; 4175 ps_dec->i4_decode_header = 1; 4176 4177 ps_ctl_op->u4_error_code = 0; 4178 } 4179 4180 4181 return ret; 4182} 4183 4184/*****************************************************************************/ 4185/* */ 4186/* Function Name : ih264d_reset */ 4187/* */ 4188/* Description : */ 4189/* */ 4190/* Inputs :iv_obj_t decoder handle */ 4191/* :pv_api_ip pointer to input structure */ 4192/* :pv_api_op pointer to output structure */ 4193/* Globals : <Does it use any global variables?> */ 4194/* Outputs : */ 4195/* Returns : void */ 4196/* */ 4197/* Issues : none */ 4198/* */ 4199/* Revision History: */ 4200/* */ 4201/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4202/* 22 10 2008 100356 Draft */ 4203/* */ 4204/*****************************************************************************/ 4205WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 4206{ 4207 dec_struct_t * ps_dec; 4208 ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op; 4209 UNUSED(pv_api_ip); 4210 ps_ctl_op->u4_error_code = 0; 4211 4212 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 4213//CHECK 4214 if(ps_dec != NULL) 4215 { 4216 4217 ih264d_init_decoder(ps_dec); 4218 4219 /* 4220 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t)); 4221 memset(ps_dec->u4_disp_buf_mapping, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 4222 memset(ps_dec->u4_disp_buf_to_be_freed, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 4223 */ 4224 } 4225 else 4226 { 4227 H264_DEC_DEBUG_PRINT( 4228 "\nReset called without Initializing the decoder\n"); 4229 ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE; 4230 } 4231 4232 return IV_SUCCESS; 4233} 4234 4235/*****************************************************************************/ 4236/* */ 4237/* Function Name : ih264d_ctl */ 4238/* */ 4239/* Description : */ 4240/* */ 4241/* Inputs :iv_obj_t decoder handle */ 4242/* :pv_api_ip pointer to input structure */ 4243/* :pv_api_op pointer to output structure */ 4244/* Outputs : */ 4245/* Returns : void */ 4246/* */ 4247/* Issues : none */ 4248/* */ 4249/* Revision History: */ 4250/* */ 4251/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4252/* 22 10 2008 100356 Draft */ 4253/* */ 4254/*****************************************************************************/ 4255WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 4256{ 4257 ivd_ctl_set_config_ip_t *ps_ctl_ip; 4258 ivd_ctl_set_config_op_t *ps_ctl_op; 4259 WORD32 ret = IV_SUCCESS; 4260 UWORD32 subcommand; 4261 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 4262 4263 if(ps_dec->init_done != 1) 4264 { 4265 //Return proper Error Code 4266 return IV_FAIL; 4267 } 4268 ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip; 4269 ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op; 4270 ps_ctl_op->u4_error_code = 0; 4271 subcommand = ps_ctl_ip->e_sub_cmd; 4272 4273 switch(subcommand) 4274 { 4275 case IVD_CMD_CTL_GETPARAMS: 4276 ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip, 4277 (void *)pv_api_op); 4278 break; 4279 case IVD_CMD_CTL_SETPARAMS: 4280 ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip, 4281 (void *)pv_api_op); 4282 break; 4283 case IVD_CMD_CTL_RESET: 4284 ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op); 4285 break; 4286 case IVD_CMD_CTL_SETDEFAULT: 4287 ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip, 4288 (void *)pv_api_op); 4289 break; 4290 case IVD_CMD_CTL_FLUSH: 4291 ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip, 4292 (void *)pv_api_op); 4293 break; 4294 case IVD_CMD_CTL_GETBUFINFO: 4295 ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip, 4296 (void *)pv_api_op); 4297 break; 4298 case IVD_CMD_CTL_GETVERSION: 4299 ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip, 4300 (void *)pv_api_op); 4301 break; 4302 case IH264D_CMD_CTL_DEGRADE: 4303 ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip, 4304 (void *)pv_api_op); 4305 break; 4306 4307 case IH264D_CMD_CTL_SET_NUM_CORES: 4308 ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip, 4309 (void *)pv_api_op); 4310 break; 4311 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS: 4312 ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip, 4313 (void *)pv_api_op); 4314 break; 4315 case IH264D_CMD_CTL_SET_PROCESSOR: 4316 ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip, 4317 (void *)pv_api_op); 4318 break; 4319 default: 4320 H264_DEC_DEBUG_PRINT("\ndo nothing\n") 4321 ; 4322 break; 4323 } 4324 4325 return ret; 4326} 4327/*****************************************************************************/ 4328/* */ 4329/* Function Name : ih264d_rel_display_frame */ 4330/* */ 4331/* Description : */ 4332/* */ 4333/* Inputs :iv_obj_t decoder handle */ 4334/* :pv_api_ip pointer to input structure */ 4335/* :pv_api_op pointer to output structure */ 4336/* Outputs : */ 4337/* Returns : void */ 4338/* */ 4339/* Issues : none */ 4340/* */ 4341/* Revision History: */ 4342/* */ 4343/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4344/* 22 10 2008 100356 Draft */ 4345/* */ 4346/*****************************************************************************/ 4347WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl, 4348 void *pv_api_ip, 4349 void *pv_api_op) 4350{ 4351 4352 ivd_rel_display_frame_ip_t *ps_rel_ip; 4353 ivd_rel_display_frame_op_t *ps_rel_op; 4354 UWORD32 buf_released = 0; 4355 4356 UWORD32 u4_ts = -1; 4357 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 4358 4359 ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip; 4360 ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op; 4361 ps_rel_op->u4_error_code = 0; 4362 u4_ts = ps_rel_ip->u4_disp_buf_id; 4363 4364 if(0 == ps_dec->u4_share_disp_buf) 4365 { 4366 ps_dec->u4_disp_buf_mapping[u4_ts] = 0; 4367 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0; 4368 return IV_SUCCESS; 4369 } 4370 4371 if(ps_dec->pv_pic_buf_mgr != NULL) 4372 { 4373 if(1 == ps_dec->u4_disp_buf_mapping[u4_ts]) 4374 { 4375 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 4376 ps_rel_ip->u4_disp_buf_id, 4377 BUF_MGR_IO); 4378 ps_dec->u4_disp_buf_mapping[u4_ts] = 0; 4379 buf_released = 1; 4380 } 4381 } 4382 4383 if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released)) 4384 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1; 4385 4386 return IV_SUCCESS; 4387} 4388 4389/** 4390 ******************************************************************************* 4391 * 4392 * @brief 4393 * Sets degrade params 4394 * 4395 * @par Description: 4396 * Sets degrade params. 4397 * Refer to ih264d_ctl_degrade_ip_t definition for details 4398 * 4399 * @param[in] ps_codec_obj 4400 * Pointer to codec object at API level 4401 * 4402 * @param[in] pv_api_ip 4403 * Pointer to input argument structure 4404 * 4405 * @param[out] pv_api_op 4406 * Pointer to output argument structure 4407 * 4408 * @returns Status 4409 * 4410 * @remarks 4411 * 4412 * 4413 ******************************************************************************* 4414 */ 4415 4416WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj, 4417 void *pv_api_ip, 4418 void *pv_api_op) 4419{ 4420 ih264d_ctl_degrade_ip_t *ps_ip; 4421 ih264d_ctl_degrade_op_t *ps_op; 4422 dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle; 4423 4424 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip; 4425 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op; 4426 4427 ps_codec->i4_degrade_type = ps_ip->i4_degrade_type; 4428 ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval; 4429 ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics; 4430 4431 ps_op->u4_error_code = 0; 4432 ps_codec->i4_degrade_pic_cnt = 0; 4433 4434 return IV_SUCCESS; 4435} 4436 4437WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl, 4438 void *pv_api_ip, 4439 void *pv_api_op) 4440{ 4441 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip; 4442 ih264d_ctl_get_frame_dimensions_op_t *ps_op; 4443 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 4444 UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset; 4445 4446 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 4447 4448 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op; 4449 UNUSED(ps_ip); 4450 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 4451 { 4452 disp_wd = ps_dec->u2_disp_width; 4453 disp_ht = ps_dec->u2_disp_height; 4454 4455 if(0 == ps_dec->u4_share_disp_buf) 4456 { 4457 buffer_wd = disp_wd; 4458 buffer_ht = disp_ht; 4459 } 4460 else 4461 { 4462 buffer_wd = ps_dec->u2_frm_wd_y; 4463 buffer_ht = ps_dec->u2_frm_ht_y; 4464 } 4465 } 4466 else 4467 { 4468 disp_wd = ps_dec->u4_width_at_init; 4469 disp_ht = ps_dec->u4_height_at_init; 4470 4471 if(0 == ps_dec->u4_share_disp_buf) 4472 { 4473 buffer_wd = disp_wd; 4474 buffer_ht = disp_ht; 4475 } 4476 else 4477 { 4478 buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1); 4479 buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2); 4480 } 4481 } 4482 if(ps_dec->u4_app_disp_width > buffer_wd) 4483 buffer_wd = ps_dec->u4_app_disp_width; 4484 4485 if(0 == ps_dec->u4_share_disp_buf) 4486 { 4487 x_offset = 0; 4488 y_offset = 0; 4489 } 4490 else 4491 { 4492 y_offset = (PAD_LEN_Y_V << 1); 4493 x_offset = PAD_LEN_Y_H; 4494 4495 if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid)) 4496 && (0 != ps_dec->u2_crop_offset_y)) 4497 { 4498 y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y; 4499 x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y; 4500 } 4501 } 4502 4503 ps_op->u4_disp_wd[0] = disp_wd; 4504 ps_op->u4_disp_ht[0] = disp_ht; 4505 ps_op->u4_buffer_wd[0] = buffer_wd; 4506 ps_op->u4_buffer_ht[0] = buffer_ht; 4507 ps_op->u4_x_offset[0] = x_offset; 4508 ps_op->u4_y_offset[0] = y_offset; 4509 4510 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1) 4511 >> 1); 4512 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1) 4513 >> 1); 4514 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0] 4515 >> 1); 4516 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0] 4517 >> 1); 4518 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = 4519 (ps_op->u4_x_offset[0] >> 1); 4520 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = 4521 (ps_op->u4_y_offset[0] >> 1); 4522 4523 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 4524 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 4525 { 4526 ps_op->u4_disp_wd[2] = 0; 4527 ps_op->u4_disp_ht[2] = 0; 4528 ps_op->u4_buffer_wd[2] = 0; 4529 ps_op->u4_buffer_ht[2] = 0; 4530 ps_op->u4_x_offset[2] = 0; 4531 ps_op->u4_y_offset[2] = 0; 4532 4533 ps_op->u4_disp_wd[1] <<= 1; 4534 ps_op->u4_buffer_wd[1] <<= 1; 4535 ps_op->u4_x_offset[1] <<= 1; 4536 } 4537 4538 return IV_SUCCESS; 4539 4540} 4541 4542WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 4543{ 4544 ih264d_ctl_set_num_cores_ip_t *ps_ip; 4545 ih264d_ctl_set_num_cores_op_t *ps_op; 4546 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 4547 4548 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip; 4549 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op; 4550 ps_op->u4_error_code = 0; 4551 ps_dec->u4_num_cores = ps_ip->u4_num_cores; 4552 if(ps_dec->u4_num_cores == 1) 4553 { 4554 ps_dec->u1_separate_parse = 0; 4555 ps_dec->pi4_ctxt_save_register_dec = ps_dec->pi4_ctxt_save_register; 4556 } 4557 else 4558 { 4559 ps_dec->u1_separate_parse = 1; 4560 } 4561 4562 /*using only upto three threads currently*/ 4563 if(ps_dec->u4_num_cores > 3) 4564 ps_dec->u4_num_cores = 3; 4565 4566 return IV_SUCCESS; 4567} 4568 4569void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec, 4570 ivd_video_decode_op_t *ps_dec_op) 4571{ 4572 if((ps_dec_op->u4_error_code & 0xff) 4573 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED) 4574 { 4575 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 4576 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 4577 } 4578 ps_dec_op->e_pic_type = ps_dec->i4_frametype; 4579 4580 ps_dec_op->u4_new_seq = 0; 4581 ps_dec_op->u4_output_present = ps_dec->u4_output_present; 4582 ps_dec_op->u4_progressive_frame_flag = 4583 ps_dec->s_disp_op.u4_progressive_frame_flag; 4584 4585 ps_dec_op->u4_is_ref_flag = 1; 4586 if(ps_dec_op->u4_frame_decoded_flag) 4587 { 4588 if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0) 4589 ps_dec_op->u4_is_ref_flag = 0; 4590 } 4591 4592 ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format; 4593 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf; 4594 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type; 4595 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts; 4596 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id; 4597} 4598 4599/*****************************************************************************/ 4600/* */ 4601/* Function Name : ih264d_api_function */ 4602/* */ 4603/* Description : */ 4604/* */ 4605/* Inputs :iv_obj_t decoder handle */ 4606/* :pv_api_ip pointer to input structure */ 4607/* :pv_api_op pointer to output structure */ 4608/* Outputs : */ 4609/* Returns : void */ 4610/* */ 4611/* Issues : none */ 4612/* */ 4613/* Revision History: */ 4614/* */ 4615/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4616/* 22 10 2008 100356 Draft */ 4617/* */ 4618/*****************************************************************************/ 4619IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl, 4620 void *pv_api_ip, 4621 void *pv_api_op) 4622{ 4623 UWORD32 command; 4624 UWORD32 *pu2_ptr_cmd; 4625 UWORD32 u4_api_ret; 4626 IV_API_CALL_STATUS_T e_status; 4627 e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op); 4628 4629 if(e_status != IV_SUCCESS) 4630 { 4631 UWORD32 *ptr_err; 4632 4633 ptr_err = (UWORD32 *)pv_api_op; 4634 UNUSED(ptr_err); 4635 H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1)); 4636 return IV_FAIL; 4637 } 4638 4639 pu2_ptr_cmd = (UWORD32 *)pv_api_ip; 4640 pu2_ptr_cmd++; 4641 4642 command = *pu2_ptr_cmd; 4643// H264_DEC_DEBUG_PRINT("inside lib = %d\n",command); 4644 switch(command) 4645 { 4646 4647 case IV_CMD_GET_NUM_MEM_REC: 4648 u4_api_ret = ih264d_get_num_rec((void *)pv_api_ip, 4649 (void *)pv_api_op); 4650 4651 break; 4652 case IV_CMD_FILL_NUM_MEM_REC: 4653 4654 u4_api_ret = ih264d_fill_num_mem_rec((void *)pv_api_ip, 4655 (void *)pv_api_op); 4656 break; 4657 case IV_CMD_INIT: 4658 u4_api_ret = ih264d_init(dec_hdl, (void *)pv_api_ip, 4659 (void *)pv_api_op); 4660 break; 4661 4662 case IVD_CMD_VIDEO_DECODE: 4663 u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip, 4664 (void *)pv_api_op); 4665 break; 4666 4667 case IVD_CMD_GET_DISPLAY_FRAME: 4668 u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip, 4669 (void *)pv_api_op); 4670 4671 break; 4672 4673 case IVD_CMD_SET_DISPLAY_FRAME: 4674 u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip, 4675 (void *)pv_api_op); 4676 4677 break; 4678 4679 case IVD_CMD_REL_DISPLAY_FRAME: 4680 u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip, 4681 (void *)pv_api_op); 4682 break; 4683 4684 case IV_CMD_RETRIEVE_MEMREC: 4685 u4_api_ret = ih264d_clr(dec_hdl, (void *)pv_api_ip, 4686 (void *)pv_api_op); 4687 break; 4688 4689 case IVD_CMD_VIDEO_CTL: 4690 u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip, 4691 (void *)pv_api_op); 4692 break; 4693 default: 4694 u4_api_ret = IV_FAIL; 4695 break; 4696 } 4697 4698 return u4_api_ret; 4699} 4700