ih264d_api.c revision aa11ab9fdbb63766703a6280f4fc778f2f2c91ed
1/****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19*/ 20 21/*****************************************************************************/ 22/* */ 23/* File Name : ih264d_api.c */ 24/* */ 25/* Description : Has all API related functions */ 26/* */ 27/* */ 28/* List of Functions : api_check_struct_sanity */ 29/* ih264d_set_processor */ 30/* ih264d_get_num_rec */ 31/* ih264d_init_decoder */ 32/* ih264d_init_video_decoder */ 33/* ih264d_fill_num_mem_rec */ 34/* ih264d_clr */ 35/* ih264d_init */ 36/* ih264d_map_error */ 37/* ih264d_video_decode */ 38/* ih264d_get_version */ 39/* ih264d_get_display_frame */ 40/* ih264d_set_display_frame */ 41/* ih264d_set_flush_mode */ 42/* ih264d_get_status */ 43/* ih264d_get_buf_info */ 44/* ih264d_set_params */ 45/* ih264d_set_default_params */ 46/* ih264d_reset */ 47/* ih264d_ctl */ 48/* ih264d_rel_display_frame */ 49/* ih264d_set_degrade */ 50/* ih264d_get_frame_dimensions */ 51/* ih264d_set_num_cores */ 52/* ih264d_fill_output_struct_from_context */ 53/* ih264d_api_function */ 54/* */ 55/* Issues / Problems : None */ 56/* */ 57/* Revision History : */ 58/* */ 59/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 60/* 14 10 2008 100356(SKV) Draft */ 61/* */ 62/*****************************************************************************/ 63#include "ih264_typedefs.h" 64#include "ih264_macros.h" 65#include "ih264_platform_macros.h" 66#include "ih264d_tables.h" 67#include "iv.h" 68#include "ivd.h" 69#include "ih264d.h" 70#include "ih264d_defs.h" 71 72#include <string.h> 73#include <limits.h> 74#include <stddef.h> 75 76#include "ih264d_inter_pred.h" 77 78#include "ih264d_structs.h" 79#include "ih264d_nal.h" 80#include "ih264d_error_handler.h" 81 82#include "ih264d_defs.h" 83 84#include "ithread.h" 85#include "ih264d_parse_slice.h" 86#include "ih264d_function_selector.h" 87#include "ih264_error.h" 88#include "ih264_disp_mgr.h" 89#include "ih264_buf_mgr.h" 90#include "ih264d_deblocking.h" 91#include "ih264d_parse_cavlc.h" 92#include "ih264d_parse_cabac.h" 93#include "ih264d_utils.h" 94#include "ih264d_format_conv.h" 95#include "ih264d_parse_headers.h" 96#include "ih264d_thread_compute_bs.h" 97#include <assert.h> 98 99 100/*********************/ 101/* Codec Versioning */ 102/*********************/ 103//Move this to where it is used 104#define CODEC_NAME "H264VDEC" 105#define CODEC_RELEASE_TYPE "production" 106#define CODEC_RELEASE_VER "04.00" 107#define CODEC_VENDOR "ITTIAM" 108#define MAXVERSION_STRLEN 511 109#define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \ 110 snprintf(version_string, MAXVERSION_STRLEN, \ 111 "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s", \ 112 codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__) 113 114#define MAX_NAL_UNIT_SIZE MAX((H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_HEIGHT),MIN_NALUNIT_SIZE) 115#define MIN_NALUNIT_SIZE 200000 116 117 118#define MIN_IN_BUFS 1 119#define MIN_OUT_BUFS_420 3 120#define MIN_OUT_BUFS_422ILE 1 121#define MIN_OUT_BUFS_RGB565 1 122#define MIN_OUT_BUFS_420SP 2 123#define MIN_IN_BUF_SIZE (2*1024*1024) // Currently, i4_size set to 500kb, CHECK LATER 124 125#define NUM_FRAMES_LIMIT_ENABLED 0 126 127#if NUM_FRAMES_LIMIT_ENABLED 128#define NUM_FRAMES_LIMIT 10000 129#else 130#define NUM_FRAMES_LIMIT 0x7FFFFFFF 131#endif 132 133 134UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height); 135WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl, 136 void *pv_api_ip, 137 void *pv_api_op); 138WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op); 139 140WORD32 ih264d_deblock_display(dec_struct_t *ps_dec); 141 142void ih264d_signal_decode_thread(dec_struct_t *ps_dec); 143 144void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec); 145void ih264d_decode_picture_thread(dec_struct_t *ps_dec); 146 147WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj, 148 void *pv_api_ip, 149 void *pv_api_op); 150 151void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec, 152 ivd_video_decode_op_t *ps_dec_op); 153 154static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle, 155 void *pv_api_ip, 156 void *pv_api_op) 157{ 158 IVD_API_COMMAND_TYPE_T e_cmd; 159 UWORD32 *pu4_api_ip; 160 UWORD32 *pu4_api_op; 161 UWORD32 i, j; 162 163 if(NULL == pv_api_op) 164 return (IV_FAIL); 165 166 if(NULL == pv_api_ip) 167 return (IV_FAIL); 168 169 pu4_api_ip = (UWORD32 *)pv_api_ip; 170 pu4_api_op = (UWORD32 *)pv_api_op; 171 e_cmd = *(pu4_api_ip + 1); 172 173 /* error checks on handle */ 174 switch((WORD32)e_cmd) 175 { 176 case IV_CMD_GET_NUM_MEM_REC: 177 case IV_CMD_FILL_NUM_MEM_REC: 178 break; 179 case IV_CMD_INIT: 180 if(ps_handle == NULL) 181 { 182 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 183 *(pu4_api_op + 1) |= IVD_HANDLE_NULL; 184 return IV_FAIL; 185 } 186 187 if(ps_handle->u4_size != sizeof(iv_obj_t)) 188 { 189 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 190 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT; 191 H264_DEC_DEBUG_PRINT( 192 "Sizes do not match. Expected: %d, Got: %d", 193 sizeof(iv_obj_t), ps_handle->u4_size); 194 return IV_FAIL; 195 } 196 break; 197 case IVD_CMD_REL_DISPLAY_FRAME: 198 case IVD_CMD_SET_DISPLAY_FRAME: 199 case IVD_CMD_GET_DISPLAY_FRAME: 200 case IVD_CMD_VIDEO_DECODE: 201 case IV_CMD_RETRIEVE_MEMREC: 202 case IVD_CMD_VIDEO_CTL: 203 if(ps_handle == NULL) 204 { 205 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 206 *(pu4_api_op + 1) |= IVD_HANDLE_NULL; 207 return IV_FAIL; 208 } 209 210 if(ps_handle->u4_size != sizeof(iv_obj_t)) 211 { 212 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 213 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT; 214 return IV_FAIL; 215 } 216 217 if(ps_handle->pv_fxns != ih264d_api_function) 218 { 219 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 220 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 221 return IV_FAIL; 222 } 223 224 if(ps_handle->pv_codec_handle == NULL) 225 { 226 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 227 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 228 return IV_FAIL; 229 } 230 break; 231 default: 232 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 233 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD; 234 return IV_FAIL; 235 } 236 237 switch((WORD32)e_cmd) 238 { 239 case IV_CMD_GET_NUM_MEM_REC: 240 { 241 ih264d_num_mem_rec_ip_t *ps_ip = 242 (ih264d_num_mem_rec_ip_t *)pv_api_ip; 243 ih264d_num_mem_rec_op_t *ps_op = 244 (ih264d_num_mem_rec_op_t *)pv_api_op; 245 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0; 246 247 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size 248 != sizeof(ih264d_num_mem_rec_ip_t)) 249 { 250 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 251 << IVD_UNSUPPORTEDPARAM; 252 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 253 IVD_IP_API_STRUCT_SIZE_INCORRECT; 254 return (IV_FAIL); 255 } 256 257 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size 258 != sizeof(ih264d_num_mem_rec_op_t)) 259 { 260 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 261 << IVD_UNSUPPORTEDPARAM; 262 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 263 IVD_OP_API_STRUCT_SIZE_INCORRECT; 264 return (IV_FAIL); 265 } 266 } 267 break; 268 case IV_CMD_FILL_NUM_MEM_REC: 269 { 270 ih264d_fill_mem_rec_ip_t *ps_ip = 271 (ih264d_fill_mem_rec_ip_t *)pv_api_ip; 272 ih264d_fill_mem_rec_op_t *ps_op = 273 (ih264d_fill_mem_rec_op_t *)pv_api_op; 274 iv_mem_rec_t *ps_mem_rec; 275 WORD32 max_wd = ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd; 276 WORD32 max_ht = ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht; 277 278 max_wd = ALIGN16(max_wd); 279 max_ht = ALIGN32(max_ht); 280 281 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0; 282 283 if((ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size 284 > sizeof(ih264d_fill_mem_rec_ip_t)) 285 || (ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size 286 < sizeof(iv_fill_mem_rec_ip_t))) 287 { 288 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 289 << IVD_UNSUPPORTEDPARAM; 290 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 291 IVD_IP_API_STRUCT_SIZE_INCORRECT; 292 return (IV_FAIL); 293 } 294 295 if((ps_op->s_ivd_fill_mem_rec_op_t.u4_size 296 != sizeof(ih264d_fill_mem_rec_op_t)) 297 && (ps_op->s_ivd_fill_mem_rec_op_t.u4_size 298 != sizeof(iv_fill_mem_rec_op_t))) 299 { 300 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 301 << IVD_UNSUPPORTEDPARAM; 302 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 303 IVD_OP_API_STRUCT_SIZE_INCORRECT; 304 return (IV_FAIL); 305 } 306 307 if(max_wd < H264_MIN_FRAME_WIDTH) 308 { 309 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 310 << IVD_UNSUPPORTEDPARAM; 311 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 312 IVD_REQUESTED_WIDTH_NOT_SUPPPORTED; 313 return (IV_FAIL); 314 } 315 316 if(max_wd > H264_MAX_FRAME_WIDTH) 317 { 318 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 319 << IVD_UNSUPPORTEDPARAM; 320 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 321 IVD_REQUESTED_WIDTH_NOT_SUPPPORTED; 322 return (IV_FAIL); 323 } 324 325 if(max_ht < H264_MIN_FRAME_HEIGHT) 326 { 327 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 328 << IVD_UNSUPPORTEDPARAM; 329 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 330 IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED; 331 return (IV_FAIL); 332 } 333 334 if((max_ht * max_wd) 335 > (H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_WIDTH)) 336 337 { 338 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 339 << IVD_UNSUPPORTEDPARAM; 340 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 341 IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED; 342 return (IV_FAIL); 343 } 344 345 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location) 346 { 347 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 348 << IVD_UNSUPPORTEDPARAM; 349 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 350 IVD_NUM_REC_NOT_SUFFICIENT; 351 return (IV_FAIL); 352 } 353 354 /* check memrecords sizes are correct */ 355 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location; 356 for(i = 0; i < MEM_REC_CNT; i++) 357 { 358 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 359 { 360 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 361 << IVD_UNSUPPORTEDPARAM; 362 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 363 IVD_MEM_REC_STRUCT_SIZE_INCORRECT; 364 return IV_FAIL; 365 } 366 } 367 } 368 break; 369 370 case IV_CMD_INIT: 371 { 372 ih264d_init_ip_t *ps_ip = (ih264d_init_ip_t *)pv_api_ip; 373 ih264d_init_op_t *ps_op = (ih264d_init_op_t *)pv_api_op; 374 iv_mem_rec_t *ps_mem_rec; 375 WORD32 max_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd; 376 WORD32 max_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht; 377 378 max_wd = ALIGN16(max_wd); 379 max_ht = ALIGN32(max_ht); 380 381 ps_op->s_ivd_init_op_t.u4_error_code = 0; 382 383 if((ps_ip->s_ivd_init_ip_t.u4_size > sizeof(ih264d_init_ip_t)) 384 || (ps_ip->s_ivd_init_ip_t.u4_size 385 < sizeof(ivd_init_ip_t))) 386 { 387 ps_op->s_ivd_init_op_t.u4_error_code |= 1 388 << IVD_UNSUPPORTEDPARAM; 389 ps_op->s_ivd_init_op_t.u4_error_code |= 390 IVD_IP_API_STRUCT_SIZE_INCORRECT; 391 H264_DEC_DEBUG_PRINT("\n"); 392 return (IV_FAIL); 393 } 394 395 if((ps_op->s_ivd_init_op_t.u4_size != sizeof(ih264d_init_op_t)) 396 && (ps_op->s_ivd_init_op_t.u4_size 397 != sizeof(ivd_init_op_t))) 398 { 399 ps_op->s_ivd_init_op_t.u4_error_code |= 1 400 << IVD_UNSUPPORTEDPARAM; 401 ps_op->s_ivd_init_op_t.u4_error_code |= 402 IVD_OP_API_STRUCT_SIZE_INCORRECT; 403 H264_DEC_DEBUG_PRINT("\n"); 404 return (IV_FAIL); 405 } 406 407 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec != MEM_REC_CNT) 408 { 409 ps_op->s_ivd_init_op_t.u4_error_code |= 1 410 << IVD_UNSUPPORTEDPARAM; 411 ps_op->s_ivd_init_op_t.u4_error_code |= 412 IVD_INIT_DEC_NOT_SUFFICIENT; 413 H264_DEC_DEBUG_PRINT("\n"); 414 return (IV_FAIL); 415 } 416 417 if(max_wd < H264_MIN_FRAME_WIDTH) 418 { 419 ps_op->s_ivd_init_op_t.u4_error_code |= 1 420 << IVD_UNSUPPORTEDPARAM; 421 ps_op->s_ivd_init_op_t.u4_error_code |= 422 IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED; 423 H264_DEC_DEBUG_PRINT("\n"); 424 return (IV_FAIL); 425 } 426 427 if(max_wd > H264_MAX_FRAME_WIDTH) 428 { 429 ps_op->s_ivd_init_op_t.u4_error_code |= 1 430 << IVD_UNSUPPORTEDPARAM; 431 ps_op->s_ivd_init_op_t.u4_error_code |= 432 IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED; 433 H264_DEC_DEBUG_PRINT("\n"); 434 return (IV_FAIL); 435 } 436 437 if(max_ht < H264_MIN_FRAME_HEIGHT) 438 { 439 ps_op->s_ivd_init_op_t.u4_error_code |= 1 440 << IVD_UNSUPPORTEDPARAM; 441 ps_op->s_ivd_init_op_t.u4_error_code |= 442 IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED; 443 H264_DEC_DEBUG_PRINT("\n"); 444 return (IV_FAIL); 445 } 446 447 if((max_ht * max_wd) 448 > (H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_WIDTH)) 449 450 { 451 ps_op->s_ivd_init_op_t.u4_error_code |= 1 452 << IVD_UNSUPPORTEDPARAM; 453 ps_op->s_ivd_init_op_t.u4_error_code |= 454 IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED; 455 H264_DEC_DEBUG_PRINT("\n"); 456 return (IV_FAIL); 457 } 458 459 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location) 460 { 461 ps_op->s_ivd_init_op_t.u4_error_code |= 1 462 << IVD_UNSUPPORTEDPARAM; 463 ps_op->s_ivd_init_op_t.u4_error_code |= 464 IVD_NUM_REC_NOT_SUFFICIENT; 465 H264_DEC_DEBUG_PRINT("\n"); 466 return (IV_FAIL); 467 } 468 469 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) 470 && (ps_ip->s_ivd_init_ip_t.e_output_format 471 != IV_YUV_422ILE) 472 && (ps_ip->s_ivd_init_ip_t.e_output_format 473 != IV_RGB_565) 474 && (ps_ip->s_ivd_init_ip_t.e_output_format 475 != IV_YUV_420SP_UV) 476 && (ps_ip->s_ivd_init_ip_t.e_output_format 477 != IV_YUV_420SP_VU)) 478 { 479 ps_op->s_ivd_init_op_t.u4_error_code |= 1 480 << IVD_UNSUPPORTEDPARAM; 481 ps_op->s_ivd_init_op_t.u4_error_code |= 482 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED; 483 H264_DEC_DEBUG_PRINT("\n"); 484 return (IV_FAIL); 485 } 486 487 /* verify number of mem records */ 488 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < MEM_REC_CNT) 489 { 490 ps_op->s_ivd_init_op_t.u4_error_code |= 1 491 << IVD_UNSUPPORTEDPARAM; 492 ps_op->s_ivd_init_op_t.u4_error_code |= 493 IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT; 494 H264_DEC_DEBUG_PRINT("\n"); 495 return IV_FAIL; 496 } 497 498 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location; 499 /* check memrecords sizes are correct */ 500 for(i = 0; i < ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++) 501 { 502 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 503 { 504 ps_op->s_ivd_init_op_t.u4_error_code |= 1 505 << IVD_UNSUPPORTEDPARAM; 506 ps_op->s_ivd_init_op_t.u4_error_code |= 507 IVD_MEM_REC_STRUCT_SIZE_INCORRECT; 508 H264_DEC_DEBUG_PRINT("i: %d\n", i); 509 return IV_FAIL; 510 } 511 /* check memrecords pointers are not NULL */ 512 513 if(ps_mem_rec[i].pv_base == NULL) 514 { 515 516 ps_op->s_ivd_init_op_t.u4_error_code |= 1 517 << IVD_UNSUPPORTEDPARAM; 518 ps_op->s_ivd_init_op_t.u4_error_code |= 519 IVD_INIT_DEC_MEM_REC_BASE_NULL; 520 H264_DEC_DEBUG_PRINT("i: %d\n", i); 521 return IV_FAIL; 522 523 } 524 525 } 526 527 /* verify memtabs for overlapping regions */ 528 { 529 void *start[MEM_REC_CNT]; 530 void *end[MEM_REC_CNT]; 531 532 start[0] = (void *)(ps_mem_rec[0].pv_base); 533 end[0] = (void *)((UWORD8 *)ps_mem_rec[0].pv_base 534 + ps_mem_rec[0].u4_mem_size - 1); 535 for(i = 1; i < MEM_REC_CNT; i++) 536 { 537 /* This array is populated to check memtab overlapp */ 538 start[i] = (void *)(ps_mem_rec[i].pv_base); 539 end[i] = (void *)((UWORD8 *)ps_mem_rec[i].pv_base 540 + ps_mem_rec[i].u4_mem_size - 1); 541 542 for(j = 0; j < i; j++) 543 { 544 if((start[i] >= start[j]) && (start[i] <= end[j])) 545 { 546 ps_op->s_ivd_init_op_t.u4_error_code |= 1 547 << IVD_UNSUPPORTEDPARAM; 548 ps_op->s_ivd_init_op_t.u4_error_code |= 549 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR; 550 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j); 551 return IV_FAIL; 552 } 553 554 if((end[i] >= start[j]) && (end[i] <= end[j])) 555 { 556 ps_op->s_ivd_init_op_t.u4_error_code |= 1 557 << IVD_UNSUPPORTEDPARAM; 558 ps_op->s_ivd_init_op_t.u4_error_code |= 559 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR; 560 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j); 561 return IV_FAIL; 562 } 563 564 if((start[i] < start[j]) && (end[i] > end[j])) 565 { 566 ps_op->s_ivd_init_op_t.u4_error_code |= 1 567 << IVD_UNSUPPORTEDPARAM; 568 ps_op->s_ivd_init_op_t.u4_error_code |= 569 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR; 570 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j); 571 return IV_FAIL; 572 } 573 } 574 575 } 576 } 577 578 { 579 iv_mem_rec_t mem_rec_ittiam_api[MEM_REC_CNT]; 580 ih264d_fill_mem_rec_ip_t s_fill_mem_rec_ip; 581 ih264d_fill_mem_rec_op_t s_fill_mem_rec_op; 582 IV_API_CALL_STATUS_T e_status; 583 584 UWORD32 i; 585 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd = 586 IV_CMD_FILL_NUM_MEM_REC; 587 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location = 588 mem_rec_ittiam_api; 589 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd = 590 max_wd; 591 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht = 592 max_ht; 593 594 if(ps_ip->s_ivd_init_ip_t.u4_size 595 > offsetof(ih264d_init_ip_t, i4_level)) 596 { 597 s_fill_mem_rec_ip.i4_level = ps_ip->i4_level; 598 } 599 else 600 { 601 s_fill_mem_rec_ip.i4_level = H264_LEVEL_3_1; 602 } 603 604 if(ps_ip->s_ivd_init_ip_t.u4_size 605 > offsetof(ih264d_init_ip_t, u4_num_ref_frames)) 606 { 607 s_fill_mem_rec_ip.u4_num_ref_frames = 608 ps_ip->u4_num_ref_frames; 609 } 610 else 611 { 612 s_fill_mem_rec_ip.u4_num_ref_frames = 613 (H264_MAX_REF_PICS + 1); 614 } 615 616 if(ps_ip->s_ivd_init_ip_t.u4_size 617 > offsetof(ih264d_init_ip_t, 618 u4_num_reorder_frames)) 619 { 620 s_fill_mem_rec_ip.u4_num_reorder_frames = 621 ps_ip->u4_num_reorder_frames; 622 } 623 else 624 { 625 s_fill_mem_rec_ip.u4_num_reorder_frames = (H264_MAX_REF_PICS 626 + 1); 627 } 628 629 if(ps_ip->s_ivd_init_ip_t.u4_size 630 > offsetof(ih264d_init_ip_t, 631 u4_num_extra_disp_buf)) 632 { 633 s_fill_mem_rec_ip.u4_num_extra_disp_buf = 634 ps_ip->u4_num_extra_disp_buf; 635 } 636 else 637 { 638 s_fill_mem_rec_ip.u4_num_extra_disp_buf = 0; 639 } 640 641 if(ps_ip->s_ivd_init_ip_t.u4_size 642 > offsetof(ih264d_init_ip_t, u4_share_disp_buf)) 643 { 644#ifndef LOGO_EN 645 s_fill_mem_rec_ip.u4_share_disp_buf = 646 ps_ip->u4_share_disp_buf; 647#else 648 s_fill_mem_rec_ip.u4_share_disp_buf = 0; 649#endif 650 } 651 else 652 { 653 s_fill_mem_rec_ip.u4_share_disp_buf = 0; 654 } 655 656 s_fill_mem_rec_ip.e_output_format = 657 ps_ip->s_ivd_init_ip_t.e_output_format; 658 659 if((s_fill_mem_rec_ip.e_output_format != IV_YUV_420P) 660 && (s_fill_mem_rec_ip.e_output_format 661 != IV_YUV_420SP_UV) 662 && (s_fill_mem_rec_ip.e_output_format 663 != IV_YUV_420SP_VU)) 664 { 665 s_fill_mem_rec_ip.u4_share_disp_buf = 0; 666 } 667 668 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size = 669 sizeof(ih264d_fill_mem_rec_ip_t); 670 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size = 671 sizeof(ih264d_fill_mem_rec_op_t); 672 673 for(i = 0; i < MEM_REC_CNT; i++) 674 mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t); 675 676 e_status = ih264d_api_function(NULL, 677 (void *)&s_fill_mem_rec_ip, 678 (void *)&s_fill_mem_rec_op); 679 if(IV_FAIL == e_status) 680 { 681 ps_op->s_ivd_init_op_t.u4_error_code = 682 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code; 683 H264_DEC_DEBUG_PRINT("Fail\n"); 684 return (IV_FAIL); 685 } 686 687 for(i = 0; i < MEM_REC_CNT; i++) 688 { 689 if(ps_mem_rec[i].u4_mem_size 690 < mem_rec_ittiam_api[i].u4_mem_size) 691 { 692 ps_op->s_ivd_init_op_t.u4_error_code |= 1 693 << IVD_UNSUPPORTEDPARAM; 694 ps_op->s_ivd_init_op_t.u4_error_code |= 695 IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE; 696 H264_DEC_DEBUG_PRINT("i: %d \n", i); 697 return IV_FAIL; 698 } 699 if(ps_mem_rec[i].u4_mem_alignment 700 != mem_rec_ittiam_api[i].u4_mem_alignment) 701 { 702 ps_op->s_ivd_init_op_t.u4_error_code |= 1 703 << IVD_UNSUPPORTEDPARAM; 704 ps_op->s_ivd_init_op_t.u4_error_code |= 705 IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR; 706 H264_DEC_DEBUG_PRINT("i: %d \n", i); 707 return IV_FAIL; 708 } 709 if(ps_mem_rec[i].e_mem_type 710 != mem_rec_ittiam_api[i].e_mem_type) 711 { 712 UWORD32 check = IV_SUCCESS; 713 UWORD32 diff = mem_rec_ittiam_api[i].e_mem_type 714 - ps_mem_rec[i].e_mem_type; 715 716 if((ps_mem_rec[i].e_mem_type 717 <= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM) 718 && (mem_rec_ittiam_api[i].e_mem_type 719 >= IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM)) 720 { 721 check = IV_FAIL; 722 } 723 if(3 != MOD(mem_rec_ittiam_api[i].e_mem_type, 4)) 724 { 725 /* 726 * It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM 727 */ 728 if((diff < 1) || (diff > 3)) 729 { 730 // Difference between 1 and 3 is okay for all cases other than the two filtered 731 // with the MOD condition above 732 check = IV_FAIL; 733 } 734 } 735 else 736 { 737 if(diff == 1) 738 { 739 /* 740 * This particular case is when codec asked for External Persistent, but got 741 * Internal Scratch. 742 */ 743 check = IV_FAIL; 744 } 745 if((diff != 2) && (diff != 3)) 746 { 747 check = IV_FAIL; 748 } 749 } 750 if(check == IV_FAIL) 751 { 752 ps_op->s_ivd_init_op_t.u4_error_code |= 1 753 << IVD_UNSUPPORTEDPARAM; 754 ps_op->s_ivd_init_op_t.u4_error_code |= 755 IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE; 756 H264_DEC_DEBUG_PRINT("i: %d \n", i); 757 return IV_FAIL; 758 } 759 } 760 } 761 } 762 763 } 764 break; 765 766 case IVD_CMD_GET_DISPLAY_FRAME: 767 { 768 ih264d_get_display_frame_ip_t *ps_ip = 769 (ih264d_get_display_frame_ip_t *)pv_api_ip; 770 ih264d_get_display_frame_op_t *ps_op = 771 (ih264d_get_display_frame_op_t *)pv_api_op; 772 773 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0; 774 775 if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size 776 != sizeof(ih264d_get_display_frame_ip_t)) 777 && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size 778 != sizeof(ivd_get_display_frame_ip_t))) 779 { 780 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 781 << IVD_UNSUPPORTEDPARAM; 782 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 783 IVD_IP_API_STRUCT_SIZE_INCORRECT; 784 return (IV_FAIL); 785 } 786 787 if((ps_op->s_ivd_get_display_frame_op_t.u4_size 788 != sizeof(ih264d_get_display_frame_op_t)) 789 && (ps_op->s_ivd_get_display_frame_op_t.u4_size 790 != sizeof(ivd_get_display_frame_op_t))) 791 { 792 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 793 << IVD_UNSUPPORTEDPARAM; 794 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 795 IVD_OP_API_STRUCT_SIZE_INCORRECT; 796 return (IV_FAIL); 797 } 798 } 799 break; 800 801 case IVD_CMD_REL_DISPLAY_FRAME: 802 { 803 ih264d_rel_display_frame_ip_t *ps_ip = 804 (ih264d_rel_display_frame_ip_t *)pv_api_ip; 805 ih264d_rel_display_frame_op_t *ps_op = 806 (ih264d_rel_display_frame_op_t *)pv_api_op; 807 808 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0; 809 810 if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size 811 != sizeof(ih264d_rel_display_frame_ip_t)) 812 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size 813 != sizeof(ivd_rel_display_frame_ip_t))) 814 { 815 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 816 << IVD_UNSUPPORTEDPARAM; 817 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 818 IVD_IP_API_STRUCT_SIZE_INCORRECT; 819 return (IV_FAIL); 820 } 821 822 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size 823 != sizeof(ih264d_rel_display_frame_op_t)) 824 && (ps_op->s_ivd_rel_display_frame_op_t.u4_size 825 != sizeof(ivd_rel_display_frame_op_t))) 826 { 827 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 828 << IVD_UNSUPPORTEDPARAM; 829 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 830 IVD_OP_API_STRUCT_SIZE_INCORRECT; 831 return (IV_FAIL); 832 } 833 834 } 835 break; 836 837 case IVD_CMD_SET_DISPLAY_FRAME: 838 { 839 ih264d_set_display_frame_ip_t *ps_ip = 840 (ih264d_set_display_frame_ip_t *)pv_api_ip; 841 ih264d_set_display_frame_op_t *ps_op = 842 (ih264d_set_display_frame_op_t *)pv_api_op; 843 UWORD32 j; 844 845 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0; 846 847 if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size 848 != sizeof(ih264d_set_display_frame_ip_t)) 849 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size 850 != sizeof(ivd_set_display_frame_ip_t))) 851 { 852 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 853 << IVD_UNSUPPORTEDPARAM; 854 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 855 IVD_IP_API_STRUCT_SIZE_INCORRECT; 856 return (IV_FAIL); 857 } 858 859 if((ps_op->s_ivd_set_display_frame_op_t.u4_size 860 != sizeof(ih264d_set_display_frame_op_t)) 861 && (ps_op->s_ivd_set_display_frame_op_t.u4_size 862 != sizeof(ivd_set_display_frame_op_t))) 863 { 864 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 865 << IVD_UNSUPPORTEDPARAM; 866 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 867 IVD_OP_API_STRUCT_SIZE_INCORRECT; 868 return (IV_FAIL); 869 } 870 871 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0) 872 { 873 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 874 << IVD_UNSUPPORTEDPARAM; 875 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 876 IVD_DISP_FRM_ZERO_OP_BUFS; 877 return IV_FAIL; 878 } 879 880 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; 881 j++) 882 { 883 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs 884 == 0) 885 { 886 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 887 << IVD_UNSUPPORTEDPARAM; 888 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 889 IVD_DISP_FRM_ZERO_OP_BUFS; 890 return IV_FAIL; 891 } 892 893 for(i = 0; 894 i 895 < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs; 896 i++) 897 { 898 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] 899 == NULL) 900 { 901 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 902 << IVD_UNSUPPORTEDPARAM; 903 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 904 IVD_DISP_FRM_OP_BUF_NULL; 905 return IV_FAIL; 906 } 907 908 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] 909 == 0) 910 { 911 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 912 << IVD_UNSUPPORTEDPARAM; 913 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 914 IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 915 return IV_FAIL; 916 } 917 } 918 } 919 } 920 break; 921 922 case IVD_CMD_VIDEO_DECODE: 923 { 924 ih264d_video_decode_ip_t *ps_ip = 925 (ih264d_video_decode_ip_t *)pv_api_ip; 926 ih264d_video_decode_op_t *ps_op = 927 (ih264d_video_decode_op_t *)pv_api_op; 928 929 H264_DEC_DEBUG_PRINT("The input bytes is: %d", 930 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes); 931 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0; 932 933 if(ps_ip->s_ivd_video_decode_ip_t.u4_size 934 != sizeof(ih264d_video_decode_ip_t)&& 935 ps_ip->s_ivd_video_decode_ip_t.u4_size != offsetof(ivd_video_decode_ip_t, s_out_buffer)) 936 { 937 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 938 << IVD_UNSUPPORTEDPARAM; 939 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 940 IVD_IP_API_STRUCT_SIZE_INCORRECT; 941 return (IV_FAIL); 942 } 943 944 if(ps_op->s_ivd_video_decode_op_t.u4_size 945 != sizeof(ih264d_video_decode_op_t)&& 946 ps_op->s_ivd_video_decode_op_t.u4_size != offsetof(ivd_video_decode_op_t, u4_output_present)) 947 { 948 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 949 << IVD_UNSUPPORTEDPARAM; 950 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 951 IVD_OP_API_STRUCT_SIZE_INCORRECT; 952 return (IV_FAIL); 953 } 954 955 } 956 break; 957 958 case IV_CMD_RETRIEVE_MEMREC: 959 { 960 ih264d_retrieve_mem_rec_ip_t *ps_ip = 961 (ih264d_retrieve_mem_rec_ip_t *)pv_api_ip; 962 ih264d_retrieve_mem_rec_op_t *ps_op = 963 (ih264d_retrieve_mem_rec_op_t *)pv_api_op; 964 iv_mem_rec_t *ps_mem_rec; 965 966 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0; 967 968 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size 969 != sizeof(ih264d_retrieve_mem_rec_ip_t)) 970 { 971 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 972 << IVD_UNSUPPORTEDPARAM; 973 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 974 IVD_IP_API_STRUCT_SIZE_INCORRECT; 975 return (IV_FAIL); 976 } 977 978 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size 979 != sizeof(ih264d_retrieve_mem_rec_op_t)) 980 { 981 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 982 << IVD_UNSUPPORTEDPARAM; 983 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 984 IVD_OP_API_STRUCT_SIZE_INCORRECT; 985 return (IV_FAIL); 986 } 987 988 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location; 989 /* check memrecords sizes are correct */ 990 for(i = 0; i < MEM_REC_CNT; i++) 991 { 992 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 993 { 994 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 995 << IVD_UNSUPPORTEDPARAM; 996 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 997 IVD_MEM_REC_STRUCT_SIZE_INCORRECT; 998 return IV_FAIL; 999 } 1000 } 1001 } 1002 break; 1003 1004 case IVD_CMD_VIDEO_CTL: 1005 { 1006 UWORD32 *pu4_ptr_cmd; 1007 UWORD32 sub_command; 1008 1009 pu4_ptr_cmd = (UWORD32 *)pv_api_ip; 1010 pu4_ptr_cmd += 2; 1011 sub_command = *pu4_ptr_cmd; 1012 1013 switch(sub_command) 1014 { 1015 case IVD_CMD_CTL_SETPARAMS: 1016 { 1017 ih264d_ctl_set_config_ip_t *ps_ip; 1018 ih264d_ctl_set_config_op_t *ps_op; 1019 ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip; 1020 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op; 1021 1022 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size 1023 != sizeof(ih264d_ctl_set_config_ip_t)) 1024 { 1025 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 1026 << IVD_UNSUPPORTEDPARAM; 1027 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1028 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1029 return IV_FAIL; 1030 } 1031 } 1032 //no break; is needed here 1033 case IVD_CMD_CTL_SETDEFAULT: 1034 { 1035 ih264d_ctl_set_config_op_t *ps_op; 1036 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op; 1037 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size 1038 != sizeof(ih264d_ctl_set_config_op_t)) 1039 { 1040 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 1041 << IVD_UNSUPPORTEDPARAM; 1042 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1043 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1044 return IV_FAIL; 1045 } 1046 } 1047 break; 1048 1049 case IVD_CMD_CTL_GETPARAMS: 1050 { 1051 ih264d_ctl_getstatus_ip_t *ps_ip; 1052 ih264d_ctl_getstatus_op_t *ps_op; 1053 1054 ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip; 1055 ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op; 1056 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size 1057 != sizeof(ih264d_ctl_getstatus_ip_t)) 1058 { 1059 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 1060 << IVD_UNSUPPORTEDPARAM; 1061 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1062 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1063 return IV_FAIL; 1064 } 1065 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size 1066 != sizeof(ih264d_ctl_getstatus_op_t)) 1067 { 1068 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 1069 << IVD_UNSUPPORTEDPARAM; 1070 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1071 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1072 return IV_FAIL; 1073 } 1074 } 1075 break; 1076 1077 case IVD_CMD_CTL_GETBUFINFO: 1078 { 1079 ih264d_ctl_getbufinfo_ip_t *ps_ip; 1080 ih264d_ctl_getbufinfo_op_t *ps_op; 1081 ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip; 1082 ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op; 1083 1084 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size 1085 != sizeof(ih264d_ctl_getbufinfo_ip_t)) 1086 { 1087 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 1088 << IVD_UNSUPPORTEDPARAM; 1089 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1090 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1091 return IV_FAIL; 1092 } 1093 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size 1094 != sizeof(ih264d_ctl_getbufinfo_op_t)) 1095 { 1096 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 1097 << IVD_UNSUPPORTEDPARAM; 1098 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1099 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1100 return IV_FAIL; 1101 } 1102 } 1103 break; 1104 1105 case IVD_CMD_CTL_GETVERSION: 1106 { 1107 ih264d_ctl_getversioninfo_ip_t *ps_ip; 1108 ih264d_ctl_getversioninfo_op_t *ps_op; 1109 ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip; 1110 ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op; 1111 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size 1112 != sizeof(ih264d_ctl_getversioninfo_ip_t)) 1113 { 1114 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 1115 << IVD_UNSUPPORTEDPARAM; 1116 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1117 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1118 return IV_FAIL; 1119 } 1120 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size 1121 != sizeof(ih264d_ctl_getversioninfo_op_t)) 1122 { 1123 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 1124 << IVD_UNSUPPORTEDPARAM; 1125 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1126 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1127 return IV_FAIL; 1128 } 1129 } 1130 break; 1131 1132 case IVD_CMD_CTL_FLUSH: 1133 { 1134 ih264d_ctl_flush_ip_t *ps_ip; 1135 ih264d_ctl_flush_op_t *ps_op; 1136 ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip; 1137 ps_op = (ih264d_ctl_flush_op_t *)pv_api_op; 1138 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size 1139 != sizeof(ih264d_ctl_flush_ip_t)) 1140 { 1141 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 1142 << IVD_UNSUPPORTEDPARAM; 1143 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1144 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1145 return IV_FAIL; 1146 } 1147 if(ps_op->s_ivd_ctl_flush_op_t.u4_size 1148 != sizeof(ih264d_ctl_flush_op_t)) 1149 { 1150 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 1151 << IVD_UNSUPPORTEDPARAM; 1152 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1153 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1154 return IV_FAIL; 1155 } 1156 } 1157 break; 1158 1159 case IVD_CMD_CTL_RESET: 1160 { 1161 ih264d_ctl_reset_ip_t *ps_ip; 1162 ih264d_ctl_reset_op_t *ps_op; 1163 ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip; 1164 ps_op = (ih264d_ctl_reset_op_t *)pv_api_op; 1165 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size 1166 != sizeof(ih264d_ctl_reset_ip_t)) 1167 { 1168 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 1169 << IVD_UNSUPPORTEDPARAM; 1170 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1171 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1172 return IV_FAIL; 1173 } 1174 if(ps_op->s_ivd_ctl_reset_op_t.u4_size 1175 != sizeof(ih264d_ctl_reset_op_t)) 1176 { 1177 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 1178 << IVD_UNSUPPORTEDPARAM; 1179 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1180 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1181 return IV_FAIL; 1182 } 1183 } 1184 break; 1185 1186 case IH264D_CMD_CTL_DEGRADE: 1187 { 1188 ih264d_ctl_degrade_ip_t *ps_ip; 1189 ih264d_ctl_degrade_op_t *ps_op; 1190 1191 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip; 1192 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op; 1193 1194 if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t)) 1195 { 1196 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1197 ps_op->u4_error_code |= 1198 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1199 return IV_FAIL; 1200 } 1201 1202 if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t)) 1203 { 1204 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1205 ps_op->u4_error_code |= 1206 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1207 return IV_FAIL; 1208 } 1209 1210 if((ps_ip->i4_degrade_pics < 0) 1211 || (ps_ip->i4_degrade_pics > 4) 1212 || (ps_ip->i4_nondegrade_interval < 0) 1213 || (ps_ip->i4_degrade_type < 0) 1214 || (ps_ip->i4_degrade_type > 15)) 1215 { 1216 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1217 return IV_FAIL; 1218 } 1219 1220 break; 1221 } 1222 1223 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS: 1224 { 1225 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip; 1226 ih264d_ctl_get_frame_dimensions_op_t *ps_op; 1227 1228 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 1229 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op; 1230 1231 if(ps_ip->u4_size 1232 != sizeof(ih264d_ctl_get_frame_dimensions_ip_t)) 1233 { 1234 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1235 ps_op->u4_error_code |= 1236 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1237 return IV_FAIL; 1238 } 1239 1240 if(ps_op->u4_size 1241 != sizeof(ih264d_ctl_get_frame_dimensions_op_t)) 1242 { 1243 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1244 ps_op->u4_error_code |= 1245 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1246 return IV_FAIL; 1247 } 1248 1249 break; 1250 } 1251 1252 case IH264D_CMD_CTL_SET_NUM_CORES: 1253 { 1254 ih264d_ctl_set_num_cores_ip_t *ps_ip; 1255 ih264d_ctl_set_num_cores_op_t *ps_op; 1256 1257 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip; 1258 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op; 1259 1260 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t)) 1261 { 1262 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1263 ps_op->u4_error_code |= 1264 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1265 return IV_FAIL; 1266 } 1267 1268 if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t)) 1269 { 1270 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1271 ps_op->u4_error_code |= 1272 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1273 return IV_FAIL; 1274 } 1275 1276 if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2) 1277 && (ps_ip->u4_num_cores != 3) 1278 && (ps_ip->u4_num_cores != 4)) 1279 { 1280 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1281 return IV_FAIL; 1282 } 1283 break; 1284 } 1285 case IH264D_CMD_CTL_SET_PROCESSOR: 1286 { 1287 ih264d_ctl_set_processor_ip_t *ps_ip; 1288 ih264d_ctl_set_processor_op_t *ps_op; 1289 1290 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip; 1291 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op; 1292 1293 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t)) 1294 { 1295 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1296 ps_op->u4_error_code |= 1297 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1298 return IV_FAIL; 1299 } 1300 1301 if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t)) 1302 { 1303 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1304 ps_op->u4_error_code |= 1305 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1306 return IV_FAIL; 1307 } 1308 1309 break; 1310 } 1311 default: 1312 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 1313 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD; 1314 return IV_FAIL; 1315 break; 1316 } 1317 } 1318 break; 1319 } 1320 1321 return IV_SUCCESS; 1322} 1323 1324 1325/** 1326 ******************************************************************************* 1327 * 1328 * @brief 1329 * Sets Processor type 1330 * 1331 * @par Description: 1332 * Sets Processor type 1333 * 1334 * @param[in] ps_codec_obj 1335 * Pointer to codec object at API level 1336 * 1337 * @param[in] pv_api_ip 1338 * Pointer to input argument structure 1339 * 1340 * @param[out] pv_api_op 1341 * Pointer to output argument structure 1342 * 1343 * @returns Status 1344 * 1345 * @remarks 1346 * 1347 * 1348 ******************************************************************************* 1349 */ 1350 1351WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 1352{ 1353 ih264d_ctl_set_processor_ip_t *ps_ip; 1354 ih264d_ctl_set_processor_op_t *ps_op; 1355 dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle; 1356 1357 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip; 1358 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op; 1359 1360 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch; 1361 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc; 1362 1363 ih264d_init_function_ptr(ps_codec); 1364 1365 ps_op->u4_error_code = 0; 1366 return IV_SUCCESS; 1367} 1368/*****************************************************************************/ 1369/* */ 1370/* Function Name : ih264d_get_num_rec */ 1371/* */ 1372/* Description : returns number of mem records required */ 1373/* */ 1374/* Inputs : pv_api_ip input api structure */ 1375/* : pv_api_op output api structure */ 1376/* Outputs : */ 1377/* Outputs : */ 1378/* Returns : void */ 1379/* */ 1380/* Issues : none */ 1381/* */ 1382/* Revision History: */ 1383/* */ 1384/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1385/* 22 10 2008 100356 Draft */ 1386/* */ 1387/*****************************************************************************/ 1388WORD32 ih264d_get_num_rec(void *pv_api_ip, void *pv_api_op) 1389{ 1390 iv_num_mem_rec_ip_t *ps_mem_q_ip; 1391 iv_num_mem_rec_op_t *ps_mem_q_op; 1392 ps_mem_q_ip = (iv_num_mem_rec_ip_t *)pv_api_ip; 1393 ps_mem_q_op = (iv_num_mem_rec_op_t *)pv_api_op; 1394 UNUSED(ps_mem_q_ip); 1395 ps_mem_q_op->u4_num_mem_rec = MEM_REC_CNT; 1396 1397 return IV_SUCCESS; 1398 1399} 1400 1401 1402/************************************************************************** 1403 * \if Function name : ih264d_init_decoder \endif 1404 * 1405 * 1406 * \brief 1407 * Initializes the decoder 1408 * 1409 * \param apiVersion : Version of the api being used. 1410 * \param errorHandlingMechanism : Mechanism to be used for errror handling. 1411 * \param postFilteringType: Type of post filtering operation to be used. 1412 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0]. 1413 * \param uc_dispBufs: Number of Display Buffers. 1414 * \param p_NALBufAPI: Pointer to NAL Buffer API. 1415 * \param p_DispBufAPI: Pointer to Display Buffer API. 1416 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder 1417 * for memory allocation and freeing. 1418 * 1419 * \return 1420 * 0 on Success and -1 on error 1421 * 1422 ************************************************************************** 1423 */ 1424void ih264d_init_decoder(void * ps_dec_params) 1425{ 1426 dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params; 1427 dec_slice_params_t *ps_cur_slice; 1428 pocstruct_t *ps_prev_poc, *ps_cur_poc; 1429 WORD32 size; 1430 1431 size = sizeof(dec_err_status_t); 1432 memset(ps_dec->ps_dec_err_status, 0, size); 1433 1434 size = sizeof(sei); 1435 memset(ps_dec->ps_sei, 0, size); 1436 1437 size = sizeof(dpb_commands_t); 1438 memset(ps_dec->ps_dpb_cmds, 0, size); 1439 1440 size = sizeof(dec_bit_stream_t); 1441 memset(ps_dec->ps_bitstrm, 0, size); 1442 1443 size = sizeof(dec_slice_params_t); 1444 memset(ps_dec->ps_cur_slice, 0, size); 1445 1446 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t)); 1447 memset(ps_dec->pv_scratch_sps_pps, 0, size); 1448 1449 1450 1451 /* Set pic_parameter_set_id to -1 */ 1452 1453 1454 1455 ps_cur_slice = ps_dec->ps_cur_slice; 1456 ps_dec->init_done = 0; 1457 1458 ps_dec->u4_num_cores = 1; 1459 1460 ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0; 1461 1462 ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE; 1463 ps_dec->u4_app_disable_deblk_frm = 0; 1464 ps_dec->i4_degrade_type = 0; 1465 ps_dec->i4_degrade_pics = 0; 1466 1467 ps_dec->i4_app_skip_mode = IVD_SKIP_NONE; 1468 ps_dec->i4_dec_skip_mode = IVD_SKIP_NONE; 1469 1470 memset(ps_dec->ps_pps, 0, 1471 ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS)); 1472 memset(ps_dec->ps_sps, 0, 1473 ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS)); 1474 1475 /* Initialization of function pointers ih264d_deblock_picture function*/ 1476 1477 ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff; 1478 ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff; 1479 1480 ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec; 1481 1482 ps_dec->u4_num_fld_in_frm = 0; 1483 1484 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec; 1485 1486 /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/ 1487 ps_dec->ps_sei->u1_is_valid = 0; 1488 1489 /* decParams Initializations */ 1490 ps_dec->ps_cur_pps = NULL; 1491 ps_dec->ps_cur_sps = NULL; 1492 ps_dec->u1_init_dec_flag = 0; 1493 ps_dec->u1_first_slice_in_stream = 1; 1494 ps_dec->u1_last_pic_not_decoded = 0; 1495 ps_dec->u4_app_disp_width = 0; 1496 ps_dec->i4_header_decoded = 0; 1497 ps_dec->u4_total_frames_decoded = 0; 1498 1499 ps_dec->i4_error_code = 0; 1500 ps_dec->i4_content_type = -1; 1501 ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0; 1502 1503 ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS; 1504 ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN; 1505 ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT; 1506 ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME; 1507 ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN; 1508 1509 ps_dec->u1_pr_sl_type = 0xFF; 1510 ps_dec->u2_mbx = 0xffff; 1511 ps_dec->u2_mby = 0; 1512 ps_dec->u2_total_mbs_coded = 0; 1513 1514 /* POC initializations */ 1515 ps_prev_poc = &ps_dec->s_prev_pic_poc; 1516 ps_cur_poc = &ps_dec->s_cur_pic_poc; 1517 ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0; 1518 ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0; 1519 ps_prev_poc->i4_delta_pic_order_cnt_bottom = 1520 ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0; 1521 ps_prev_poc->i4_delta_pic_order_cnt[0] = 1522 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0; 1523 ps_prev_poc->i4_delta_pic_order_cnt[1] = 1524 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0; 1525 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0; 1526 ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count = 1527 0; 1528 ps_prev_poc->i4_bottom_field_order_count = 1529 ps_cur_poc->i4_bottom_field_order_count = 0; 1530 ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0; 1531 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0; 1532 ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0; 1533 ps_cur_slice->u1_mmco_equalto5 = 0; 1534 ps_cur_slice->u2_frame_num = 0; 1535 1536 ps_dec->i4_max_poc = 0; 1537 ps_dec->i4_prev_max_display_seq = 0; 1538 ps_dec->u1_recon_mb_grp = 4; 1539 1540 /* Field PIC initializations */ 1541 ps_dec->u1_second_field = 0; 1542 ps_dec->s_prev_seq_params.u1_eoseq_pending = 0; 1543 1544 /* Set the cropping parameters as zero */ 1545 ps_dec->u2_crop_offset_y = 0; 1546 ps_dec->u2_crop_offset_uv = 0; 1547 1548 /* The Initial Frame Rate Info is not Present */ 1549 ps_dec->i4_vui_frame_rate = -1; 1550 ps_dec->i4_pic_type = -1; 1551 ps_dec->i4_frametype = -1; 1552 ps_dec->i4_content_type = -1; 1553 1554 ps_dec->u1_res_changed = 0; 1555 1556 1557 ps_dec->u1_frame_decoded_flag = 0; 1558 1559 /* Set the default frame seek mask mode */ 1560 ps_dec->u4_skip_frm_mask = SKIP_NONE; 1561 1562 /********************************************************/ 1563 /* Initialize CAVLC residual decoding function pointers */ 1564 /********************************************************/ 1565 ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1; 1566 ps_dec->pf_cavlc_4x4res_block[1] = 1567 ih264d_cavlc_4x4res_block_totalcoeff_2to10; 1568 ps_dec->pf_cavlc_4x4res_block[2] = 1569 ih264d_cavlc_4x4res_block_totalcoeff_11to16; 1570 1571 ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7; 1572 ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8; 1573 1574 ps_dec->pf_cavlc_parse_8x8block[0] = 1575 ih264d_cavlc_parse_8x8block_none_available; 1576 ps_dec->pf_cavlc_parse_8x8block[1] = 1577 ih264d_cavlc_parse_8x8block_left_available; 1578 ps_dec->pf_cavlc_parse_8x8block[2] = 1579 ih264d_cavlc_parse_8x8block_top_available; 1580 ps_dec->pf_cavlc_parse_8x8block[3] = 1581 ih264d_cavlc_parse_8x8block_both_available; 1582 1583 /***************************************************************************/ 1584 /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */ 1585 /***************************************************************************/ 1586 ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice; 1587 ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice; 1588 1589 ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice; 1590 ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice; 1591 1592 ps_dec->pf_fill_bs_xtra_left_edge[0] = 1593 ih264d_fill_bs_xtra_left_edge_cur_frm; 1594 ps_dec->pf_fill_bs_xtra_left_edge[1] = 1595 ih264d_fill_bs_xtra_left_edge_cur_fld; 1596 1597 /* Initialize Reference Pic Buffers */ 1598 ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr); 1599 1600#if VERT_SCALE_UP_AND_422 1601 ps_dec->u1_vert_up_scale_flag = 1; 1602#else 1603 ps_dec->u1_vert_up_scale_flag = 0; 1604#endif 1605 1606 ps_dec->u2_prv_frame_num = 0; 1607 ps_dec->u1_top_bottom_decoded = 0; 1608 ps_dec->u1_dangling_field = 0; 1609 1610 ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table; 1611 1612 ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0]; 1613 ps_dec->pi1_left_ref_idx_ctxt_inc = 1614 &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0]; 1615 ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb; 1616 1617 /* ! */ 1618 /* Initializing flush frame u4_flag */ 1619 ps_dec->u1_flushfrm = 0; 1620 1621 { 1622 ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec; 1623 ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec; 1624 ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec; 1625 ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec; 1626 } 1627 1628 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t)); 1629 memset(ps_dec->u4_disp_buf_mapping, 0, 1630 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1631 memset(ps_dec->u4_disp_buf_to_be_freed, 0, 1632 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1633 memset(ps_dec->ps_cur_slice, 0, sizeof(dec_slice_params_t)); 1634 1635 ih264d_init_arch(ps_dec); 1636 ih264d_init_function_ptr(ps_dec); 1637 1638 ps_dec->init_done = 1; 1639 ps_dec->process_called = 1; 1640 1641 ps_dec->pv_pic_buf_mgr = NULL; 1642 ps_dec->pv_mv_buf_mgr = NULL; 1643} 1644 1645/************************************************************************** 1646 * \if Function name : ih264d_init_video_decoder \endif 1647 * 1648 * \brief 1649 * Wrapper for the decoder init 1650 * 1651 * \param p_NALBufAPI: Pointer to NAL Buffer API. 1652 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder 1653 * for memory allocation and freeing. 1654 * 1655 * \return 1656 * pointer to the decparams 1657 * 1658 ************************************************************************** 1659 */ 1660 1661WORD32 ih264d_init_video_decoder(iv_obj_t *dec_hdl, 1662 ih264d_init_ip_t *ps_init_ip, 1663 ih264d_init_op_t *ps_init_op) 1664{ 1665 dec_struct_t * ps_dec; 1666 iv_mem_rec_t *memtab; 1667 UWORD8 *pu1_extra_mem_base,*pu1_mem_base; 1668 1669 memtab = ps_init_ip->s_ivd_init_ip_t.pv_mem_rec_location; 1670 1671 dec_hdl->pv_codec_handle = memtab[MEM_REC_CODEC].pv_base; 1672 ps_dec = dec_hdl->pv_codec_handle; 1673 1674 memset(ps_dec, 0, sizeof(dec_struct_t)); 1675 1676 if(ps_init_ip->s_ivd_init_ip_t.u4_size 1677 > offsetof(ih264d_init_ip_t, i4_level)) 1678 { 1679 ps_dec->u4_level_at_init = ps_init_ip->i4_level; 1680 } 1681 else 1682 { 1683 ps_dec->u4_level_at_init = H264_LEVEL_3_1; 1684 } 1685 1686 if(ps_init_ip->s_ivd_init_ip_t.u4_size 1687 > offsetof(ih264d_init_ip_t, u4_num_ref_frames)) 1688 { 1689 ps_dec->u4_num_ref_frames_at_init = ps_init_ip->u4_num_ref_frames; 1690 } 1691 else 1692 { 1693 ps_dec->u4_num_ref_frames_at_init = H264_MAX_REF_PICS; 1694 } 1695 1696 if(ps_init_ip->s_ivd_init_ip_t.u4_size 1697 > offsetof(ih264d_init_ip_t, u4_num_reorder_frames)) 1698 { 1699 ps_dec->u4_num_reorder_frames_at_init = 1700 ps_init_ip->u4_num_reorder_frames; 1701 } 1702 else 1703 { 1704 ps_dec->u4_num_reorder_frames_at_init = H264_MAX_REF_PICS; 1705 } 1706 1707 if(ps_init_ip->s_ivd_init_ip_t.u4_size 1708 > offsetof(ih264d_init_ip_t, u4_num_extra_disp_buf)) 1709 { 1710 ps_dec->u4_num_extra_disp_bufs_at_init = 1711 ps_init_ip->u4_num_extra_disp_buf; 1712 } 1713 else 1714 { 1715 ps_dec->u4_num_extra_disp_bufs_at_init = 0; 1716 } 1717 1718 if(ps_init_ip->s_ivd_init_ip_t.u4_size 1719 > offsetof(ih264d_init_ip_t, u4_share_disp_buf)) 1720 { 1721#ifndef LOGO_EN 1722 ps_dec->u4_share_disp_buf = ps_init_ip->u4_share_disp_buf; 1723#else 1724 ps_dec->u4_share_disp_buf = 0; 1725#endif 1726 } 1727 else 1728 { 1729 ps_dec->u4_share_disp_buf = 0; 1730 } 1731 1732 if((ps_init_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) 1733 && (ps_init_ip->s_ivd_init_ip_t.e_output_format 1734 != IV_YUV_420SP_UV) 1735 && (ps_init_ip->s_ivd_init_ip_t.e_output_format 1736 != IV_YUV_420SP_VU)) 1737 { 1738 ps_dec->u4_share_disp_buf = 0; 1739 } 1740 1741 if((ps_dec->u4_level_at_init < MIN_LEVEL_SUPPORTED) 1742 || (ps_dec->u4_level_at_init > MAX_LEVEL_SUPPORTED)) 1743 { 1744 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_LEVEL_UNSUPPORTED; 1745 return (IV_FAIL); 1746 } 1747 1748 if(ps_dec->u4_num_ref_frames_at_init > H264_MAX_REF_PICS) 1749 { 1750 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF; 1751 ps_dec->u4_num_ref_frames_at_init = H264_MAX_REF_PICS; 1752 } 1753 1754 if(ps_dec->u4_num_reorder_frames_at_init > H264_MAX_REF_PICS) 1755 { 1756 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF; 1757 ps_dec->u4_num_reorder_frames_at_init = H264_MAX_REF_PICS; 1758 } 1759 1760 if(ps_dec->u4_num_extra_disp_bufs_at_init > H264_MAX_REF_PICS) 1761 { 1762 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF; 1763 ps_dec->u4_num_extra_disp_bufs_at_init = 0; 1764 } 1765 1766 if(0 == ps_dec->u4_share_disp_buf) 1767 ps_dec->u4_num_extra_disp_bufs_at_init = 0; 1768 1769 ps_dec->u4_num_disp_bufs_requested = 1; 1770 1771 ps_dec->u4_width_at_init = ps_init_ip->s_ivd_init_ip_t.u4_frm_max_wd; 1772 ps_dec->u4_height_at_init = ps_init_ip->s_ivd_init_ip_t.u4_frm_max_ht; 1773 1774 ps_dec->u4_width_at_init = ALIGN16(ps_dec->u4_width_at_init); 1775 ps_dec->u4_height_at_init = ALIGN32(ps_dec->u4_height_at_init); 1776 1777 ps_dec->pv_dec_thread_handle = memtab[MEM_REC_THREAD_HANDLE].pv_base; 1778 1779 pu1_mem_base = memtab[MEM_REC_THREAD_HANDLE].pv_base; 1780 ps_dec->pv_bs_deblk_thread_handle = pu1_mem_base 1781 + ithread_get_handle_size(); 1782 1783 ps_dec->u4_extra_mem_used = 0; 1784 1785 pu1_extra_mem_base = memtab[MEM_REC_EXTRA_MEM].pv_base; 1786 1787 ps_dec->ps_dec_err_status = (dec_err_status_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1788 ps_dec->u4_extra_mem_used += (((sizeof(dec_err_status_t) + 127) >> 7) << 7); 1789 1790 ps_dec->ps_mem_tab = memtab[MEM_REC_BACKUP].pv_base; 1791 1792 memcpy(ps_dec->ps_mem_tab, memtab, sizeof(iv_mem_rec_t) * MEM_REC_CNT); 1793 1794 ps_dec->ps_pps = memtab[MEM_REC_PPS].pv_base; 1795 1796 ps_dec->ps_sps = memtab[MEM_REC_SPS].pv_base; 1797 1798 ps_dec->ps_sei = (sei *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1799 ps_dec->u4_extra_mem_used += sizeof(sei); 1800 1801 ps_dec->ps_dpb_mgr = memtab[MEM_REC_DPB_MGR].pv_base; 1802 1803 ps_dec->ps_dpb_cmds = (dpb_commands_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1804 ps_dec->u4_extra_mem_used += sizeof(dpb_commands_t); 1805 1806 ps_dec->ps_bitstrm = (dec_bit_stream_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1807 ps_dec->u4_extra_mem_used += sizeof(dec_bit_stream_t); 1808 1809 ps_dec->ps_cur_slice =(dec_slice_params_t *) (pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1810 ps_dec->u4_extra_mem_used += sizeof(dec_slice_params_t); 1811 1812 ps_dec->pv_scratch_sps_pps = (void *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1813 1814 1815 ps_dec->u4_extra_mem_used += MAX(sizeof(dec_seq_params_t), 1816 sizeof(dec_pic_params_t)); 1817 ps_dec->ps_pred_pkd = memtab[MEM_REC_PRED_INFO_PKD].pv_base; 1818 1819 1820 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec; 1821 1822 ps_dec->pv_dec_out = (void *)ps_init_op; 1823 ps_dec->pv_dec_in = (void *)ps_init_ip; 1824 1825 ps_dec->u1_chroma_format = 1826 (UWORD8)(ps_init_ip->s_ivd_init_ip_t.e_output_format); 1827 1828 1829 1830 ih264d_init_decoder(ps_dec); 1831 1832 return (IV_SUCCESS); 1833 1834} 1835 1836 1837/*****************************************************************************/ 1838/* */ 1839/* Function Name : ih264d_fill_num_mem_rec */ 1840/* */ 1841/* Description : fills memory records */ 1842/* */ 1843/* Inputs : pv_api_ip input api structure */ 1844/* : pv_api_op output api structure */ 1845/* Outputs : */ 1846/* Returns : void */ 1847/* */ 1848/* Issues : none */ 1849/* */ 1850/* Revision History: */ 1851/* */ 1852/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1853/* 22 10 2008 100356 Draft */ 1854/* */ 1855/*****************************************************************************/ 1856WORD32 ih264d_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op) 1857{ 1858 1859 ih264d_fill_mem_rec_ip_t *ps_mem_q_ip; 1860 ih264d_fill_mem_rec_op_t *ps_mem_q_op; 1861 WORD32 level; 1862 UWORD32 num_reorder_frames; 1863 UWORD32 num_ref_frames; 1864 UWORD32 num_extra_disp_bufs; 1865 UWORD32 u4_dpb_size_num_frames; 1866 iv_mem_rec_t *memTab; 1867 1868 UWORD32 chroma_format, u4_share_disp_buf; 1869 UWORD32 u4_total_num_mbs; 1870 UWORD32 luma_width, luma_width_in_mbs; 1871 UWORD32 luma_height, luma_height_in_mbs; 1872 UWORD32 max_dpb_size; 1873 1874 ps_mem_q_ip = (ih264d_fill_mem_rec_ip_t *)pv_api_ip; 1875 ps_mem_q_op = (ih264d_fill_mem_rec_op_t *)pv_api_op; 1876 1877 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1878 > offsetof(ih264d_fill_mem_rec_ip_t, i4_level)) 1879 { 1880 level = ps_mem_q_ip->i4_level; 1881 } 1882 else 1883 { 1884 level = H264_LEVEL_3_1; 1885 } 1886 1887 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1888 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_reorder_frames)) 1889 { 1890 num_reorder_frames = ps_mem_q_ip->u4_num_reorder_frames; 1891 } 1892 else 1893 { 1894 num_reorder_frames = H264_MAX_REF_PICS; 1895 } 1896 1897 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1898 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_ref_frames)) 1899 { 1900 num_ref_frames = ps_mem_q_ip->u4_num_ref_frames; 1901 } 1902 else 1903 { 1904 num_ref_frames = H264_MAX_REF_PICS; 1905 } 1906 1907 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1908 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_extra_disp_buf)) 1909 { 1910 num_extra_disp_bufs = ps_mem_q_ip->u4_num_extra_disp_buf; 1911 } 1912 else 1913 { 1914 num_extra_disp_bufs = 0; 1915 } 1916 1917 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1918 > offsetof(ih264d_fill_mem_rec_ip_t, u4_share_disp_buf)) 1919 { 1920#ifndef LOGO_EN 1921 u4_share_disp_buf = ps_mem_q_ip->u4_share_disp_buf; 1922#else 1923 u4_share_disp_buf = 0; 1924#endif 1925 } 1926 else 1927 { 1928 u4_share_disp_buf = 0; 1929 } 1930 1931 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1932 > offsetof(ih264d_fill_mem_rec_ip_t, e_output_format)) 1933 { 1934 chroma_format = ps_mem_q_ip->e_output_format; 1935 } 1936 else 1937 { 1938 chroma_format = -1; 1939 } 1940 1941 if((chroma_format != IV_YUV_420P) && (chroma_format != IV_YUV_420SP_UV) 1942 && (chroma_format != IV_YUV_420SP_VU)) 1943 { 1944 u4_share_disp_buf = 0; 1945 } 1946 if(0 == u4_share_disp_buf) 1947 num_extra_disp_bufs = 0; 1948 1949 { 1950 1951 luma_height = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht; 1952 luma_width = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd; 1953 1954 luma_height = ALIGN32(luma_height); 1955 luma_width = ALIGN16(luma_width); 1956 luma_width_in_mbs = luma_width >> 4; 1957 luma_height_in_mbs = luma_height >> 4; 1958 u4_total_num_mbs = (luma_height * luma_width) >> 8; 1959 } 1960 /* 1961 * If level is lesser than 31 and the resolution required is higher, 1962 * then make the level at least 31. 1963 */ 1964 if(u4_total_num_mbs > MAX_MBS_LEVEL_30 && level < H264_LEVEL_3_1) 1965 { 1966 level = H264_LEVEL_3_1; 1967 } 1968 1969 if((level < MIN_LEVEL_SUPPORTED) || (level > MAX_LEVEL_SUPPORTED)) 1970 { 1971 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1972 ERROR_LEVEL_UNSUPPORTED; 1973 return (IV_FAIL); 1974 } 1975 1976 if(num_ref_frames > H264_MAX_REF_PICS) 1977 { 1978 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= ERROR_NUM_REF; 1979 num_ref_frames = H264_MAX_REF_PICS; 1980 } 1981 1982 if(num_reorder_frames > H264_MAX_REF_PICS) 1983 { 1984 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= ERROR_NUM_REF; 1985 num_reorder_frames = H264_MAX_REF_PICS; 1986 } 1987 memTab = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location; 1988 1989 memTab[MEM_REC_IV_OBJ].u4_mem_size = sizeof(iv_obj_t); 1990 memTab[MEM_REC_IV_OBJ].u4_mem_alignment = (128 * 8) / CHAR_BIT; 1991 memTab[MEM_REC_IV_OBJ].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 1992 H264_DEC_DEBUG_PRINT("MEM_REC_IV_OBJ MEM Size = %d\n", 1993 memTab[MEM_REC_IV_OBJ].u4_mem_size); 1994 1995 memTab[MEM_REC_CODEC].u4_mem_alignment = (128 * 8) / CHAR_BIT; 1996 memTab[MEM_REC_CODEC].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 1997 memTab[MEM_REC_CODEC].u4_mem_size = sizeof(dec_struct_t); 1998 1999 { 2000 UWORD32 mvinfo_size, mv_info_size_pad; 2001 UWORD32 MVbank, MVbank_pad; 2002 UWORD32 Ysize; 2003 UWORD32 UVsize; 2004 UWORD32 one_frm_size; 2005 2006 UWORD32 extra_mem = 0; 2007 2008 UWORD32 pad_len_h, pad_len_v; 2009 2010 /* 2011 * For low_delay, use num_buf as 2 - 2012 * num_buf = (num_buf_ref) + 1; 2013 * where num_buf_ref is 1. 2014 */ 2015 UWORD32 num_buf; 2016 2017 { 2018 UWORD32 num_bufs_app, num_bufs_level; 2019 2020 num_bufs_app = num_ref_frames + num_reorder_frames + 1; 2021 2022 if(num_bufs_app <= 1) 2023 num_bufs_app = 2; 2024 2025 num_bufs_level = ih264d_get_dpb_size_new(level, (luma_width >> 4), 2026 (luma_height >> 4)); 2027 2028 max_dpb_size = num_bufs_level; 2029 2030 num_bufs_level = num_bufs_level * 2 + 1; 2031 2032 num_buf = MIN(num_bufs_level, num_bufs_app); 2033 2034 num_buf += num_extra_disp_bufs; 2035 2036 } 2037 2038 mvinfo_size = ((luma_width * (luma_height)) >> 4); 2039 2040 mv_info_size_pad = ((luma_width * (PAD_MV_BANK_ROW)) >> 4); 2041 2042 Ysize = ALIGN32((luma_width + (PAD_LEN_Y_H << 1))) 2043 * (luma_height + (PAD_LEN_Y_V << 2)); 2044 2045 2046 UVsize = Ysize >> 2; 2047 if(u4_share_disp_buf == 1) 2048 { 2049 /* In case of buffers getting shared between application and library 2050 there is no need of reference memtabs. Instead of setting the i4_size 2051 to zero, it is reduced to a small i4_size to ensure that changes 2052 in the code are minimal */ 2053 2054 if((chroma_format == IV_YUV_420P) 2055 || (chroma_format == IV_YUV_420SP_UV) 2056 || (chroma_format == IV_YUV_420SP_VU)) 2057 { 2058 Ysize = 64; 2059 } 2060 if(chroma_format == IV_YUV_420SP_UV) 2061 { 2062 UVsize = 64; 2063 } 2064 } 2065 2066 one_frm_size = (((Ysize + 127) >> 7) << 7) 2067 + ((((UVsize << 1) + 127) >> 7) << 7); 2068 2069 //Note that for ARM RVDS WS the sizeof(mv_pred_t) is 16 2070 2071 /*Add memory for colocated MB*/ 2072 MVbank = sizeof(mv_pred_t) * mvinfo_size; 2073 MVbank_pad = sizeof(mv_pred_t) * mv_info_size_pad; 2074 2075 MVbank = (((MVbank + 127) >> 7) << 7); 2076 2077 MVbank_pad = (((MVbank_pad + 127) >> 7) << 7); 2078 2079 memTab[MEM_REC_MVBANK].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2080 memTab[MEM_REC_MVBANK].e_mem_type = 2081 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2082 memTab[MEM_REC_MVBANK].u4_mem_size = (MVbank + MVbank_pad) 2083 * (MIN(max_dpb_size, num_ref_frames) + 1); 2084 2085 2086 memTab[MEM_REC_REF_PIC].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2087 memTab[MEM_REC_REF_PIC].e_mem_type = 2088 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2089 memTab[MEM_REC_REF_PIC].u4_mem_size = one_frm_size * num_buf; 2090 2091 } 2092 2093 memTab[MEM_REC_DEBLK_MB_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2094 memTab[MEM_REC_DEBLK_MB_INFO].e_mem_type = 2095 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2096 memTab[MEM_REC_DEBLK_MB_INFO].u4_mem_size = (((((u4_total_num_mbs 2097 + (luma_width >> 4)) * sizeof(deblk_mb_t)) + 127) >> 7) << 7); 2098 2099 memTab[MEM_REC_NEIGHBOR_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2100 memTab[MEM_REC_NEIGHBOR_INFO].e_mem_type = 2101 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2102 memTab[MEM_REC_NEIGHBOR_INFO].u4_mem_size = sizeof(mb_neigbour_params_t) 2103 * ((luma_width + 16) >> 4) * 2 * 2; 2104 { 2105 WORD32 size; 2106 WORD32 num_entries; 2107 2108 num_entries = MIN(MAX_FRAMES, num_ref_frames); 2109 num_entries = 2 * ((2 * num_entries) + 1); 2110 2111 size = num_entries * sizeof(void *); 2112 size += PAD_MAP_IDX_POC * sizeof(void *); 2113 size *= u4_total_num_mbs; 2114 size += sizeof(dec_slice_struct_t) * u4_total_num_mbs; 2115 memTab[MEM_REC_SLICE_HDR].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2116 memTab[MEM_REC_SLICE_HDR].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2117 memTab[MEM_REC_SLICE_HDR].u4_mem_size = size; 2118 } 2119 { 2120 2121 UWORD32 u4_num_entries; 2122 2123 u4_num_entries = u4_total_num_mbs; 2124 2125 memTab[MEM_REC_MB_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2126 memTab[MEM_REC_MB_INFO].e_mem_type = 2127 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2128 memTab[MEM_REC_MB_INFO].u4_mem_size = sizeof(dec_mb_info_t) 2129 * u4_num_entries; 2130 2131 memTab[MEM_REC_PRED_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2132 memTab[MEM_REC_PRED_INFO].e_mem_type = 2133 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2134 2135 memTab[MEM_REC_PRED_INFO].u4_mem_size = sizeof(pred_info_t) * 2*32; 2136 2137 memTab[MEM_REC_COEFF_DATA].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2138 memTab[MEM_REC_COEFF_DATA].e_mem_type = 2139 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2140 memTab[MEM_REC_COEFF_DATA].u4_mem_size = MB_LUM_SIZE * sizeof(WORD16); 2141 /*For I16x16 MBs, 16 4x4 AC coeffs and 1 4x4 DC coeff TU blocks will be sent 2142 For all MBs along with 8 4x4 AC coeffs 2 2x2 DC coeff TU blocks will be sent 2143 So use 17 4x4 TU blocks for luma and 9 4x4 TU blocks for chroma */ 2144 memTab[MEM_REC_COEFF_DATA].u4_mem_size += u4_num_entries 2145 * (MAX(17 * sizeof(tu_sblk4x4_coeff_data_t),4 * sizeof(tu_blk8x8_coeff_data_t)) 2146 + 9 * sizeof(tu_sblk4x4_coeff_data_t)); 2147 //32 bytes for each mb to store u1_prev_intra4x4_pred_mode and u1_rem_intra4x4_pred_mode data 2148 memTab[MEM_REC_COEFF_DATA].u4_mem_size += u4_num_entries * 32; 2149 2150 } 2151 2152 memTab[MEM_REC_SPS].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2153 memTab[MEM_REC_SPS].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2154 memTab[MEM_REC_SPS].u4_mem_size = ((sizeof(dec_seq_params_t)) 2155 * MAX_NUM_SEQ_PARAMS); 2156 2157 memTab[MEM_REC_PPS].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2158 memTab[MEM_REC_PPS].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2159 memTab[MEM_REC_PPS].u4_mem_size = (sizeof(dec_pic_params_t)) 2160 * MAX_NUM_PIC_PARAMS; 2161 2162 { 2163 UWORD32 u4_mem_size; 2164 2165 u4_mem_size = 0; 2166 u4_mem_size += (((sizeof(dec_err_status_t) + 127) >> 7) << 7); 2167 u4_mem_size += sizeof(sei); 2168 u4_mem_size += sizeof(dpb_commands_t); 2169 u4_mem_size += sizeof(dec_bit_stream_t); 2170 u4_mem_size += sizeof(dec_slice_params_t); 2171 u4_mem_size += MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t)); 2172 2173 memTab[MEM_REC_EXTRA_MEM].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2174 memTab[MEM_REC_EXTRA_MEM].e_mem_type = 2175 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2176 memTab[MEM_REC_EXTRA_MEM].u4_mem_size = u4_mem_size; 2177 } 2178 2179 { 2180 2181 UWORD32 u4_mem_size; 2182 2183 u4_mem_size = 0; 2184 u4_mem_size += ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC) * sizeof(void *)); 2185 u4_mem_size = ALIGN64(u4_mem_size); 2186 u4_mem_size += (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS); 2187 u4_mem_size = ALIGN64(u4_mem_size); 2188 u4_mem_size += sizeof(ctxt_inc_mb_info_t); 2189 u4_mem_size = ALIGN64(u4_mem_size); 2190 u4_mem_size += sizeof(UWORD32) * (MAX_REF_BUFS * MAX_REF_BUFS); 2191 u4_mem_size = ALIGN64(u4_mem_size); 2192 2193 u4_mem_size += MAX_REF_BUF_SIZE * 2; 2194 u4_mem_size = ALIGN64(u4_mem_size); 2195 u4_mem_size += ((sizeof(WORD16)) * PRED_BUFFER_WIDTH 2196 * PRED_BUFFER_HEIGHT * 2); 2197 u4_mem_size = ALIGN64(u4_mem_size); 2198 u4_mem_size += sizeof(UWORD8) * (MB_LUM_SIZE); 2199 u4_mem_size = ALIGN64(u4_mem_size); 2200 u4_mem_size += sizeof(parse_pmbarams_t) * luma_width_in_mbs; //Max recon mb group*/ 2201 u4_mem_size = ALIGN64(u4_mem_size); 2202 u4_mem_size += (sizeof(parse_part_params_t) * luma_width_in_mbs) << 4; //Max recon mb group*/ 2203 u4_mem_size = ALIGN64(u4_mem_size); 2204 2205 u4_mem_size += 2 * MAX_REF_BUFS * sizeof(struct pic_buffer_t); 2206 u4_mem_size = ALIGN64(u4_mem_size); 2207 u4_mem_size += 2 * MAX_REF_BUFS * sizeof(struct pic_buffer_t); 2208 u4_mem_size = ALIGN64(u4_mem_size); 2209 u4_mem_size += (sizeof(UWORD32) * 3 * (MAX_REF_BUFS * MAX_REF_BUFS)) << 3; 2210 u4_mem_size = ALIGN64(u4_mem_size); 2211 2212 u4_mem_size += sizeof(UWORD32) * 2 * 3 2213 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1)); 2214 u4_mem_size = ALIGN64(u4_mem_size); 2215 2216 memTab[MEM_REC_INTERNAL_SCRATCH].u4_mem_alignment = 2217 (128 * 8) / CHAR_BIT; 2218 memTab[MEM_REC_INTERNAL_SCRATCH].e_mem_type = 2219 IV_EXTERNAL_CACHEABLE_SCRATCH_MEM; 2220 memTab[MEM_REC_INTERNAL_SCRATCH].u4_mem_size = u4_mem_size; 2221 } 2222 2223 { 2224 2225 UWORD32 u4_mem_used; 2226 UWORD32 u4_numRows = MB_SIZE << 1; 2227 UWORD32 u4_blk_wd = ((luma_width_in_mbs << 4) >> 1) + 8; 2228 2229 u4_mem_used = 0; 2230 u4_mem_used += ((luma_width_in_mbs * sizeof(deblkmb_neighbour_t)) << 1); 2231 u4_mem_used = ALIGN64(u4_mem_used); 2232 u4_mem_used += (sizeof(neighbouradd_t) << 2); 2233 u4_mem_used = ALIGN64(u4_mem_used); 2234 u4_mem_used += ((sizeof(ctxt_inc_mb_info_t)) 2235 * (((luma_width_in_mbs + 1) << 1) + 1)); 2236 u4_mem_used = ALIGN64(u4_mem_used); 2237 2238 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 16); 2239 u4_mem_used = ALIGN64(u4_mem_used); 2240 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 16); 2241 u4_mem_used = ALIGN64(u4_mem_used); 2242 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 4 2243 * MV_SCRATCH_BUFS); 2244 u4_mem_used = ALIGN64(u4_mem_used); 2245 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2246 u4_mem_used = ALIGN64(u4_mem_used); 2247 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2248 u4_mem_used = ALIGN64(u4_mem_used); 2249 u4_numRows = BLK8x8SIZE << 1; 2250 2251 u4_blk_wd = ((luma_width_in_mbs << 3) >> 1) + 8; 2252 2253 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2254 u4_mem_used = ALIGN64(u4_mem_used); 2255 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2256 u4_mem_used = ALIGN64(u4_mem_used); 2257 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2258 u4_mem_used = ALIGN64(u4_mem_used); 2259 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2260 u4_mem_used += 32; 2261 u4_mem_used = ALIGN64(u4_mem_used); 2262 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2; 2263 u4_mem_used = ALIGN64(u4_mem_used); 2264 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2; 2265 u4_mem_used = ALIGN64(u4_mem_used); 2266 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2; 2267 u4_mem_used = ALIGN64(u4_mem_used); 2268 u4_mem_used += sizeof(mb_neigbour_params_t) * (luma_width_in_mbs + 1) 2269 * luma_height_in_mbs; 2270 u4_mem_used += luma_width; 2271 u4_mem_used = ALIGN64(u4_mem_used); 2272 u4_mem_used += luma_width; 2273 u4_mem_used = ALIGN64(u4_mem_used); 2274 u4_mem_used += luma_width; 2275 u4_mem_used = ALIGN64(u4_mem_used); 2276 2277 u4_mem_used += ((MB_SIZE + 4) << 1) * PAD_LEN_Y_H; 2278 u4_mem_used = ALIGN64(u4_mem_used); 2279 u4_mem_used += ((BLK8x8SIZE + 2) << 1) * PAD_LEN_UV_H; 2280 u4_mem_used = ALIGN64(u4_mem_used); 2281 u4_mem_used += ((BLK8x8SIZE + 2) << 1) * PAD_LEN_UV_H; 2282 u4_mem_used = ALIGN64(u4_mem_used); 2283 memTab[MEM_REC_INTERNAL_PERSIST].u4_mem_alignment = 2284 (128 * 8) / CHAR_BIT; 2285 memTab[MEM_REC_INTERNAL_PERSIST].e_mem_type = 2286 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2287 memTab[MEM_REC_INTERNAL_PERSIST].u4_mem_size = u4_mem_used; 2288 } 2289 2290 memTab[MEM_REC_BITSBUF].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2291 memTab[MEM_REC_BITSBUF].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2292 memTab[MEM_REC_BITSBUF].u4_mem_size = MAX(256000, (luma_width * luma_height * 3 / 2)); 2293 2294 { 2295 2296 UWORD32 u4_thread_struct_size = ithread_get_handle_size(); 2297 2298 memTab[MEM_REC_THREAD_HANDLE].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2299 memTab[MEM_REC_THREAD_HANDLE].e_mem_type = 2300 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2301 memTab[MEM_REC_THREAD_HANDLE].u4_mem_size = u4_thread_struct_size * 2; 2302 2303 } 2304 2305 memTab[MEM_REC_PARSE_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2306 memTab[MEM_REC_PARSE_MAP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2307 memTab[MEM_REC_PARSE_MAP].u4_mem_size = u4_total_num_mbs; 2308 2309 memTab[MEM_REC_PROC_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2310 memTab[MEM_REC_PROC_MAP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2311 memTab[MEM_REC_PROC_MAP].u4_mem_size = u4_total_num_mbs; 2312 2313 memTab[MEM_REC_SLICE_NUM_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2314 memTab[MEM_REC_SLICE_NUM_MAP].e_mem_type = 2315 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2316 memTab[MEM_REC_SLICE_NUM_MAP].u4_mem_size = u4_total_num_mbs 2317 * sizeof(UWORD16); 2318 2319 memTab[MEM_REC_DPB_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2320 memTab[MEM_REC_DPB_MGR].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2321 memTab[MEM_REC_DPB_MGR].u4_mem_size = sizeof(dpb_manager_t); 2322 2323 memTab[MEM_REC_BACKUP].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2324 memTab[MEM_REC_BACKUP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2325 memTab[MEM_REC_BACKUP].u4_mem_size = sizeof(iv_mem_rec_t) * MEM_REC_CNT; 2326 2327 { 2328 2329 UWORD32 u4_mem_size; 2330 2331 u4_mem_size = sizeof(disp_mgr_t); 2332 u4_mem_size += sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 2333 u4_mem_size += sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2); 2334 2335 memTab[MEM_REC_PIC_BUF_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2336 memTab[MEM_REC_PIC_BUF_MGR].e_mem_type = 2337 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2338 memTab[MEM_REC_PIC_BUF_MGR].u4_mem_size = u4_mem_size; 2339 } 2340 2341 { 2342 UWORD32 u4_mem_size; 2343 2344 u4_mem_size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 2345 u4_mem_size += sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2); 2346 u4_mem_size = ALIGN128(u4_mem_size); 2347 u4_mem_size += ((luma_width * luma_height) >> 4) 2348 * (MIN(max_dpb_size, num_ref_frames) + 1); 2349 memTab[MEM_REC_MV_BUF_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2350 memTab[MEM_REC_MV_BUF_MGR].e_mem_type = 2351 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2352 memTab[MEM_REC_MV_BUF_MGR].u4_mem_size = u4_mem_size; 2353 } 2354 2355 memTab[MEM_REC_PRED_INFO_PKD].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2356 memTab[MEM_REC_PRED_INFO_PKD].e_mem_type = 2357 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2358 2359 { 2360 UWORD32 u4_num_entries; 2361 u4_num_entries = u4_total_num_mbs; 2362 2363 2364 u4_num_entries *= 16 * 2; 2365 2366 memTab[MEM_REC_PRED_INFO_PKD].u4_mem_size = sizeof(pred_info_pkd_t) 2367 * u4_num_entries; 2368 } 2369 2370 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = MEM_REC_CNT; 2371 2372 2373 return IV_SUCCESS; 2374} 2375/*****************************************************************************/ 2376/* */ 2377/* Function Name : ih264d_clr */ 2378/* */ 2379/* Description : returns memory records to app */ 2380/* */ 2381/* Inputs :iv_obj_t decoder handle */ 2382/* :pv_api_ip pointer to input structure */ 2383/* :pv_api_op pointer to output structure */ 2384/* Outputs : */ 2385/* Returns : void */ 2386/* */ 2387/* Issues : none */ 2388/* */ 2389/* Revision History: */ 2390/* */ 2391/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2392/* 22 10 2008 100356 Draft */ 2393/* */ 2394/*****************************************************************************/ 2395WORD32 ih264d_clr(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2396{ 2397 2398 dec_struct_t * ps_dec; 2399 iv_retrieve_mem_rec_ip_t *dec_clr_ip; 2400 iv_retrieve_mem_rec_op_t *dec_clr_op; 2401 2402 dec_clr_ip = (iv_retrieve_mem_rec_ip_t *)pv_api_ip; 2403 dec_clr_op = (iv_retrieve_mem_rec_op_t *)pv_api_op; 2404 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2405 2406 if(ps_dec->init_done != 1) 2407 { 2408 //return a proper Error Code 2409 return IV_FAIL; 2410 } 2411 2412 if(ps_dec->pv_pic_buf_mgr) 2413 ih264_buf_mgr_free((buf_mgr_t *)ps_dec->pv_pic_buf_mgr); 2414 if(ps_dec->pv_mv_buf_mgr) 2415 ih264_buf_mgr_free((buf_mgr_t *)ps_dec->pv_mv_buf_mgr); 2416 2417 memcpy(dec_clr_ip->pv_mem_rec_location, ps_dec->ps_mem_tab, 2418 MEM_REC_CNT * (sizeof(iv_mem_rec_t))); 2419 dec_clr_op->u4_num_mem_rec_filled = MEM_REC_CNT; 2420 2421 H264_DEC_DEBUG_PRINT("The clear non-conceal num mem recs: %d\n", 2422 dec_clr_op->u4_num_mem_rec_filled); 2423 2424 return IV_SUCCESS; 2425 2426} 2427 2428/*****************************************************************************/ 2429/* */ 2430/* Function Name : ih264d_init */ 2431/* */ 2432/* Description : initializes decoder */ 2433/* */ 2434/* Inputs :iv_obj_t decoder handle */ 2435/* :pv_api_ip pointer to input structure */ 2436/* :pv_api_op pointer to output structure */ 2437/* Outputs : */ 2438/* Returns : void */ 2439/* */ 2440/* Issues : none */ 2441/* */ 2442/* Revision History: */ 2443/* */ 2444/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2445/* 22 10 2008 100356 Draft */ 2446/* */ 2447/*****************************************************************************/ 2448WORD32 ih264d_init(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2449{ 2450 ih264d_init_ip_t *ps_init_ip; 2451 ih264d_init_op_t *ps_init_op; 2452 WORD32 init_status = IV_SUCCESS; 2453 ps_init_ip = (ih264d_init_ip_t *)pv_api_ip; 2454 ps_init_op = (ih264d_init_op_t *)pv_api_op; 2455 2456 init_status = ih264d_init_video_decoder(dec_hdl, ps_init_ip, ps_init_op); 2457 2458 if(IV_SUCCESS != init_status) 2459 { 2460 return init_status; 2461 } 2462 2463 return init_status; 2464} 2465/*****************************************************************************/ 2466/* */ 2467/* Function Name : ih264d_map_error */ 2468/* */ 2469/* Description : Maps error codes to IVD error groups */ 2470/* */ 2471/* Inputs : */ 2472/* Globals : <Does it use any global variables?> */ 2473/* Outputs : */ 2474/* Returns : void */ 2475/* */ 2476/* Issues : none */ 2477/* */ 2478/* Revision History: */ 2479/* */ 2480/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2481/* 22 10 2008 100356 Draft */ 2482/* */ 2483/*****************************************************************************/ 2484UWORD32 ih264d_map_error(UWORD32 i4_err_status) 2485{ 2486 UWORD32 temp = 0; 2487 2488 switch(i4_err_status) 2489 { 2490 case ERROR_MEM_ALLOC_ISRAM_T: 2491 case ERROR_MEM_ALLOC_SDRAM_T: 2492 case ERROR_BUF_MGR: 2493 case ERROR_MB_GROUP_ASSGN_T: 2494 case ERROR_FRAME_LIMIT_OVER: 2495 case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT: 2496 case ERROR_PROFILE_NOT_SUPPORTED: 2497 case ERROR_INIT_NOT_DONE: 2498 temp = 1 << IVD_FATALERROR; 2499 H264_DEC_DEBUG_PRINT("\nFatal Error\n"); 2500 break; 2501 2502 case ERROR_DBP_MANAGER_T: 2503 case ERROR_GAPS_IN_FRM_NUM: 2504 case ERROR_UNKNOWN_NAL: 2505 case ERROR_INV_MB_SLC_GRP_T: 2506 case ERROR_MULTIPLE_SLC_GRP_T: 2507 case ERROR_UNKNOWN_LEVEL: 2508 case ERROR_UNAVAIL_PICBUF_T: 2509 case ERROR_UNAVAIL_MVBUF_T: 2510 case ERROR_UNAVAIL_DISPBUF_T: 2511 case ERROR_NUM_REF: 2512 case ERROR_REFIDX_ORDER_T: 2513 case ERROR_PIC0_NOT_FOUND_T: 2514 case ERROR_MB_TYPE: 2515 case ERROR_SUB_MB_TYPE: 2516 case ERROR_CBP: 2517 case ERROR_REF_IDX: 2518 case ERROR_NUM_MV: 2519 case ERROR_CHROMA_PRED_MODE: 2520 case ERROR_INTRAPRED: 2521 case ERROR_NEXT_MB_ADDRESS_T: 2522 case ERROR_MB_ADDRESS_T: 2523 case ERROR_PIC1_NOT_FOUND_T: 2524 case ERROR_CAVLC_NUM_COEFF_T: 2525 case ERROR_CAVLC_SCAN_POS_T: 2526 case ERROR_PRED_WEIGHT_TABLE_T: 2527 case ERROR_CORRUPTED_SLICE: 2528 temp = 1 << IVD_CORRUPTEDDATA; 2529 break; 2530 2531 case ERROR_NOT_SUPP_RESOLUTION: 2532 case ERROR_FEATURE_UNAVAIL: 2533 case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT: 2534 temp = 1 << IVD_UNSUPPORTEDINPUT; 2535 break; 2536 2537 case ERROR_INVALID_PIC_PARAM: 2538 case ERROR_INVALID_SEQ_PARAM: 2539 case ERROR_EGC_EXCEED_32_1_T: 2540 case ERROR_EGC_EXCEED_32_2_T: 2541 case ERROR_INV_RANGE_TEV_T: 2542 case ERROR_INV_SLC_TYPE_T: 2543 case ERROR_INV_POC_TYPE_T: 2544 case ERROR_INV_RANGE_QP_T: 2545 case ERROR_INV_SPS_PPS_T: 2546 case ERROR_INV_SLICE_HDR_T: 2547 temp = 1 << IVD_CORRUPTEDHEADER; 2548 break; 2549 2550 case ERROR_EOB_FLUSHBITS_T: 2551 case ERROR_EOB_GETBITS_T: 2552 case ERROR_EOB_GETBIT_T: 2553 case ERROR_EOB_BYPASS_T: 2554 case ERROR_EOB_DECISION_T: 2555 case ERROR_EOB_TERMINATE_T: 2556 case ERROR_EOB_READCOEFF4X4CAB_T: 2557 temp = 1 << IVD_INSUFFICIENTDATA; 2558 break; 2559 case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED: 2560 case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH: 2561 temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR; 2562 break; 2563 2564 case ERROR_DANGLING_FIELD_IN_PIC: 2565 temp = 1 << IVD_APPLIEDCONCEALMENT; 2566 break; 2567 2568 } 2569 2570 return temp; 2571 2572} 2573 2574UWORD32 ih264d_get_outbuf_size(WORD32 pic_wd, 2575 UWORD32 pic_ht, 2576 UWORD8 u1_chroma_format, 2577 UWORD32 *p_buf_size) 2578{ 2579 UWORD32 u4_min_num_out_bufs = 0; 2580 2581 if(u1_chroma_format == IV_YUV_420P) 2582 u4_min_num_out_bufs = MIN_OUT_BUFS_420; 2583 else if(u1_chroma_format == IV_YUV_422ILE) 2584 u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 2585 else if(u1_chroma_format == IV_RGB_565) 2586 u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 2587 else if((u1_chroma_format == IV_YUV_420SP_UV) 2588 || (u1_chroma_format == IV_YUV_420SP_VU)) 2589 u4_min_num_out_bufs = MIN_OUT_BUFS_420SP; 2590 2591 if(u1_chroma_format == IV_YUV_420P) 2592 { 2593 p_buf_size[0] = (pic_wd * pic_ht); 2594 p_buf_size[1] = (pic_wd * pic_ht) >> 2; 2595 p_buf_size[2] = (pic_wd * pic_ht) >> 2; 2596 } 2597 else if(u1_chroma_format == IV_YUV_422ILE) 2598 { 2599 p_buf_size[0] = (pic_wd * pic_ht) * 2; 2600 p_buf_size[1] = p_buf_size[2] = 0; 2601 } 2602 else if(u1_chroma_format == IV_RGB_565) 2603 { 2604 p_buf_size[0] = (pic_wd * pic_ht) * 2; 2605 p_buf_size[1] = p_buf_size[2] = 0; 2606 } 2607 else if((u1_chroma_format == IV_YUV_420SP_UV) 2608 || (u1_chroma_format == IV_YUV_420SP_VU)) 2609 { 2610 p_buf_size[0] = (pic_wd * pic_ht); 2611 p_buf_size[1] = (pic_wd * pic_ht) >> 1; 2612 p_buf_size[2] = 0; 2613 } 2614 2615 return u4_min_num_out_bufs; 2616} 2617 2618WORD32 check_app_out_buf_size(dec_struct_t *ps_dec) 2619{ 2620 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS]; 2621 UWORD32 u4_min_num_out_bufs, i; 2622 UWORD32 pic_wd, pic_ht; 2623 2624 if(0 == ps_dec->u4_share_disp_buf) 2625 { 2626 pic_wd = ps_dec->u2_disp_width; 2627 pic_ht = ps_dec->u2_disp_height; 2628 2629 } 2630 else 2631 { 2632 /* In case of shared mode, do not check validity of ps_dec->ps_out_buffer */ 2633 return (IV_SUCCESS); 2634 } 2635 2636 if(ps_dec->u4_app_disp_width > pic_wd) 2637 pic_wd = ps_dec->u4_app_disp_width; 2638 2639 u4_min_num_out_bufs = ih264d_get_outbuf_size(pic_wd, pic_ht, 2640 ps_dec->u1_chroma_format, 2641 &au4_min_out_buf_size[0]); 2642 2643 if(ps_dec->ps_out_buffer->u4_num_bufs < u4_min_num_out_bufs) 2644 return IV_FAIL; 2645 2646 for(i = 0; i < u4_min_num_out_bufs; i++) 2647 { 2648 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] 2649 < au4_min_out_buf_size[i]) 2650 return (IV_FAIL); 2651 } 2652 2653 return (IV_SUCCESS); 2654} 2655 2656 2657/*****************************************************************************/ 2658/* */ 2659/* Function Name : ih264d_video_decode */ 2660/* */ 2661/* Description : handle video decode API command */ 2662/* */ 2663/* Inputs :iv_obj_t decoder handle */ 2664/* :pv_api_ip pointer to input structure */ 2665/* :pv_api_op pointer to output structure */ 2666/* Outputs : */ 2667/* Returns : void */ 2668/* */ 2669/* Issues : none */ 2670/* */ 2671/* Revision History: */ 2672/* */ 2673/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2674/* 22 10 2008 100356 Draft */ 2675/* */ 2676/*****************************************************************************/ 2677 2678WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2679{ 2680 /* ! */ 2681 2682 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2683 2684 WORD32 i4_err_status = 0; 2685 UWORD8 *pu1_buf = NULL; 2686 WORD32 buflen; 2687 UWORD32 u4_max_ofst, u4_length_of_start_code = 0; 2688 2689 UWORD32 bytes_consumed = 0; 2690 UWORD32 cur_slice_is_nonref = 0; 2691 UWORD32 u4_next_is_aud; 2692 UWORD32 u4_first_start_code_found = 0; 2693 WORD32 ret = 0,api_ret_value = IV_SUCCESS; 2694 WORD32 header_data_left = 0,frame_data_left = 0; 2695 UWORD8 *pu1_bitstrm_buf; 2696 ivd_video_decode_ip_t *ps_dec_ip; 2697 ivd_video_decode_op_t *ps_dec_op; 2698 2699 ithread_set_name((void*)"Parse_thread"); 2700 2701 ps_dec_ip = (ivd_video_decode_ip_t *)pv_api_ip; 2702 ps_dec_op = (ivd_video_decode_op_t *)pv_api_op; 2703 2704 { 2705 UWORD32 u4_size; 2706 u4_size = ps_dec_op->u4_size; 2707 memset(ps_dec_op, 0, sizeof(ivd_video_decode_op_t)); 2708 ps_dec_op->u4_size = u4_size; 2709 } 2710 2711 ps_dec->pv_dec_out = ps_dec_op; 2712 ps_dec->process_called = 1; 2713 if(ps_dec->init_done != 1) 2714 { 2715 return IV_FAIL; 2716 } 2717 2718 /*Data memory barries instruction,so that bitstream write by the application is complete*/ 2719 DATA_SYNC(); 2720 2721 if(0 == ps_dec->u1_flushfrm) 2722 { 2723 if(ps_dec_ip->pv_stream_buffer == NULL) 2724 { 2725 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2726 ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL; 2727 return IV_FAIL; 2728 } 2729 if(ps_dec_ip->u4_num_Bytes <= 0) 2730 { 2731 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2732 ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV; 2733 return IV_FAIL; 2734 2735 } 2736 } 2737 ps_dec->u1_pic_decode_done = 0; 2738 2739 ps_dec_op->u4_num_bytes_consumed = 0; 2740 2741 ps_dec->ps_out_buffer = NULL; 2742 2743 if(ps_dec_ip->u4_size 2744 >= offsetof(ivd_video_decode_ip_t, s_out_buffer)) 2745 ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer; 2746 2747 ps_dec->u4_fmt_conv_cur_row = 0; 2748 2749 ps_dec->u4_output_present = 0; 2750 ps_dec->s_disp_op.u4_error_code = 1; 2751 ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS; 2752 ps_dec->u4_stop_threads = 0; 2753 if(0 == ps_dec->u4_share_disp_buf 2754 && ps_dec->i4_decode_header == 0) 2755 { 2756 UWORD32 i; 2757 if((ps_dec->ps_out_buffer->u4_num_bufs == 0) || 2758 (ps_dec->ps_out_buffer->u4_num_bufs > IVD_VIDDEC_MAX_IO_BUFFERS)) 2759 { 2760 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2761 ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS; 2762 return IV_FAIL; 2763 } 2764 2765 for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++) 2766 { 2767 if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL) 2768 { 2769 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2770 ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL; 2771 return IV_FAIL; 2772 } 2773 2774 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0) 2775 { 2776 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2777 ps_dec_op->u4_error_code |= 2778 IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 2779 return IV_FAIL; 2780 } 2781 } 2782 } 2783 2784 if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT) 2785 { 2786 ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER; 2787 return IV_FAIL; 2788 } 2789 2790 /* ! */ 2791 ps_dec->u4_ts = ps_dec_ip->u4_ts; 2792 2793 ps_dec_op->u4_error_code = 0; 2794 ps_dec_op->e_pic_type = -1; 2795 ps_dec_op->u4_output_present = 0; 2796 ps_dec_op->u4_frame_decoded_flag = 0; 2797 2798 ps_dec->i4_frametype = -1; 2799 ps_dec->i4_content_type = -1; 2800 2801 ps_dec->u4_slice_start_code_found = 0; 2802 2803 /* In case the deocder is not in flush mode(in shared mode), 2804 then decoder has to pick up a buffer to write current frame. 2805 Check if a frame is available in such cases */ 2806 2807 if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1 2808 && ps_dec->u1_flushfrm == 0) 2809 { 2810 UWORD32 i; 2811 2812 WORD32 disp_avail = 0, free_id; 2813 2814 /* Check if at least one buffer is available with the codec */ 2815 /* If not then return to application with error */ 2816 for(i = 0; i < ps_dec->u1_pic_bufs; i++) 2817 { 2818 if(0 == ps_dec->u4_disp_buf_mapping[i] 2819 || 1 == ps_dec->u4_disp_buf_to_be_freed[i]) 2820 { 2821 disp_avail = 1; 2822 break; 2823 } 2824 2825 } 2826 2827 if(0 == disp_avail) 2828 { 2829 /* If something is queued for display wait for that buffer to be returned */ 2830 2831 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL; 2832 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 2833 return (IV_FAIL); 2834 } 2835 2836 while(1) 2837 { 2838 pic_buffer_t *ps_pic_buf; 2839 ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free( 2840 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id); 2841 2842 if(ps_pic_buf == NULL) 2843 { 2844 UWORD32 i, display_queued = 0; 2845 2846 /* check if any buffer was given for display which is not returned yet */ 2847 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++) 2848 { 2849 if(0 != ps_dec->u4_disp_buf_mapping[i]) 2850 { 2851 display_queued = 1; 2852 break; 2853 } 2854 } 2855 /* If some buffer is queued for display, then codec has to singal an error and wait 2856 for that buffer to be returned. 2857 If nothing is queued for display then codec has ownership of all display buffers 2858 and it can reuse any of the existing buffers and continue decoding */ 2859 2860 if(1 == display_queued) 2861 { 2862 /* If something is queued for display wait for that buffer to be returned */ 2863 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL; 2864 ps_dec_op->u4_error_code |= (1 2865 << IVD_UNSUPPORTEDPARAM); 2866 return (IV_FAIL); 2867 } 2868 } 2869 else 2870 { 2871 /* If the buffer is with display, then mark it as in use and then look for a buffer again */ 2872 if(1 == ps_dec->u4_disp_buf_mapping[free_id]) 2873 { 2874 ih264_buf_mgr_set_status( 2875 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 2876 free_id, 2877 BUF_MGR_IO); 2878 } 2879 else 2880 { 2881 /** 2882 * Found a free buffer for present call. Release it now. 2883 * Will be again obtained later. 2884 */ 2885 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 2886 free_id, 2887 BUF_MGR_IO); 2888 break; 2889 } 2890 } 2891 } 2892 2893 } 2894 2895 if(ps_dec->u1_flushfrm && ps_dec->u1_init_dec_flag) 2896 { 2897 2898 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer, 2899 &(ps_dec->s_disp_op)); 2900 if(0 == ps_dec->s_disp_op.u4_error_code) 2901 { 2902 /* check output buffer size given by the application */ 2903 if(check_app_out_buf_size(ps_dec) != IV_SUCCESS) 2904 { 2905 ps_dec_op->u4_error_code= IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 2906 return (IV_FAIL); 2907 } 2908 2909 ps_dec->u4_fmt_conv_cur_row = 0; 2910 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht; 2911 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 2912 ps_dec->u4_fmt_conv_cur_row, 2913 ps_dec->u4_fmt_conv_num_rows); 2914 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 2915 ps_dec->u4_output_present = 1; 2916 2917 } 2918 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op)); 2919 2920 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 2921 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 2922 2923 ps_dec_op->u4_new_seq = 0; 2924 2925 ps_dec_op->u4_output_present = ps_dec->u4_output_present; 2926 ps_dec_op->u4_progressive_frame_flag = 2927 ps_dec->s_disp_op.u4_progressive_frame_flag; 2928 ps_dec_op->e_output_format = 2929 ps_dec->s_disp_op.e_output_format; 2930 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf; 2931 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type; 2932 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts; 2933 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id; 2934 2935 /*In the case of flush ,since no frame is decoded set pic type as invalid*/ 2936 ps_dec_op->u4_is_ref_flag = -1; 2937 ps_dec_op->e_pic_type = IV_NA_FRAME; 2938 ps_dec_op->u4_frame_decoded_flag = 0; 2939 2940 if(0 == ps_dec->s_disp_op.u4_error_code) 2941 { 2942 return (IV_SUCCESS); 2943 } 2944 else 2945 return (IV_FAIL); 2946 2947 } 2948 if(ps_dec->u1_res_changed == 1) 2949 { 2950 /*if resolution has changed and all buffers have been flushed, reset decoder*/ 2951 ih264d_init_decoder(ps_dec); 2952 } 2953 2954 ps_dec->u4_prev_nal_skipped = 0; 2955 2956 ps_dec->u2_cur_mb_addr = 0; 2957 ps_dec->u2_total_mbs_coded = 0; 2958 ps_dec->u2_cur_slice_num = 0; 2959 ps_dec->cur_dec_mb_num = 0; 2960 ps_dec->cur_recon_mb_num = 0; 2961 ps_dec->u4_first_slice_in_pic = 1; 2962 ps_dec->u1_slice_header_done = 0; 2963 ps_dec->u1_dangling_field = 0; 2964 2965 ps_dec->u4_dec_thread_created = 0; 2966 ps_dec->u4_bs_deblk_thread_created = 0; 2967 ps_dec->u4_cur_bs_mb_num = 0; 2968 ps_dec->u4_start_recon_deblk = 0; 2969 ps_dec->u4_sps_cnt_in_process = 0; 2970 2971 DEBUG_THREADS_PRINTF(" Starting process call\n"); 2972 2973 ps_dec->u4_pic_buf_got = 0; 2974 2975 do 2976 { 2977 2978 pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer 2979 + ps_dec_op->u4_num_bytes_consumed; 2980 2981 u4_max_ofst = ps_dec_ip->u4_num_Bytes 2982 - ps_dec_op->u4_num_bytes_consumed; 2983 pu1_bitstrm_buf = ps_dec->ps_mem_tab[MEM_REC_BITSBUF].pv_base; 2984 2985 u4_next_is_aud = 0; 2986 2987 buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst, 2988 &u4_length_of_start_code, 2989 &u4_next_is_aud); 2990 2991 if(buflen == -1) 2992 buflen = 0; 2993 /* Ignore bytes beyond the allocated size of intermediate buffer */ 2994 /* Since 8 bytes are read ahead, ensure 8 bytes are free at the 2995 end of the buffer, which will be memset to 0 after emulation prevention */ 2996 buflen = MIN(buflen, (WORD32)(ps_dec->ps_mem_tab[MEM_REC_BITSBUF].u4_mem_size - 8)); 2997 2998 bytes_consumed = buflen + u4_length_of_start_code; 2999 ps_dec_op->u4_num_bytes_consumed += bytes_consumed; 3000 3001 if(buflen >= MAX_NAL_UNIT_SIZE) 3002 { 3003 3004 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op); 3005 H264_DEC_DEBUG_PRINT( 3006 "\nNal Size exceeded %d, Processing Stopped..\n", 3007 MAX_NAL_UNIT_SIZE); 3008 ps_dec->i4_error_code = 1 << IVD_CORRUPTEDDATA; 3009 3010 ps_dec_op->e_pic_type = -1; 3011 /*signal the decode thread*/ 3012 ih264d_signal_decode_thread(ps_dec); 3013 /*signal end of frame decode for curren frame*/ 3014 3015 if(ps_dec->u4_pic_buf_got == 0) 3016 { 3017 if(ps_dec->i4_header_decoded == 3) 3018 { 3019 ps_dec->u2_total_mbs_coded = 3020 ps_dec->ps_cur_sps->u2_max_mb_addr + 1; 3021 } 3022 3023 /* close deblock thread if it is not closed yet*/ 3024 if(ps_dec->u4_num_cores == 3) 3025 { 3026 ih264d_signal_bs_deblk_thread(ps_dec); 3027 } 3028 return IV_FAIL; 3029 } 3030 else 3031 { 3032 ps_dec->u1_pic_decode_done = 1; 3033 continue; 3034 } 3035 } 3036 3037 { 3038 UWORD8 u1_firstbyte, u1_nal_ref_idc; 3039 3040 if(ps_dec->i4_app_skip_mode == IVD_SKIP_B) 3041 { 3042 u1_firstbyte = *(pu1_buf + u4_length_of_start_code); 3043 u1_nal_ref_idc = (UWORD8)(NAL_REF_IDC(u1_firstbyte)); 3044 if(u1_nal_ref_idc == 0) 3045 { 3046 /*skip non reference frames*/ 3047 cur_slice_is_nonref = 1; 3048 continue; 3049 } 3050 else 3051 { 3052 if(1 == cur_slice_is_nonref) 3053 { 3054 /*We have encountered a referenced frame,return to app*/ 3055 ps_dec_op->u4_num_bytes_consumed -= 3056 bytes_consumed; 3057 ps_dec_op->e_pic_type = IV_B_FRAME; 3058 ps_dec_op->u4_error_code = 3059 IVD_DEC_FRM_SKIPPED; 3060 ps_dec_op->u4_error_code |= (1 3061 << IVD_UNSUPPORTEDPARAM); 3062 ps_dec_op->u4_frame_decoded_flag = 0; 3063 ps_dec_op->u4_size = 3064 sizeof(ivd_video_decode_op_t); 3065 /*signal the decode thread*/ 3066 ih264d_signal_decode_thread(ps_dec); 3067 /* close deblock thread if it is not closed yet*/ 3068 if(ps_dec->u4_num_cores == 3) 3069 { 3070 ih264d_signal_bs_deblk_thread(ps_dec); 3071 } 3072 3073 return (IV_FAIL); 3074 } 3075 } 3076 3077 } 3078 3079 } 3080 3081 3082 if(buflen) 3083 { 3084 memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code, 3085 buflen); 3086 u4_first_start_code_found = 1; 3087 3088 } 3089 else 3090 { 3091 /*start code not found*/ 3092 3093 if(u4_first_start_code_found == 0) 3094 { 3095 /*no start codes found in current process call*/ 3096 3097 ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND; 3098 ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA; 3099 3100 if(ps_dec->u4_pic_buf_got == 0) 3101 { 3102 3103 ih264d_fill_output_struct_from_context(ps_dec, 3104 ps_dec_op); 3105 3106 ps_dec_op->u4_error_code = ps_dec->i4_error_code; 3107 ps_dec_op->u4_frame_decoded_flag = 0; 3108 3109 return (IV_FAIL); 3110 } 3111 else 3112 { 3113 ps_dec->u1_pic_decode_done = 1; 3114 continue; 3115 } 3116 } 3117 else 3118 { 3119 /* a start code has already been found earlier in the same process call*/ 3120 frame_data_left = 0; 3121 header_data_left = 0; 3122 continue; 3123 } 3124 3125 } 3126 3127 ps_dec->u4_return_to_app = 0; 3128 ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op, 3129 pu1_bitstrm_buf, buflen); 3130 if(ret != OK) 3131 { 3132 UWORD32 error = ih264d_map_error(ret); 3133 ps_dec_op->u4_error_code = error | ret; 3134 api_ret_value = IV_FAIL; 3135 3136 if((ret == IVD_RES_CHANGED) 3137 || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED) 3138 || (ret == ERROR_UNAVAIL_PICBUF_T) 3139 || (ret == ERROR_UNAVAIL_MVBUF_T) 3140 || (ret == ERROR_INV_SPS_PPS_T) 3141 || (ret == IVD_DISP_FRM_ZERO_OP_BUF_SIZE)) 3142 { 3143 ps_dec->u4_slice_start_code_found = 0; 3144 break; 3145 } 3146 3147 if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC)) 3148 { 3149 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 3150 api_ret_value = IV_FAIL; 3151 break; 3152 } 3153 3154 if(ret == ERROR_IN_LAST_SLICE_OF_PIC) 3155 { 3156 api_ret_value = IV_FAIL; 3157 break; 3158 } 3159 3160 } 3161 3162 if(ps_dec->u4_return_to_app) 3163 { 3164 /*We have encountered a referenced frame,return to app*/ 3165 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 3166 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED; 3167 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 3168 ps_dec_op->u4_frame_decoded_flag = 0; 3169 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t); 3170 /*signal the decode thread*/ 3171 ih264d_signal_decode_thread(ps_dec); 3172 /* close deblock thread if it is not closed yet*/ 3173 if(ps_dec->u4_num_cores == 3) 3174 { 3175 ih264d_signal_bs_deblk_thread(ps_dec); 3176 } 3177 return (IV_FAIL); 3178 3179 } 3180 3181 3182 3183 header_data_left = ((ps_dec->i4_decode_header == 1) 3184 && (ps_dec->i4_header_decoded != 3) 3185 && (ps_dec_op->u4_num_bytes_consumed 3186 < ps_dec_ip->u4_num_Bytes)); 3187 frame_data_left = (((ps_dec->i4_decode_header == 0) 3188 && ((ps_dec->u1_pic_decode_done == 0) 3189 || (u4_next_is_aud == 1))) 3190 && (ps_dec_op->u4_num_bytes_consumed 3191 < ps_dec_ip->u4_num_Bytes)); 3192 } 3193 while(( header_data_left == 1)||(frame_data_left == 1)); 3194 3195 if((ps_dec->u4_slice_start_code_found == 1) 3196 && ps_dec->u2_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs) 3197 { 3198 // last slice - missing/corruption 3199 WORD32 num_mb_skipped; 3200 WORD32 prev_slice_err; 3201 pocstruct_t temp_poc; 3202 WORD32 ret1; 3203 WORD32 ht_in_mbs; 3204 ht_in_mbs = ps_dec->u2_pic_ht >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag); 3205 num_mb_skipped = (ht_in_mbs * ps_dec->u2_frm_wd_in_mbs) 3206 - ps_dec->u2_total_mbs_coded; 3207 3208 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0)) 3209 prev_slice_err = 1; 3210 else 3211 prev_slice_err = 2; 3212 3213 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u2_total_mbs_coded == 0)) 3214 prev_slice_err = 1; 3215 3216 ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num, 3217 &temp_poc, prev_slice_err); 3218 3219 if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T) || 3220 (ret1 == ERROR_INV_SPS_PPS_T)) 3221 { 3222 ret = ret1; 3223 } 3224 } 3225 3226 if((ret == IVD_RES_CHANGED) 3227 || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED) 3228 || (ret == ERROR_UNAVAIL_PICBUF_T) 3229 || (ret == ERROR_UNAVAIL_MVBUF_T) 3230 || (ret == ERROR_INV_SPS_PPS_T)) 3231 { 3232 3233 /* signal the decode thread */ 3234 ih264d_signal_decode_thread(ps_dec); 3235 /* close deblock thread if it is not closed yet */ 3236 if(ps_dec->u4_num_cores == 3) 3237 { 3238 ih264d_signal_bs_deblk_thread(ps_dec); 3239 } 3240 /* dont consume bitstream for change in resolution case */ 3241 if(ret == IVD_RES_CHANGED) 3242 { 3243 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 3244 } 3245 return IV_FAIL; 3246 } 3247 3248 3249 if(ps_dec->u1_separate_parse) 3250 { 3251 /* If Format conversion is not complete, 3252 complete it here */ 3253 if(ps_dec->u4_num_cores == 2) 3254 { 3255 3256 /*do deblocking of all mbs*/ 3257 if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0)) 3258 { 3259 UWORD32 u4_num_mbs,u4_max_addr; 3260 tfr_ctxt_t s_tfr_ctxt; 3261 tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt; 3262 pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr; 3263 3264 /*BS is done for all mbs while parsing*/ 3265 u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1; 3266 ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1; 3267 3268 3269 ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt, 3270 ps_dec->u2_frm_wd_in_mbs, 0); 3271 3272 3273 u4_num_mbs = u4_max_addr 3274 - ps_dec->u4_cur_deblk_mb_num + 1; 3275 3276 DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs); 3277 3278 if(u4_num_mbs != 0) 3279 ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs, 3280 ps_tfr_cxt,1); 3281 3282 ps_dec->u4_start_recon_deblk = 0; 3283 3284 } 3285 3286 } 3287 3288 /*signal the decode thread*/ 3289 ih264d_signal_decode_thread(ps_dec); 3290 /* close deblock thread if it is not closed yet*/ 3291 if(ps_dec->u4_num_cores == 3) 3292 { 3293 ih264d_signal_bs_deblk_thread(ps_dec); 3294 } 3295 } 3296 3297 3298 DATA_SYNC(); 3299 3300 3301 if((ps_dec_op->u4_error_code & 0xff) 3302 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED) 3303 { 3304 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 3305 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 3306 } 3307 3308//Report if header (sps and pps) has not been decoded yet 3309 if(ps_dec->i4_header_decoded != 3) 3310 { 3311 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA); 3312 3313 } 3314 3315 if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3) 3316 { 3317 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA); 3318 3319 } 3320 if(ps_dec->u4_prev_nal_skipped) 3321 { 3322 /*We have encountered a referenced frame,return to app*/ 3323 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED; 3324 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 3325 ps_dec_op->u4_frame_decoded_flag = 0; 3326 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t); 3327 /* close deblock thread if it is not closed yet*/ 3328 if(ps_dec->u4_num_cores == 3) 3329 { 3330 ih264d_signal_bs_deblk_thread(ps_dec); 3331 } 3332 return (IV_FAIL); 3333 3334 } 3335 3336 if((ps_dec->u4_slice_start_code_found == 1) 3337 && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status)) 3338 { 3339 /* 3340 * For field pictures, set the bottom and top picture decoded u4_flag correctly. 3341 */ 3342 3343 if(ps_dec->ps_cur_slice->u1_field_pic_flag) 3344 { 3345 if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag) 3346 { 3347 ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY; 3348 } 3349 else 3350 { 3351 ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY; 3352 } 3353 } 3354 else 3355 { 3356 ps_dec->u1_top_bottom_decoded = TOP_FIELD_ONLY | BOT_FIELD_ONLY; 3357 } 3358 3359 /* if new frame in not found (if we are still getting slices from previous frame) 3360 * ih264d_deblock_display is not called. Such frames will not be added to reference /display 3361 */ 3362 if (((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0) 3363 && (ps_dec->u4_pic_buf_got == 1)) 3364 { 3365 /* Calling Function to deblock Picture and Display */ 3366 ret = ih264d_deblock_display(ps_dec); 3367 } 3368 3369 3370 /*set to complete ,as we dont support partial frame decode*/ 3371 if(ps_dec->i4_header_decoded == 3) 3372 { 3373 ps_dec->u2_total_mbs_coded = ps_dec->ps_cur_sps->u2_max_mb_addr + 1; 3374 } 3375 3376 /*Update the i4_frametype at the end of picture*/ 3377 if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL) 3378 { 3379 ps_dec->i4_frametype = IV_IDR_FRAME; 3380 } 3381 else if(ps_dec->i4_pic_type == B_SLICE) 3382 { 3383 ps_dec->i4_frametype = IV_B_FRAME; 3384 } 3385 else if(ps_dec->i4_pic_type == P_SLICE) 3386 { 3387 ps_dec->i4_frametype = IV_P_FRAME; 3388 } 3389 else if(ps_dec->i4_pic_type == I_SLICE) 3390 { 3391 ps_dec->i4_frametype = IV_I_FRAME; 3392 } 3393 else 3394 { 3395 H264_DEC_DEBUG_PRINT("Shouldn't come here\n"); 3396 } 3397 3398 //Update the content type 3399 ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag; 3400 3401 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2; 3402 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded 3403 - ps_dec->ps_cur_slice->u1_field_pic_flag; 3404 3405 } 3406 3407 /* close deblock thread if it is not closed yet*/ 3408 if(ps_dec->u4_num_cores == 3) 3409 { 3410 ih264d_signal_bs_deblk_thread(ps_dec); 3411 } 3412 3413 3414 { 3415 /* In case the decoder is configured to run in low delay mode, 3416 * then get display buffer and then format convert. 3417 * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles 3418 */ 3419 3420 if((0 == ps_dec->u4_num_reorder_frames_at_init) 3421 && ps_dec->u1_init_dec_flag) 3422 { 3423 3424 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer, 3425 &(ps_dec->s_disp_op)); 3426 if(0 == ps_dec->s_disp_op.u4_error_code) 3427 { 3428 ps_dec->u4_fmt_conv_cur_row = 0; 3429 ps_dec->u4_output_present = 1; 3430 } 3431 } 3432 3433 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op); 3434 3435 /* If Format conversion is not complete, 3436 complete it here */ 3437 if(ps_dec->u4_output_present && 3438 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht)) 3439 { 3440 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht 3441 - ps_dec->u4_fmt_conv_cur_row; 3442 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 3443 ps_dec->u4_fmt_conv_cur_row, 3444 ps_dec->u4_fmt_conv_num_rows); 3445 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 3446 } 3447 3448 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op)); 3449 } 3450 3451 if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1) 3452 { 3453 ps_dec_op->u4_progressive_frame_flag = 1; 3454 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3455 { 3456 if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag) 3457 && (0 == ps_dec->ps_sps->u1_mb_aff_flag)) 3458 ps_dec_op->u4_progressive_frame_flag = 0; 3459 3460 } 3461 } 3462 3463 if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded) 3464 { 3465 ps_dec->u1_top_bottom_decoded = 0; 3466 } 3467 /*--------------------------------------------------------------------*/ 3468 /* Do End of Pic processing. */ 3469 /* Should be called only if frame was decoded in previous process call*/ 3470 /*--------------------------------------------------------------------*/ 3471 if(ps_dec->u4_pic_buf_got == 1) 3472 { 3473 if(1 == ps_dec->u1_last_pic_not_decoded) 3474 { 3475 ret = ih264d_end_of_pic_dispbuf_mgr(ps_dec); 3476 3477 if(ret != OK) 3478 return ret; 3479 3480 ret = ih264d_end_of_pic(ps_dec); 3481 if(ret != OK) 3482 return ret; 3483 } 3484 else 3485 { 3486 ret = ih264d_end_of_pic(ps_dec); 3487 if(ret != OK) 3488 return ret; 3489 } 3490 3491 } 3492 3493 3494 /*Data memory barrier instruction,so that yuv write by the library is complete*/ 3495 DATA_SYNC(); 3496 3497 H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n", 3498 ps_dec_op->u4_num_bytes_consumed); 3499 return api_ret_value; 3500} 3501 3502WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3503{ 3504 char version_string[MAXVERSION_STRLEN + 1]; 3505 UWORD32 version_string_len; 3506 3507 ivd_ctl_getversioninfo_ip_t *ps_ip; 3508 ivd_ctl_getversioninfo_op_t *ps_op; 3509 3510 ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip; 3511 ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op; 3512 UNUSED(dec_hdl); 3513 ps_op->u4_error_code = IV_SUCCESS; 3514 3515 VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER, 3516 CODEC_VENDOR); 3517 3518 if((WORD32)ps_ip->u4_version_buffer_size <= 0) 3519 { 3520 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT; 3521 return (IV_FAIL); 3522 } 3523 3524 version_string_len = strlen(version_string) + 1; 3525 3526 if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string))) 3527 { 3528 memcpy(ps_ip->pv_version_buffer, version_string, version_string_len); 3529 ps_op->u4_error_code = IV_SUCCESS; 3530 } 3531 else 3532 { 3533 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT; 3534 return IV_FAIL; 3535 } 3536 return (IV_SUCCESS); 3537} 3538 3539/*****************************************************************************/ 3540/* */ 3541/* Function Name : ih264d_get_display_frame */ 3542/* */ 3543/* Description : */ 3544/* Inputs :iv_obj_t decoder handle */ 3545/* :pv_api_ip pointer to input structure */ 3546/* :pv_api_op pointer to output structure */ 3547/* Outputs : */ 3548/* Returns : void */ 3549/* */ 3550/* Issues : none */ 3551/* */ 3552/* Revision History: */ 3553/* */ 3554/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3555/* 22 10 2008 100356 Draft */ 3556/* */ 3557/*****************************************************************************/ 3558WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl, 3559 void *pv_api_ip, 3560 void *pv_api_op) 3561{ 3562 3563 UNUSED(dec_hdl); 3564 UNUSED(pv_api_ip); 3565 UNUSED(pv_api_op); 3566 // This function is no longer needed, output is returned in the process() 3567 return IV_FAIL; 3568} 3569 3570/*****************************************************************************/ 3571/* */ 3572/* Function Name : ih264d_set_display_frame */ 3573/* */ 3574/* Description : */ 3575/* */ 3576/* Inputs :iv_obj_t decoder handle */ 3577/* :pv_api_ip pointer to input structure */ 3578/* :pv_api_op pointer to output structure */ 3579/* Outputs : */ 3580/* Returns : void */ 3581/* */ 3582/* Issues : none */ 3583/* */ 3584/* Revision History: */ 3585/* */ 3586/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3587/* 22 10 2008 100356 Draft */ 3588/* */ 3589/*****************************************************************************/ 3590WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl, 3591 void *pv_api_ip, 3592 void *pv_api_op) 3593{ 3594 3595 ivd_set_display_frame_ip_t *dec_disp_ip; 3596 ivd_set_display_frame_op_t *dec_disp_op; 3597 3598 UWORD32 i, num_mvbank_req; 3599 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3600 3601 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip; 3602 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op; 3603 dec_disp_op->u4_error_code = 0; 3604 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3605 { 3606 UWORD32 level, width_mbs, height_mbs; 3607 3608 level = ps_dec->u4_level_at_init; 3609 width_mbs = ps_dec->u2_frm_wd_in_mbs; 3610 height_mbs = ps_dec->u2_frm_ht_in_mbs; 3611 3612 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) 3613 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames != 64)) 3614 { 3615 num_mvbank_req = ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2; 3616 } 3617 else 3618 { 3619 /*if VUI is not present assume maximum possible refrence frames for the level, 3620 * as max reorder frames*/ 3621 num_mvbank_req = ih264d_get_dpb_size_new(level, width_mbs, 3622 height_mbs); 3623 } 3624 3625 num_mvbank_req += ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 3626 } 3627 else 3628 { 3629 UWORD32 num_bufs_app, num_bufs_level; 3630 UWORD32 num_ref_frames, num_reorder_frames, luma_width; 3631 UWORD32 luma_height, level; 3632 3633 num_ref_frames = ps_dec->u4_num_ref_frames_at_init; 3634 num_reorder_frames = ps_dec->u4_num_reorder_frames_at_init; 3635 level = ps_dec->u4_level_at_init; 3636 luma_width = ps_dec->u4_width_at_init; 3637 luma_height = ps_dec->u4_height_at_init; 3638 3639 num_bufs_app = num_ref_frames + num_reorder_frames + 1; 3640 3641 if(num_bufs_app <= 1) 3642 num_bufs_app = 2; 3643 3644 num_bufs_level = ih264d_get_dpb_size_new(level, (luma_width >> 4), 3645 (luma_height >> 4)); 3646 3647 num_bufs_level = num_bufs_level * 2 + 1; 3648 3649 num_mvbank_req = MIN(num_bufs_level, num_bufs_app); 3650 3651 num_mvbank_req += ps_dec->u4_num_extra_disp_bufs_at_init; 3652 3653 } 3654 3655 ps_dec->u4_num_disp_bufs = 0; 3656 if(ps_dec->u4_share_disp_buf) 3657 { 3658 UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs; 3659 if(u4_num_bufs > MAX_DISP_BUFS_NEW) 3660 u4_num_bufs = MAX_DISP_BUFS_NEW; 3661 3662 u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW); 3663 u4_num_bufs = MIN(u4_num_bufs, num_mvbank_req); 3664 3665 ps_dec->u4_num_disp_bufs = u4_num_bufs; 3666 for(i = 0; i < u4_num_bufs; i++) 3667 { 3668 ps_dec->disp_bufs[i].u4_num_bufs = 3669 dec_disp_ip->s_disp_buffer[i].u4_num_bufs; 3670 3671 ps_dec->disp_bufs[i].buf[0] = 3672 dec_disp_ip->s_disp_buffer[i].pu1_bufs[0]; 3673 ps_dec->disp_bufs[i].buf[1] = 3674 dec_disp_ip->s_disp_buffer[i].pu1_bufs[1]; 3675 ps_dec->disp_bufs[i].buf[2] = 3676 dec_disp_ip->s_disp_buffer[i].pu1_bufs[2]; 3677 3678 ps_dec->disp_bufs[i].u4_bufsize[0] = 3679 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]; 3680 ps_dec->disp_bufs[i].u4_bufsize[1] = 3681 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]; 3682 ps_dec->disp_bufs[i].u4_bufsize[2] = 3683 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]; 3684 3685 } 3686 } 3687 return IV_SUCCESS; 3688 3689} 3690 3691/*****************************************************************************/ 3692/* */ 3693/* Function Name : ih264d_set_flush_mode */ 3694/* */ 3695/* Description : */ 3696/* */ 3697/* Inputs :iv_obj_t decoder handle */ 3698/* :pv_api_ip pointer to input structure */ 3699/* :pv_api_op pointer to output structure */ 3700/* Globals : <Does it use any global variables?> */ 3701/* Outputs : */ 3702/* Returns : void */ 3703/* */ 3704/* Issues : none */ 3705/* */ 3706/* Revision History: */ 3707/* */ 3708/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3709/* 22 10 2008 100356 Draft */ 3710/* */ 3711/*****************************************************************************/ 3712WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3713{ 3714 3715 dec_struct_t * ps_dec; 3716 ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op; 3717 ps_ctl_op->u4_error_code = 0; 3718 3719 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3720 UNUSED(pv_api_ip); 3721 /* ! */ 3722 /* Signal flush frame control call */ 3723 ps_dec->u1_flushfrm = 1; 3724 3725 if( ps_dec->u1_init_dec_flag == 1) 3726 { 3727 3728 ih264d_release_pics_in_dpb((void *)ps_dec, 3729 ps_dec->u1_pic_bufs); 3730 ih264d_release_display_bufs(ps_dec); 3731 } 3732 3733 ps_ctl_op->u4_error_code = 3734 ((ivd_ctl_flush_op_t*)ps_dec->pv_dec_out)->u4_error_code; //verify the value 3735 3736 return IV_SUCCESS; 3737 3738} 3739 3740/*****************************************************************************/ 3741/* */ 3742/* Function Name : ih264d_get_status */ 3743/* */ 3744/* Description : */ 3745/* */ 3746/* Inputs :iv_obj_t decoder handle */ 3747/* :pv_api_ip pointer to input structure */ 3748/* :pv_api_op pointer to output structure */ 3749/* Globals : <Does it use any global variables?> */ 3750/* Outputs : */ 3751/* Returns : void */ 3752/* */ 3753/* Issues : none */ 3754/* */ 3755/* Revision History: */ 3756/* */ 3757/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3758/* 22 10 2008 100356 Draft */ 3759/* */ 3760/*****************************************************************************/ 3761 3762WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3763{ 3764 3765 UWORD32 i; 3766 dec_struct_t * ps_dec; 3767 UWORD32 pic_wd, pic_ht; 3768 ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op; 3769 UNUSED(pv_api_ip); 3770 ps_ctl_op->u4_error_code = 0; 3771 3772 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3773 3774 pic_wd = ps_dec->u4_width_at_init; 3775 pic_ht = ps_dec->u4_height_at_init; 3776 3777 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3778 { 3779 ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height; 3780 ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width; 3781 3782 if(0 == ps_dec->u4_share_disp_buf) 3783 { 3784 pic_wd = ps_dec->u2_disp_width; 3785 pic_ht = ps_dec->u2_disp_height; 3786 3787 } 3788 else 3789 { 3790 pic_wd = ps_dec->u2_frm_wd_y; 3791 pic_ht = ps_dec->u2_frm_ht_y; 3792 } 3793 } 3794 else 3795 { 3796 ps_ctl_op->u4_pic_ht = pic_wd; 3797 ps_ctl_op->u4_pic_wd = pic_ht; 3798 3799 if(1 == ps_dec->u4_share_disp_buf) 3800 { 3801 pic_wd += (PAD_LEN_Y_H << 1); 3802 pic_ht += (PAD_LEN_Y_V << 2); 3803 3804 } 3805 3806 } 3807 3808 if(ps_dec->u4_app_disp_width > pic_wd) 3809 pic_wd = ps_dec->u4_app_disp_width; 3810 if(0 == ps_dec->u4_share_disp_buf) 3811 ps_ctl_op->u4_num_disp_bufs = 1; 3812 else 3813 { 3814 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3815 { 3816 UWORD32 level, width_mbs, height_mbs; 3817 3818 level = ps_dec->u4_level_at_init; 3819 width_mbs = ps_dec->u2_frm_wd_in_mbs; 3820 height_mbs = ps_dec->u2_frm_ht_in_mbs; 3821 3822 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) 3823 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames 3824 != 64)) 3825 { 3826 ps_ctl_op->u4_num_disp_bufs = 3827 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2; 3828 } 3829 else 3830 { 3831 /*if VUI is not present assume maximum possible refrence frames for the level, 3832 * as max reorder frames*/ 3833 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new( 3834 level, width_mbs, height_mbs); 3835 } 3836 3837 ps_ctl_op->u4_num_disp_bufs += 3838 ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 3839 } 3840 else 3841 { 3842 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new( 3843 ps_dec->u4_level_at_init, 3844 (ps_dec->u4_width_at_init >> 4), 3845 (ps_dec->u4_height_at_init >> 4)); 3846 3847 ps_ctl_op->u4_num_disp_bufs += 3848 ps_ctl_op->u4_num_disp_bufs; 3849 3850 ps_ctl_op->u4_num_disp_bufs = 3851 MIN(ps_ctl_op->u4_num_disp_bufs, 3852 (ps_dec->u4_num_ref_frames_at_init 3853 + ps_dec->u4_num_reorder_frames_at_init)); 3854 3855 } 3856 3857 ps_ctl_op->u4_num_disp_bufs = MAX( 3858 ps_ctl_op->u4_num_disp_bufs, 6); 3859 ps_ctl_op->u4_num_disp_bufs = MIN( 3860 ps_ctl_op->u4_num_disp_bufs, 32); 3861 } 3862 3863 ps_ctl_op->u4_error_code = ps_dec->i4_error_code; 3864 3865 ps_ctl_op->u4_frame_rate = 0; //make it proper 3866 ps_ctl_op->u4_bit_rate = 0; //make it proper 3867 ps_ctl_op->e_content_type = ps_dec->i4_content_type; 3868 ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format; 3869 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS; 3870 3871 if(ps_dec->u1_chroma_format == IV_YUV_420P) 3872 { 3873 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420; 3874 } 3875 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 3876 { 3877 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 3878 } 3879 else if(ps_dec->u1_chroma_format == IV_RGB_565) 3880 { 3881 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 3882 } 3883 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 3884 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 3885 { 3886 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP; 3887 } 3888 3889 else 3890 { 3891 //Invalid chroma format; Error code may be updated, verify in testing if needed 3892 ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL; 3893 return IV_FAIL; 3894 } 3895 3896 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++) 3897 { 3898 ps_ctl_op->u4_min_in_buf_size[i] = MIN_IN_BUF_SIZE; 3899 } 3900 3901 /*!*/ 3902 if(ps_dec->u1_chroma_format == IV_YUV_420P) 3903 { 3904 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 3905 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 3906 >> 2; 3907 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht) 3908 >> 2; 3909 } 3910 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 3911 { 3912 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 3913 * 2; 3914 ps_ctl_op->u4_min_out_buf_size[1] = 3915 ps_ctl_op->u4_min_out_buf_size[2] = 0; 3916 } 3917 else if(ps_dec->u1_chroma_format == IV_RGB_565) 3918 { 3919 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 3920 * 2; 3921 ps_ctl_op->u4_min_out_buf_size[1] = 3922 ps_ctl_op->u4_min_out_buf_size[2] = 0; 3923 } 3924 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 3925 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 3926 { 3927 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 3928 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 3929 >> 1; 3930 ps_ctl_op->u4_min_out_buf_size[2] = 0; 3931 } 3932 3933 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs; 3934 return IV_SUCCESS; 3935} 3936 3937/*****************************************************************************/ 3938/* */ 3939/* Function Name : ih264d_get_buf_info */ 3940/* */ 3941/* Description : */ 3942/* */ 3943/* Inputs :iv_obj_t decoder handle */ 3944/* :pv_api_ip pointer to input structure */ 3945/* :pv_api_op pointer to output structure */ 3946/* Globals : <Does it use any global variables?> */ 3947/* Outputs : */ 3948/* Returns : void */ 3949/* */ 3950/* Issues : none */ 3951/* */ 3952/* Revision History: */ 3953/* */ 3954/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3955/* 22 10 2008 100356 Draft */ 3956/* */ 3957/*****************************************************************************/ 3958WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3959{ 3960 3961 dec_struct_t * ps_dec; 3962 UWORD8 i = 0; // Default for 420P format 3963 UWORD16 pic_wd, pic_ht; 3964 ivd_ctl_getbufinfo_op_t *ps_ctl_op = 3965 (ivd_ctl_getbufinfo_op_t*)pv_api_op; 3966 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS]; 3967 UNUSED(pv_api_ip); 3968 3969 ps_ctl_op->u4_error_code = 0; 3970 3971 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3972 3973 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS; 3974 3975 3976 ps_ctl_op->u4_num_disp_bufs = 1; 3977 3978 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++) 3979 { 3980 ps_ctl_op->u4_min_in_buf_size[i] = MIN_IN_BUF_SIZE; 3981 } 3982 3983 pic_wd = ps_dec->u4_width_at_init; 3984 pic_ht = ps_dec->u4_height_at_init; 3985 3986 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3987 { 3988 3989 if(0 == ps_dec->u4_share_disp_buf) 3990 { 3991 pic_wd = ps_dec->u2_disp_width; 3992 pic_ht = ps_dec->u2_disp_height; 3993 3994 } 3995 else 3996 { 3997 pic_wd = ps_dec->u2_frm_wd_y; 3998 pic_ht = ps_dec->u2_frm_ht_y; 3999 } 4000 4001 } 4002 else 4003 { 4004 if(1 == ps_dec->u4_share_disp_buf) 4005 { 4006 pic_wd += (PAD_LEN_Y_H << 1); 4007 pic_ht += (PAD_LEN_Y_V << 2); 4008 4009 } 4010 } 4011 4012 if((WORD32)ps_dec->u4_app_disp_width > pic_wd) 4013 pic_wd = ps_dec->u4_app_disp_width; 4014 4015 if(0 == ps_dec->u4_share_disp_buf) 4016 ps_ctl_op->u4_num_disp_bufs = 1; 4017 else 4018 { 4019 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 4020 { 4021 UWORD32 level, width_mbs, height_mbs; 4022 4023 level = ps_dec->u4_level_at_init; 4024 width_mbs = ps_dec->u2_frm_wd_in_mbs; 4025 height_mbs = ps_dec->u2_frm_ht_in_mbs; 4026 4027 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) 4028 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames 4029 != 64)) 4030 { 4031 ps_ctl_op->u4_num_disp_bufs = 4032 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2; 4033 } 4034 else 4035 { 4036 /*if VUI is not present assume maximum possible refrence frames for the level, 4037 * as max reorder frames*/ 4038 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new( 4039 level, width_mbs, height_mbs); 4040 } 4041 4042 ps_ctl_op->u4_num_disp_bufs += 4043 ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 4044 4045 } 4046 else 4047 { 4048 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new( 4049 ps_dec->u4_level_at_init, 4050 (ps_dec->u4_width_at_init >> 4), 4051 (ps_dec->u4_height_at_init >> 4)); 4052 4053 ps_ctl_op->u4_num_disp_bufs += 4054 ps_ctl_op->u4_num_disp_bufs; 4055 4056 ps_ctl_op->u4_num_disp_bufs = 4057 MIN(ps_ctl_op->u4_num_disp_bufs, 4058 (ps_dec->u4_num_ref_frames_at_init 4059 + ps_dec->u4_num_reorder_frames_at_init)); 4060 4061 } 4062 4063 ps_ctl_op->u4_num_disp_bufs = MAX( 4064 ps_ctl_op->u4_num_disp_bufs, 6); 4065 ps_ctl_op->u4_num_disp_bufs = MIN( 4066 ps_ctl_op->u4_num_disp_bufs, 32); 4067 } 4068 4069 ps_ctl_op->u4_min_num_out_bufs = ih264d_get_outbuf_size( 4070 pic_wd, pic_ht, ps_dec->u1_chroma_format, 4071 &au4_min_out_buf_size[0]); 4072 4073 for(i = 0; i < ps_ctl_op->u4_min_num_out_bufs; i++) 4074 { 4075 ps_ctl_op->u4_min_out_buf_size[i] = au4_min_out_buf_size[i]; 4076 } 4077 4078 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs; 4079 4080 return IV_SUCCESS; 4081} 4082 4083/*****************************************************************************/ 4084/* */ 4085/* Function Name : ih264d_set_params */ 4086/* */ 4087/* Description : */ 4088/* */ 4089/* Inputs :iv_obj_t decoder handle */ 4090/* :pv_api_ip pointer to input structure */ 4091/* :pv_api_op pointer to output structure */ 4092/* Outputs : */ 4093/* Returns : void */ 4094/* */ 4095/* Issues : none */ 4096/* */ 4097/* Revision History: */ 4098/* */ 4099/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4100/* 22 10 2008 100356 Draft */ 4101/* */ 4102/*****************************************************************************/ 4103WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 4104{ 4105 4106 dec_struct_t * ps_dec; 4107 WORD32 ret = IV_SUCCESS; 4108 4109 ivd_ctl_set_config_ip_t *ps_ctl_ip = 4110 (ivd_ctl_set_config_ip_t *)pv_api_ip; 4111 ivd_ctl_set_config_op_t *ps_ctl_op = 4112 (ivd_ctl_set_config_op_t *)pv_api_op; 4113 4114 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 4115 4116 ps_dec->u4_skip_frm_mask = 0; 4117 4118 ps_ctl_op->u4_error_code = 0; 4119 4120 ps_dec->i4_app_skip_mode = ps_ctl_ip->e_frm_skip_mode; 4121 4122 /*Is it really supported test it when you so the corner testing using test app*/ 4123 4124 if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE) 4125 { 4126 4127 if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_P) 4128 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT; 4129 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_B) 4130 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT; 4131 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_PB) 4132 { 4133 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT; 4134 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT; 4135 } 4136 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_I) 4137 ps_dec->u4_skip_frm_mask |= 1 << I_SLC_BIT; 4138 else 4139 { 4140 //dynamic parameter not supported 4141 //Put an appropriate error code to return the error.. 4142 //when you do the error code tests and after that remove this comment 4143 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 4144 ret = IV_FAIL; 4145 } 4146 } 4147 4148 if((0 != ps_dec->u4_app_disp_width) 4149 && (ps_ctl_ip->u4_disp_wd 4150 != ps_dec->u4_app_disp_width)) 4151 { 4152 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 4153 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID; 4154 ret = IV_FAIL; 4155 } 4156 else 4157 { 4158 if((ps_ctl_ip->u4_disp_wd >= ps_dec->u2_pic_wd)/* && (ps_ctl_ip->u4_disp_wd <= ps_dec->u4_width_at_init) */) 4159 { 4160 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd; 4161 } 4162 else if((0 == ps_dec->i4_header_decoded) /*&& (ps_ctl_ip->u4_disp_wd <= ps_dec->u4_width_at_init)*/) 4163 { 4164 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd; 4165 } 4166 else if(ps_ctl_ip->u4_disp_wd == 0) 4167 { 4168 ps_dec->u4_app_disp_width = 0; 4169 } 4170 else 4171 { 4172 /* 4173 * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF) 4174 * does not propogate. 4175 */ 4176 ps_dec->u4_app_disp_width = 0; 4177 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 4178 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID; 4179 ret = IV_FAIL; 4180 } 4181 } 4182 if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME) 4183 ps_dec->i4_decode_header = 0; 4184 else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER) 4185 ps_dec->i4_decode_header = 1; 4186 else 4187 { 4188 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 4189 ps_dec->i4_decode_header = 1; 4190 ret = IV_FAIL; 4191 } 4192 4193 return ret; 4194 4195} 4196 4197/*****************************************************************************/ 4198/* */ 4199/* Function Name : ih264d_set_default_params */ 4200/* */ 4201/* Description : */ 4202/* */ 4203/* Inputs :iv_obj_t decoder handle */ 4204/* :pv_api_ip pointer to input structure */ 4205/* :pv_api_op pointer to output structure */ 4206/* Outputs : */ 4207/* Returns : void */ 4208/* */ 4209/* Issues : none */ 4210/* */ 4211/* Revision History: */ 4212/* */ 4213/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4214/* 08 08 2011 100421 Copied from set_params */ 4215/* */ 4216/*****************************************************************************/ 4217WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl, 4218 void *pv_api_ip, 4219 void *pv_api_op) 4220{ 4221 4222 dec_struct_t * ps_dec; 4223 WORD32 ret = IV_SUCCESS; 4224 4225 ivd_ctl_set_config_op_t *ps_ctl_op = 4226 (ivd_ctl_set_config_op_t *)pv_api_op; 4227 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 4228 UNUSED(pv_api_ip); 4229 4230 4231 { 4232 ps_dec->u4_app_disp_width = 0; 4233 ps_dec->u4_skip_frm_mask = 0; 4234 ps_dec->i4_decode_header = 1; 4235 4236 ps_ctl_op->u4_error_code = 0; 4237 } 4238 4239 4240 return ret; 4241} 4242 4243/*****************************************************************************/ 4244/* */ 4245/* Function Name : ih264d_reset */ 4246/* */ 4247/* Description : */ 4248/* */ 4249/* Inputs :iv_obj_t decoder handle */ 4250/* :pv_api_ip pointer to input structure */ 4251/* :pv_api_op pointer to output structure */ 4252/* Globals : <Does it use any global variables?> */ 4253/* Outputs : */ 4254/* Returns : void */ 4255/* */ 4256/* Issues : none */ 4257/* */ 4258/* Revision History: */ 4259/* */ 4260/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4261/* 22 10 2008 100356 Draft */ 4262/* */ 4263/*****************************************************************************/ 4264WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 4265{ 4266 dec_struct_t * ps_dec; 4267 ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op; 4268 UNUSED(pv_api_ip); 4269 ps_ctl_op->u4_error_code = 0; 4270 4271 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 4272//CHECK 4273 if(ps_dec != NULL) 4274 { 4275 4276 ih264d_init_decoder(ps_dec); 4277 4278 /* 4279 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t)); 4280 memset(ps_dec->u4_disp_buf_mapping, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 4281 memset(ps_dec->u4_disp_buf_to_be_freed, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 4282 */ 4283 } 4284 else 4285 { 4286 H264_DEC_DEBUG_PRINT( 4287 "\nReset called without Initializing the decoder\n"); 4288 ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE; 4289 } 4290 4291 return IV_SUCCESS; 4292} 4293 4294/*****************************************************************************/ 4295/* */ 4296/* Function Name : ih264d_ctl */ 4297/* */ 4298/* Description : */ 4299/* */ 4300/* Inputs :iv_obj_t decoder handle */ 4301/* :pv_api_ip pointer to input structure */ 4302/* :pv_api_op pointer to output structure */ 4303/* Outputs : */ 4304/* Returns : void */ 4305/* */ 4306/* Issues : none */ 4307/* */ 4308/* Revision History: */ 4309/* */ 4310/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4311/* 22 10 2008 100356 Draft */ 4312/* */ 4313/*****************************************************************************/ 4314WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 4315{ 4316 ivd_ctl_set_config_ip_t *ps_ctl_ip; 4317 ivd_ctl_set_config_op_t *ps_ctl_op; 4318 WORD32 ret = IV_SUCCESS; 4319 UWORD32 subcommand; 4320 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 4321 4322 if(ps_dec->init_done != 1) 4323 { 4324 //Return proper Error Code 4325 return IV_FAIL; 4326 } 4327 ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip; 4328 ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op; 4329 ps_ctl_op->u4_error_code = 0; 4330 subcommand = ps_ctl_ip->e_sub_cmd; 4331 4332 switch(subcommand) 4333 { 4334 case IVD_CMD_CTL_GETPARAMS: 4335 ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip, 4336 (void *)pv_api_op); 4337 break; 4338 case IVD_CMD_CTL_SETPARAMS: 4339 ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip, 4340 (void *)pv_api_op); 4341 break; 4342 case IVD_CMD_CTL_RESET: 4343 ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op); 4344 break; 4345 case IVD_CMD_CTL_SETDEFAULT: 4346 ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip, 4347 (void *)pv_api_op); 4348 break; 4349 case IVD_CMD_CTL_FLUSH: 4350 ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip, 4351 (void *)pv_api_op); 4352 break; 4353 case IVD_CMD_CTL_GETBUFINFO: 4354 ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip, 4355 (void *)pv_api_op); 4356 break; 4357 case IVD_CMD_CTL_GETVERSION: 4358 ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip, 4359 (void *)pv_api_op); 4360 break; 4361 case IH264D_CMD_CTL_DEGRADE: 4362 ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip, 4363 (void *)pv_api_op); 4364 break; 4365 4366 case IH264D_CMD_CTL_SET_NUM_CORES: 4367 ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip, 4368 (void *)pv_api_op); 4369 break; 4370 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS: 4371 ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip, 4372 (void *)pv_api_op); 4373 break; 4374 case IH264D_CMD_CTL_SET_PROCESSOR: 4375 ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip, 4376 (void *)pv_api_op); 4377 break; 4378 default: 4379 H264_DEC_DEBUG_PRINT("\ndo nothing\n") 4380 ; 4381 break; 4382 } 4383 4384 return ret; 4385} 4386/*****************************************************************************/ 4387/* */ 4388/* Function Name : ih264d_rel_display_frame */ 4389/* */ 4390/* Description : */ 4391/* */ 4392/* Inputs :iv_obj_t decoder handle */ 4393/* :pv_api_ip pointer to input structure */ 4394/* :pv_api_op pointer to output structure */ 4395/* Outputs : */ 4396/* Returns : void */ 4397/* */ 4398/* Issues : none */ 4399/* */ 4400/* Revision History: */ 4401/* */ 4402/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4403/* 22 10 2008 100356 Draft */ 4404/* */ 4405/*****************************************************************************/ 4406WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl, 4407 void *pv_api_ip, 4408 void *pv_api_op) 4409{ 4410 4411 ivd_rel_display_frame_ip_t *ps_rel_ip; 4412 ivd_rel_display_frame_op_t *ps_rel_op; 4413 UWORD32 buf_released = 0; 4414 4415 UWORD32 u4_ts = -1; 4416 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 4417 4418 ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip; 4419 ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op; 4420 ps_rel_op->u4_error_code = 0; 4421 u4_ts = ps_rel_ip->u4_disp_buf_id; 4422 4423 if(0 == ps_dec->u4_share_disp_buf) 4424 { 4425 ps_dec->u4_disp_buf_mapping[u4_ts] = 0; 4426 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0; 4427 return IV_SUCCESS; 4428 } 4429 4430 if(ps_dec->pv_pic_buf_mgr != NULL) 4431 { 4432 if(1 == ps_dec->u4_disp_buf_mapping[u4_ts]) 4433 { 4434 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 4435 ps_rel_ip->u4_disp_buf_id, 4436 BUF_MGR_IO); 4437 ps_dec->u4_disp_buf_mapping[u4_ts] = 0; 4438 buf_released = 1; 4439 } 4440 } 4441 4442 if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released)) 4443 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1; 4444 4445 return IV_SUCCESS; 4446} 4447 4448/** 4449 ******************************************************************************* 4450 * 4451 * @brief 4452 * Sets degrade params 4453 * 4454 * @par Description: 4455 * Sets degrade params. 4456 * Refer to ih264d_ctl_degrade_ip_t definition for details 4457 * 4458 * @param[in] ps_codec_obj 4459 * Pointer to codec object at API level 4460 * 4461 * @param[in] pv_api_ip 4462 * Pointer to input argument structure 4463 * 4464 * @param[out] pv_api_op 4465 * Pointer to output argument structure 4466 * 4467 * @returns Status 4468 * 4469 * @remarks 4470 * 4471 * 4472 ******************************************************************************* 4473 */ 4474 4475WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj, 4476 void *pv_api_ip, 4477 void *pv_api_op) 4478{ 4479 ih264d_ctl_degrade_ip_t *ps_ip; 4480 ih264d_ctl_degrade_op_t *ps_op; 4481 dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle; 4482 4483 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip; 4484 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op; 4485 4486 ps_codec->i4_degrade_type = ps_ip->i4_degrade_type; 4487 ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval; 4488 ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics; 4489 4490 ps_op->u4_error_code = 0; 4491 ps_codec->i4_degrade_pic_cnt = 0; 4492 4493 return IV_SUCCESS; 4494} 4495 4496WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl, 4497 void *pv_api_ip, 4498 void *pv_api_op) 4499{ 4500 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip; 4501 ih264d_ctl_get_frame_dimensions_op_t *ps_op; 4502 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 4503 UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset; 4504 4505 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 4506 4507 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op; 4508 UNUSED(ps_ip); 4509 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 4510 { 4511 disp_wd = ps_dec->u2_disp_width; 4512 disp_ht = ps_dec->u2_disp_height; 4513 4514 if(0 == ps_dec->u4_share_disp_buf) 4515 { 4516 buffer_wd = disp_wd; 4517 buffer_ht = disp_ht; 4518 } 4519 else 4520 { 4521 buffer_wd = ps_dec->u2_frm_wd_y; 4522 buffer_ht = ps_dec->u2_frm_ht_y; 4523 } 4524 } 4525 else 4526 { 4527 disp_wd = ps_dec->u4_width_at_init; 4528 disp_ht = ps_dec->u4_height_at_init; 4529 4530 if(0 == ps_dec->u4_share_disp_buf) 4531 { 4532 buffer_wd = disp_wd; 4533 buffer_ht = disp_ht; 4534 } 4535 else 4536 { 4537 buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1); 4538 buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2); 4539 } 4540 } 4541 if(ps_dec->u4_app_disp_width > buffer_wd) 4542 buffer_wd = ps_dec->u4_app_disp_width; 4543 4544 if(0 == ps_dec->u4_share_disp_buf) 4545 { 4546 x_offset = 0; 4547 y_offset = 0; 4548 } 4549 else 4550 { 4551 y_offset = (PAD_LEN_Y_V << 1); 4552 x_offset = PAD_LEN_Y_H; 4553 4554 if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid)) 4555 && (0 != ps_dec->u2_crop_offset_y)) 4556 { 4557 y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y; 4558 x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y; 4559 } 4560 } 4561 4562 ps_op->u4_disp_wd[0] = disp_wd; 4563 ps_op->u4_disp_ht[0] = disp_ht; 4564 ps_op->u4_buffer_wd[0] = buffer_wd; 4565 ps_op->u4_buffer_ht[0] = buffer_ht; 4566 ps_op->u4_x_offset[0] = x_offset; 4567 ps_op->u4_y_offset[0] = y_offset; 4568 4569 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1) 4570 >> 1); 4571 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1) 4572 >> 1); 4573 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0] 4574 >> 1); 4575 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0] 4576 >> 1); 4577 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = 4578 (ps_op->u4_x_offset[0] >> 1); 4579 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = 4580 (ps_op->u4_y_offset[0] >> 1); 4581 4582 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 4583 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 4584 { 4585 ps_op->u4_disp_wd[2] = 0; 4586 ps_op->u4_disp_ht[2] = 0; 4587 ps_op->u4_buffer_wd[2] = 0; 4588 ps_op->u4_buffer_ht[2] = 0; 4589 ps_op->u4_x_offset[2] = 0; 4590 ps_op->u4_y_offset[2] = 0; 4591 4592 ps_op->u4_disp_wd[1] <<= 1; 4593 ps_op->u4_buffer_wd[1] <<= 1; 4594 ps_op->u4_x_offset[1] <<= 1; 4595 } 4596 4597 return IV_SUCCESS; 4598 4599} 4600 4601WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 4602{ 4603 ih264d_ctl_set_num_cores_ip_t *ps_ip; 4604 ih264d_ctl_set_num_cores_op_t *ps_op; 4605 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 4606 4607 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip; 4608 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op; 4609 ps_op->u4_error_code = 0; 4610 ps_dec->u4_num_cores = ps_ip->u4_num_cores; 4611 if(ps_dec->u4_num_cores == 1) 4612 { 4613 ps_dec->u1_separate_parse = 0; 4614 ps_dec->pi4_ctxt_save_register_dec = ps_dec->pi4_ctxt_save_register; 4615 } 4616 else 4617 { 4618 ps_dec->u1_separate_parse = 1; 4619 } 4620 4621 /*using only upto three threads currently*/ 4622 if(ps_dec->u4_num_cores > 3) 4623 ps_dec->u4_num_cores = 3; 4624 4625 return IV_SUCCESS; 4626} 4627 4628void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec, 4629 ivd_video_decode_op_t *ps_dec_op) 4630{ 4631 if((ps_dec_op->u4_error_code & 0xff) 4632 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED) 4633 { 4634 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 4635 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 4636 } 4637 ps_dec_op->e_pic_type = ps_dec->i4_frametype; 4638 4639 ps_dec_op->u4_new_seq = 0; 4640 ps_dec_op->u4_output_present = ps_dec->u4_output_present; 4641 ps_dec_op->u4_progressive_frame_flag = 4642 ps_dec->s_disp_op.u4_progressive_frame_flag; 4643 4644 ps_dec_op->u4_is_ref_flag = 1; 4645 if(ps_dec_op->u4_frame_decoded_flag) 4646 { 4647 if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0) 4648 ps_dec_op->u4_is_ref_flag = 0; 4649 } 4650 4651 ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format; 4652 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf; 4653 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type; 4654 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts; 4655 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id; 4656} 4657 4658/*****************************************************************************/ 4659/* */ 4660/* Function Name : ih264d_api_function */ 4661/* */ 4662/* Description : */ 4663/* */ 4664/* Inputs :iv_obj_t decoder handle */ 4665/* :pv_api_ip pointer to input structure */ 4666/* :pv_api_op pointer to output structure */ 4667/* Outputs : */ 4668/* Returns : void */ 4669/* */ 4670/* Issues : none */ 4671/* */ 4672/* Revision History: */ 4673/* */ 4674/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4675/* 22 10 2008 100356 Draft */ 4676/* */ 4677/*****************************************************************************/ 4678IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl, 4679 void *pv_api_ip, 4680 void *pv_api_op) 4681{ 4682 UWORD32 command; 4683 UWORD32 *pu2_ptr_cmd; 4684 UWORD32 u4_api_ret; 4685 IV_API_CALL_STATUS_T e_status; 4686 e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op); 4687 4688 if(e_status != IV_SUCCESS) 4689 { 4690 UWORD32 *ptr_err; 4691 4692 ptr_err = (UWORD32 *)pv_api_op; 4693 UNUSED(ptr_err); 4694 H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1)); 4695 return IV_FAIL; 4696 } 4697 4698 pu2_ptr_cmd = (UWORD32 *)pv_api_ip; 4699 pu2_ptr_cmd++; 4700 4701 command = *pu2_ptr_cmd; 4702// H264_DEC_DEBUG_PRINT("inside lib = %d\n",command); 4703 switch(command) 4704 { 4705 4706 case IV_CMD_GET_NUM_MEM_REC: 4707 u4_api_ret = ih264d_get_num_rec((void *)pv_api_ip, 4708 (void *)pv_api_op); 4709 4710 break; 4711 case IV_CMD_FILL_NUM_MEM_REC: 4712 4713 u4_api_ret = ih264d_fill_num_mem_rec((void *)pv_api_ip, 4714 (void *)pv_api_op); 4715 break; 4716 case IV_CMD_INIT: 4717 u4_api_ret = ih264d_init(dec_hdl, (void *)pv_api_ip, 4718 (void *)pv_api_op); 4719 break; 4720 4721 case IVD_CMD_VIDEO_DECODE: 4722 u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip, 4723 (void *)pv_api_op); 4724 break; 4725 4726 case IVD_CMD_GET_DISPLAY_FRAME: 4727 u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip, 4728 (void *)pv_api_op); 4729 4730 break; 4731 4732 case IVD_CMD_SET_DISPLAY_FRAME: 4733 u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip, 4734 (void *)pv_api_op); 4735 4736 break; 4737 4738 case IVD_CMD_REL_DISPLAY_FRAME: 4739 u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip, 4740 (void *)pv_api_op); 4741 break; 4742 4743 case IV_CMD_RETRIEVE_MEMREC: 4744 u4_api_ret = ih264d_clr(dec_hdl, (void *)pv_api_ip, 4745 (void *)pv_api_op); 4746 break; 4747 4748 case IVD_CMD_VIDEO_CTL: 4749 u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip, 4750 (void *)pv_api_op); 4751 break; 4752 default: 4753 u4_api_ret = IV_FAIL; 4754 break; 4755 } 4756 4757 return u4_api_ret; 4758} 4759