ih264d_api.c revision cdfd7573ecb1e838e755d178022faa0df171df1a
1/****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19*/ 20 21/*****************************************************************************/ 22/* */ 23/* File Name : ih264d_api.c */ 24/* */ 25/* Description : Has all API related functions */ 26/* */ 27/* */ 28/* List of Functions : api_check_struct_sanity */ 29/* ih264d_set_processor */ 30/* ih264d_get_num_rec */ 31/* ih264d_init_decoder */ 32/* ih264d_init_video_decoder */ 33/* ih264d_fill_num_mem_rec */ 34/* ih264d_clr */ 35/* ih264d_init */ 36/* ih264d_map_error */ 37/* ih264d_video_decode */ 38/* ih264d_get_version */ 39/* ih264d_get_display_frame */ 40/* ih264d_set_display_frame */ 41/* ih264d_set_flush_mode */ 42/* ih264d_get_status */ 43/* ih264d_get_buf_info */ 44/* ih264d_set_params */ 45/* ih264d_set_default_params */ 46/* ih264d_reset */ 47/* ih264d_ctl */ 48/* ih264d_rel_display_frame */ 49/* ih264d_set_degrade */ 50/* ih264d_get_frame_dimensions */ 51/* ih264d_set_num_cores */ 52/* ih264d_fill_output_struct_from_context */ 53/* ih264d_api_function */ 54/* */ 55/* Issues / Problems : None */ 56/* */ 57/* Revision History : */ 58/* */ 59/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 60/* 14 10 2008 100356(SKV) Draft */ 61/* */ 62/*****************************************************************************/ 63#include "ih264_typedefs.h" 64#include "ih264_macros.h" 65#include "ih264_platform_macros.h" 66#include "ih264d_tables.h" 67#include "iv.h" 68#include "ivd.h" 69#include "ih264d.h" 70#include "ih264d_defs.h" 71 72#include <string.h> 73#include <limits.h> 74#include <stddef.h> 75 76#include "ih264d_inter_pred.h" 77 78#include "ih264d_structs.h" 79#include "ih264d_nal.h" 80#include "ih264d_error_handler.h" 81 82#include "ih264d_defs.h" 83 84#include "ithread.h" 85#include "ih264d_parse_slice.h" 86#include "ih264d_function_selector.h" 87#include "ih264_error.h" 88#include "ih264_disp_mgr.h" 89#include "ih264_buf_mgr.h" 90#include "ih264d_deblocking.h" 91#include "ih264d_parse_cavlc.h" 92#include "ih264d_parse_cabac.h" 93#include "ih264d_utils.h" 94#include "ih264d_format_conv.h" 95#include "ih264d_parse_headers.h" 96#include "ih264d_thread_compute_bs.h" 97#include <assert.h> 98 99 100/*********************/ 101/* Codec Versioning */ 102/*********************/ 103//Move this to where it is used 104#define CODEC_NAME "H264VDEC" 105#define CODEC_RELEASE_TYPE "production" 106#define CODEC_RELEASE_VER "04.00" 107#define CODEC_VENDOR "ITTIAM" 108#define MAXVERSION_STRLEN 511 109#define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \ 110 snprintf(version_string, MAXVERSION_STRLEN, \ 111 "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s", \ 112 codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__) 113 114#define MAX_NAL_UNIT_SIZE MAX((H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_HEIGHT),MIN_NALUNIT_SIZE) 115#define MIN_NALUNIT_SIZE 200000 116 117 118#define MIN_IN_BUFS 1 119#define MIN_OUT_BUFS_420 3 120#define MIN_OUT_BUFS_422ILE 1 121#define MIN_OUT_BUFS_RGB565 1 122#define MIN_OUT_BUFS_420SP 2 123#define MIN_IN_BUF_SIZE (2*1024*1024) // Currently, i4_size set to 500kb, CHECK LATER 124 125#define NUM_FRAMES_LIMIT_ENABLED 0 126 127#if NUM_FRAMES_LIMIT_ENABLED 128#define NUM_FRAMES_LIMIT 10000 129#else 130#define NUM_FRAMES_LIMIT 0x7FFFFFFF 131#endif 132 133 134UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height); 135WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl, 136 void *pv_api_ip, 137 void *pv_api_op); 138WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op); 139 140WORD32 ih264d_deblock_display(dec_struct_t *ps_dec); 141 142void ih264d_signal_decode_thread(dec_struct_t *ps_dec); 143 144void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec); 145void ih264d_decode_picture_thread(dec_struct_t *ps_dec); 146 147WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj, 148 void *pv_api_ip, 149 void *pv_api_op); 150 151void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec, 152 ivd_video_decode_op_t *ps_dec_op); 153 154static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle, 155 void *pv_api_ip, 156 void *pv_api_op) 157{ 158 IVD_API_COMMAND_TYPE_T e_cmd; 159 UWORD32 *pu4_api_ip; 160 UWORD32 *pu4_api_op; 161 UWORD32 i, j; 162 163 if(NULL == pv_api_op) 164 return (IV_FAIL); 165 166 if(NULL == pv_api_ip) 167 return (IV_FAIL); 168 169 pu4_api_ip = (UWORD32 *)pv_api_ip; 170 pu4_api_op = (UWORD32 *)pv_api_op; 171 e_cmd = *(pu4_api_ip + 1); 172 173 /* error checks on handle */ 174 switch((WORD32)e_cmd) 175 { 176 case IV_CMD_GET_NUM_MEM_REC: 177 case IV_CMD_FILL_NUM_MEM_REC: 178 break; 179 case IV_CMD_INIT: 180 if(ps_handle == NULL) 181 { 182 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 183 *(pu4_api_op + 1) |= IVD_HANDLE_NULL; 184 return IV_FAIL; 185 } 186 187 if(ps_handle->u4_size != sizeof(iv_obj_t)) 188 { 189 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 190 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT; 191 H264_DEC_DEBUG_PRINT( 192 "Sizes do not match. Expected: %d, Got: %d", 193 sizeof(iv_obj_t), ps_handle->u4_size); 194 return IV_FAIL; 195 } 196 break; 197 case IVD_CMD_REL_DISPLAY_FRAME: 198 case IVD_CMD_SET_DISPLAY_FRAME: 199 case IVD_CMD_GET_DISPLAY_FRAME: 200 case IVD_CMD_VIDEO_DECODE: 201 case IV_CMD_RETRIEVE_MEMREC: 202 case IVD_CMD_VIDEO_CTL: 203 if(ps_handle == NULL) 204 { 205 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 206 *(pu4_api_op + 1) |= IVD_HANDLE_NULL; 207 return IV_FAIL; 208 } 209 210 if(ps_handle->u4_size != sizeof(iv_obj_t)) 211 { 212 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 213 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT; 214 return IV_FAIL; 215 } 216 217 if(ps_handle->pv_fxns != ih264d_api_function) 218 { 219 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 220 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 221 return IV_FAIL; 222 } 223 224 if(ps_handle->pv_codec_handle == NULL) 225 { 226 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 227 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 228 return IV_FAIL; 229 } 230 break; 231 default: 232 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 233 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD; 234 return IV_FAIL; 235 } 236 237 switch((WORD32)e_cmd) 238 { 239 case IV_CMD_GET_NUM_MEM_REC: 240 { 241 ih264d_num_mem_rec_ip_t *ps_ip = 242 (ih264d_num_mem_rec_ip_t *)pv_api_ip; 243 ih264d_num_mem_rec_op_t *ps_op = 244 (ih264d_num_mem_rec_op_t *)pv_api_op; 245 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0; 246 247 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size 248 != sizeof(ih264d_num_mem_rec_ip_t)) 249 { 250 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 251 << IVD_UNSUPPORTEDPARAM; 252 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 253 IVD_IP_API_STRUCT_SIZE_INCORRECT; 254 return (IV_FAIL); 255 } 256 257 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size 258 != sizeof(ih264d_num_mem_rec_op_t)) 259 { 260 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 261 << IVD_UNSUPPORTEDPARAM; 262 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 263 IVD_OP_API_STRUCT_SIZE_INCORRECT; 264 return (IV_FAIL); 265 } 266 } 267 break; 268 case IV_CMD_FILL_NUM_MEM_REC: 269 { 270 ih264d_fill_mem_rec_ip_t *ps_ip = 271 (ih264d_fill_mem_rec_ip_t *)pv_api_ip; 272 ih264d_fill_mem_rec_op_t *ps_op = 273 (ih264d_fill_mem_rec_op_t *)pv_api_op; 274 iv_mem_rec_t *ps_mem_rec; 275 WORD32 max_wd = ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd; 276 WORD32 max_ht = ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht; 277 278 max_wd = ALIGN16(max_wd); 279 max_ht = ALIGN32(max_ht); 280 281 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0; 282 283 if((ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size 284 > sizeof(ih264d_fill_mem_rec_ip_t)) 285 || (ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size 286 < sizeof(iv_fill_mem_rec_ip_t))) 287 { 288 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 289 << IVD_UNSUPPORTEDPARAM; 290 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 291 IVD_IP_API_STRUCT_SIZE_INCORRECT; 292 return (IV_FAIL); 293 } 294 295 if((ps_op->s_ivd_fill_mem_rec_op_t.u4_size 296 != sizeof(ih264d_fill_mem_rec_op_t)) 297 && (ps_op->s_ivd_fill_mem_rec_op_t.u4_size 298 != sizeof(iv_fill_mem_rec_op_t))) 299 { 300 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 301 << IVD_UNSUPPORTEDPARAM; 302 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 303 IVD_OP_API_STRUCT_SIZE_INCORRECT; 304 return (IV_FAIL); 305 } 306 307 if(max_wd < H264_MIN_FRAME_WIDTH) 308 { 309 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 310 << IVD_UNSUPPORTEDPARAM; 311 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 312 IVD_REQUESTED_WIDTH_NOT_SUPPPORTED; 313 return (IV_FAIL); 314 } 315 316 if(max_wd > H264_MAX_FRAME_WIDTH) 317 { 318 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 319 << IVD_UNSUPPORTEDPARAM; 320 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 321 IVD_REQUESTED_WIDTH_NOT_SUPPPORTED; 322 return (IV_FAIL); 323 } 324 325 if(max_ht < H264_MIN_FRAME_HEIGHT) 326 { 327 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 328 << IVD_UNSUPPORTEDPARAM; 329 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 330 IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED; 331 return (IV_FAIL); 332 } 333 334 if((max_ht * max_wd) 335 > (H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_WIDTH)) 336 337 { 338 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 339 << IVD_UNSUPPORTEDPARAM; 340 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 341 IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED; 342 return (IV_FAIL); 343 } 344 345 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location) 346 { 347 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 348 << IVD_UNSUPPORTEDPARAM; 349 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 350 IVD_NUM_REC_NOT_SUFFICIENT; 351 return (IV_FAIL); 352 } 353 354 /* check memrecords sizes are correct */ 355 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location; 356 for(i = 0; i < MEM_REC_CNT; i++) 357 { 358 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 359 { 360 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 361 << IVD_UNSUPPORTEDPARAM; 362 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 363 IVD_MEM_REC_STRUCT_SIZE_INCORRECT; 364 return IV_FAIL; 365 } 366 } 367 } 368 break; 369 370 case IV_CMD_INIT: 371 { 372 ih264d_init_ip_t *ps_ip = (ih264d_init_ip_t *)pv_api_ip; 373 ih264d_init_op_t *ps_op = (ih264d_init_op_t *)pv_api_op; 374 iv_mem_rec_t *ps_mem_rec; 375 WORD32 max_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd; 376 WORD32 max_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht; 377 378 max_wd = ALIGN16(max_wd); 379 max_ht = ALIGN32(max_ht); 380 381 ps_op->s_ivd_init_op_t.u4_error_code = 0; 382 383 if((ps_ip->s_ivd_init_ip_t.u4_size > sizeof(ih264d_init_ip_t)) 384 || (ps_ip->s_ivd_init_ip_t.u4_size 385 < sizeof(ivd_init_ip_t))) 386 { 387 ps_op->s_ivd_init_op_t.u4_error_code |= 1 388 << IVD_UNSUPPORTEDPARAM; 389 ps_op->s_ivd_init_op_t.u4_error_code |= 390 IVD_IP_API_STRUCT_SIZE_INCORRECT; 391 H264_DEC_DEBUG_PRINT("\n"); 392 return (IV_FAIL); 393 } 394 395 if((ps_op->s_ivd_init_op_t.u4_size != sizeof(ih264d_init_op_t)) 396 && (ps_op->s_ivd_init_op_t.u4_size 397 != sizeof(ivd_init_op_t))) 398 { 399 ps_op->s_ivd_init_op_t.u4_error_code |= 1 400 << IVD_UNSUPPORTEDPARAM; 401 ps_op->s_ivd_init_op_t.u4_error_code |= 402 IVD_OP_API_STRUCT_SIZE_INCORRECT; 403 H264_DEC_DEBUG_PRINT("\n"); 404 return (IV_FAIL); 405 } 406 407 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec != MEM_REC_CNT) 408 { 409 ps_op->s_ivd_init_op_t.u4_error_code |= 1 410 << IVD_UNSUPPORTEDPARAM; 411 ps_op->s_ivd_init_op_t.u4_error_code |= 412 IVD_INIT_DEC_NOT_SUFFICIENT; 413 H264_DEC_DEBUG_PRINT("\n"); 414 return (IV_FAIL); 415 } 416 417 if(max_wd < H264_MIN_FRAME_WIDTH) 418 { 419 ps_op->s_ivd_init_op_t.u4_error_code |= 1 420 << IVD_UNSUPPORTEDPARAM; 421 ps_op->s_ivd_init_op_t.u4_error_code |= 422 IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED; 423 H264_DEC_DEBUG_PRINT("\n"); 424 return (IV_FAIL); 425 } 426 427 if(max_wd > H264_MAX_FRAME_WIDTH) 428 { 429 ps_op->s_ivd_init_op_t.u4_error_code |= 1 430 << IVD_UNSUPPORTEDPARAM; 431 ps_op->s_ivd_init_op_t.u4_error_code |= 432 IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED; 433 H264_DEC_DEBUG_PRINT("\n"); 434 return (IV_FAIL); 435 } 436 437 if(max_ht < H264_MIN_FRAME_HEIGHT) 438 { 439 ps_op->s_ivd_init_op_t.u4_error_code |= 1 440 << IVD_UNSUPPORTEDPARAM; 441 ps_op->s_ivd_init_op_t.u4_error_code |= 442 IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED; 443 H264_DEC_DEBUG_PRINT("\n"); 444 return (IV_FAIL); 445 } 446 447 if((max_ht * max_wd) 448 > (H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_WIDTH)) 449 450 { 451 ps_op->s_ivd_init_op_t.u4_error_code |= 1 452 << IVD_UNSUPPORTEDPARAM; 453 ps_op->s_ivd_init_op_t.u4_error_code |= 454 IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED; 455 H264_DEC_DEBUG_PRINT("\n"); 456 return (IV_FAIL); 457 } 458 459 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location) 460 { 461 ps_op->s_ivd_init_op_t.u4_error_code |= 1 462 << IVD_UNSUPPORTEDPARAM; 463 ps_op->s_ivd_init_op_t.u4_error_code |= 464 IVD_NUM_REC_NOT_SUFFICIENT; 465 H264_DEC_DEBUG_PRINT("\n"); 466 return (IV_FAIL); 467 } 468 469 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) 470 && (ps_ip->s_ivd_init_ip_t.e_output_format 471 != IV_YUV_422ILE) 472 && (ps_ip->s_ivd_init_ip_t.e_output_format 473 != IV_RGB_565) 474 && (ps_ip->s_ivd_init_ip_t.e_output_format 475 != IV_YUV_420SP_UV) 476 && (ps_ip->s_ivd_init_ip_t.e_output_format 477 != IV_YUV_420SP_VU)) 478 { 479 ps_op->s_ivd_init_op_t.u4_error_code |= 1 480 << IVD_UNSUPPORTEDPARAM; 481 ps_op->s_ivd_init_op_t.u4_error_code |= 482 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED; 483 H264_DEC_DEBUG_PRINT("\n"); 484 return (IV_FAIL); 485 } 486 487 /* verify number of mem records */ 488 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < MEM_REC_CNT) 489 { 490 ps_op->s_ivd_init_op_t.u4_error_code |= 1 491 << IVD_UNSUPPORTEDPARAM; 492 ps_op->s_ivd_init_op_t.u4_error_code |= 493 IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT; 494 H264_DEC_DEBUG_PRINT("\n"); 495 return IV_FAIL; 496 } 497 498 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location; 499 /* check memrecords sizes are correct */ 500 for(i = 0; i < ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++) 501 { 502 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 503 { 504 ps_op->s_ivd_init_op_t.u4_error_code |= 1 505 << IVD_UNSUPPORTEDPARAM; 506 ps_op->s_ivd_init_op_t.u4_error_code |= 507 IVD_MEM_REC_STRUCT_SIZE_INCORRECT; 508 H264_DEC_DEBUG_PRINT("i: %d\n", i); 509 return IV_FAIL; 510 } 511 /* check memrecords pointers are not NULL */ 512 513 if(ps_mem_rec[i].pv_base == NULL) 514 { 515 516 ps_op->s_ivd_init_op_t.u4_error_code |= 1 517 << IVD_UNSUPPORTEDPARAM; 518 ps_op->s_ivd_init_op_t.u4_error_code |= 519 IVD_INIT_DEC_MEM_REC_BASE_NULL; 520 H264_DEC_DEBUG_PRINT("i: %d\n", i); 521 return IV_FAIL; 522 523 } 524 525 } 526 527 /* verify memtabs for overlapping regions */ 528 { 529 void *start[MEM_REC_CNT]; 530 void *end[MEM_REC_CNT]; 531 532 start[0] = (void *)(ps_mem_rec[0].pv_base); 533 end[0] = (void *)((UWORD8 *)ps_mem_rec[0].pv_base 534 + ps_mem_rec[0].u4_mem_size - 1); 535 for(i = 1; i < MEM_REC_CNT; i++) 536 { 537 /* This array is populated to check memtab overlapp */ 538 start[i] = (void *)(ps_mem_rec[i].pv_base); 539 end[i] = (void *)((UWORD8 *)ps_mem_rec[i].pv_base 540 + ps_mem_rec[i].u4_mem_size - 1); 541 542 for(j = 0; j < i; j++) 543 { 544 if((start[i] >= start[j]) && (start[i] <= end[j])) 545 { 546 ps_op->s_ivd_init_op_t.u4_error_code |= 1 547 << IVD_UNSUPPORTEDPARAM; 548 ps_op->s_ivd_init_op_t.u4_error_code |= 549 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR; 550 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j); 551 return IV_FAIL; 552 } 553 554 if((end[i] >= start[j]) && (end[i] <= end[j])) 555 { 556 ps_op->s_ivd_init_op_t.u4_error_code |= 1 557 << IVD_UNSUPPORTEDPARAM; 558 ps_op->s_ivd_init_op_t.u4_error_code |= 559 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR; 560 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j); 561 return IV_FAIL; 562 } 563 564 if((start[i] < start[j]) && (end[i] > end[j])) 565 { 566 ps_op->s_ivd_init_op_t.u4_error_code |= 1 567 << IVD_UNSUPPORTEDPARAM; 568 ps_op->s_ivd_init_op_t.u4_error_code |= 569 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR; 570 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j); 571 return IV_FAIL; 572 } 573 } 574 575 } 576 } 577 578 { 579 iv_mem_rec_t mem_rec_ittiam_api[MEM_REC_CNT]; 580 ih264d_fill_mem_rec_ip_t s_fill_mem_rec_ip; 581 ih264d_fill_mem_rec_op_t s_fill_mem_rec_op; 582 IV_API_CALL_STATUS_T e_status; 583 584 UWORD32 i; 585 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd = 586 IV_CMD_FILL_NUM_MEM_REC; 587 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location = 588 mem_rec_ittiam_api; 589 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd = 590 max_wd; 591 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht = 592 max_ht; 593 594 if(ps_ip->s_ivd_init_ip_t.u4_size 595 > offsetof(ih264d_init_ip_t, i4_level)) 596 { 597 s_fill_mem_rec_ip.i4_level = ps_ip->i4_level; 598 } 599 else 600 { 601 s_fill_mem_rec_ip.i4_level = H264_LEVEL_3_1; 602 } 603 604 if(ps_ip->s_ivd_init_ip_t.u4_size 605 > offsetof(ih264d_init_ip_t, u4_num_ref_frames)) 606 { 607 s_fill_mem_rec_ip.u4_num_ref_frames = 608 ps_ip->u4_num_ref_frames; 609 } 610 else 611 { 612 s_fill_mem_rec_ip.u4_num_ref_frames = 613 (H264_MAX_REF_PICS + 1); 614 } 615 616 if(ps_ip->s_ivd_init_ip_t.u4_size 617 > offsetof(ih264d_init_ip_t, 618 u4_num_reorder_frames)) 619 { 620 s_fill_mem_rec_ip.u4_num_reorder_frames = 621 ps_ip->u4_num_reorder_frames; 622 } 623 else 624 { 625 s_fill_mem_rec_ip.u4_num_reorder_frames = (H264_MAX_REF_PICS 626 + 1); 627 } 628 629 if(ps_ip->s_ivd_init_ip_t.u4_size 630 > offsetof(ih264d_init_ip_t, 631 u4_num_extra_disp_buf)) 632 { 633 s_fill_mem_rec_ip.u4_num_extra_disp_buf = 634 ps_ip->u4_num_extra_disp_buf; 635 } 636 else 637 { 638 s_fill_mem_rec_ip.u4_num_extra_disp_buf = 0; 639 } 640 641 if(ps_ip->s_ivd_init_ip_t.u4_size 642 > offsetof(ih264d_init_ip_t, u4_share_disp_buf)) 643 { 644#ifndef LOGO_EN 645 s_fill_mem_rec_ip.u4_share_disp_buf = 646 ps_ip->u4_share_disp_buf; 647#else 648 s_fill_mem_rec_ip.u4_share_disp_buf = 0; 649#endif 650 } 651 else 652 { 653 s_fill_mem_rec_ip.u4_share_disp_buf = 0; 654 } 655 656 s_fill_mem_rec_ip.e_output_format = 657 ps_ip->s_ivd_init_ip_t.e_output_format; 658 659 if((s_fill_mem_rec_ip.e_output_format != IV_YUV_420P) 660 && (s_fill_mem_rec_ip.e_output_format 661 != IV_YUV_420SP_UV) 662 && (s_fill_mem_rec_ip.e_output_format 663 != IV_YUV_420SP_VU)) 664 { 665 s_fill_mem_rec_ip.u4_share_disp_buf = 0; 666 } 667 668 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size = 669 sizeof(ih264d_fill_mem_rec_ip_t); 670 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size = 671 sizeof(ih264d_fill_mem_rec_op_t); 672 673 for(i = 0; i < MEM_REC_CNT; i++) 674 mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t); 675 676 e_status = ih264d_api_function(NULL, 677 (void *)&s_fill_mem_rec_ip, 678 (void *)&s_fill_mem_rec_op); 679 if(IV_FAIL == e_status) 680 { 681 ps_op->s_ivd_init_op_t.u4_error_code = 682 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code; 683 H264_DEC_DEBUG_PRINT("Fail\n"); 684 return (IV_FAIL); 685 } 686 687 for(i = 0; i < MEM_REC_CNT; i++) 688 { 689 if(ps_mem_rec[i].u4_mem_size 690 < mem_rec_ittiam_api[i].u4_mem_size) 691 { 692 ps_op->s_ivd_init_op_t.u4_error_code |= 1 693 << IVD_UNSUPPORTEDPARAM; 694 ps_op->s_ivd_init_op_t.u4_error_code |= 695 IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE; 696 H264_DEC_DEBUG_PRINT("i: %d \n", i); 697 return IV_FAIL; 698 } 699 if(ps_mem_rec[i].u4_mem_alignment 700 != mem_rec_ittiam_api[i].u4_mem_alignment) 701 { 702 ps_op->s_ivd_init_op_t.u4_error_code |= 1 703 << IVD_UNSUPPORTEDPARAM; 704 ps_op->s_ivd_init_op_t.u4_error_code |= 705 IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR; 706 H264_DEC_DEBUG_PRINT("i: %d \n", i); 707 return IV_FAIL; 708 } 709 if(ps_mem_rec[i].e_mem_type 710 != mem_rec_ittiam_api[i].e_mem_type) 711 { 712 UWORD32 check = IV_SUCCESS; 713 UWORD32 diff = mem_rec_ittiam_api[i].e_mem_type 714 - ps_mem_rec[i].e_mem_type; 715 716 if((ps_mem_rec[i].e_mem_type 717 <= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM) 718 && (mem_rec_ittiam_api[i].e_mem_type 719 >= IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM)) 720 { 721 check = IV_FAIL; 722 } 723 if(3 != MOD(mem_rec_ittiam_api[i].e_mem_type, 4)) 724 { 725 /* 726 * It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM 727 */ 728 if((diff < 1) || (diff > 3)) 729 { 730 // Difference between 1 and 3 is okay for all cases other than the two filtered 731 // with the MOD condition above 732 check = IV_FAIL; 733 } 734 } 735 else 736 { 737 if(diff == 1) 738 { 739 /* 740 * This particular case is when codec asked for External Persistent, but got 741 * Internal Scratch. 742 */ 743 check = IV_FAIL; 744 } 745 if((diff != 2) && (diff != 3)) 746 { 747 check = IV_FAIL; 748 } 749 } 750 if(check == IV_FAIL) 751 { 752 ps_op->s_ivd_init_op_t.u4_error_code |= 1 753 << IVD_UNSUPPORTEDPARAM; 754 ps_op->s_ivd_init_op_t.u4_error_code |= 755 IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE; 756 H264_DEC_DEBUG_PRINT("i: %d \n", i); 757 return IV_FAIL; 758 } 759 } 760 } 761 } 762 763 } 764 break; 765 766 case IVD_CMD_GET_DISPLAY_FRAME: 767 { 768 ih264d_get_display_frame_ip_t *ps_ip = 769 (ih264d_get_display_frame_ip_t *)pv_api_ip; 770 ih264d_get_display_frame_op_t *ps_op = 771 (ih264d_get_display_frame_op_t *)pv_api_op; 772 773 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0; 774 775 if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size 776 != sizeof(ih264d_get_display_frame_ip_t)) 777 && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size 778 != sizeof(ivd_get_display_frame_ip_t))) 779 { 780 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 781 << IVD_UNSUPPORTEDPARAM; 782 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 783 IVD_IP_API_STRUCT_SIZE_INCORRECT; 784 return (IV_FAIL); 785 } 786 787 if((ps_op->s_ivd_get_display_frame_op_t.u4_size 788 != sizeof(ih264d_get_display_frame_op_t)) 789 && (ps_op->s_ivd_get_display_frame_op_t.u4_size 790 != sizeof(ivd_get_display_frame_op_t))) 791 { 792 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 793 << IVD_UNSUPPORTEDPARAM; 794 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 795 IVD_OP_API_STRUCT_SIZE_INCORRECT; 796 return (IV_FAIL); 797 } 798 } 799 break; 800 801 case IVD_CMD_REL_DISPLAY_FRAME: 802 { 803 ih264d_rel_display_frame_ip_t *ps_ip = 804 (ih264d_rel_display_frame_ip_t *)pv_api_ip; 805 ih264d_rel_display_frame_op_t *ps_op = 806 (ih264d_rel_display_frame_op_t *)pv_api_op; 807 808 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0; 809 810 if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size 811 != sizeof(ih264d_rel_display_frame_ip_t)) 812 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size 813 != sizeof(ivd_rel_display_frame_ip_t))) 814 { 815 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 816 << IVD_UNSUPPORTEDPARAM; 817 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 818 IVD_IP_API_STRUCT_SIZE_INCORRECT; 819 return (IV_FAIL); 820 } 821 822 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size 823 != sizeof(ih264d_rel_display_frame_op_t)) 824 && (ps_op->s_ivd_rel_display_frame_op_t.u4_size 825 != sizeof(ivd_rel_display_frame_op_t))) 826 { 827 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 828 << IVD_UNSUPPORTEDPARAM; 829 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 830 IVD_OP_API_STRUCT_SIZE_INCORRECT; 831 return (IV_FAIL); 832 } 833 834 } 835 break; 836 837 case IVD_CMD_SET_DISPLAY_FRAME: 838 { 839 ih264d_set_display_frame_ip_t *ps_ip = 840 (ih264d_set_display_frame_ip_t *)pv_api_ip; 841 ih264d_set_display_frame_op_t *ps_op = 842 (ih264d_set_display_frame_op_t *)pv_api_op; 843 UWORD32 j; 844 845 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0; 846 847 if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size 848 != sizeof(ih264d_set_display_frame_ip_t)) 849 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size 850 != sizeof(ivd_set_display_frame_ip_t))) 851 { 852 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 853 << IVD_UNSUPPORTEDPARAM; 854 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 855 IVD_IP_API_STRUCT_SIZE_INCORRECT; 856 return (IV_FAIL); 857 } 858 859 if((ps_op->s_ivd_set_display_frame_op_t.u4_size 860 != sizeof(ih264d_set_display_frame_op_t)) 861 && (ps_op->s_ivd_set_display_frame_op_t.u4_size 862 != sizeof(ivd_set_display_frame_op_t))) 863 { 864 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 865 << IVD_UNSUPPORTEDPARAM; 866 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 867 IVD_OP_API_STRUCT_SIZE_INCORRECT; 868 return (IV_FAIL); 869 } 870 871 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0) 872 { 873 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 874 << IVD_UNSUPPORTEDPARAM; 875 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 876 IVD_DISP_FRM_ZERO_OP_BUFS; 877 return IV_FAIL; 878 } 879 880 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; 881 j++) 882 { 883 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs 884 == 0) 885 { 886 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 887 << IVD_UNSUPPORTEDPARAM; 888 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 889 IVD_DISP_FRM_ZERO_OP_BUFS; 890 return IV_FAIL; 891 } 892 893 for(i = 0; 894 i 895 < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs; 896 i++) 897 { 898 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] 899 == NULL) 900 { 901 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 902 << IVD_UNSUPPORTEDPARAM; 903 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 904 IVD_DISP_FRM_OP_BUF_NULL; 905 return IV_FAIL; 906 } 907 908 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] 909 == 0) 910 { 911 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 912 << IVD_UNSUPPORTEDPARAM; 913 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 914 IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 915 return IV_FAIL; 916 } 917 } 918 } 919 } 920 break; 921 922 case IVD_CMD_VIDEO_DECODE: 923 { 924 ih264d_video_decode_ip_t *ps_ip = 925 (ih264d_video_decode_ip_t *)pv_api_ip; 926 ih264d_video_decode_op_t *ps_op = 927 (ih264d_video_decode_op_t *)pv_api_op; 928 929 H264_DEC_DEBUG_PRINT("The input bytes is: %d", 930 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes); 931 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0; 932 933 if(ps_ip->s_ivd_video_decode_ip_t.u4_size 934 != sizeof(ih264d_video_decode_ip_t)&& 935 ps_ip->s_ivd_video_decode_ip_t.u4_size != offsetof(ivd_video_decode_ip_t, s_out_buffer)) 936 { 937 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 938 << IVD_UNSUPPORTEDPARAM; 939 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 940 IVD_IP_API_STRUCT_SIZE_INCORRECT; 941 return (IV_FAIL); 942 } 943 944 if(ps_op->s_ivd_video_decode_op_t.u4_size 945 != sizeof(ih264d_video_decode_op_t)&& 946 ps_op->s_ivd_video_decode_op_t.u4_size != offsetof(ivd_video_decode_op_t, u4_output_present)) 947 { 948 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 949 << IVD_UNSUPPORTEDPARAM; 950 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 951 IVD_OP_API_STRUCT_SIZE_INCORRECT; 952 return (IV_FAIL); 953 } 954 955 } 956 break; 957 958 case IV_CMD_RETRIEVE_MEMREC: 959 { 960 ih264d_retrieve_mem_rec_ip_t *ps_ip = 961 (ih264d_retrieve_mem_rec_ip_t *)pv_api_ip; 962 ih264d_retrieve_mem_rec_op_t *ps_op = 963 (ih264d_retrieve_mem_rec_op_t *)pv_api_op; 964 iv_mem_rec_t *ps_mem_rec; 965 966 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0; 967 968 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size 969 != sizeof(ih264d_retrieve_mem_rec_ip_t)) 970 { 971 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 972 << IVD_UNSUPPORTEDPARAM; 973 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 974 IVD_IP_API_STRUCT_SIZE_INCORRECT; 975 return (IV_FAIL); 976 } 977 978 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size 979 != sizeof(ih264d_retrieve_mem_rec_op_t)) 980 { 981 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 982 << IVD_UNSUPPORTEDPARAM; 983 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 984 IVD_OP_API_STRUCT_SIZE_INCORRECT; 985 return (IV_FAIL); 986 } 987 988 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location; 989 /* check memrecords sizes are correct */ 990 for(i = 0; i < MEM_REC_CNT; i++) 991 { 992 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 993 { 994 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 995 << IVD_UNSUPPORTEDPARAM; 996 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 997 IVD_MEM_REC_STRUCT_SIZE_INCORRECT; 998 return IV_FAIL; 999 } 1000 } 1001 } 1002 break; 1003 1004 case IVD_CMD_VIDEO_CTL: 1005 { 1006 UWORD32 *pu4_ptr_cmd; 1007 UWORD32 sub_command; 1008 1009 pu4_ptr_cmd = (UWORD32 *)pv_api_ip; 1010 pu4_ptr_cmd += 2; 1011 sub_command = *pu4_ptr_cmd; 1012 1013 switch(sub_command) 1014 { 1015 case IVD_CMD_CTL_SETPARAMS: 1016 { 1017 ih264d_ctl_set_config_ip_t *ps_ip; 1018 ih264d_ctl_set_config_op_t *ps_op; 1019 ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip; 1020 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op; 1021 1022 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size 1023 != sizeof(ih264d_ctl_set_config_ip_t)) 1024 { 1025 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 1026 << IVD_UNSUPPORTEDPARAM; 1027 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1028 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1029 return IV_FAIL; 1030 } 1031 } 1032 //no break; is needed here 1033 case IVD_CMD_CTL_SETDEFAULT: 1034 { 1035 ih264d_ctl_set_config_op_t *ps_op; 1036 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op; 1037 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size 1038 != sizeof(ih264d_ctl_set_config_op_t)) 1039 { 1040 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 1041 << IVD_UNSUPPORTEDPARAM; 1042 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1043 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1044 return IV_FAIL; 1045 } 1046 } 1047 break; 1048 1049 case IVD_CMD_CTL_GETPARAMS: 1050 { 1051 ih264d_ctl_getstatus_ip_t *ps_ip; 1052 ih264d_ctl_getstatus_op_t *ps_op; 1053 1054 ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip; 1055 ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op; 1056 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size 1057 != sizeof(ih264d_ctl_getstatus_ip_t)) 1058 { 1059 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 1060 << IVD_UNSUPPORTEDPARAM; 1061 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1062 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1063 return IV_FAIL; 1064 } 1065 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size 1066 != sizeof(ih264d_ctl_getstatus_op_t)) 1067 { 1068 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 1069 << IVD_UNSUPPORTEDPARAM; 1070 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1071 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1072 return IV_FAIL; 1073 } 1074 } 1075 break; 1076 1077 case IVD_CMD_CTL_GETBUFINFO: 1078 { 1079 ih264d_ctl_getbufinfo_ip_t *ps_ip; 1080 ih264d_ctl_getbufinfo_op_t *ps_op; 1081 ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip; 1082 ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op; 1083 1084 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size 1085 != sizeof(ih264d_ctl_getbufinfo_ip_t)) 1086 { 1087 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 1088 << IVD_UNSUPPORTEDPARAM; 1089 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1090 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1091 return IV_FAIL; 1092 } 1093 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size 1094 != sizeof(ih264d_ctl_getbufinfo_op_t)) 1095 { 1096 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 1097 << IVD_UNSUPPORTEDPARAM; 1098 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1099 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1100 return IV_FAIL; 1101 } 1102 } 1103 break; 1104 1105 case IVD_CMD_CTL_GETVERSION: 1106 { 1107 ih264d_ctl_getversioninfo_ip_t *ps_ip; 1108 ih264d_ctl_getversioninfo_op_t *ps_op; 1109 ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip; 1110 ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op; 1111 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size 1112 != sizeof(ih264d_ctl_getversioninfo_ip_t)) 1113 { 1114 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 1115 << IVD_UNSUPPORTEDPARAM; 1116 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1117 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1118 return IV_FAIL; 1119 } 1120 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size 1121 != sizeof(ih264d_ctl_getversioninfo_op_t)) 1122 { 1123 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 1124 << IVD_UNSUPPORTEDPARAM; 1125 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1126 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1127 return IV_FAIL; 1128 } 1129 } 1130 break; 1131 1132 case IVD_CMD_CTL_FLUSH: 1133 { 1134 ih264d_ctl_flush_ip_t *ps_ip; 1135 ih264d_ctl_flush_op_t *ps_op; 1136 ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip; 1137 ps_op = (ih264d_ctl_flush_op_t *)pv_api_op; 1138 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size 1139 != sizeof(ih264d_ctl_flush_ip_t)) 1140 { 1141 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 1142 << IVD_UNSUPPORTEDPARAM; 1143 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1144 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1145 return IV_FAIL; 1146 } 1147 if(ps_op->s_ivd_ctl_flush_op_t.u4_size 1148 != sizeof(ih264d_ctl_flush_op_t)) 1149 { 1150 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 1151 << IVD_UNSUPPORTEDPARAM; 1152 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1153 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1154 return IV_FAIL; 1155 } 1156 } 1157 break; 1158 1159 case IVD_CMD_CTL_RESET: 1160 { 1161 ih264d_ctl_reset_ip_t *ps_ip; 1162 ih264d_ctl_reset_op_t *ps_op; 1163 ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip; 1164 ps_op = (ih264d_ctl_reset_op_t *)pv_api_op; 1165 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size 1166 != sizeof(ih264d_ctl_reset_ip_t)) 1167 { 1168 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 1169 << IVD_UNSUPPORTEDPARAM; 1170 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1171 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1172 return IV_FAIL; 1173 } 1174 if(ps_op->s_ivd_ctl_reset_op_t.u4_size 1175 != sizeof(ih264d_ctl_reset_op_t)) 1176 { 1177 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 1178 << IVD_UNSUPPORTEDPARAM; 1179 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1180 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1181 return IV_FAIL; 1182 } 1183 } 1184 break; 1185 1186 case IH264D_CMD_CTL_DEGRADE: 1187 { 1188 ih264d_ctl_degrade_ip_t *ps_ip; 1189 ih264d_ctl_degrade_op_t *ps_op; 1190 1191 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip; 1192 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op; 1193 1194 if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t)) 1195 { 1196 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1197 ps_op->u4_error_code |= 1198 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1199 return IV_FAIL; 1200 } 1201 1202 if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t)) 1203 { 1204 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1205 ps_op->u4_error_code |= 1206 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1207 return IV_FAIL; 1208 } 1209 1210 if((ps_ip->i4_degrade_pics < 0) 1211 || (ps_ip->i4_degrade_pics > 4) 1212 || (ps_ip->i4_nondegrade_interval < 0) 1213 || (ps_ip->i4_degrade_type < 0) 1214 || (ps_ip->i4_degrade_type > 15)) 1215 { 1216 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1217 return IV_FAIL; 1218 } 1219 1220 break; 1221 } 1222 1223 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS: 1224 { 1225 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip; 1226 ih264d_ctl_get_frame_dimensions_op_t *ps_op; 1227 1228 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 1229 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op; 1230 1231 if(ps_ip->u4_size 1232 != sizeof(ih264d_ctl_get_frame_dimensions_ip_t)) 1233 { 1234 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1235 ps_op->u4_error_code |= 1236 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1237 return IV_FAIL; 1238 } 1239 1240 if(ps_op->u4_size 1241 != sizeof(ih264d_ctl_get_frame_dimensions_op_t)) 1242 { 1243 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1244 ps_op->u4_error_code |= 1245 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1246 return IV_FAIL; 1247 } 1248 1249 break; 1250 } 1251 1252 case IH264D_CMD_CTL_SET_NUM_CORES: 1253 { 1254 ih264d_ctl_set_num_cores_ip_t *ps_ip; 1255 ih264d_ctl_set_num_cores_op_t *ps_op; 1256 1257 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip; 1258 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op; 1259 1260 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t)) 1261 { 1262 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1263 ps_op->u4_error_code |= 1264 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1265 return IV_FAIL; 1266 } 1267 1268 if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t)) 1269 { 1270 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1271 ps_op->u4_error_code |= 1272 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1273 return IV_FAIL; 1274 } 1275 1276 if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2) 1277 && (ps_ip->u4_num_cores != 3) 1278 && (ps_ip->u4_num_cores != 4)) 1279 { 1280 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1281 return IV_FAIL; 1282 } 1283 break; 1284 } 1285 case IH264D_CMD_CTL_SET_PROCESSOR: 1286 { 1287 ih264d_ctl_set_processor_ip_t *ps_ip; 1288 ih264d_ctl_set_processor_op_t *ps_op; 1289 1290 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip; 1291 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op; 1292 1293 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t)) 1294 { 1295 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1296 ps_op->u4_error_code |= 1297 IVD_IP_API_STRUCT_SIZE_INCORRECT; 1298 return IV_FAIL; 1299 } 1300 1301 if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t)) 1302 { 1303 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1304 ps_op->u4_error_code |= 1305 IVD_OP_API_STRUCT_SIZE_INCORRECT; 1306 return IV_FAIL; 1307 } 1308 1309 break; 1310 } 1311 default: 1312 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 1313 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD; 1314 return IV_FAIL; 1315 break; 1316 } 1317 } 1318 break; 1319 } 1320 1321 return IV_SUCCESS; 1322} 1323 1324 1325/** 1326 ******************************************************************************* 1327 * 1328 * @brief 1329 * Sets Processor type 1330 * 1331 * @par Description: 1332 * Sets Processor type 1333 * 1334 * @param[in] ps_codec_obj 1335 * Pointer to codec object at API level 1336 * 1337 * @param[in] pv_api_ip 1338 * Pointer to input argument structure 1339 * 1340 * @param[out] pv_api_op 1341 * Pointer to output argument structure 1342 * 1343 * @returns Status 1344 * 1345 * @remarks 1346 * 1347 * 1348 ******************************************************************************* 1349 */ 1350 1351WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 1352{ 1353 ih264d_ctl_set_processor_ip_t *ps_ip; 1354 ih264d_ctl_set_processor_op_t *ps_op; 1355 dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle; 1356 1357 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip; 1358 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op; 1359 1360 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch; 1361 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc; 1362 1363 ih264d_init_function_ptr(ps_codec); 1364 1365 ps_op->u4_error_code = 0; 1366 return IV_SUCCESS; 1367} 1368/*****************************************************************************/ 1369/* */ 1370/* Function Name : ih264d_get_num_rec */ 1371/* */ 1372/* Description : returns number of mem records required */ 1373/* */ 1374/* Inputs : pv_api_ip input api structure */ 1375/* : pv_api_op output api structure */ 1376/* Outputs : */ 1377/* Outputs : */ 1378/* Returns : void */ 1379/* */ 1380/* Issues : none */ 1381/* */ 1382/* Revision History: */ 1383/* */ 1384/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1385/* 22 10 2008 100356 Draft */ 1386/* */ 1387/*****************************************************************************/ 1388WORD32 ih264d_get_num_rec(void *pv_api_ip, void *pv_api_op) 1389{ 1390 iv_num_mem_rec_ip_t *ps_mem_q_ip; 1391 iv_num_mem_rec_op_t *ps_mem_q_op; 1392 ps_mem_q_ip = (iv_num_mem_rec_ip_t *)pv_api_ip; 1393 ps_mem_q_op = (iv_num_mem_rec_op_t *)pv_api_op; 1394 UNUSED(ps_mem_q_ip); 1395 ps_mem_q_op->u4_num_mem_rec = MEM_REC_CNT; 1396 1397 return IV_SUCCESS; 1398 1399} 1400 1401 1402/************************************************************************** 1403 * \if Function name : ih264d_init_decoder \endif 1404 * 1405 * 1406 * \brief 1407 * Initializes the decoder 1408 * 1409 * \param apiVersion : Version of the api being used. 1410 * \param errorHandlingMechanism : Mechanism to be used for errror handling. 1411 * \param postFilteringType: Type of post filtering operation to be used. 1412 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0]. 1413 * \param uc_dispBufs: Number of Display Buffers. 1414 * \param p_NALBufAPI: Pointer to NAL Buffer API. 1415 * \param p_DispBufAPI: Pointer to Display Buffer API. 1416 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder 1417 * for memory allocation and freeing. 1418 * 1419 * \return 1420 * 0 on Success and -1 on error 1421 * 1422 ************************************************************************** 1423 */ 1424void ih264d_init_decoder(void * ps_dec_params) 1425{ 1426 dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params; 1427 dec_slice_params_t *ps_cur_slice; 1428 pocstruct_t *ps_prev_poc, *ps_cur_poc; 1429 WORD32 size; 1430 1431 size = sizeof(dec_err_status_t); 1432 memset(ps_dec->ps_dec_err_status, 0, size); 1433 1434 size = sizeof(sei); 1435 memset(ps_dec->ps_sei, 0, size); 1436 1437 size = sizeof(dpb_commands_t); 1438 memset(ps_dec->ps_dpb_cmds, 0, size); 1439 1440 size = sizeof(dec_bit_stream_t); 1441 memset(ps_dec->ps_bitstrm, 0, size); 1442 1443 size = sizeof(dec_slice_params_t); 1444 memset(ps_dec->ps_cur_slice, 0, size); 1445 1446 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t)); 1447 memset(ps_dec->pv_scratch_sps_pps, 0, size); 1448 1449 1450 1451 /* Set pic_parameter_set_id to -1 */ 1452 1453 1454 1455 ps_cur_slice = ps_dec->ps_cur_slice; 1456 ps_dec->init_done = 0; 1457 1458 ps_dec->u4_num_cores = 1; 1459 1460 ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0; 1461 1462 ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE; 1463 ps_dec->u4_app_disable_deblk_frm = 0; 1464 ps_dec->i4_degrade_type = 0; 1465 ps_dec->i4_degrade_pics = 0; 1466 1467 ps_dec->i4_app_skip_mode = IVD_SKIP_NONE; 1468 ps_dec->i4_dec_skip_mode = IVD_SKIP_NONE; 1469 1470 memset(ps_dec->ps_pps, 0, 1471 ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS)); 1472 memset(ps_dec->ps_sps, 0, 1473 ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS)); 1474 1475 /* Initialization of function pointers ih264d_deblock_picture function*/ 1476 1477 ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff; 1478 ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff; 1479 1480 ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec; 1481 1482 ps_dec->u4_num_fld_in_frm = 0; 1483 1484 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec; 1485 1486 /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/ 1487 ps_dec->ps_sei->u1_is_valid = 0; 1488 1489 /* decParams Initializations */ 1490 ps_dec->ps_cur_pps = NULL; 1491 ps_dec->ps_cur_sps = NULL; 1492 ps_dec->u1_init_dec_flag = 0; 1493 ps_dec->u1_first_slice_in_stream = 1; 1494 ps_dec->u1_first_pb_nal_in_pic = 1; 1495 ps_dec->u1_last_pic_not_decoded = 0; 1496 ps_dec->u4_app_disp_width = 0; 1497 ps_dec->i4_header_decoded = 0; 1498 ps_dec->u4_total_frames_decoded = 0; 1499 1500 ps_dec->i4_error_code = 0; 1501 ps_dec->i4_content_type = -1; 1502 ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0; 1503 1504 ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS; 1505 ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN; 1506 ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT; 1507 ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME; 1508 ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN; 1509 1510 ps_dec->u1_pr_sl_type = 0xFF; 1511 ps_dec->u2_mbx = 0xffff; 1512 ps_dec->u2_mby = 0; 1513 ps_dec->u2_total_mbs_coded = 0; 1514 1515 /* POC initializations */ 1516 ps_prev_poc = &ps_dec->s_prev_pic_poc; 1517 ps_cur_poc = &ps_dec->s_cur_pic_poc; 1518 ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0; 1519 ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0; 1520 ps_prev_poc->i4_delta_pic_order_cnt_bottom = 1521 ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0; 1522 ps_prev_poc->i4_delta_pic_order_cnt[0] = 1523 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0; 1524 ps_prev_poc->i4_delta_pic_order_cnt[1] = 1525 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0; 1526 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0; 1527 ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count = 1528 0; 1529 ps_prev_poc->i4_bottom_field_order_count = 1530 ps_cur_poc->i4_bottom_field_order_count = 0; 1531 ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0; 1532 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0; 1533 ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0; 1534 ps_cur_slice->u1_mmco_equalto5 = 0; 1535 ps_cur_slice->u2_frame_num = 0; 1536 1537 ps_dec->i4_max_poc = 0; 1538 ps_dec->i4_prev_max_display_seq = 0; 1539 ps_dec->u1_recon_mb_grp = 4; 1540 1541 /* Field PIC initializations */ 1542 ps_dec->u1_second_field = 0; 1543 ps_dec->s_prev_seq_params.u1_eoseq_pending = 0; 1544 1545 /* Set the cropping parameters as zero */ 1546 ps_dec->u2_crop_offset_y = 0; 1547 ps_dec->u2_crop_offset_uv = 0; 1548 1549 /* The Initial Frame Rate Info is not Present */ 1550 ps_dec->i4_vui_frame_rate = -1; 1551 ps_dec->i4_pic_type = -1; 1552 ps_dec->i4_frametype = -1; 1553 ps_dec->i4_content_type = -1; 1554 1555 ps_dec->u1_res_changed = 0; 1556 1557 1558 ps_dec->u1_frame_decoded_flag = 0; 1559 1560 /* Set the default frame seek mask mode */ 1561 ps_dec->u4_skip_frm_mask = SKIP_NONE; 1562 1563 /********************************************************/ 1564 /* Initialize CAVLC residual decoding function pointers */ 1565 /********************************************************/ 1566 ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1; 1567 ps_dec->pf_cavlc_4x4res_block[1] = 1568 ih264d_cavlc_4x4res_block_totalcoeff_2to10; 1569 ps_dec->pf_cavlc_4x4res_block[2] = 1570 ih264d_cavlc_4x4res_block_totalcoeff_11to16; 1571 1572 ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7; 1573 ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8; 1574 1575 ps_dec->pf_cavlc_parse_8x8block[0] = 1576 ih264d_cavlc_parse_8x8block_none_available; 1577 ps_dec->pf_cavlc_parse_8x8block[1] = 1578 ih264d_cavlc_parse_8x8block_left_available; 1579 ps_dec->pf_cavlc_parse_8x8block[2] = 1580 ih264d_cavlc_parse_8x8block_top_available; 1581 ps_dec->pf_cavlc_parse_8x8block[3] = 1582 ih264d_cavlc_parse_8x8block_both_available; 1583 1584 /***************************************************************************/ 1585 /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */ 1586 /***************************************************************************/ 1587 ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice; 1588 ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice; 1589 1590 ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice; 1591 ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice; 1592 1593 ps_dec->pf_fill_bs_xtra_left_edge[0] = 1594 ih264d_fill_bs_xtra_left_edge_cur_frm; 1595 ps_dec->pf_fill_bs_xtra_left_edge[1] = 1596 ih264d_fill_bs_xtra_left_edge_cur_fld; 1597 1598 /* Initialize Reference Pic Buffers */ 1599 ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr); 1600 1601#if VERT_SCALE_UP_AND_422 1602 ps_dec->u1_vert_up_scale_flag = 1; 1603#else 1604 ps_dec->u1_vert_up_scale_flag = 0; 1605#endif 1606 1607 ps_dec->u2_prv_frame_num = 0; 1608 ps_dec->u1_top_bottom_decoded = 0; 1609 ps_dec->u1_dangling_field = 0; 1610 1611 ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table; 1612 1613 ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0]; 1614 ps_dec->pi1_left_ref_idx_ctxt_inc = 1615 &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0]; 1616 ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb; 1617 1618 /* ! */ 1619 /* Initializing flush frame u4_flag */ 1620 ps_dec->u1_flushfrm = 0; 1621 1622 { 1623 ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec; 1624 ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec; 1625 ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec; 1626 ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec; 1627 } 1628 1629 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t)); 1630 memset(ps_dec->u4_disp_buf_mapping, 0, 1631 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1632 memset(ps_dec->u4_disp_buf_to_be_freed, 0, 1633 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1634 memset(ps_dec->ps_cur_slice, 0, sizeof(dec_slice_params_t)); 1635 1636 ih264d_init_arch(ps_dec); 1637 ih264d_init_function_ptr(ps_dec); 1638 1639 ps_dec->init_done = 1; 1640 ps_dec->process_called = 1; 1641 1642 ps_dec->pv_pic_buf_mgr = NULL; 1643 ps_dec->pv_mv_buf_mgr = NULL; 1644} 1645 1646/************************************************************************** 1647 * \if Function name : ih264d_init_video_decoder \endif 1648 * 1649 * \brief 1650 * Wrapper for the decoder init 1651 * 1652 * \param p_NALBufAPI: Pointer to NAL Buffer API. 1653 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder 1654 * for memory allocation and freeing. 1655 * 1656 * \return 1657 * pointer to the decparams 1658 * 1659 ************************************************************************** 1660 */ 1661 1662WORD32 ih264d_init_video_decoder(iv_obj_t *dec_hdl, 1663 ih264d_init_ip_t *ps_init_ip, 1664 ih264d_init_op_t *ps_init_op) 1665{ 1666 dec_struct_t * ps_dec; 1667 iv_mem_rec_t *memtab; 1668 UWORD8 *pu1_extra_mem_base,*pu1_mem_base; 1669 1670 memtab = ps_init_ip->s_ivd_init_ip_t.pv_mem_rec_location; 1671 1672 dec_hdl->pv_codec_handle = memtab[MEM_REC_CODEC].pv_base; 1673 ps_dec = dec_hdl->pv_codec_handle; 1674 1675 memset(ps_dec, 0, sizeof(dec_struct_t)); 1676 1677 if(ps_init_ip->s_ivd_init_ip_t.u4_size 1678 > offsetof(ih264d_init_ip_t, i4_level)) 1679 { 1680 ps_dec->u4_level_at_init = ps_init_ip->i4_level; 1681 } 1682 else 1683 { 1684 ps_dec->u4_level_at_init = H264_LEVEL_3_1; 1685 } 1686 1687 if(ps_init_ip->s_ivd_init_ip_t.u4_size 1688 > offsetof(ih264d_init_ip_t, u4_num_ref_frames)) 1689 { 1690 ps_dec->u4_num_ref_frames_at_init = ps_init_ip->u4_num_ref_frames; 1691 } 1692 else 1693 { 1694 ps_dec->u4_num_ref_frames_at_init = H264_MAX_REF_PICS; 1695 } 1696 1697 if(ps_init_ip->s_ivd_init_ip_t.u4_size 1698 > offsetof(ih264d_init_ip_t, u4_num_reorder_frames)) 1699 { 1700 ps_dec->u4_num_reorder_frames_at_init = 1701 ps_init_ip->u4_num_reorder_frames; 1702 } 1703 else 1704 { 1705 ps_dec->u4_num_reorder_frames_at_init = H264_MAX_REF_PICS; 1706 } 1707 1708 if(ps_init_ip->s_ivd_init_ip_t.u4_size 1709 > offsetof(ih264d_init_ip_t, u4_num_extra_disp_buf)) 1710 { 1711 ps_dec->u4_num_extra_disp_bufs_at_init = 1712 ps_init_ip->u4_num_extra_disp_buf; 1713 } 1714 else 1715 { 1716 ps_dec->u4_num_extra_disp_bufs_at_init = 0; 1717 } 1718 1719 if(ps_init_ip->s_ivd_init_ip_t.u4_size 1720 > offsetof(ih264d_init_ip_t, u4_share_disp_buf)) 1721 { 1722#ifndef LOGO_EN 1723 ps_dec->u4_share_disp_buf = ps_init_ip->u4_share_disp_buf; 1724#else 1725 ps_dec->u4_share_disp_buf = 0; 1726#endif 1727 } 1728 else 1729 { 1730 ps_dec->u4_share_disp_buf = 0; 1731 } 1732 1733 if((ps_init_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) 1734 && (ps_init_ip->s_ivd_init_ip_t.e_output_format 1735 != IV_YUV_420SP_UV) 1736 && (ps_init_ip->s_ivd_init_ip_t.e_output_format 1737 != IV_YUV_420SP_VU)) 1738 { 1739 ps_dec->u4_share_disp_buf = 0; 1740 } 1741 1742 if((ps_dec->u4_level_at_init < MIN_LEVEL_SUPPORTED) 1743 || (ps_dec->u4_level_at_init > MAX_LEVEL_SUPPORTED)) 1744 { 1745 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_LEVEL_UNSUPPORTED; 1746 return (IV_FAIL); 1747 } 1748 1749 if(ps_dec->u4_num_ref_frames_at_init > H264_MAX_REF_PICS) 1750 { 1751 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF; 1752 ps_dec->u4_num_ref_frames_at_init = H264_MAX_REF_PICS; 1753 } 1754 1755 if(ps_dec->u4_num_reorder_frames_at_init > H264_MAX_REF_PICS) 1756 { 1757 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF; 1758 ps_dec->u4_num_reorder_frames_at_init = H264_MAX_REF_PICS; 1759 } 1760 1761 if(ps_dec->u4_num_extra_disp_bufs_at_init > H264_MAX_REF_PICS) 1762 { 1763 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF; 1764 ps_dec->u4_num_extra_disp_bufs_at_init = 0; 1765 } 1766 1767 if(0 == ps_dec->u4_share_disp_buf) 1768 ps_dec->u4_num_extra_disp_bufs_at_init = 0; 1769 1770 ps_dec->u4_num_disp_bufs_requested = 1; 1771 1772 ps_dec->u4_width_at_init = ps_init_ip->s_ivd_init_ip_t.u4_frm_max_wd; 1773 ps_dec->u4_height_at_init = ps_init_ip->s_ivd_init_ip_t.u4_frm_max_ht; 1774 1775 ps_dec->u4_width_at_init = ALIGN16(ps_dec->u4_width_at_init); 1776 ps_dec->u4_height_at_init = ALIGN32(ps_dec->u4_height_at_init); 1777 1778 ps_dec->pv_dec_thread_handle = memtab[MEM_REC_THREAD_HANDLE].pv_base; 1779 1780 pu1_mem_base = memtab[MEM_REC_THREAD_HANDLE].pv_base; 1781 ps_dec->pv_bs_deblk_thread_handle = pu1_mem_base 1782 + ithread_get_handle_size(); 1783 1784 ps_dec->u4_extra_mem_used = 0; 1785 1786 pu1_extra_mem_base = memtab[MEM_REC_EXTRA_MEM].pv_base; 1787 1788 ps_dec->ps_dec_err_status = (dec_err_status_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1789 ps_dec->u4_extra_mem_used += (((sizeof(dec_err_status_t) + 127) >> 7) << 7); 1790 1791 ps_dec->ps_mem_tab = memtab[MEM_REC_BACKUP].pv_base; 1792 1793 memcpy(ps_dec->ps_mem_tab, memtab, sizeof(iv_mem_rec_t) * MEM_REC_CNT); 1794 1795 ps_dec->ps_pps = memtab[MEM_REC_PPS].pv_base; 1796 1797 ps_dec->ps_sps = memtab[MEM_REC_SPS].pv_base; 1798 1799 ps_dec->ps_sei = (sei *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1800 ps_dec->u4_extra_mem_used += sizeof(sei); 1801 1802 ps_dec->ps_dpb_mgr = memtab[MEM_REC_DPB_MGR].pv_base; 1803 1804 ps_dec->ps_dpb_cmds = (dpb_commands_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1805 ps_dec->u4_extra_mem_used += sizeof(dpb_commands_t); 1806 1807 ps_dec->ps_bitstrm = (dec_bit_stream_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1808 ps_dec->u4_extra_mem_used += sizeof(dec_bit_stream_t); 1809 1810 ps_dec->ps_cur_slice =(dec_slice_params_t *) (pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1811 ps_dec->u4_extra_mem_used += sizeof(dec_slice_params_t); 1812 1813 ps_dec->pv_scratch_sps_pps = (void *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used); 1814 1815 1816 ps_dec->u4_extra_mem_used += MAX(sizeof(dec_seq_params_t), 1817 sizeof(dec_pic_params_t)); 1818 ps_dec->ps_pred_pkd = memtab[MEM_REC_PRED_INFO_PKD].pv_base; 1819 1820 1821 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec; 1822 1823 ps_dec->pv_dec_out = (void *)ps_init_op; 1824 ps_dec->pv_dec_in = (void *)ps_init_ip; 1825 1826 ps_dec->u1_chroma_format = 1827 (UWORD8)(ps_init_ip->s_ivd_init_ip_t.e_output_format); 1828 1829 1830 1831 ih264d_init_decoder(ps_dec); 1832 1833 return (IV_SUCCESS); 1834 1835} 1836 1837 1838/*****************************************************************************/ 1839/* */ 1840/* Function Name : ih264d_fill_num_mem_rec */ 1841/* */ 1842/* Description : fills memory records */ 1843/* */ 1844/* Inputs : pv_api_ip input api structure */ 1845/* : pv_api_op output api structure */ 1846/* Outputs : */ 1847/* Returns : void */ 1848/* */ 1849/* Issues : none */ 1850/* */ 1851/* Revision History: */ 1852/* */ 1853/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1854/* 22 10 2008 100356 Draft */ 1855/* */ 1856/*****************************************************************************/ 1857WORD32 ih264d_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op) 1858{ 1859 1860 ih264d_fill_mem_rec_ip_t *ps_mem_q_ip; 1861 ih264d_fill_mem_rec_op_t *ps_mem_q_op; 1862 WORD32 level; 1863 UWORD32 num_reorder_frames; 1864 UWORD32 num_ref_frames; 1865 UWORD32 num_extra_disp_bufs; 1866 UWORD32 u4_dpb_size_num_frames; 1867 iv_mem_rec_t *memTab; 1868 1869 UWORD32 chroma_format, u4_share_disp_buf; 1870 UWORD32 u4_total_num_mbs; 1871 UWORD32 luma_width, luma_width_in_mbs; 1872 UWORD32 luma_height, luma_height_in_mbs; 1873 UWORD32 max_dpb_size; 1874 1875 ps_mem_q_ip = (ih264d_fill_mem_rec_ip_t *)pv_api_ip; 1876 ps_mem_q_op = (ih264d_fill_mem_rec_op_t *)pv_api_op; 1877 1878 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1879 > offsetof(ih264d_fill_mem_rec_ip_t, i4_level)) 1880 { 1881 level = ps_mem_q_ip->i4_level; 1882 } 1883 else 1884 { 1885 level = H264_LEVEL_3_1; 1886 } 1887 1888 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1889 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_reorder_frames)) 1890 { 1891 num_reorder_frames = ps_mem_q_ip->u4_num_reorder_frames; 1892 } 1893 else 1894 { 1895 num_reorder_frames = H264_MAX_REF_PICS; 1896 } 1897 1898 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1899 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_ref_frames)) 1900 { 1901 num_ref_frames = ps_mem_q_ip->u4_num_ref_frames; 1902 } 1903 else 1904 { 1905 num_ref_frames = H264_MAX_REF_PICS; 1906 } 1907 1908 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1909 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_extra_disp_buf)) 1910 { 1911 num_extra_disp_bufs = ps_mem_q_ip->u4_num_extra_disp_buf; 1912 } 1913 else 1914 { 1915 num_extra_disp_bufs = 0; 1916 } 1917 1918 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1919 > offsetof(ih264d_fill_mem_rec_ip_t, u4_share_disp_buf)) 1920 { 1921#ifndef LOGO_EN 1922 u4_share_disp_buf = ps_mem_q_ip->u4_share_disp_buf; 1923#else 1924 u4_share_disp_buf = 0; 1925#endif 1926 } 1927 else 1928 { 1929 u4_share_disp_buf = 0; 1930 } 1931 1932 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size 1933 > offsetof(ih264d_fill_mem_rec_ip_t, e_output_format)) 1934 { 1935 chroma_format = ps_mem_q_ip->e_output_format; 1936 } 1937 else 1938 { 1939 chroma_format = -1; 1940 } 1941 1942 if((chroma_format != IV_YUV_420P) && (chroma_format != IV_YUV_420SP_UV) 1943 && (chroma_format != IV_YUV_420SP_VU)) 1944 { 1945 u4_share_disp_buf = 0; 1946 } 1947 if(0 == u4_share_disp_buf) 1948 num_extra_disp_bufs = 0; 1949 1950 { 1951 1952 luma_height = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht; 1953 luma_width = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd; 1954 1955 luma_height = ALIGN32(luma_height); 1956 luma_width = ALIGN16(luma_width); 1957 luma_width_in_mbs = luma_width >> 4; 1958 luma_height_in_mbs = luma_height >> 4; 1959 u4_total_num_mbs = (luma_height * luma_width) >> 8; 1960 } 1961 /* 1962 * If level is lesser than 31 and the resolution required is higher, 1963 * then make the level at least 31. 1964 */ 1965 if(u4_total_num_mbs > MAX_MBS_LEVEL_30 && level < H264_LEVEL_3_1) 1966 { 1967 level = H264_LEVEL_3_1; 1968 } 1969 1970 if((level < MIN_LEVEL_SUPPORTED) || (level > MAX_LEVEL_SUPPORTED)) 1971 { 1972 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1973 ERROR_LEVEL_UNSUPPORTED; 1974 return (IV_FAIL); 1975 } 1976 1977 if(num_ref_frames > H264_MAX_REF_PICS) 1978 { 1979 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= ERROR_NUM_REF; 1980 num_ref_frames = H264_MAX_REF_PICS; 1981 } 1982 1983 if(num_reorder_frames > H264_MAX_REF_PICS) 1984 { 1985 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= ERROR_NUM_REF; 1986 num_reorder_frames = H264_MAX_REF_PICS; 1987 } 1988 memTab = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location; 1989 1990 memTab[MEM_REC_IV_OBJ].u4_mem_size = sizeof(iv_obj_t); 1991 memTab[MEM_REC_IV_OBJ].u4_mem_alignment = (128 * 8) / CHAR_BIT; 1992 memTab[MEM_REC_IV_OBJ].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 1993 H264_DEC_DEBUG_PRINT("MEM_REC_IV_OBJ MEM Size = %d\n", 1994 memTab[MEM_REC_IV_OBJ].u4_mem_size); 1995 1996 memTab[MEM_REC_CODEC].u4_mem_alignment = (128 * 8) / CHAR_BIT; 1997 memTab[MEM_REC_CODEC].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 1998 memTab[MEM_REC_CODEC].u4_mem_size = sizeof(dec_struct_t); 1999 2000 { 2001 UWORD32 mvinfo_size, mv_info_size_pad; 2002 UWORD32 MVbank, MVbank_pad; 2003 UWORD32 Ysize; 2004 UWORD32 UVsize; 2005 UWORD32 one_frm_size; 2006 2007 UWORD32 extra_mem = 0; 2008 2009 UWORD32 pad_len_h, pad_len_v; 2010 2011 /* 2012 * For low_delay, use num_buf as 2 - 2013 * num_buf = (num_buf_ref) + 1; 2014 * where num_buf_ref is 1. 2015 */ 2016 UWORD32 num_buf; 2017 2018 { 2019 UWORD32 num_bufs_app, num_bufs_level; 2020 2021 num_bufs_app = num_ref_frames + num_reorder_frames + 1; 2022 2023 if(num_bufs_app <= 1) 2024 num_bufs_app = 2; 2025 2026 num_bufs_level = ih264d_get_dpb_size_new(level, (luma_width >> 4), 2027 (luma_height >> 4)); 2028 2029 max_dpb_size = num_bufs_level; 2030 2031 num_bufs_level = num_bufs_level * 2 + 1; 2032 2033 num_buf = MIN(num_bufs_level, num_bufs_app); 2034 2035 num_buf += num_extra_disp_bufs; 2036 2037 } 2038 2039 mvinfo_size = ((luma_width * (luma_height)) >> 4); 2040 2041 mv_info_size_pad = ((luma_width * (PAD_MV_BANK_ROW)) >> 4); 2042 2043 Ysize = ALIGN32((luma_width + (PAD_LEN_Y_H << 1))) 2044 * (luma_height + (PAD_LEN_Y_V << 2)); 2045 2046 2047 UVsize = Ysize >> 2; 2048 if(u4_share_disp_buf == 1) 2049 { 2050 /* In case of buffers getting shared between application and library 2051 there is no need of reference memtabs. Instead of setting the i4_size 2052 to zero, it is reduced to a small i4_size to ensure that changes 2053 in the code are minimal */ 2054 2055 if((chroma_format == IV_YUV_420P) 2056 || (chroma_format == IV_YUV_420SP_UV) 2057 || (chroma_format == IV_YUV_420SP_VU)) 2058 { 2059 Ysize = 64; 2060 } 2061 if(chroma_format == IV_YUV_420SP_UV) 2062 { 2063 UVsize = 64; 2064 } 2065 } 2066 2067 one_frm_size = (((Ysize + 127) >> 7) << 7) 2068 + ((((UVsize << 1) + 127) >> 7) << 7); 2069 2070 //Note that for ARM RVDS WS the sizeof(mv_pred_t) is 16 2071 2072 /*Add memory for colocated MB*/ 2073 MVbank = sizeof(mv_pred_t) * mvinfo_size; 2074 MVbank_pad = sizeof(mv_pred_t) * mv_info_size_pad; 2075 2076 MVbank = (((MVbank + 127) >> 7) << 7); 2077 2078 MVbank_pad = (((MVbank_pad + 127) >> 7) << 7); 2079 2080 memTab[MEM_REC_MVBANK].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2081 memTab[MEM_REC_MVBANK].e_mem_type = 2082 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2083 memTab[MEM_REC_MVBANK].u4_mem_size = (MVbank + MVbank_pad) 2084 * (MIN(max_dpb_size, num_ref_frames) + 1); 2085 2086 2087 memTab[MEM_REC_REF_PIC].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2088 memTab[MEM_REC_REF_PIC].e_mem_type = 2089 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2090 memTab[MEM_REC_REF_PIC].u4_mem_size = one_frm_size * num_buf; 2091 2092 } 2093 2094 memTab[MEM_REC_DEBLK_MB_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2095 memTab[MEM_REC_DEBLK_MB_INFO].e_mem_type = 2096 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2097 memTab[MEM_REC_DEBLK_MB_INFO].u4_mem_size = (((((u4_total_num_mbs 2098 + (luma_width >> 4)) * sizeof(deblk_mb_t)) + 127) >> 7) << 7); 2099 2100 memTab[MEM_REC_NEIGHBOR_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2101 memTab[MEM_REC_NEIGHBOR_INFO].e_mem_type = 2102 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2103 memTab[MEM_REC_NEIGHBOR_INFO].u4_mem_size = sizeof(mb_neigbour_params_t) 2104 * ((luma_width + 16) >> 4) * 2 * 2; 2105 { 2106 WORD32 size; 2107 WORD32 num_entries; 2108 2109 num_entries = MIN(MAX_FRAMES, num_ref_frames); 2110 num_entries = 2 * ((2 * num_entries) + 1); 2111 2112 size = num_entries * sizeof(void *); 2113 size += PAD_MAP_IDX_POC * sizeof(void *); 2114 size *= u4_total_num_mbs; 2115 size += sizeof(dec_slice_struct_t) * u4_total_num_mbs; 2116 memTab[MEM_REC_SLICE_HDR].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2117 memTab[MEM_REC_SLICE_HDR].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2118 memTab[MEM_REC_SLICE_HDR].u4_mem_size = size; 2119 } 2120 { 2121 2122 UWORD32 u4_num_entries; 2123 2124 u4_num_entries = u4_total_num_mbs; 2125 2126 memTab[MEM_REC_MB_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2127 memTab[MEM_REC_MB_INFO].e_mem_type = 2128 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2129 memTab[MEM_REC_MB_INFO].u4_mem_size = sizeof(dec_mb_info_t) 2130 * u4_num_entries; 2131 2132 memTab[MEM_REC_PRED_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2133 memTab[MEM_REC_PRED_INFO].e_mem_type = 2134 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2135 2136 memTab[MEM_REC_PRED_INFO].u4_mem_size = sizeof(pred_info_t) * 2*32; 2137 2138 memTab[MEM_REC_COEFF_DATA].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2139 memTab[MEM_REC_COEFF_DATA].e_mem_type = 2140 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2141 memTab[MEM_REC_COEFF_DATA].u4_mem_size = MB_LUM_SIZE * sizeof(WORD16); 2142 /*For I16x16 MBs, 16 4x4 AC coeffs and 1 4x4 DC coeff TU blocks will be sent 2143 For all MBs along with 8 4x4 AC coeffs 2 2x2 DC coeff TU blocks will be sent 2144 So use 17 4x4 TU blocks for luma and 9 4x4 TU blocks for chroma */ 2145 memTab[MEM_REC_COEFF_DATA].u4_mem_size += u4_num_entries 2146 * (MAX(17 * sizeof(tu_sblk4x4_coeff_data_t),4 * sizeof(tu_blk8x8_coeff_data_t)) 2147 + 9 * sizeof(tu_sblk4x4_coeff_data_t)); 2148 //32 bytes for each mb to store u1_prev_intra4x4_pred_mode and u1_rem_intra4x4_pred_mode data 2149 memTab[MEM_REC_COEFF_DATA].u4_mem_size += u4_num_entries * 32; 2150 2151 } 2152 2153 memTab[MEM_REC_SPS].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2154 memTab[MEM_REC_SPS].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2155 memTab[MEM_REC_SPS].u4_mem_size = ((sizeof(dec_seq_params_t)) 2156 * MAX_NUM_SEQ_PARAMS); 2157 2158 memTab[MEM_REC_PPS].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2159 memTab[MEM_REC_PPS].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2160 memTab[MEM_REC_PPS].u4_mem_size = (sizeof(dec_pic_params_t)) 2161 * MAX_NUM_PIC_PARAMS; 2162 2163 { 2164 UWORD32 u4_mem_size; 2165 2166 u4_mem_size = 0; 2167 u4_mem_size += (((sizeof(dec_err_status_t) + 127) >> 7) << 7); 2168 u4_mem_size += sizeof(sei); 2169 u4_mem_size += sizeof(dpb_commands_t); 2170 u4_mem_size += sizeof(dec_bit_stream_t); 2171 u4_mem_size += sizeof(dec_slice_params_t); 2172 u4_mem_size += MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t)); 2173 2174 memTab[MEM_REC_EXTRA_MEM].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2175 memTab[MEM_REC_EXTRA_MEM].e_mem_type = 2176 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2177 memTab[MEM_REC_EXTRA_MEM].u4_mem_size = u4_mem_size; 2178 } 2179 2180 { 2181 2182 UWORD32 u4_mem_size; 2183 2184 u4_mem_size = 0; 2185 u4_mem_size += ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC) * sizeof(void *)); 2186 u4_mem_size = ALIGN64(u4_mem_size); 2187 u4_mem_size += (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS); 2188 u4_mem_size = ALIGN64(u4_mem_size); 2189 u4_mem_size += sizeof(ctxt_inc_mb_info_t); 2190 u4_mem_size = ALIGN64(u4_mem_size); 2191 u4_mem_size += sizeof(UWORD32) * (MAX_REF_BUFS * MAX_REF_BUFS); 2192 u4_mem_size = ALIGN64(u4_mem_size); 2193 2194 u4_mem_size += MAX_REF_BUF_SIZE * 2; 2195 u4_mem_size = ALIGN64(u4_mem_size); 2196 u4_mem_size += ((sizeof(WORD16)) * PRED_BUFFER_WIDTH 2197 * PRED_BUFFER_HEIGHT * 2); 2198 u4_mem_size = ALIGN64(u4_mem_size); 2199 u4_mem_size += sizeof(UWORD8) * (MB_LUM_SIZE); 2200 u4_mem_size = ALIGN64(u4_mem_size); 2201 u4_mem_size += sizeof(parse_pmbarams_t) * luma_width_in_mbs; //Max recon mb group*/ 2202 u4_mem_size = ALIGN64(u4_mem_size); 2203 u4_mem_size += (sizeof(parse_part_params_t) * luma_width_in_mbs) << 4; //Max recon mb group*/ 2204 u4_mem_size = ALIGN64(u4_mem_size); 2205 2206 u4_mem_size += 2 * MAX_REF_BUFS * sizeof(struct pic_buffer_t); 2207 u4_mem_size = ALIGN64(u4_mem_size); 2208 u4_mem_size += 2 * MAX_REF_BUFS * sizeof(struct pic_buffer_t); 2209 u4_mem_size = ALIGN64(u4_mem_size); 2210 u4_mem_size += (sizeof(UWORD32) * 3 * (MAX_REF_BUFS * MAX_REF_BUFS)) << 3; 2211 u4_mem_size = ALIGN64(u4_mem_size); 2212 2213 u4_mem_size += sizeof(UWORD32) * 2 * 3 * (MAX_REF_BUFS * MAX_REF_BUFS); 2214 u4_mem_size = ALIGN64(u4_mem_size); 2215 2216 memTab[MEM_REC_INTERNAL_SCRATCH].u4_mem_alignment = 2217 (128 * 8) / CHAR_BIT; 2218 memTab[MEM_REC_INTERNAL_SCRATCH].e_mem_type = 2219 IV_EXTERNAL_CACHEABLE_SCRATCH_MEM; 2220 memTab[MEM_REC_INTERNAL_SCRATCH].u4_mem_size = u4_mem_size; 2221 } 2222 2223 { 2224 2225 UWORD32 u4_mem_used; 2226 UWORD32 u4_numRows = MB_SIZE << 1; 2227 UWORD32 u4_blk_wd = ((luma_width_in_mbs << 4) >> 1) + 8; 2228 2229 u4_mem_used = 0; 2230 u4_mem_used += ((luma_width_in_mbs * sizeof(deblkmb_neighbour_t)) << 1); 2231 u4_mem_used = ALIGN64(u4_mem_used); 2232 u4_mem_used += (sizeof(neighbouradd_t) << 2); 2233 u4_mem_used = ALIGN64(u4_mem_used); 2234 u4_mem_used += ((sizeof(ctxt_inc_mb_info_t)) 2235 * (((luma_width_in_mbs + 1) << 1) + 1)); 2236 u4_mem_used = ALIGN64(u4_mem_used); 2237 2238 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 16); 2239 u4_mem_used = ALIGN64(u4_mem_used); 2240 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 16); 2241 u4_mem_used = ALIGN64(u4_mem_used); 2242 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 4 2243 * MV_SCRATCH_BUFS); 2244 u4_mem_used = ALIGN64(u4_mem_used); 2245 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2246 u4_mem_used = ALIGN64(u4_mem_used); 2247 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2248 u4_mem_used = ALIGN64(u4_mem_used); 2249 u4_numRows = BLK8x8SIZE << 1; 2250 2251 u4_blk_wd = ((luma_width_in_mbs << 3) >> 1) + 8; 2252 2253 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2254 u4_mem_used = ALIGN64(u4_mem_used); 2255 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2256 u4_mem_used = ALIGN64(u4_mem_used); 2257 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2258 u4_mem_used = ALIGN64(u4_mem_used); 2259 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2260 u4_mem_used += 32; 2261 u4_mem_used = ALIGN64(u4_mem_used); 2262 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2; 2263 u4_mem_used = ALIGN64(u4_mem_used); 2264 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2; 2265 u4_mem_used = ALIGN64(u4_mem_used); 2266 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2; 2267 u4_mem_used = ALIGN64(u4_mem_used); 2268 u4_mem_used += sizeof(mb_neigbour_params_t) * (luma_width_in_mbs + 1) 2269 * luma_height_in_mbs; 2270 u4_mem_used += luma_width; 2271 u4_mem_used = ALIGN64(u4_mem_used); 2272 u4_mem_used += luma_width; 2273 u4_mem_used = ALIGN64(u4_mem_used); 2274 u4_mem_used += luma_width; 2275 u4_mem_used = ALIGN64(u4_mem_used); 2276 2277 u4_mem_used += ((MB_SIZE + 4) << 1) * PAD_LEN_Y_H; 2278 u4_mem_used = ALIGN64(u4_mem_used); 2279 u4_mem_used += ((BLK8x8SIZE + 2) << 1) * PAD_LEN_UV_H; 2280 u4_mem_used = ALIGN64(u4_mem_used); 2281 u4_mem_used += ((BLK8x8SIZE + 2) << 1) * PAD_LEN_UV_H; 2282 u4_mem_used = ALIGN64(u4_mem_used); 2283 memTab[MEM_REC_INTERNAL_PERSIST].u4_mem_alignment = 2284 (128 * 8) / CHAR_BIT; 2285 memTab[MEM_REC_INTERNAL_PERSIST].e_mem_type = 2286 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2287 memTab[MEM_REC_INTERNAL_PERSIST].u4_mem_size = u4_mem_used; 2288 } 2289 2290 memTab[MEM_REC_BITSBUF].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2291 memTab[MEM_REC_BITSBUF].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2292 memTab[MEM_REC_BITSBUF].u4_mem_size = MAX(256000, (luma_width * luma_height * 3 / 2)); 2293 2294 { 2295 2296 UWORD32 u4_thread_struct_size = ithread_get_handle_size(); 2297 2298 memTab[MEM_REC_THREAD_HANDLE].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2299 memTab[MEM_REC_THREAD_HANDLE].e_mem_type = 2300 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2301 memTab[MEM_REC_THREAD_HANDLE].u4_mem_size = u4_thread_struct_size * 2; 2302 2303 } 2304 2305 memTab[MEM_REC_PARSE_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2306 memTab[MEM_REC_PARSE_MAP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2307 memTab[MEM_REC_PARSE_MAP].u4_mem_size = u4_total_num_mbs; 2308 2309 memTab[MEM_REC_PROC_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2310 memTab[MEM_REC_PROC_MAP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2311 memTab[MEM_REC_PROC_MAP].u4_mem_size = u4_total_num_mbs; 2312 2313 memTab[MEM_REC_SLICE_NUM_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2314 memTab[MEM_REC_SLICE_NUM_MAP].e_mem_type = 2315 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2316 memTab[MEM_REC_SLICE_NUM_MAP].u4_mem_size = u4_total_num_mbs 2317 * sizeof(UWORD16); 2318 2319 memTab[MEM_REC_DPB_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2320 memTab[MEM_REC_DPB_MGR].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2321 memTab[MEM_REC_DPB_MGR].u4_mem_size = sizeof(dpb_manager_t); 2322 2323 memTab[MEM_REC_BACKUP].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2324 memTab[MEM_REC_BACKUP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2325 memTab[MEM_REC_BACKUP].u4_mem_size = sizeof(iv_mem_rec_t) * MEM_REC_CNT; 2326 2327 { 2328 2329 UWORD32 u4_mem_size; 2330 2331 u4_mem_size = sizeof(disp_mgr_t); 2332 u4_mem_size += sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 2333 u4_mem_size += sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2); 2334 2335 memTab[MEM_REC_PIC_BUF_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2336 memTab[MEM_REC_PIC_BUF_MGR].e_mem_type = 2337 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2338 memTab[MEM_REC_PIC_BUF_MGR].u4_mem_size = u4_mem_size; 2339 } 2340 2341 { 2342 UWORD32 u4_mem_size; 2343 2344 u4_mem_size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 2345 u4_mem_size += sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2); 2346 u4_mem_size = ALIGN128(u4_mem_size); 2347 u4_mem_size += ((luma_width * luma_height) >> 4) 2348 * (MIN(max_dpb_size, num_ref_frames) + 1); 2349 memTab[MEM_REC_MV_BUF_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2350 memTab[MEM_REC_MV_BUF_MGR].e_mem_type = 2351 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2352 memTab[MEM_REC_MV_BUF_MGR].u4_mem_size = u4_mem_size; 2353 } 2354 2355 memTab[MEM_REC_PRED_INFO_PKD].u4_mem_alignment = (128 * 8) / CHAR_BIT; 2356 memTab[MEM_REC_PRED_INFO_PKD].e_mem_type = 2357 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2358 2359 { 2360 UWORD32 u4_num_entries; 2361 u4_num_entries = u4_total_num_mbs; 2362 2363 if(1 == num_ref_frames) 2364 u4_num_entries *= 16; 2365 else 2366 u4_num_entries *= 16 * 2; 2367 2368 memTab[MEM_REC_PRED_INFO_PKD].u4_mem_size = sizeof(pred_info_pkd_t) 2369 * u4_num_entries; 2370 } 2371 2372 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = MEM_REC_CNT; 2373 2374 2375 return IV_SUCCESS; 2376} 2377/*****************************************************************************/ 2378/* */ 2379/* Function Name : ih264d_clr */ 2380/* */ 2381/* Description : returns memory records to app */ 2382/* */ 2383/* Inputs :iv_obj_t decoder handle */ 2384/* :pv_api_ip pointer to input structure */ 2385/* :pv_api_op pointer to output structure */ 2386/* Outputs : */ 2387/* Returns : void */ 2388/* */ 2389/* Issues : none */ 2390/* */ 2391/* Revision History: */ 2392/* */ 2393/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2394/* 22 10 2008 100356 Draft */ 2395/* */ 2396/*****************************************************************************/ 2397WORD32 ih264d_clr(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2398{ 2399 2400 dec_struct_t * ps_dec; 2401 iv_retrieve_mem_rec_ip_t *dec_clr_ip; 2402 iv_retrieve_mem_rec_op_t *dec_clr_op; 2403 2404 dec_clr_ip = (iv_retrieve_mem_rec_ip_t *)pv_api_ip; 2405 dec_clr_op = (iv_retrieve_mem_rec_op_t *)pv_api_op; 2406 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2407 2408 if(ps_dec->init_done != 1) 2409 { 2410 //return a proper Error Code 2411 return IV_FAIL; 2412 } 2413 2414 if(ps_dec->pv_pic_buf_mgr) 2415 ih264_buf_mgr_free((buf_mgr_t *)ps_dec->pv_pic_buf_mgr); 2416 if(ps_dec->pv_mv_buf_mgr) 2417 ih264_buf_mgr_free((buf_mgr_t *)ps_dec->pv_mv_buf_mgr); 2418 2419 memcpy(dec_clr_ip->pv_mem_rec_location, ps_dec->ps_mem_tab, 2420 MEM_REC_CNT * (sizeof(iv_mem_rec_t))); 2421 dec_clr_op->u4_num_mem_rec_filled = MEM_REC_CNT; 2422 2423 H264_DEC_DEBUG_PRINT("The clear non-conceal num mem recs: %d\n", 2424 dec_clr_op->u4_num_mem_rec_filled); 2425 2426 return IV_SUCCESS; 2427 2428} 2429 2430/*****************************************************************************/ 2431/* */ 2432/* Function Name : ih264d_init */ 2433/* */ 2434/* Description : initializes decoder */ 2435/* */ 2436/* Inputs :iv_obj_t decoder handle */ 2437/* :pv_api_ip pointer to input structure */ 2438/* :pv_api_op pointer to output structure */ 2439/* Outputs : */ 2440/* Returns : void */ 2441/* */ 2442/* Issues : none */ 2443/* */ 2444/* Revision History: */ 2445/* */ 2446/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2447/* 22 10 2008 100356 Draft */ 2448/* */ 2449/*****************************************************************************/ 2450WORD32 ih264d_init(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2451{ 2452 ih264d_init_ip_t *ps_init_ip; 2453 ih264d_init_op_t *ps_init_op; 2454 WORD32 init_status = IV_SUCCESS; 2455 ps_init_ip = (ih264d_init_ip_t *)pv_api_ip; 2456 ps_init_op = (ih264d_init_op_t *)pv_api_op; 2457 2458 init_status = ih264d_init_video_decoder(dec_hdl, ps_init_ip, ps_init_op); 2459 2460 if(IV_SUCCESS != init_status) 2461 { 2462 return init_status; 2463 } 2464 2465 return init_status; 2466} 2467/*****************************************************************************/ 2468/* */ 2469/* Function Name : ih264d_map_error */ 2470/* */ 2471/* Description : Maps error codes to IVD error groups */ 2472/* */ 2473/* Inputs : */ 2474/* Globals : <Does it use any global variables?> */ 2475/* Outputs : */ 2476/* Returns : void */ 2477/* */ 2478/* Issues : none */ 2479/* */ 2480/* Revision History: */ 2481/* */ 2482/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2483/* 22 10 2008 100356 Draft */ 2484/* */ 2485/*****************************************************************************/ 2486UWORD32 ih264d_map_error(UWORD32 i4_err_status) 2487{ 2488 UWORD32 temp = 0; 2489 2490 switch(i4_err_status) 2491 { 2492 case ERROR_MEM_ALLOC_ISRAM_T: 2493 case ERROR_MEM_ALLOC_SDRAM_T: 2494 case ERROR_BUF_MGR: 2495 case ERROR_MB_GROUP_ASSGN_T: 2496 case ERROR_FRAME_LIMIT_OVER: 2497 case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT: 2498 case ERROR_PROFILE_NOT_SUPPORTED: 2499 case ERROR_INIT_NOT_DONE: 2500 temp = 1 << IVD_FATALERROR; 2501 H264_DEC_DEBUG_PRINT("\nFatal Error\n"); 2502 break; 2503 2504 case ERROR_DBP_MANAGER_T: 2505 case ERROR_GAPS_IN_FRM_NUM: 2506 case ERROR_UNKNOWN_NAL: 2507 case ERROR_INV_MB_SLC_GRP_T: 2508 case ERROR_MULTIPLE_SLC_GRP_T: 2509 case ERROR_UNKNOWN_LEVEL: 2510 case ERROR_UNAVAIL_PICBUF_T: 2511 case ERROR_UNAVAIL_MVBUF_T: 2512 case ERROR_UNAVAIL_DISPBUF_T: 2513 case ERROR_NUM_REF: 2514 case ERROR_REFIDX_ORDER_T: 2515 case ERROR_PIC0_NOT_FOUND_T: 2516 case ERROR_MB_TYPE: 2517 case ERROR_SUB_MB_TYPE: 2518 case ERROR_CBP: 2519 case ERROR_REF_IDX: 2520 case ERROR_NUM_MV: 2521 case ERROR_CHROMA_PRED_MODE: 2522 case ERROR_INTRAPRED: 2523 case ERROR_NEXT_MB_ADDRESS_T: 2524 case ERROR_MB_ADDRESS_T: 2525 case ERROR_PIC1_NOT_FOUND_T: 2526 case ERROR_CAVLC_NUM_COEFF_T: 2527 case ERROR_CAVLC_SCAN_POS_T: 2528 case ERROR_PRED_WEIGHT_TABLE_T: 2529 case ERROR_CORRUPTED_SLICE: 2530 temp = 1 << IVD_CORRUPTEDDATA; 2531 break; 2532 2533 case ERROR_NOT_SUPP_RESOLUTION: 2534 case ERROR_FEATURE_UNAVAIL: 2535 case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT: 2536 temp = 1 << IVD_UNSUPPORTEDINPUT; 2537 break; 2538 2539 case ERROR_INVALID_PIC_PARAM: 2540 case ERROR_INVALID_SEQ_PARAM: 2541 case ERROR_EGC_EXCEED_32_1_T: 2542 case ERROR_EGC_EXCEED_32_2_T: 2543 case ERROR_INV_RANGE_TEV_T: 2544 case ERROR_INV_SLC_TYPE_T: 2545 case ERROR_INV_POC_TYPE_T: 2546 case ERROR_INV_RANGE_QP_T: 2547 case ERROR_INV_SPS_PPS_T: 2548 case ERROR_INV_SLICE_HDR_T: 2549 temp = 1 << IVD_CORRUPTEDHEADER; 2550 break; 2551 2552 case ERROR_EOB_FLUSHBITS_T: 2553 case ERROR_EOB_GETBITS_T: 2554 case ERROR_EOB_GETBIT_T: 2555 case ERROR_EOB_BYPASS_T: 2556 case ERROR_EOB_DECISION_T: 2557 case ERROR_EOB_TERMINATE_T: 2558 case ERROR_EOB_READCOEFF4X4CAB_T: 2559 temp = 1 << IVD_INSUFFICIENTDATA; 2560 break; 2561 case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED: 2562 case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH: 2563 temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR; 2564 break; 2565 2566 case ERROR_DANGLING_FIELD_IN_PIC: 2567 temp = 1 << IVD_APPLIEDCONCEALMENT; 2568 break; 2569 2570 } 2571 2572 return temp; 2573 2574} 2575 2576/*****************************************************************************/ 2577/* */ 2578/* Function Name : ih264d_video_decode */ 2579/* */ 2580/* Description : handle video decode API command */ 2581/* */ 2582/* Inputs :iv_obj_t decoder handle */ 2583/* :pv_api_ip pointer to input structure */ 2584/* :pv_api_op pointer to output structure */ 2585/* Outputs : */ 2586/* Returns : void */ 2587/* */ 2588/* Issues : none */ 2589/* */ 2590/* Revision History: */ 2591/* */ 2592/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2593/* 22 10 2008 100356 Draft */ 2594/* */ 2595/*****************************************************************************/ 2596 2597WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2598{ 2599 /* ! */ 2600 2601 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2602 2603 WORD32 i4_err_status = 0; 2604 UWORD8 *pu1_buf = NULL; 2605 WORD32 buflen; 2606 UWORD32 u4_max_ofst, u4_length_of_start_code = 0; 2607 2608 UWORD32 bytes_consumed = 0; 2609 UWORD32 cur_slice_is_nonref = 0; 2610 UWORD32 u4_next_is_aud; 2611 UWORD32 u4_first_start_code_found = 0; 2612 WORD32 ret = 0,api_ret_value = IV_SUCCESS; 2613 WORD32 header_data_left = 0,frame_data_left = 0; 2614 UWORD8 *pu1_bitstrm_buf; 2615 ivd_video_decode_ip_t *ps_dec_ip; 2616 ivd_video_decode_op_t *ps_dec_op; 2617 2618 ithread_set_name((void*)"Parse_thread"); 2619 2620 ps_dec_ip = (ivd_video_decode_ip_t *)pv_api_ip; 2621 ps_dec_op = (ivd_video_decode_op_t *)pv_api_op; 2622 2623 { 2624 UWORD32 u4_size; 2625 u4_size = ps_dec_op->u4_size; 2626 memset(ps_dec_op, 0, sizeof(ivd_video_decode_op_t)); 2627 ps_dec_op->u4_size = u4_size; 2628 } 2629 2630 ps_dec->pv_dec_out = ps_dec_op; 2631 ps_dec->process_called = 1; 2632 if(ps_dec->init_done != 1) 2633 { 2634 return IV_FAIL; 2635 } 2636 2637 /*Data memory barries instruction,so that bitstream write by the application is complete*/ 2638 DATA_SYNC(); 2639 2640 if(0 == ps_dec->u1_flushfrm) 2641 { 2642 if(ps_dec_ip->pv_stream_buffer == NULL) 2643 { 2644 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2645 ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL; 2646 return IV_FAIL; 2647 } 2648 if(ps_dec_ip->u4_num_Bytes <= 0) 2649 { 2650 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2651 ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV; 2652 return IV_FAIL; 2653 2654 } 2655 } 2656 ps_dec->u1_pic_decode_done = 0; 2657 2658 ps_dec_op->u4_num_bytes_consumed = 0; 2659 2660 ps_dec->ps_out_buffer = NULL; 2661 2662 if(ps_dec_ip->u4_size 2663 >= offsetof(ivd_video_decode_ip_t, s_out_buffer)) 2664 ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer; 2665 2666 ps_dec->u4_fmt_conv_cur_row = 0; 2667 2668 ps_dec->u4_output_present = 0; 2669 ps_dec->s_disp_op.u4_error_code = 1; 2670 ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS; 2671 ps_dec->u4_stop_threads = 0; 2672 if(0 == ps_dec->u4_share_disp_buf 2673 && ps_dec->i4_decode_header == 0) 2674 { 2675 UWORD32 i; 2676 if(ps_dec->ps_out_buffer->u4_num_bufs == 0) 2677 { 2678 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2679 ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS; 2680 return IV_FAIL; 2681 } 2682 2683 for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++) 2684 { 2685 if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL) 2686 { 2687 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2688 ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL; 2689 return IV_FAIL; 2690 } 2691 2692 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0) 2693 { 2694 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2695 ps_dec_op->u4_error_code |= 2696 IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 2697 return IV_FAIL; 2698 } 2699 } 2700 } 2701 2702 if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT) 2703 { 2704 ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER; 2705 return IV_FAIL; 2706 } 2707 2708 /* ! */ 2709 ps_dec->u4_ts = ps_dec_ip->u4_ts; 2710 2711 ps_dec_op->u4_error_code = 0; 2712 ps_dec_op->e_pic_type = -1; 2713 ps_dec_op->u4_output_present = 0; 2714 ps_dec_op->u4_frame_decoded_flag = 0; 2715 2716 ps_dec->i4_frametype = -1; 2717 ps_dec->i4_content_type = -1; 2718 /* 2719 * For field pictures, set the bottom and top picture decoded u4_flag correctly. 2720 */ 2721 { 2722 if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded) 2723 { 2724 ps_dec->u1_top_bottom_decoded = 0; 2725 } 2726 } 2727 ps_dec->u4_slice_start_code_found = 0; 2728 2729 /* In case the deocder is not in flush mode(in shared mode), 2730 then decoder has to pick up a buffer to write current frame. 2731 Check if a frame is available in such cases */ 2732 2733 if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1 2734 && ps_dec->u1_flushfrm == 0) 2735 { 2736 UWORD32 i; 2737 2738 WORD32 disp_avail = 0, free_id; 2739 2740 /* Check if at least one buffer is available with the codec */ 2741 /* If not then return to application with error */ 2742 for(i = 0; i < ps_dec->u1_pic_bufs; i++) 2743 { 2744 if(0 == ps_dec->u4_disp_buf_mapping[i] 2745 || 1 == ps_dec->u4_disp_buf_to_be_freed[i]) 2746 { 2747 disp_avail = 1; 2748 break; 2749 } 2750 2751 } 2752 2753 if(0 == disp_avail) 2754 { 2755 /* If something is queued for display wait for that buffer to be returned */ 2756 2757 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL; 2758 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 2759 return (IV_FAIL); 2760 } 2761 2762 while(1) 2763 { 2764 pic_buffer_t *ps_pic_buf; 2765 ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free( 2766 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id); 2767 2768 if(ps_pic_buf == NULL) 2769 { 2770 UWORD32 i, display_queued = 0; 2771 2772 /* check if any buffer was given for display which is not returned yet */ 2773 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++) 2774 { 2775 if(0 != ps_dec->u4_disp_buf_mapping[i]) 2776 { 2777 display_queued = 1; 2778 break; 2779 } 2780 } 2781 /* If some buffer is queued for display, then codec has to singal an error and wait 2782 for that buffer to be returned. 2783 If nothing is queued for display then codec has ownership of all display buffers 2784 and it can reuse any of the existing buffers and continue decoding */ 2785 2786 if(1 == display_queued) 2787 { 2788 /* If something is queued for display wait for that buffer to be returned */ 2789 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL; 2790 ps_dec_op->u4_error_code |= (1 2791 << IVD_UNSUPPORTEDPARAM); 2792 return (IV_FAIL); 2793 } 2794 } 2795 else 2796 { 2797 /* If the buffer is with display, then mark it as in use and then look for a buffer again */ 2798 if(1 == ps_dec->u4_disp_buf_mapping[free_id]) 2799 { 2800 ih264_buf_mgr_set_status( 2801 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 2802 free_id, 2803 BUF_MGR_IO); 2804 } 2805 else 2806 { 2807 /** 2808 * Found a free buffer for present call. Release it now. 2809 * Will be again obtained later. 2810 */ 2811 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 2812 free_id, 2813 BUF_MGR_IO); 2814 break; 2815 } 2816 } 2817 } 2818 2819 } 2820 2821 if(ps_dec->u1_flushfrm && ps_dec->u1_init_dec_flag) 2822 { 2823 2824 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer, 2825 &(ps_dec->s_disp_op)); 2826 if(0 == ps_dec->s_disp_op.u4_error_code) 2827 { 2828 ps_dec->u4_fmt_conv_cur_row = 0; 2829 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht; 2830 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 2831 ps_dec->u4_fmt_conv_cur_row, 2832 ps_dec->u4_fmt_conv_num_rows); 2833 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 2834 ps_dec->u4_output_present = 1; 2835 2836 } 2837 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op)); 2838 2839 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 2840 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 2841 2842 ps_dec_op->u4_new_seq = 0; 2843 2844 ps_dec_op->u4_output_present = ps_dec->u4_output_present; 2845 ps_dec_op->u4_progressive_frame_flag = 2846 ps_dec->s_disp_op.u4_progressive_frame_flag; 2847 ps_dec_op->e_output_format = 2848 ps_dec->s_disp_op.e_output_format; 2849 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf; 2850 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type; 2851 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts; 2852 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id; 2853 2854 /*In the case of flush ,since no frame is decoded set pic type as invalid*/ 2855 ps_dec_op->u4_is_ref_flag = -1; 2856 ps_dec_op->e_pic_type = IV_NA_FRAME; 2857 ps_dec_op->u4_frame_decoded_flag = 0; 2858 2859 if(0 == ps_dec->s_disp_op.u4_error_code) 2860 { 2861 return (IV_SUCCESS); 2862 } 2863 else 2864 return (IV_FAIL); 2865 2866 } 2867 if(ps_dec->u1_res_changed == 1) 2868 { 2869 /*if resolution has changed and all buffers have been flushed, reset decoder*/ 2870 ih264d_init_decoder(ps_dec); 2871 } 2872 2873 ps_dec->u4_prev_nal_skipped = 0; 2874 2875 ps_dec->u2_cur_mb_addr = 0; 2876 ps_dec->u2_total_mbs_coded = 0; 2877 ps_dec->u2_cur_slice_num = 0; 2878 ps_dec->cur_dec_mb_num = 0; 2879 ps_dec->cur_recon_mb_num = 0; 2880 ps_dec->u4_first_slice_in_pic = 2; 2881 ps_dec->u1_slice_header_done = 0; 2882 ps_dec->u1_dangling_field = 0; 2883 2884 ps_dec->u4_dec_thread_created = 0; 2885 ps_dec->u4_bs_deblk_thread_created = 0; 2886 ps_dec->u4_cur_bs_mb_num = 0; 2887 2888 DEBUG_THREADS_PRINTF(" Starting process call\n"); 2889 2890 ps_dec->u4_pic_buf_got = 0; 2891 2892 do 2893 { 2894 2895 pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer 2896 + ps_dec_op->u4_num_bytes_consumed; 2897 2898 u4_max_ofst = ps_dec_ip->u4_num_Bytes 2899 - ps_dec_op->u4_num_bytes_consumed; 2900 pu1_bitstrm_buf = ps_dec->ps_mem_tab[MEM_REC_BITSBUF].pv_base; 2901 2902 u4_next_is_aud = 0; 2903 2904 buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst, 2905 &u4_length_of_start_code, 2906 &u4_next_is_aud); 2907 2908 if(buflen == -1) 2909 buflen = 0; 2910 /* Ignore bytes beyond the allocated size of intermediate buffer */ 2911 buflen = MIN(buflen, (WORD32)ps_dec->ps_mem_tab[MEM_REC_BITSBUF].u4_mem_size); 2912 2913 bytes_consumed = buflen + u4_length_of_start_code; 2914 ps_dec_op->u4_num_bytes_consumed += bytes_consumed; 2915 2916 if(buflen >= MAX_NAL_UNIT_SIZE) 2917 { 2918 2919 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op); 2920 H264_DEC_DEBUG_PRINT( 2921 "\nNal Size exceeded %d, Processing Stopped..\n", 2922 MAX_NAL_UNIT_SIZE); 2923 ps_dec->i4_error_code = 1 << IVD_CORRUPTEDDATA; 2924 2925 ps_dec_op->e_pic_type = -1; 2926 /*signal the decode thread*/ 2927 ih264d_signal_decode_thread(ps_dec); 2928 /*signal end of frame decode for curren frame*/ 2929 2930 if(ps_dec->u4_pic_buf_got == 0) 2931 { 2932 if(ps_dec->i4_header_decoded == 3) 2933 { 2934 ps_dec->u2_total_mbs_coded = 2935 ps_dec->ps_cur_sps->u2_max_mb_addr + 1; 2936 } 2937 2938 /* close deblock thread if it is not closed yet*/ 2939 if(ps_dec->u4_num_cores == 3) 2940 { 2941 ih264d_signal_bs_deblk_thread(ps_dec); 2942 } 2943 return IV_FAIL; 2944 } 2945 else 2946 { 2947 ps_dec->u1_pic_decode_done = 1; 2948 continue; 2949 } 2950 } 2951 2952 { 2953 UWORD8 u1_firstbyte, u1_nal_ref_idc; 2954 2955 if(ps_dec->i4_app_skip_mode == IVD_SKIP_B) 2956 { 2957 u1_firstbyte = *(pu1_buf + u4_length_of_start_code); 2958 u1_nal_ref_idc = (UWORD8)(NAL_REF_IDC(u1_firstbyte)); 2959 if(u1_nal_ref_idc == 0) 2960 { 2961 /*skip non reference frames*/ 2962 cur_slice_is_nonref = 1; 2963 continue; 2964 } 2965 else 2966 { 2967 if(1 == cur_slice_is_nonref) 2968 { 2969 /*We have encountered a referenced frame,return to app*/ 2970 ps_dec_op->u4_num_bytes_consumed -= 2971 bytes_consumed; 2972 ps_dec_op->e_pic_type = IV_B_FRAME; 2973 ps_dec_op->u4_error_code = 2974 IVD_DEC_FRM_SKIPPED; 2975 ps_dec_op->u4_error_code |= (1 2976 << IVD_UNSUPPORTEDPARAM); 2977 ps_dec_op->u4_frame_decoded_flag = 0; 2978 ps_dec_op->u4_size = 2979 sizeof(ivd_video_decode_op_t); 2980 /*signal the decode thread*/ 2981 ih264d_signal_decode_thread(ps_dec); 2982 /* close deblock thread if it is not closed yet*/ 2983 if(ps_dec->u4_num_cores == 3) 2984 { 2985 ih264d_signal_bs_deblk_thread(ps_dec); 2986 } 2987 2988 return (IV_FAIL); 2989 } 2990 } 2991 2992 } 2993 2994 } 2995 2996 2997 if(buflen) 2998 { 2999 memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code, 3000 buflen); 3001 u4_first_start_code_found = 1; 3002 3003 } 3004 else 3005 { 3006 /*start code not found*/ 3007 3008 if(u4_first_start_code_found == 0) 3009 { 3010 /*no start codes found in current process call*/ 3011 3012 ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND; 3013 ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA; 3014 3015 if(ps_dec->u4_pic_buf_got == 0) 3016 { 3017 3018 ih264d_fill_output_struct_from_context(ps_dec, 3019 ps_dec_op); 3020 3021 ps_dec_op->u4_error_code = ps_dec->i4_error_code; 3022 ps_dec_op->u4_frame_decoded_flag = 0; 3023 3024 return (IV_FAIL); 3025 } 3026 else 3027 { 3028 ps_dec->u1_pic_decode_done = 1; 3029 continue; 3030 } 3031 } 3032 else 3033 { 3034 /* a start code has already been found earlier in the same process call*/ 3035 frame_data_left = 0; 3036 continue; 3037 } 3038 3039 } 3040 3041 ps_dec->u4_return_to_app = 0; 3042 ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op, 3043 pu1_bitstrm_buf, buflen); 3044 if(ret != OK) 3045 { 3046 UWORD32 error = ih264d_map_error(ret); 3047 ps_dec_op->u4_error_code = error | ret; 3048 api_ret_value = IV_FAIL; 3049 3050 if((ret == IVD_RES_CHANGED) 3051 || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED) 3052 || (ret == ERROR_UNAVAIL_PICBUF_T) 3053 || (ret == ERROR_UNAVAIL_MVBUF_T)) 3054 { 3055 break; 3056 } 3057 3058 if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC)) 3059 { 3060 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 3061 api_ret_value = IV_FAIL; 3062 break; 3063 } 3064 3065 if(ret == ERROR_IN_LAST_SLICE_OF_PIC) 3066 { 3067 api_ret_value = IV_FAIL; 3068 break; 3069 } 3070 3071 } 3072 3073 if(ps_dec->u4_return_to_app) 3074 { 3075 /*We have encountered a referenced frame,return to app*/ 3076 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 3077 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED; 3078 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 3079 ps_dec_op->u4_frame_decoded_flag = 0; 3080 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t); 3081 /*signal the decode thread*/ 3082 ih264d_signal_decode_thread(ps_dec); 3083 /* close deblock thread if it is not closed yet*/ 3084 if(ps_dec->u4_num_cores == 3) 3085 { 3086 ih264d_signal_bs_deblk_thread(ps_dec); 3087 } 3088 return (IV_FAIL); 3089 3090 } 3091 3092 3093 3094 header_data_left = ((ps_dec->i4_decode_header == 1) 3095 && (ps_dec->i4_header_decoded != 3) 3096 && (ps_dec_op->u4_num_bytes_consumed 3097 < ps_dec_ip->u4_num_Bytes)); 3098 frame_data_left = (((ps_dec->i4_decode_header == 0) 3099 && ((ps_dec->u1_pic_decode_done == 0) 3100 || (u4_next_is_aud == 1))) 3101 && (ps_dec_op->u4_num_bytes_consumed 3102 < ps_dec_ip->u4_num_Bytes)); 3103 } 3104 while(( header_data_left == 1)||(frame_data_left == 1)); 3105 3106 if((ps_dec->u4_slice_start_code_found == 1) 3107 && ps_dec->u2_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs) 3108 { 3109 // last slice - missing/corruption 3110 WORD32 num_mb_skipped; 3111 WORD32 prev_slice_err; 3112 pocstruct_t temp_poc; 3113 WORD32 ret1; 3114 3115 num_mb_skipped = (ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs) 3116 - ps_dec->u2_total_mbs_coded; 3117 3118 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0)) 3119 prev_slice_err = 1; 3120 else 3121 prev_slice_err = 2; 3122 3123 ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num, 3124 &temp_poc, prev_slice_err); 3125 3126 if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T)) 3127 { 3128 return IV_FAIL; 3129 } 3130 } 3131 3132 if((ret == IVD_RES_CHANGED) 3133 || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED) 3134 || (ret == ERROR_UNAVAIL_PICBUF_T) 3135 || (ret == ERROR_UNAVAIL_MVBUF_T)) 3136 { 3137 3138 /* signal the decode thread */ 3139 ih264d_signal_decode_thread(ps_dec); 3140 /* close deblock thread if it is not closed yet */ 3141 if(ps_dec->u4_num_cores == 3) 3142 { 3143 ih264d_signal_bs_deblk_thread(ps_dec); 3144 } 3145 /* dont consume bitstream for change in resolution case */ 3146 if(ret == IVD_RES_CHANGED) 3147 { 3148 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 3149 } 3150 return IV_FAIL; 3151 } 3152 3153 3154 if(ps_dec->u1_separate_parse) 3155 { 3156 /* If Format conversion is not complete, 3157 complete it here */ 3158 if(ps_dec->u4_num_cores == 2) 3159 { 3160 3161 /*do deblocking of all mbs*/ 3162 if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0)) 3163 { 3164 UWORD32 u4_num_mbs,u4_max_addr; 3165 tfr_ctxt_t s_tfr_ctxt; 3166 tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt; 3167 pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr; 3168 3169 /*BS is done for all mbs while parsing*/ 3170 u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1; 3171 ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1; 3172 3173 3174 ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt, 3175 ps_dec->u2_frm_wd_in_mbs, 0); 3176 3177 3178 u4_num_mbs = u4_max_addr 3179 - ps_dec->u4_cur_deblk_mb_num + 1; 3180 3181 DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs); 3182 3183 if(u4_num_mbs != 0) 3184 ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs, 3185 ps_tfr_cxt,1); 3186 3187 ps_dec->u4_start_recon_deblk = 0; 3188 3189 } 3190 3191 } 3192 3193 /*signal the decode thread*/ 3194 ih264d_signal_decode_thread(ps_dec); 3195 /* close deblock thread if it is not closed yet*/ 3196 if(ps_dec->u4_num_cores == 3) 3197 { 3198 ih264d_signal_bs_deblk_thread(ps_dec); 3199 } 3200 } 3201 3202 3203 DATA_SYNC(); 3204 3205 3206 if((ps_dec_op->u4_error_code & 0xff) 3207 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED) 3208 { 3209 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 3210 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 3211 } 3212 3213//Report if header (sps and pps) has not been decoded yet 3214 if(ps_dec->i4_header_decoded != 3) 3215 { 3216 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA); 3217 3218 } 3219 3220 if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3) 3221 { 3222 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA); 3223 3224 } 3225 if(ps_dec->u4_prev_nal_skipped) 3226 { 3227 /*We have encountered a referenced frame,return to app*/ 3228 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED; 3229 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 3230 ps_dec_op->u4_frame_decoded_flag = 0; 3231 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t); 3232 /* close deblock thread if it is not closed yet*/ 3233 if(ps_dec->u4_num_cores == 3) 3234 { 3235 ih264d_signal_bs_deblk_thread(ps_dec); 3236 } 3237 return (IV_FAIL); 3238 3239 } 3240 3241 if((ps_dec->u4_slice_start_code_found == 1) 3242 && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status)) 3243 { 3244 /* 3245 * For field pictures, set the bottom and top picture decoded u4_flag correctly. 3246 */ 3247 3248 if(ps_dec->ps_cur_slice->u1_field_pic_flag) 3249 { 3250 if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag) 3251 { 3252 ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY; 3253 } 3254 else 3255 { 3256 ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY; 3257 } 3258 } 3259 3260 /* if new frame in not found (if we are still getting slices from previous frame) 3261 * ih264d_deblock_display is not called. Such frames will not be added to reference /display 3262 */ 3263 if((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0) 3264 { 3265 /* Calling Function to deblock Picture and Display */ 3266 ret = ih264d_deblock_display(ps_dec); 3267 if(ret != 0) 3268 { 3269 return IV_FAIL; 3270 } 3271 } 3272 3273 3274 /*set to complete ,as we dont support partial frame decode*/ 3275 if(ps_dec->i4_header_decoded == 3) 3276 { 3277 ps_dec->u2_total_mbs_coded = ps_dec->ps_cur_sps->u2_max_mb_addr + 1; 3278 } 3279 3280 /*Update the i4_frametype at the end of picture*/ 3281 if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL) 3282 { 3283 ps_dec->i4_frametype = IV_IDR_FRAME; 3284 } 3285 else if(ps_dec->i4_pic_type == B_SLICE) 3286 { 3287 ps_dec->i4_frametype = IV_B_FRAME; 3288 } 3289 else if(ps_dec->i4_pic_type == P_SLICE) 3290 { 3291 ps_dec->i4_frametype = IV_P_FRAME; 3292 } 3293 else if(ps_dec->i4_pic_type == I_SLICE) 3294 { 3295 ps_dec->i4_frametype = IV_I_FRAME; 3296 } 3297 else 3298 { 3299 H264_DEC_DEBUG_PRINT("Shouldn't come here\n"); 3300 } 3301 3302 //Update the content type 3303 ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag; 3304 3305 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2; 3306 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded 3307 - ps_dec->ps_cur_slice->u1_field_pic_flag; 3308 3309 } 3310 3311 /* close deblock thread if it is not closed yet*/ 3312 if(ps_dec->u4_num_cores == 3) 3313 { 3314 ih264d_signal_bs_deblk_thread(ps_dec); 3315 } 3316 3317 3318 { 3319 /* In case the decoder is configured to run in low delay mode, 3320 * then get display buffer and then format convert. 3321 * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles 3322 */ 3323 3324 if((0 == ps_dec->u4_num_reorder_frames_at_init) 3325 && ps_dec->u1_init_dec_flag) 3326 { 3327 3328 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer, 3329 &(ps_dec->s_disp_op)); 3330 if(0 == ps_dec->s_disp_op.u4_error_code) 3331 { 3332 ps_dec->u4_fmt_conv_cur_row = 0; 3333 ps_dec->u4_output_present = 1; 3334 } 3335 } 3336 3337 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op); 3338 3339 /* If Format conversion is not complete, 3340 complete it here */ 3341 if(ps_dec->u4_output_present && 3342 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht)) 3343 { 3344 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht 3345 - ps_dec->u4_fmt_conv_cur_row; 3346 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 3347 ps_dec->u4_fmt_conv_cur_row, 3348 ps_dec->u4_fmt_conv_num_rows); 3349 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 3350 } 3351 3352 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op)); 3353 } 3354 3355 if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1) 3356 { 3357 ps_dec_op->u4_progressive_frame_flag = 1; 3358 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3359 { 3360 if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag) 3361 && (0 == ps_dec->ps_sps->u1_mb_aff_flag)) 3362 ps_dec_op->u4_progressive_frame_flag = 0; 3363 3364 } 3365 } 3366 3367 /*Data memory barrier instruction,so that yuv write by the library is complete*/ 3368 DATA_SYNC(); 3369 3370 H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n", 3371 ps_dec_op->u4_num_bytes_consumed); 3372 return api_ret_value; 3373} 3374 3375WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3376{ 3377 char version_string[MAXVERSION_STRLEN + 1]; 3378 UWORD32 version_string_len; 3379 3380 ivd_ctl_getversioninfo_ip_t *ps_ip; 3381 ivd_ctl_getversioninfo_op_t *ps_op; 3382 3383 ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip; 3384 ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op; 3385 UNUSED(dec_hdl); 3386 ps_op->u4_error_code = IV_SUCCESS; 3387 3388 VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER, 3389 CODEC_VENDOR); 3390 3391 if((WORD32)ps_ip->u4_version_buffer_size <= 0) 3392 { 3393 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT; 3394 return (IV_FAIL); 3395 } 3396 3397 version_string_len = strlen(version_string) + 1; 3398 3399 if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string))) 3400 { 3401 memcpy(ps_ip->pv_version_buffer, version_string, version_string_len); 3402 ps_op->u4_error_code = IV_SUCCESS; 3403 } 3404 else 3405 { 3406 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT; 3407 return IV_FAIL; 3408 } 3409 return (IV_SUCCESS); 3410} 3411 3412/*****************************************************************************/ 3413/* */ 3414/* Function Name : ih264d_get_display_frame */ 3415/* */ 3416/* Description : */ 3417/* Inputs :iv_obj_t decoder handle */ 3418/* :pv_api_ip pointer to input structure */ 3419/* :pv_api_op pointer to output structure */ 3420/* Outputs : */ 3421/* Returns : void */ 3422/* */ 3423/* Issues : none */ 3424/* */ 3425/* Revision History: */ 3426/* */ 3427/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3428/* 22 10 2008 100356 Draft */ 3429/* */ 3430/*****************************************************************************/ 3431WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl, 3432 void *pv_api_ip, 3433 void *pv_api_op) 3434{ 3435 3436 UNUSED(dec_hdl); 3437 UNUSED(pv_api_ip); 3438 UNUSED(pv_api_op); 3439 // This function is no longer needed, output is returned in the process() 3440 return IV_FAIL; 3441} 3442 3443/*****************************************************************************/ 3444/* */ 3445/* Function Name : ih264d_set_display_frame */ 3446/* */ 3447/* Description : */ 3448/* */ 3449/* Inputs :iv_obj_t decoder handle */ 3450/* :pv_api_ip pointer to input structure */ 3451/* :pv_api_op pointer to output structure */ 3452/* Outputs : */ 3453/* Returns : void */ 3454/* */ 3455/* Issues : none */ 3456/* */ 3457/* Revision History: */ 3458/* */ 3459/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3460/* 22 10 2008 100356 Draft */ 3461/* */ 3462/*****************************************************************************/ 3463WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl, 3464 void *pv_api_ip, 3465 void *pv_api_op) 3466{ 3467 3468 ivd_set_display_frame_ip_t *dec_disp_ip; 3469 ivd_set_display_frame_op_t *dec_disp_op; 3470 3471 UWORD32 i, num_mvbank_req; 3472 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3473 3474 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip; 3475 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op; 3476 dec_disp_op->u4_error_code = 0; 3477 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3478 { 3479 UWORD32 level, width_mbs, height_mbs; 3480 3481 level = ps_dec->u4_level_at_init; 3482 width_mbs = ps_dec->u2_frm_wd_in_mbs; 3483 height_mbs = ps_dec->u2_frm_ht_in_mbs; 3484 3485 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) 3486 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames != 64)) 3487 { 3488 num_mvbank_req = ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2; 3489 } 3490 else 3491 { 3492 /*if VUI is not present assume maximum possible refrence frames for the level, 3493 * as max reorder frames*/ 3494 num_mvbank_req = ih264d_get_dpb_size_new(level, width_mbs, 3495 height_mbs); 3496 } 3497 3498 num_mvbank_req += ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 3499 } 3500 else 3501 { 3502 UWORD32 num_bufs_app, num_bufs_level; 3503 UWORD32 num_ref_frames, num_reorder_frames, luma_width; 3504 UWORD32 luma_height, level; 3505 3506 num_ref_frames = ps_dec->u4_num_ref_frames_at_init; 3507 num_reorder_frames = ps_dec->u4_num_reorder_frames_at_init; 3508 level = ps_dec->u4_level_at_init; 3509 luma_width = ps_dec->u4_width_at_init; 3510 luma_height = ps_dec->u4_height_at_init; 3511 3512 num_bufs_app = num_ref_frames + num_reorder_frames + 1; 3513 3514 if(num_bufs_app <= 1) 3515 num_bufs_app = 2; 3516 3517 num_bufs_level = ih264d_get_dpb_size_new(level, (luma_width >> 4), 3518 (luma_height >> 4)); 3519 3520 num_bufs_level = num_bufs_level * 2 + 1; 3521 3522 num_mvbank_req = MIN(num_bufs_level, num_bufs_app); 3523 3524 num_mvbank_req += ps_dec->u4_num_extra_disp_bufs_at_init; 3525 3526 } 3527 3528 ps_dec->u4_num_disp_bufs = 0; 3529 if(ps_dec->u4_share_disp_buf) 3530 { 3531 UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs; 3532 if(u4_num_bufs > MAX_DISP_BUFS_NEW) 3533 u4_num_bufs = MAX_DISP_BUFS_NEW; 3534 3535 u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW); 3536 u4_num_bufs = MIN(u4_num_bufs, num_mvbank_req); 3537 3538 ps_dec->u4_num_disp_bufs = u4_num_bufs; 3539 for(i = 0; i < u4_num_bufs; i++) 3540 { 3541 ps_dec->disp_bufs[i].u4_num_bufs = 3542 dec_disp_ip->s_disp_buffer[i].u4_num_bufs; 3543 3544 ps_dec->disp_bufs[i].buf[0] = 3545 dec_disp_ip->s_disp_buffer[i].pu1_bufs[0]; 3546 ps_dec->disp_bufs[i].buf[1] = 3547 dec_disp_ip->s_disp_buffer[i].pu1_bufs[1]; 3548 ps_dec->disp_bufs[i].buf[2] = 3549 dec_disp_ip->s_disp_buffer[i].pu1_bufs[2]; 3550 3551 ps_dec->disp_bufs[i].u4_bufsize[0] = 3552 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]; 3553 ps_dec->disp_bufs[i].u4_bufsize[1] = 3554 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]; 3555 ps_dec->disp_bufs[i].u4_bufsize[2] = 3556 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]; 3557 3558 } 3559 } 3560 return IV_SUCCESS; 3561 3562} 3563 3564/*****************************************************************************/ 3565/* */ 3566/* Function Name : ih264d_set_flush_mode */ 3567/* */ 3568/* Description : */ 3569/* */ 3570/* Inputs :iv_obj_t decoder handle */ 3571/* :pv_api_ip pointer to input structure */ 3572/* :pv_api_op pointer to output structure */ 3573/* Globals : <Does it use any global variables?> */ 3574/* Outputs : */ 3575/* Returns : void */ 3576/* */ 3577/* Issues : none */ 3578/* */ 3579/* Revision History: */ 3580/* */ 3581/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3582/* 22 10 2008 100356 Draft */ 3583/* */ 3584/*****************************************************************************/ 3585WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3586{ 3587 3588 dec_struct_t * ps_dec; 3589 ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op; 3590 ps_ctl_op->u4_error_code = 0; 3591 3592 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3593 UNUSED(pv_api_ip); 3594 /* ! */ 3595 /* Signal flush frame control call */ 3596 ps_dec->u1_flushfrm = 1; 3597 3598 if( ps_dec->u1_init_dec_flag == 1) 3599 { 3600 3601 ih264d_release_pics_in_dpb((void *)ps_dec, 3602 ps_dec->u1_pic_bufs); 3603 ih264d_release_display_bufs(ps_dec); 3604 } 3605 3606 ps_ctl_op->u4_error_code = 3607 ((ivd_ctl_flush_op_t*)ps_dec->pv_dec_out)->u4_error_code; //verify the value 3608 3609 return IV_SUCCESS; 3610 3611} 3612 3613/*****************************************************************************/ 3614/* */ 3615/* Function Name : ih264d_get_status */ 3616/* */ 3617/* Description : */ 3618/* */ 3619/* Inputs :iv_obj_t decoder handle */ 3620/* :pv_api_ip pointer to input structure */ 3621/* :pv_api_op pointer to output structure */ 3622/* Globals : <Does it use any global variables?> */ 3623/* Outputs : */ 3624/* Returns : void */ 3625/* */ 3626/* Issues : none */ 3627/* */ 3628/* Revision History: */ 3629/* */ 3630/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3631/* 22 10 2008 100356 Draft */ 3632/* */ 3633/*****************************************************************************/ 3634 3635WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3636{ 3637 3638 UWORD32 i; 3639 dec_struct_t * ps_dec; 3640 UWORD32 pic_wd, pic_ht; 3641 ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op; 3642 UNUSED(pv_api_ip); 3643 ps_ctl_op->u4_error_code = 0; 3644 3645 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3646 3647 pic_wd = ps_dec->u4_width_at_init; 3648 pic_ht = ps_dec->u4_height_at_init; 3649 3650 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3651 { 3652 ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height; 3653 ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width; 3654 3655 if(0 == ps_dec->u4_share_disp_buf) 3656 { 3657 pic_wd = ps_dec->u2_disp_width; 3658 pic_ht = ps_dec->u2_disp_height; 3659 3660 } 3661 else 3662 { 3663 pic_wd = ps_dec->u2_frm_wd_y; 3664 pic_ht = ps_dec->u2_frm_ht_y; 3665 } 3666 } 3667 else 3668 { 3669 ps_ctl_op->u4_pic_ht = pic_wd; 3670 ps_ctl_op->u4_pic_wd = pic_ht; 3671 3672 if(1 == ps_dec->u4_share_disp_buf) 3673 { 3674 pic_wd += (PAD_LEN_Y_H << 1); 3675 pic_ht += (PAD_LEN_Y_V << 2); 3676 3677 } 3678 3679 } 3680 3681 if(ps_dec->u4_app_disp_width > pic_wd) 3682 pic_wd = ps_dec->u4_app_disp_width; 3683 if(0 == ps_dec->u4_share_disp_buf) 3684 ps_ctl_op->u4_num_disp_bufs = 1; 3685 else 3686 { 3687 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3688 { 3689 UWORD32 level, width_mbs, height_mbs; 3690 3691 level = ps_dec->u4_level_at_init; 3692 width_mbs = ps_dec->u2_frm_wd_in_mbs; 3693 height_mbs = ps_dec->u2_frm_ht_in_mbs; 3694 3695 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) 3696 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames 3697 != 64)) 3698 { 3699 ps_ctl_op->u4_num_disp_bufs = 3700 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2; 3701 } 3702 else 3703 { 3704 /*if VUI is not present assume maximum possible refrence frames for the level, 3705 * as max reorder frames*/ 3706 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new( 3707 level, width_mbs, height_mbs); 3708 } 3709 3710 ps_ctl_op->u4_num_disp_bufs += 3711 ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 3712 } 3713 else 3714 { 3715 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new( 3716 ps_dec->u4_level_at_init, 3717 (ps_dec->u4_width_at_init >> 4), 3718 (ps_dec->u4_height_at_init >> 4)); 3719 3720 ps_ctl_op->u4_num_disp_bufs += 3721 ps_ctl_op->u4_num_disp_bufs; 3722 3723 ps_ctl_op->u4_num_disp_bufs = 3724 MIN(ps_ctl_op->u4_num_disp_bufs, 3725 (ps_dec->u4_num_ref_frames_at_init 3726 + ps_dec->u4_num_reorder_frames_at_init)); 3727 3728 } 3729 3730 ps_ctl_op->u4_num_disp_bufs = MAX( 3731 ps_ctl_op->u4_num_disp_bufs, 6); 3732 ps_ctl_op->u4_num_disp_bufs = MIN( 3733 ps_ctl_op->u4_num_disp_bufs, 32); 3734 } 3735 3736 ps_ctl_op->u4_error_code = ps_dec->i4_error_code; 3737 3738 ps_ctl_op->u4_frame_rate = 0; //make it proper 3739 ps_ctl_op->u4_bit_rate = 0; //make it proper 3740 ps_ctl_op->e_content_type = ps_dec->i4_content_type; 3741 ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format; 3742 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS; 3743 3744 if(ps_dec->u1_chroma_format == IV_YUV_420P) 3745 { 3746 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420; 3747 } 3748 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 3749 { 3750 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 3751 } 3752 else if(ps_dec->u1_chroma_format == IV_RGB_565) 3753 { 3754 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 3755 } 3756 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 3757 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 3758 { 3759 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP; 3760 } 3761 3762 else 3763 { 3764 //Invalid chroma format; Error code may be updated, verify in testing if needed 3765 ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL; 3766 return IV_FAIL; 3767 } 3768 3769 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++) 3770 { 3771 ps_ctl_op->u4_min_in_buf_size[i] = MIN_IN_BUF_SIZE; 3772 } 3773 3774 /*!*/ 3775 if(ps_dec->u1_chroma_format == IV_YUV_420P) 3776 { 3777 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 3778 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 3779 >> 2; 3780 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht) 3781 >> 2; 3782 } 3783 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 3784 { 3785 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 3786 * 2; 3787 ps_ctl_op->u4_min_out_buf_size[1] = 3788 ps_ctl_op->u4_min_out_buf_size[2] = 0; 3789 } 3790 else if(ps_dec->u1_chroma_format == IV_RGB_565) 3791 { 3792 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 3793 * 2; 3794 ps_ctl_op->u4_min_out_buf_size[1] = 3795 ps_ctl_op->u4_min_out_buf_size[2] = 0; 3796 } 3797 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 3798 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 3799 { 3800 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 3801 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 3802 >> 1; 3803 ps_ctl_op->u4_min_out_buf_size[2] = 0; 3804 } 3805 3806 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs; 3807 return IV_SUCCESS; 3808} 3809 3810/*****************************************************************************/ 3811/* */ 3812/* Function Name : ih264d_get_buf_info */ 3813/* */ 3814/* Description : */ 3815/* */ 3816/* Inputs :iv_obj_t decoder handle */ 3817/* :pv_api_ip pointer to input structure */ 3818/* :pv_api_op pointer to output structure */ 3819/* Globals : <Does it use any global variables?> */ 3820/* Outputs : */ 3821/* Returns : void */ 3822/* */ 3823/* Issues : none */ 3824/* */ 3825/* Revision History: */ 3826/* */ 3827/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3828/* 22 10 2008 100356 Draft */ 3829/* */ 3830/*****************************************************************************/ 3831WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3832{ 3833 3834 dec_struct_t * ps_dec; 3835 UWORD8 i = 0; // Default for 420P format 3836 UWORD16 pic_wd, pic_ht; 3837 ivd_ctl_getbufinfo_op_t *ps_ctl_op = 3838 (ivd_ctl_getbufinfo_op_t*)pv_api_op; 3839 UNUSED(pv_api_ip); 3840 ps_ctl_op->u4_error_code = 0; 3841 3842 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3843 3844 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS; 3845 if(ps_dec->u1_chroma_format == IV_YUV_420P) 3846 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420; 3847 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 3848 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 3849 else if(ps_dec->u1_chroma_format == IV_RGB_565) 3850 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 3851 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 3852 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 3853 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP; 3854 3855 else 3856 { 3857 //Invalid chroma format; Error code may be updated, verify in testing if needed 3858 return IV_FAIL; 3859 } 3860 3861 ps_ctl_op->u4_num_disp_bufs = 1; 3862 3863 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++) 3864 { 3865 ps_ctl_op->u4_min_in_buf_size[i] = MIN_IN_BUF_SIZE; 3866 } 3867 3868 pic_wd = ps_dec->u4_width_at_init; 3869 pic_ht = ps_dec->u4_height_at_init; 3870 3871 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3872 { 3873 3874 if(0 == ps_dec->u4_share_disp_buf) 3875 { 3876 pic_wd = ps_dec->u2_disp_width; 3877 pic_ht = ps_dec->u2_disp_height; 3878 3879 } 3880 else 3881 { 3882 pic_wd = ps_dec->u2_frm_wd_y; 3883 pic_ht = ps_dec->u2_frm_ht_y; 3884 } 3885 3886 } 3887 else 3888 { 3889 if(1 == ps_dec->u4_share_disp_buf) 3890 { 3891 pic_wd += (PAD_LEN_Y_H << 1); 3892 pic_ht += (PAD_LEN_Y_V << 2); 3893 3894 } 3895 } 3896 3897 if((WORD32)ps_dec->u4_app_disp_width > pic_wd) 3898 pic_wd = ps_dec->u4_app_disp_width; 3899 3900 if(0 == ps_dec->u4_share_disp_buf) 3901 ps_ctl_op->u4_num_disp_bufs = 1; 3902 else 3903 { 3904 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3905 { 3906 UWORD32 level, width_mbs, height_mbs; 3907 3908 level = ps_dec->u4_level_at_init; 3909 width_mbs = ps_dec->u2_frm_wd_in_mbs; 3910 height_mbs = ps_dec->u2_frm_ht_in_mbs; 3911 3912 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) 3913 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames 3914 != 64)) 3915 { 3916 ps_ctl_op->u4_num_disp_bufs = 3917 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2; 3918 } 3919 else 3920 { 3921 /*if VUI is not present assume maximum possible refrence frames for the level, 3922 * as max reorder frames*/ 3923 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new( 3924 level, width_mbs, height_mbs); 3925 } 3926 3927 ps_ctl_op->u4_num_disp_bufs += 3928 ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 3929 3930 } 3931 else 3932 { 3933 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new( 3934 ps_dec->u4_level_at_init, 3935 (ps_dec->u4_width_at_init >> 4), 3936 (ps_dec->u4_height_at_init >> 4)); 3937 3938 ps_ctl_op->u4_num_disp_bufs += 3939 ps_ctl_op->u4_num_disp_bufs; 3940 3941 ps_ctl_op->u4_num_disp_bufs = 3942 MIN(ps_ctl_op->u4_num_disp_bufs, 3943 (ps_dec->u4_num_ref_frames_at_init 3944 + ps_dec->u4_num_reorder_frames_at_init)); 3945 3946 } 3947 3948 ps_ctl_op->u4_num_disp_bufs = MAX( 3949 ps_ctl_op->u4_num_disp_bufs, 6); 3950 ps_ctl_op->u4_num_disp_bufs = MIN( 3951 ps_ctl_op->u4_num_disp_bufs, 32); 3952 } 3953 3954 /*!*/ 3955 if(ps_dec->u1_chroma_format == IV_YUV_420P) 3956 { 3957 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 3958 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 3959 >> 2; 3960 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht) 3961 >> 2; 3962 } 3963 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 3964 { 3965 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 3966 * 2; 3967 ps_ctl_op->u4_min_out_buf_size[1] = 3968 ps_ctl_op->u4_min_out_buf_size[2] = 0; 3969 } 3970 else if(ps_dec->u1_chroma_format == IV_RGB_565) 3971 { 3972 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 3973 * 2; 3974 ps_ctl_op->u4_min_out_buf_size[1] = 3975 ps_ctl_op->u4_min_out_buf_size[2] = 0; 3976 } 3977 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 3978 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 3979 { 3980 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 3981 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 3982 >> 1; 3983 ps_ctl_op->u4_min_out_buf_size[2] = 0; 3984 } 3985 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs; 3986 3987 return IV_SUCCESS; 3988} 3989 3990/*****************************************************************************/ 3991/* */ 3992/* Function Name : ih264d_set_params */ 3993/* */ 3994/* Description : */ 3995/* */ 3996/* Inputs :iv_obj_t decoder handle */ 3997/* :pv_api_ip pointer to input structure */ 3998/* :pv_api_op pointer to output structure */ 3999/* Outputs : */ 4000/* Returns : void */ 4001/* */ 4002/* Issues : none */ 4003/* */ 4004/* Revision History: */ 4005/* */ 4006/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4007/* 22 10 2008 100356 Draft */ 4008/* */ 4009/*****************************************************************************/ 4010WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 4011{ 4012 4013 dec_struct_t * ps_dec; 4014 WORD32 ret = IV_SUCCESS; 4015 4016 ivd_ctl_set_config_ip_t *ps_ctl_ip = 4017 (ivd_ctl_set_config_ip_t *)pv_api_ip; 4018 ivd_ctl_set_config_op_t *ps_ctl_op = 4019 (ivd_ctl_set_config_op_t *)pv_api_op; 4020 4021 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 4022 4023 ps_dec->u4_skip_frm_mask = 0; 4024 4025 ps_ctl_op->u4_error_code = 0; 4026 4027 ps_dec->i4_app_skip_mode = ps_ctl_ip->e_frm_skip_mode; 4028 4029 /*Is it really supported test it when you so the corner testing using test app*/ 4030 4031 if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE) 4032 { 4033 4034 if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_P) 4035 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT; 4036 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_B) 4037 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT; 4038 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_PB) 4039 { 4040 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT; 4041 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT; 4042 } 4043 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_I) 4044 ps_dec->u4_skip_frm_mask |= 1 << I_SLC_BIT; 4045 else 4046 { 4047 //dynamic parameter not supported 4048 //Put an appropriate error code to return the error.. 4049 //when you do the error code tests and after that remove this comment 4050 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 4051 ret = IV_FAIL; 4052 } 4053 } 4054 4055 if((0 != ps_dec->u4_app_disp_width) 4056 && (ps_ctl_ip->u4_disp_wd 4057 != ps_dec->u4_app_disp_width)) 4058 { 4059 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 4060 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID; 4061 ret = IV_FAIL; 4062 } 4063 else 4064 { 4065 if((ps_ctl_ip->u4_disp_wd >= ps_dec->u2_pic_wd)/* && (ps_ctl_ip->u4_disp_wd <= ps_dec->u4_width_at_init) */) 4066 { 4067 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd; 4068 } 4069 else if((0 == ps_dec->i4_header_decoded) /*&& (ps_ctl_ip->u4_disp_wd <= ps_dec->u4_width_at_init)*/) 4070 { 4071 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd; 4072 } 4073 else if(ps_ctl_ip->u4_disp_wd == 0) 4074 { 4075 ps_dec->u4_app_disp_width = 0; 4076 } 4077 else 4078 { 4079 /* 4080 * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF) 4081 * does not propogate. 4082 */ 4083 ps_dec->u4_app_disp_width = 0; 4084 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 4085 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID; 4086 ret = IV_FAIL; 4087 } 4088 } 4089 if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME) 4090 ps_dec->i4_decode_header = 0; 4091 else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER) 4092 ps_dec->i4_decode_header = 1; 4093 else 4094 { 4095 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 4096 ps_dec->i4_decode_header = 1; 4097 ret = IV_FAIL; 4098 } 4099 4100 return ret; 4101 4102} 4103 4104/*****************************************************************************/ 4105/* */ 4106/* Function Name : ih264d_set_default_params */ 4107/* */ 4108/* Description : */ 4109/* */ 4110/* Inputs :iv_obj_t decoder handle */ 4111/* :pv_api_ip pointer to input structure */ 4112/* :pv_api_op pointer to output structure */ 4113/* Outputs : */ 4114/* Returns : void */ 4115/* */ 4116/* Issues : none */ 4117/* */ 4118/* Revision History: */ 4119/* */ 4120/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4121/* 08 08 2011 100421 Copied from set_params */ 4122/* */ 4123/*****************************************************************************/ 4124WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl, 4125 void *pv_api_ip, 4126 void *pv_api_op) 4127{ 4128 4129 dec_struct_t * ps_dec; 4130 WORD32 ret = IV_SUCCESS; 4131 4132 ivd_ctl_set_config_op_t *ps_ctl_op = 4133 (ivd_ctl_set_config_op_t *)pv_api_op; 4134 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 4135 UNUSED(pv_api_ip); 4136 4137 4138 { 4139 ps_dec->u4_app_disp_width = 0; 4140 ps_dec->u4_skip_frm_mask = 0; 4141 ps_dec->i4_decode_header = 1; 4142 4143 ps_ctl_op->u4_error_code = 0; 4144 } 4145 4146 4147 return ret; 4148} 4149 4150/*****************************************************************************/ 4151/* */ 4152/* Function Name : ih264d_reset */ 4153/* */ 4154/* Description : */ 4155/* */ 4156/* Inputs :iv_obj_t decoder handle */ 4157/* :pv_api_ip pointer to input structure */ 4158/* :pv_api_op pointer to output structure */ 4159/* Globals : <Does it use any global variables?> */ 4160/* Outputs : */ 4161/* Returns : void */ 4162/* */ 4163/* Issues : none */ 4164/* */ 4165/* Revision History: */ 4166/* */ 4167/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4168/* 22 10 2008 100356 Draft */ 4169/* */ 4170/*****************************************************************************/ 4171WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 4172{ 4173 dec_struct_t * ps_dec; 4174 ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op; 4175 UNUSED(pv_api_ip); 4176 ps_ctl_op->u4_error_code = 0; 4177 4178 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 4179//CHECK 4180 if(ps_dec != NULL) 4181 { 4182 4183 ih264d_init_decoder(ps_dec); 4184 4185 /* 4186 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t)); 4187 memset(ps_dec->u4_disp_buf_mapping, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 4188 memset(ps_dec->u4_disp_buf_to_be_freed, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 4189 */ 4190 } 4191 else 4192 { 4193 H264_DEC_DEBUG_PRINT( 4194 "\nReset called without Initializing the decoder\n"); 4195 ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE; 4196 } 4197 4198 return IV_SUCCESS; 4199} 4200 4201/*****************************************************************************/ 4202/* */ 4203/* Function Name : ih264d_ctl */ 4204/* */ 4205/* Description : */ 4206/* */ 4207/* Inputs :iv_obj_t decoder handle */ 4208/* :pv_api_ip pointer to input structure */ 4209/* :pv_api_op pointer to output structure */ 4210/* Outputs : */ 4211/* Returns : void */ 4212/* */ 4213/* Issues : none */ 4214/* */ 4215/* Revision History: */ 4216/* */ 4217/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4218/* 22 10 2008 100356 Draft */ 4219/* */ 4220/*****************************************************************************/ 4221WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 4222{ 4223 ivd_ctl_set_config_ip_t *ps_ctl_ip; 4224 ivd_ctl_set_config_op_t *ps_ctl_op; 4225 WORD32 ret = IV_SUCCESS; 4226 UWORD32 subcommand; 4227 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 4228 4229 if(ps_dec->init_done != 1) 4230 { 4231 //Return proper Error Code 4232 return IV_FAIL; 4233 } 4234 ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip; 4235 ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op; 4236 ps_ctl_op->u4_error_code = 0; 4237 subcommand = ps_ctl_ip->e_sub_cmd; 4238 4239 switch(subcommand) 4240 { 4241 case IVD_CMD_CTL_GETPARAMS: 4242 ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip, 4243 (void *)pv_api_op); 4244 break; 4245 case IVD_CMD_CTL_SETPARAMS: 4246 ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip, 4247 (void *)pv_api_op); 4248 break; 4249 case IVD_CMD_CTL_RESET: 4250 ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op); 4251 break; 4252 case IVD_CMD_CTL_SETDEFAULT: 4253 ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip, 4254 (void *)pv_api_op); 4255 break; 4256 case IVD_CMD_CTL_FLUSH: 4257 ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip, 4258 (void *)pv_api_op); 4259 break; 4260 case IVD_CMD_CTL_GETBUFINFO: 4261 ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip, 4262 (void *)pv_api_op); 4263 break; 4264 case IVD_CMD_CTL_GETVERSION: 4265 ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip, 4266 (void *)pv_api_op); 4267 break; 4268 case IH264D_CMD_CTL_DEGRADE: 4269 ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip, 4270 (void *)pv_api_op); 4271 break; 4272 4273 case IH264D_CMD_CTL_SET_NUM_CORES: 4274 ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip, 4275 (void *)pv_api_op); 4276 break; 4277 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS: 4278 ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip, 4279 (void *)pv_api_op); 4280 break; 4281 case IH264D_CMD_CTL_SET_PROCESSOR: 4282 ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip, 4283 (void *)pv_api_op); 4284 break; 4285 default: 4286 H264_DEC_DEBUG_PRINT("\ndo nothing\n") 4287 ; 4288 break; 4289 } 4290 4291 return ret; 4292} 4293/*****************************************************************************/ 4294/* */ 4295/* Function Name : ih264d_rel_display_frame */ 4296/* */ 4297/* Description : */ 4298/* */ 4299/* Inputs :iv_obj_t decoder handle */ 4300/* :pv_api_ip pointer to input structure */ 4301/* :pv_api_op pointer to output structure */ 4302/* Outputs : */ 4303/* Returns : void */ 4304/* */ 4305/* Issues : none */ 4306/* */ 4307/* Revision History: */ 4308/* */ 4309/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4310/* 22 10 2008 100356 Draft */ 4311/* */ 4312/*****************************************************************************/ 4313WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl, 4314 void *pv_api_ip, 4315 void *pv_api_op) 4316{ 4317 4318 ivd_rel_display_frame_ip_t *ps_rel_ip; 4319 ivd_rel_display_frame_op_t *ps_rel_op; 4320 UWORD32 buf_released = 0; 4321 4322 UWORD32 u4_ts = -1; 4323 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 4324 4325 ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip; 4326 ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op; 4327 ps_rel_op->u4_error_code = 0; 4328 u4_ts = ps_rel_ip->u4_disp_buf_id; 4329 4330 if(0 == ps_dec->u4_share_disp_buf) 4331 { 4332 ps_dec->u4_disp_buf_mapping[u4_ts] = 0; 4333 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0; 4334 return IV_SUCCESS; 4335 } 4336 4337 if(ps_dec->pv_pic_buf_mgr != NULL) 4338 { 4339 if(1 == ps_dec->u4_disp_buf_mapping[u4_ts]) 4340 { 4341 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 4342 ps_rel_ip->u4_disp_buf_id, 4343 BUF_MGR_IO); 4344 ps_dec->u4_disp_buf_mapping[u4_ts] = 0; 4345 buf_released = 1; 4346 } 4347 } 4348 4349 if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released)) 4350 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1; 4351 4352 return IV_SUCCESS; 4353} 4354 4355/** 4356 ******************************************************************************* 4357 * 4358 * @brief 4359 * Sets degrade params 4360 * 4361 * @par Description: 4362 * Sets degrade params. 4363 * Refer to ih264d_ctl_degrade_ip_t definition for details 4364 * 4365 * @param[in] ps_codec_obj 4366 * Pointer to codec object at API level 4367 * 4368 * @param[in] pv_api_ip 4369 * Pointer to input argument structure 4370 * 4371 * @param[out] pv_api_op 4372 * Pointer to output argument structure 4373 * 4374 * @returns Status 4375 * 4376 * @remarks 4377 * 4378 * 4379 ******************************************************************************* 4380 */ 4381 4382WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj, 4383 void *pv_api_ip, 4384 void *pv_api_op) 4385{ 4386 ih264d_ctl_degrade_ip_t *ps_ip; 4387 ih264d_ctl_degrade_op_t *ps_op; 4388 dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle; 4389 4390 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip; 4391 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op; 4392 4393 ps_codec->i4_degrade_type = ps_ip->i4_degrade_type; 4394 ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval; 4395 ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics; 4396 4397 ps_op->u4_error_code = 0; 4398 ps_codec->i4_degrade_pic_cnt = 0; 4399 4400 return IV_SUCCESS; 4401} 4402 4403WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl, 4404 void *pv_api_ip, 4405 void *pv_api_op) 4406{ 4407 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip; 4408 ih264d_ctl_get_frame_dimensions_op_t *ps_op; 4409 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 4410 UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset; 4411 4412 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 4413 4414 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op; 4415 UNUSED(ps_ip); 4416 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 4417 { 4418 disp_wd = ps_dec->u2_disp_width; 4419 disp_ht = ps_dec->u2_disp_height; 4420 4421 if(0 == ps_dec->u4_share_disp_buf) 4422 { 4423 buffer_wd = disp_wd; 4424 buffer_ht = disp_ht; 4425 } 4426 else 4427 { 4428 buffer_wd = ps_dec->u2_frm_wd_y; 4429 buffer_ht = ps_dec->u2_frm_ht_y; 4430 } 4431 } 4432 else 4433 { 4434 disp_wd = ps_dec->u4_width_at_init; 4435 disp_ht = ps_dec->u4_height_at_init; 4436 4437 if(0 == ps_dec->u4_share_disp_buf) 4438 { 4439 buffer_wd = disp_wd; 4440 buffer_ht = disp_ht; 4441 } 4442 else 4443 { 4444 buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1); 4445 buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2); 4446 } 4447 } 4448 if(ps_dec->u4_app_disp_width > buffer_wd) 4449 buffer_wd = ps_dec->u4_app_disp_width; 4450 4451 if(0 == ps_dec->u4_share_disp_buf) 4452 { 4453 x_offset = 0; 4454 y_offset = 0; 4455 } 4456 else 4457 { 4458 y_offset = (PAD_LEN_Y_V << 1); 4459 x_offset = PAD_LEN_Y_H; 4460 4461 if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid)) 4462 && (0 != ps_dec->u2_crop_offset_y)) 4463 { 4464 y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y; 4465 x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y; 4466 } 4467 } 4468 4469 ps_op->u4_disp_wd[0] = disp_wd; 4470 ps_op->u4_disp_ht[0] = disp_ht; 4471 ps_op->u4_buffer_wd[0] = buffer_wd; 4472 ps_op->u4_buffer_ht[0] = buffer_ht; 4473 ps_op->u4_x_offset[0] = x_offset; 4474 ps_op->u4_y_offset[0] = y_offset; 4475 4476 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1) 4477 >> 1); 4478 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1) 4479 >> 1); 4480 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0] 4481 >> 1); 4482 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0] 4483 >> 1); 4484 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = 4485 (ps_op->u4_x_offset[0] >> 1); 4486 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = 4487 (ps_op->u4_y_offset[0] >> 1); 4488 4489 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 4490 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 4491 { 4492 ps_op->u4_disp_wd[2] = 0; 4493 ps_op->u4_disp_ht[2] = 0; 4494 ps_op->u4_buffer_wd[2] = 0; 4495 ps_op->u4_buffer_ht[2] = 0; 4496 ps_op->u4_x_offset[2] = 0; 4497 ps_op->u4_y_offset[2] = 0; 4498 4499 ps_op->u4_disp_wd[1] <<= 1; 4500 ps_op->u4_buffer_wd[1] <<= 1; 4501 ps_op->u4_x_offset[1] <<= 1; 4502 } 4503 4504 return IV_SUCCESS; 4505 4506} 4507 4508WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 4509{ 4510 ih264d_ctl_set_num_cores_ip_t *ps_ip; 4511 ih264d_ctl_set_num_cores_op_t *ps_op; 4512 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 4513 4514 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip; 4515 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op; 4516 ps_op->u4_error_code = 0; 4517 ps_dec->u4_num_cores = ps_ip->u4_num_cores; 4518 if(ps_dec->u4_num_cores == 1) 4519 { 4520 ps_dec->u1_separate_parse = 0; 4521 ps_dec->pi4_ctxt_save_register_dec = ps_dec->pi4_ctxt_save_register; 4522 } 4523 else 4524 { 4525 ps_dec->u1_separate_parse = 1; 4526 } 4527 4528 /*using only upto three threads currently*/ 4529 if(ps_dec->u4_num_cores > 3) 4530 ps_dec->u4_num_cores = 3; 4531 4532 return IV_SUCCESS; 4533} 4534 4535void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec, 4536 ivd_video_decode_op_t *ps_dec_op) 4537{ 4538 if((ps_dec_op->u4_error_code & 0xff) 4539 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED) 4540 { 4541 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 4542 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 4543 } 4544 ps_dec_op->e_pic_type = ps_dec->i4_frametype; 4545 4546 ps_dec_op->u4_new_seq = 0; 4547 ps_dec_op->u4_output_present = ps_dec->u4_output_present; 4548 ps_dec_op->u4_progressive_frame_flag = 4549 ps_dec->s_disp_op.u4_progressive_frame_flag; 4550 4551 ps_dec_op->u4_is_ref_flag = 1; 4552 if(ps_dec_op->u4_frame_decoded_flag) 4553 { 4554 if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0) 4555 ps_dec_op->u4_is_ref_flag = 0; 4556 } 4557 4558 ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format; 4559 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf; 4560 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type; 4561 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts; 4562 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id; 4563} 4564 4565/*****************************************************************************/ 4566/* */ 4567/* Function Name : ih264d_api_function */ 4568/* */ 4569/* Description : */ 4570/* */ 4571/* Inputs :iv_obj_t decoder handle */ 4572/* :pv_api_ip pointer to input structure */ 4573/* :pv_api_op pointer to output structure */ 4574/* Outputs : */ 4575/* Returns : void */ 4576/* */ 4577/* Issues : none */ 4578/* */ 4579/* Revision History: */ 4580/* */ 4581/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 4582/* 22 10 2008 100356 Draft */ 4583/* */ 4584/*****************************************************************************/ 4585IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl, 4586 void *pv_api_ip, 4587 void *pv_api_op) 4588{ 4589 UWORD32 command; 4590 UWORD32 *pu2_ptr_cmd; 4591 UWORD32 u4_api_ret; 4592 IV_API_CALL_STATUS_T e_status; 4593 e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op); 4594 4595 if(e_status != IV_SUCCESS) 4596 { 4597 UWORD32 *ptr_err; 4598 4599 ptr_err = (UWORD32 *)pv_api_op; 4600 UNUSED(ptr_err); 4601 H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1)); 4602 return IV_FAIL; 4603 } 4604 4605 pu2_ptr_cmd = (UWORD32 *)pv_api_ip; 4606 pu2_ptr_cmd++; 4607 4608 command = *pu2_ptr_cmd; 4609// H264_DEC_DEBUG_PRINT("inside lib = %d\n",command); 4610 switch(command) 4611 { 4612 4613 case IV_CMD_GET_NUM_MEM_REC: 4614 u4_api_ret = ih264d_get_num_rec((void *)pv_api_ip, 4615 (void *)pv_api_op); 4616 4617 break; 4618 case IV_CMD_FILL_NUM_MEM_REC: 4619 4620 u4_api_ret = ih264d_fill_num_mem_rec((void *)pv_api_ip, 4621 (void *)pv_api_op); 4622 break; 4623 case IV_CMD_INIT: 4624 u4_api_ret = ih264d_init(dec_hdl, (void *)pv_api_ip, 4625 (void *)pv_api_op); 4626 break; 4627 4628 case IVD_CMD_VIDEO_DECODE: 4629 u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip, 4630 (void *)pv_api_op); 4631 break; 4632 4633 case IVD_CMD_GET_DISPLAY_FRAME: 4634 u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip, 4635 (void *)pv_api_op); 4636 4637 break; 4638 4639 case IVD_CMD_SET_DISPLAY_FRAME: 4640 u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip, 4641 (void *)pv_api_op); 4642 4643 break; 4644 4645 case IVD_CMD_REL_DISPLAY_FRAME: 4646 u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip, 4647 (void *)pv_api_op); 4648 break; 4649 4650 case IV_CMD_RETRIEVE_MEMREC: 4651 u4_api_ret = ih264d_clr(dec_hdl, (void *)pv_api_ip, 4652 (void *)pv_api_op); 4653 break; 4654 4655 case IVD_CMD_VIDEO_CTL: 4656 u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip, 4657 (void *)pv_api_op); 4658 break; 4659 default: 4660 u4_api_ret = IV_FAIL; 4661 break; 4662 } 4663 4664 return u4_api_ret; 4665} 4666