i915_drm.h revision 9fb83a49cb7e3db2f168aac5172fafb6fa0d69c8
1/* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27#ifndef _I915_DRM_H_ 28#define _I915_DRM_H_ 29 30#include "drm.h" 31 32/* Please note that modifications to all structs defined here are 33 * subject to backwards-compatibility constraints. 34 */ 35 36/* Each region is a minimum of 16k, and there are at most 255 of them. 37 */ 38#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 39 * of chars for next/prev indices */ 40#define I915_LOG_MIN_TEX_REGION_SIZE 14 41 42typedef struct _drm_i915_init { 43 enum { 44 I915_INIT_DMA = 0x01, 45 I915_CLEANUP_DMA = 0x02, 46 I915_RESUME_DMA = 0x03 47 } func; 48 unsigned int mmio_offset; 49 int sarea_priv_offset; 50 unsigned int ring_start; 51 unsigned int ring_end; 52 unsigned int ring_size; 53 unsigned int front_offset; 54 unsigned int back_offset; 55 unsigned int depth_offset; 56 unsigned int w; 57 unsigned int h; 58 unsigned int pitch; 59 unsigned int pitch_bits; 60 unsigned int back_pitch; 61 unsigned int depth_pitch; 62 unsigned int cpp; 63 unsigned int chipset; 64} drm_i915_init_t; 65 66typedef struct _drm_i915_sarea { 67 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 68 int last_upload; /* last time texture was uploaded */ 69 int last_enqueue; /* last time a buffer was enqueued */ 70 int last_dispatch; /* age of the most recently dispatched buffer */ 71 int ctxOwner; /* last context to upload state */ 72 int texAge; 73 int pf_enabled; /* is pageflipping allowed? */ 74 int pf_active; 75 int pf_current_page; /* which buffer is being displayed? */ 76 int perf_boxes; /* performance boxes to be displayed */ 77 int width, height; /* screen size in pixels */ 78 79 drm_handle_t front_handle; 80 int front_offset; 81 int front_size; 82 83 drm_handle_t back_handle; 84 int back_offset; 85 int back_size; 86 87 drm_handle_t depth_handle; 88 int depth_offset; 89 int depth_size; 90 91 drm_handle_t tex_handle; 92 int tex_offset; 93 int tex_size; 94 int log_tex_granularity; 95 int pitch; 96 int rotation; /* 0, 90, 180 or 270 */ 97 int rotated_offset; 98 int rotated_size; 99 int rotated_pitch; 100 int virtualX, virtualY; 101 102 unsigned int front_tiled; 103 unsigned int back_tiled; 104 unsigned int depth_tiled; 105 unsigned int rotated_tiled; 106 unsigned int rotated2_tiled; 107 108 int pipeA_x; 109 int pipeA_y; 110 int pipeA_w; 111 int pipeA_h; 112 int pipeB_x; 113 int pipeB_y; 114 int pipeB_w; 115 int pipeB_h; 116 117 /* fill out some space for old userspace triple buffer */ 118 drm_handle_t unused_handle; 119 __u32 unused1, unused2, unused3; 120 121 /* buffer object handles for static buffers. May change 122 * over the lifetime of the client. 123 */ 124 __u32 front_bo_handle; 125 __u32 back_bo_handle; 126 __u32 unused_bo_handle; 127 __u32 depth_bo_handle; 128 129} drm_i915_sarea_t; 130 131/* due to userspace building against these headers we need some compat here */ 132#define planeA_x pipeA_x 133#define planeA_y pipeA_y 134#define planeA_w pipeA_w 135#define planeA_h pipeA_h 136#define planeB_x pipeB_x 137#define planeB_y pipeB_y 138#define planeB_w pipeB_w 139#define planeB_h pipeB_h 140 141/* Flags for perf_boxes 142 */ 143#define I915_BOX_RING_EMPTY 0x1 144#define I915_BOX_FLIP 0x2 145#define I915_BOX_WAIT 0x4 146#define I915_BOX_TEXTURE_LOAD 0x8 147#define I915_BOX_LOST_CONTEXT 0x10 148 149/* I915 specific ioctls 150 * The device specific ioctl range is 0x40 to 0x79. 151 */ 152#define DRM_I915_INIT 0x00 153#define DRM_I915_FLUSH 0x01 154#define DRM_I915_FLIP 0x02 155#define DRM_I915_BATCHBUFFER 0x03 156#define DRM_I915_IRQ_EMIT 0x04 157#define DRM_I915_IRQ_WAIT 0x05 158#define DRM_I915_GETPARAM 0x06 159#define DRM_I915_SETPARAM 0x07 160#define DRM_I915_ALLOC 0x08 161#define DRM_I915_FREE 0x09 162#define DRM_I915_INIT_HEAP 0x0a 163#define DRM_I915_CMDBUFFER 0x0b 164#define DRM_I915_DESTROY_HEAP 0x0c 165#define DRM_I915_SET_VBLANK_PIPE 0x0d 166#define DRM_I915_GET_VBLANK_PIPE 0x0e 167#define DRM_I915_VBLANK_SWAP 0x0f 168#define DRM_I915_HWS_ADDR 0x11 169#define DRM_I915_GEM_INIT 0x13 170#define DRM_I915_GEM_EXECBUFFER 0x14 171#define DRM_I915_GEM_PIN 0x15 172#define DRM_I915_GEM_UNPIN 0x16 173#define DRM_I915_GEM_BUSY 0x17 174#define DRM_I915_GEM_THROTTLE 0x18 175#define DRM_I915_GEM_ENTERVT 0x19 176#define DRM_I915_GEM_LEAVEVT 0x1a 177#define DRM_I915_GEM_CREATE 0x1b 178#define DRM_I915_GEM_PREAD 0x1c 179#define DRM_I915_GEM_PWRITE 0x1d 180#define DRM_I915_GEM_MMAP 0x1e 181#define DRM_I915_GEM_SET_DOMAIN 0x1f 182#define DRM_I915_GEM_SW_FINISH 0x20 183#define DRM_I915_GEM_SET_TILING 0x21 184#define DRM_I915_GEM_GET_TILING 0x22 185#define DRM_I915_GEM_GET_APERTURE 0x23 186#define DRM_I915_GEM_MMAP_GTT 0x24 187#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 188#define DRM_I915_GEM_MADVISE 0x26 189#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 190#define DRM_I915_OVERLAY_ATTRS 0x28 191#define DRM_I915_GEM_EXECBUFFER2 0x29 192 193#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 194#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 195#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 196#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 197#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 198#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 199#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 200#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 201#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 202#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 203#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 204#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 205#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 206#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 207#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 208#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 209#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 210#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 211#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 212#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 213#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 214#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 215#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 216#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 217#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 218#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 219#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 220#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 221#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 222#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 223#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 224#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 225#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 226#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 227#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 228#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 229#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 230#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 231#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 232#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 233 234/* Allow drivers to submit batchbuffers directly to hardware, relying 235 * on the security mechanisms provided by hardware. 236 */ 237typedef struct drm_i915_batchbuffer { 238 int start; /* agp offset */ 239 int used; /* nr bytes in use */ 240 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 241 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 242 int num_cliprects; /* mulitpass with multiple cliprects? */ 243 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ 244} drm_i915_batchbuffer_t; 245 246/* As above, but pass a pointer to userspace buffer which can be 247 * validated by the kernel prior to sending to hardware. 248 */ 249typedef struct _drm_i915_cmdbuffer { 250 char *buf; /* pointer to userspace command buffer */ 251 int sz; /* nr bytes in buf */ 252 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 253 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 254 int num_cliprects; /* mulitpass with multiple cliprects? */ 255 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ 256} drm_i915_cmdbuffer_t; 257 258/* Userspace can request & wait on irq's: 259 */ 260typedef struct drm_i915_irq_emit { 261 int *irq_seq; 262} drm_i915_irq_emit_t; 263 264typedef struct drm_i915_irq_wait { 265 int irq_seq; 266} drm_i915_irq_wait_t; 267 268/* Ioctl to query kernel params: 269 */ 270#define I915_PARAM_IRQ_ACTIVE 1 271#define I915_PARAM_ALLOW_BATCHBUFFER 2 272#define I915_PARAM_LAST_DISPATCH 3 273#define I915_PARAM_CHIPSET_ID 4 274#define I915_PARAM_HAS_GEM 5 275#define I915_PARAM_NUM_FENCES_AVAIL 6 276#define I915_PARAM_HAS_OVERLAY 7 277#define I915_PARAM_HAS_PAGEFLIPPING 8 278#define I915_PARAM_HAS_EXECBUF2 9 279#define I915_PARAM_HAS_BSD 10 280#define I915_PARAM_HAS_BLT 11 281#define I915_PARAM_HAS_RELAXED_FENCING 12 282#define I915_PARAM_HAS_COHERENT_RINGS 13 283#define I915_PARAM_HAS_EXEC_CONSTANTS 14 284#define I915_PARAM_HAS_RELAXED_DELTA 15 285#define I915_PARAM_HAS_GEN7_SOL_RESET 16 286 287typedef struct drm_i915_getparam { 288 int param; 289 int *value; 290} drm_i915_getparam_t; 291 292/* Ioctl to set kernel params: 293 */ 294#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 295#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 296#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 297#define I915_SETPARAM_NUM_USED_FENCES 4 298 299typedef struct drm_i915_setparam { 300 int param; 301 int value; 302} drm_i915_setparam_t; 303 304/* A memory manager for regions of shared memory: 305 */ 306#define I915_MEM_REGION_AGP 1 307 308typedef struct drm_i915_mem_alloc { 309 int region; 310 int alignment; 311 int size; 312 int *region_offset; /* offset from start of fb or agp */ 313} drm_i915_mem_alloc_t; 314 315typedef struct drm_i915_mem_free { 316 int region; 317 int region_offset; 318} drm_i915_mem_free_t; 319 320typedef struct drm_i915_mem_init_heap { 321 int region; 322 int size; 323 int start; 324} drm_i915_mem_init_heap_t; 325 326/* Allow memory manager to be torn down and re-initialized (eg on 327 * rotate): 328 */ 329typedef struct drm_i915_mem_destroy_heap { 330 int region; 331} drm_i915_mem_destroy_heap_t; 332 333/* Allow X server to configure which pipes to monitor for vblank signals 334 */ 335#define DRM_I915_VBLANK_PIPE_A 1 336#define DRM_I915_VBLANK_PIPE_B 2 337 338typedef struct drm_i915_vblank_pipe { 339 int pipe; 340} drm_i915_vblank_pipe_t; 341 342/* Schedule buffer swap at given vertical blank: 343 */ 344typedef struct drm_i915_vblank_swap { 345 drm_drawable_t drawable; 346 enum drm_vblank_seq_type seqtype; 347 unsigned int sequence; 348} drm_i915_vblank_swap_t; 349 350typedef struct drm_i915_hws_addr { 351 __u64 addr; 352} drm_i915_hws_addr_t; 353 354struct drm_i915_gem_init { 355 /** 356 * Beginning offset in the GTT to be managed by the DRM memory 357 * manager. 358 */ 359 __u64 gtt_start; 360 /** 361 * Ending offset in the GTT to be managed by the DRM memory 362 * manager. 363 */ 364 __u64 gtt_end; 365}; 366 367struct drm_i915_gem_create { 368 /** 369 * Requested size for the object. 370 * 371 * The (page-aligned) allocated size for the object will be returned. 372 */ 373 __u64 size; 374 /** 375 * Returned handle for the object. 376 * 377 * Object handles are nonzero. 378 */ 379 __u32 handle; 380 __u32 pad; 381}; 382 383struct drm_i915_gem_pread { 384 /** Handle for the object being read. */ 385 __u32 handle; 386 __u32 pad; 387 /** Offset into the object to read from */ 388 __u64 offset; 389 /** Length of data to read */ 390 __u64 size; 391 /** 392 * Pointer to write the data into. 393 * 394 * This is a fixed-size type for 32/64 compatibility. 395 */ 396 __u64 data_ptr; 397}; 398 399struct drm_i915_gem_pwrite { 400 /** Handle for the object being written to. */ 401 __u32 handle; 402 __u32 pad; 403 /** Offset into the object to write to */ 404 __u64 offset; 405 /** Length of data to write */ 406 __u64 size; 407 /** 408 * Pointer to read the data from. 409 * 410 * This is a fixed-size type for 32/64 compatibility. 411 */ 412 __u64 data_ptr; 413}; 414 415struct drm_i915_gem_mmap { 416 /** Handle for the object being mapped. */ 417 __u32 handle; 418 __u32 pad; 419 /** Offset in the object to map. */ 420 __u64 offset; 421 /** 422 * Length of data to map. 423 * 424 * The value will be page-aligned. 425 */ 426 __u64 size; 427 /** 428 * Returned pointer the data was mapped at. 429 * 430 * This is a fixed-size type for 32/64 compatibility. 431 */ 432 __u64 addr_ptr; 433}; 434 435struct drm_i915_gem_mmap_gtt { 436 /** Handle for the object being mapped. */ 437 __u32 handle; 438 __u32 pad; 439 /** 440 * Fake offset to use for subsequent mmap call 441 * 442 * This is a fixed-size type for 32/64 compatibility. 443 */ 444 __u64 offset; 445}; 446 447struct drm_i915_gem_set_domain { 448 /** Handle for the object */ 449 __u32 handle; 450 451 /** New read domains */ 452 __u32 read_domains; 453 454 /** New write domain */ 455 __u32 write_domain; 456}; 457 458struct drm_i915_gem_sw_finish { 459 /** Handle for the object */ 460 __u32 handle; 461}; 462 463struct drm_i915_gem_relocation_entry { 464 /** 465 * Handle of the buffer being pointed to by this relocation entry. 466 * 467 * It's appealing to make this be an index into the mm_validate_entry 468 * list to refer to the buffer, but this allows the driver to create 469 * a relocation list for state buffers and not re-write it per 470 * exec using the buffer. 471 */ 472 __u32 target_handle; 473 474 /** 475 * Value to be added to the offset of the target buffer to make up 476 * the relocation entry. 477 */ 478 __u32 delta; 479 480 /** Offset in the buffer the relocation entry will be written into */ 481 __u64 offset; 482 483 /** 484 * Offset value of the target buffer that the relocation entry was last 485 * written as. 486 * 487 * If the buffer has the same offset as last time, we can skip syncing 488 * and writing the relocation. This value is written back out by 489 * the execbuffer ioctl when the relocation is written. 490 */ 491 __u64 presumed_offset; 492 493 /** 494 * Target memory domains read by this operation. 495 */ 496 __u32 read_domains; 497 498 /** 499 * Target memory domains written by this operation. 500 * 501 * Note that only one domain may be written by the whole 502 * execbuffer operation, so that where there are conflicts, 503 * the application will get -EINVAL back. 504 */ 505 __u32 write_domain; 506}; 507 508/** @{ 509 * Intel memory domains 510 * 511 * Most of these just align with the various caches in 512 * the system and are used to flush and invalidate as 513 * objects end up cached in different domains. 514 */ 515/** CPU cache */ 516#define I915_GEM_DOMAIN_CPU 0x00000001 517/** Render cache, used by 2D and 3D drawing */ 518#define I915_GEM_DOMAIN_RENDER 0x00000002 519/** Sampler cache, used by texture engine */ 520#define I915_GEM_DOMAIN_SAMPLER 0x00000004 521/** Command queue, used to load batch buffers */ 522#define I915_GEM_DOMAIN_COMMAND 0x00000008 523/** Instruction cache, used by shader programs */ 524#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 525/** Vertex address cache */ 526#define I915_GEM_DOMAIN_VERTEX 0x00000020 527/** GTT domain - aperture and scanout */ 528#define I915_GEM_DOMAIN_GTT 0x00000040 529/** @} */ 530 531struct drm_i915_gem_exec_object { 532 /** 533 * User's handle for a buffer to be bound into the GTT for this 534 * operation. 535 */ 536 __u32 handle; 537 538 /** Number of relocations to be performed on this buffer */ 539 __u32 relocation_count; 540 /** 541 * Pointer to array of struct drm_i915_gem_relocation_entry containing 542 * the relocations to be performed in this buffer. 543 */ 544 __u64 relocs_ptr; 545 546 /** Required alignment in graphics aperture */ 547 __u64 alignment; 548 549 /** 550 * Returned value of the updated offset of the object, for future 551 * presumed_offset writes. 552 */ 553 __u64 offset; 554}; 555 556struct drm_i915_gem_execbuffer { 557 /** 558 * List of buffers to be validated with their relocations to be 559 * performend on them. 560 * 561 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 562 * 563 * These buffers must be listed in an order such that all relocations 564 * a buffer is performing refer to buffers that have already appeared 565 * in the validate list. 566 */ 567 __u64 buffers_ptr; 568 __u32 buffer_count; 569 570 /** Offset in the batchbuffer to start execution from. */ 571 __u32 batch_start_offset; 572 /** Bytes used in batchbuffer from batch_start_offset */ 573 __u32 batch_len; 574 __u32 DR1; 575 __u32 DR4; 576 __u32 num_cliprects; 577 /** This is a struct drm_clip_rect *cliprects */ 578 __u64 cliprects_ptr; 579}; 580 581struct drm_i915_gem_exec_object2 { 582 /** 583 * User's handle for a buffer to be bound into the GTT for this 584 * operation. 585 */ 586 __u32 handle; 587 588 /** Number of relocations to be performed on this buffer */ 589 __u32 relocation_count; 590 /** 591 * Pointer to array of struct drm_i915_gem_relocation_entry containing 592 * the relocations to be performed in this buffer. 593 */ 594 __u64 relocs_ptr; 595 596 /** Required alignment in graphics aperture */ 597 __u64 alignment; 598 599 /** 600 * Returned value of the updated offset of the object, for future 601 * presumed_offset writes. 602 */ 603 __u64 offset; 604 605#define EXEC_OBJECT_NEEDS_FENCE (1<<0) 606 __u64 flags; 607 __u64 rsvd1; 608 __u64 rsvd2; 609}; 610 611struct drm_i915_gem_execbuffer2 { 612 /** 613 * List of gem_exec_object2 structs 614 */ 615 __u64 buffers_ptr; 616 __u32 buffer_count; 617 618 /** Offset in the batchbuffer to start execution from. */ 619 __u32 batch_start_offset; 620 /** Bytes used in batchbuffer from batch_start_offset */ 621 __u32 batch_len; 622 __u32 DR1; 623 __u32 DR4; 624 __u32 num_cliprects; 625 /** This is a struct drm_clip_rect *cliprects */ 626 __u64 cliprects_ptr; 627#define I915_EXEC_RING_MASK (7<<0) 628#define I915_EXEC_DEFAULT (0<<0) 629#define I915_EXEC_RENDER (1<<0) 630#define I915_EXEC_BSD (2<<0) 631#define I915_EXEC_BLT (3<<0) 632 633/* Used for switching the constants addressing mode on gen4+ RENDER ring. 634 * Gen6+ only supports relative addressing to dynamic state (default) and 635 * absolute addressing. 636 * 637 * These flags are ignored for the BSD and BLT rings. 638 */ 639#define I915_EXEC_CONSTANTS_MASK (3<<6) 640#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 641#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 642#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 643 __u64 flags; 644 __u64 rsvd1; 645 __u64 rsvd2; 646}; 647 648/** Resets the SO write offset registers for transform feedback on gen7. */ 649#define I915_EXEC_GEN7_SOL_RESET (1<<8) 650 651struct drm_i915_gem_pin { 652 /** Handle of the buffer to be pinned. */ 653 __u32 handle; 654 __u32 pad; 655 656 /** alignment required within the aperture */ 657 __u64 alignment; 658 659 /** Returned GTT offset of the buffer. */ 660 __u64 offset; 661}; 662 663struct drm_i915_gem_unpin { 664 /** Handle of the buffer to be unpinned. */ 665 __u32 handle; 666 __u32 pad; 667}; 668 669struct drm_i915_gem_busy { 670 /** Handle of the buffer to check for busy */ 671 __u32 handle; 672 673 /** Return busy status (1 if busy, 0 if idle) */ 674 __u32 busy; 675}; 676 677#define I915_TILING_NONE 0 678#define I915_TILING_X 1 679#define I915_TILING_Y 2 680 681#define I915_BIT_6_SWIZZLE_NONE 0 682#define I915_BIT_6_SWIZZLE_9 1 683#define I915_BIT_6_SWIZZLE_9_10 2 684#define I915_BIT_6_SWIZZLE_9_11 3 685#define I915_BIT_6_SWIZZLE_9_10_11 4 686/* Not seen by userland */ 687#define I915_BIT_6_SWIZZLE_UNKNOWN 5 688/* Seen by userland. */ 689#define I915_BIT_6_SWIZZLE_9_17 6 690#define I915_BIT_6_SWIZZLE_9_10_17 7 691 692struct drm_i915_gem_set_tiling { 693 /** Handle of the buffer to have its tiling state updated */ 694 __u32 handle; 695 696 /** 697 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 698 * I915_TILING_Y). 699 * 700 * This value is to be set on request, and will be updated by the 701 * kernel on successful return with the actual chosen tiling layout. 702 * 703 * The tiling mode may be demoted to I915_TILING_NONE when the system 704 * has bit 6 swizzling that can't be managed correctly by GEM. 705 * 706 * Buffer contents become undefined when changing tiling_mode. 707 */ 708 __u32 tiling_mode; 709 710 /** 711 * Stride in bytes for the object when in I915_TILING_X or 712 * I915_TILING_Y. 713 */ 714 __u32 stride; 715 716 /** 717 * Returned address bit 6 swizzling required for CPU access through 718 * mmap mapping. 719 */ 720 __u32 swizzle_mode; 721}; 722 723struct drm_i915_gem_get_tiling { 724 /** Handle of the buffer to get tiling state for. */ 725 __u32 handle; 726 727 /** 728 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 729 * I915_TILING_Y). 730 */ 731 __u32 tiling_mode; 732 733 /** 734 * Returned address bit 6 swizzling required for CPU access through 735 * mmap mapping. 736 */ 737 __u32 swizzle_mode; 738}; 739 740struct drm_i915_gem_get_aperture { 741 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 742 __u64 aper_size; 743 744 /** 745 * Available space in the aperture used by i915_gem_execbuffer, in 746 * bytes 747 */ 748 __u64 aper_available_size; 749}; 750 751struct drm_i915_get_pipe_from_crtc_id { 752 /** ID of CRTC being requested **/ 753 __u32 crtc_id; 754 755 /** pipe of requested CRTC **/ 756 __u32 pipe; 757}; 758 759#define I915_MADV_WILLNEED 0 760#define I915_MADV_DONTNEED 1 761#define __I915_MADV_PURGED 2 /* internal state */ 762 763struct drm_i915_gem_madvise { 764 /** Handle of the buffer to change the backing store advice */ 765 __u32 handle; 766 767 /* Advice: either the buffer will be needed again in the near future, 768 * or wont be and could be discarded under memory pressure. 769 */ 770 __u32 madv; 771 772 /** Whether the backing store still exists. */ 773 __u32 retained; 774}; 775 776/* flags */ 777#define I915_OVERLAY_TYPE_MASK 0xff 778#define I915_OVERLAY_YUV_PLANAR 0x01 779#define I915_OVERLAY_YUV_PACKED 0x02 780#define I915_OVERLAY_RGB 0x03 781 782#define I915_OVERLAY_DEPTH_MASK 0xff00 783#define I915_OVERLAY_RGB24 0x1000 784#define I915_OVERLAY_RGB16 0x2000 785#define I915_OVERLAY_RGB15 0x3000 786#define I915_OVERLAY_YUV422 0x0100 787#define I915_OVERLAY_YUV411 0x0200 788#define I915_OVERLAY_YUV420 0x0300 789#define I915_OVERLAY_YUV410 0x0400 790 791#define I915_OVERLAY_SWAP_MASK 0xff0000 792#define I915_OVERLAY_NO_SWAP 0x000000 793#define I915_OVERLAY_UV_SWAP 0x010000 794#define I915_OVERLAY_Y_SWAP 0x020000 795#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 796 797#define I915_OVERLAY_FLAGS_MASK 0xff000000 798#define I915_OVERLAY_ENABLE 0x01000000 799 800struct drm_intel_overlay_put_image { 801 /* various flags and src format description */ 802 __u32 flags; 803 /* source picture description */ 804 __u32 bo_handle; 805 /* stride values and offsets are in bytes, buffer relative */ 806 __u16 stride_Y; /* stride for packed formats */ 807 __u16 stride_UV; 808 __u32 offset_Y; /* offset for packet formats */ 809 __u32 offset_U; 810 __u32 offset_V; 811 /* in pixels */ 812 __u16 src_width; 813 __u16 src_height; 814 /* to compensate the scaling factors for partially covered surfaces */ 815 __u16 src_scan_width; 816 __u16 src_scan_height; 817 /* output crtc description */ 818 __u32 crtc_id; 819 __u16 dst_x; 820 __u16 dst_y; 821 __u16 dst_width; 822 __u16 dst_height; 823}; 824 825/* flags */ 826#define I915_OVERLAY_UPDATE_ATTRS (1<<0) 827#define I915_OVERLAY_UPDATE_GAMMA (1<<1) 828struct drm_intel_overlay_attrs { 829 __u32 flags; 830 __u32 color_key; 831 __s32 brightness; 832 __u32 contrast; 833 __u32 saturation; 834 __u32 gamma0; 835 __u32 gamma1; 836 __u32 gamma2; 837 __u32 gamma3; 838 __u32 gamma4; 839 __u32 gamma5; 840}; 841 842#endif /* _I915_DRM_H_ */ 843