FastISel.h revision 425e951734c3a0615e22ec94ffa51cc16ce6e483
1//===-- FastISel.h - Definition of the FastISel class ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the FastISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_FASTISEL_H 15#define LLVM_CODEGEN_FASTISEL_H 16 17#include "llvm/ADT/DenseMap.h" 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/CodeGen/ValueTypes.h" 20 21namespace llvm { 22 23class AllocaInst; 24class Constant; 25class ConstantFP; 26class FunctionLoweringInfo; 27class Instruction; 28class LoadInst; 29class MachineBasicBlock; 30class MachineConstantPool; 31class MachineFunction; 32class MachineInstr; 33class MachineFrameInfo; 34class MachineRegisterInfo; 35class DataLayout; 36class TargetInstrInfo; 37class TargetLibraryInfo; 38class TargetLowering; 39class TargetMachine; 40class TargetRegisterClass; 41class TargetRegisterInfo; 42class User; 43class Value; 44 45/// FastISel - This is a fast-path instruction selection class that 46/// generates poor code and doesn't support illegal types or non-trivial 47/// lowering, but runs quickly. 48class FastISel { 49protected: 50 DenseMap<const Value *, unsigned> LocalValueMap; 51 FunctionLoweringInfo &FuncInfo; 52 MachineRegisterInfo &MRI; 53 MachineFrameInfo &MFI; 54 MachineConstantPool &MCP; 55 DebugLoc DL; 56 const TargetMachine &TM; 57 const DataLayout &TD; 58 const TargetInstrInfo &TII; 59 const TargetLowering &TLI; 60 const TargetRegisterInfo &TRI; 61 const TargetLibraryInfo *LibInfo; 62 63 /// The position of the last instruction for materializing constants 64 /// for use in the current block. It resets to EmitStartPt when it 65 /// makes sense (for example, it's usually profitable to avoid function 66 /// calls between the definition and the use) 67 MachineInstr *LastLocalValue; 68 69 /// The top most instruction in the current block that is allowed for 70 /// emitting local variables. LastLocalValue resets to EmitStartPt when 71 /// it makes sense (for example, on function calls) 72 MachineInstr *EmitStartPt; 73 74public: 75 /// getLastLocalValue - Return the position of the last instruction 76 /// emitted for materializing constants for use in the current block. 77 MachineInstr *getLastLocalValue() { return LastLocalValue; } 78 79 /// setLastLocalValue - Update the position of the last instruction 80 /// emitted for materializing constants for use in the current block. 81 void setLastLocalValue(MachineInstr *I) { 82 EmitStartPt = I; 83 LastLocalValue = I; 84 } 85 86 /// startNewBlock - Set the current block to which generated machine 87 /// instructions will be appended, and clear the local CSE map. 88 /// 89 void startNewBlock(); 90 91 /// getCurDebugLoc() - Return current debug location information. 92 DebugLoc getCurDebugLoc() const { return DL; } 93 94 /// SelectInstruction - Do "fast" instruction selection for the given 95 /// LLVM IR instruction, and append generated machine instructions to 96 /// the current block. Return true if selection was successful. 97 /// 98 bool SelectInstruction(const Instruction *I); 99 100 /// SelectOperator - Do "fast" instruction selection for the given 101 /// LLVM IR operator (Instruction or ConstantExpr), and append 102 /// generated machine instructions to the current block. Return true 103 /// if selection was successful. 104 /// 105 bool SelectOperator(const User *I, unsigned Opcode); 106 107 /// getRegForValue - Create a virtual register and arrange for it to 108 /// be assigned the value for the given LLVM value. 109 unsigned getRegForValue(const Value *V); 110 111 /// lookUpRegForValue - Look up the value to see if its value is already 112 /// cached in a register. It may be defined by instructions across blocks or 113 /// defined locally. 114 unsigned lookUpRegForValue(const Value *V); 115 116 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also 117 /// takes care of truncating or sign-extending the given getelementptr 118 /// index value. 119 std::pair<unsigned, bool> getRegForGEPIndex(const Value *V); 120 121 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that 122 /// vreg is being provided by the specified load instruction. If possible, 123 /// try to fold the load as an operand to the instruction, returning true if 124 /// possible. 125 virtual bool TryToFoldLoad(MachineInstr * /*MI*/, unsigned /*OpNo*/, 126 const LoadInst * /*LI*/) { 127 return false; 128 } 129 130 /// recomputeInsertPt - Reset InsertPt to prepare for inserting instructions 131 /// into the current block. 132 void recomputeInsertPt(); 133 134 /// removeDeadCode - Remove all dead instructions between the I and E. 135 void removeDeadCode(MachineBasicBlock::iterator I, 136 MachineBasicBlock::iterator E); 137 138 struct SavePoint { 139 MachineBasicBlock::iterator InsertPt; 140 DebugLoc DL; 141 }; 142 143 /// enterLocalValueArea - Prepare InsertPt to begin inserting instructions 144 /// into the local value area and return the old insert position. 145 SavePoint enterLocalValueArea(); 146 147 /// leaveLocalValueArea - Reset InsertPt to the given old insert position. 148 void leaveLocalValueArea(SavePoint Old); 149 150 virtual ~FastISel(); 151 152protected: 153 explicit FastISel(FunctionLoweringInfo &funcInfo, 154 const TargetLibraryInfo *libInfo); 155 156 /// TargetSelectInstruction - This method is called by target-independent 157 /// code when the normal FastISel process fails to select an instruction. 158 /// This gives targets a chance to emit code for anything that doesn't 159 /// fit into FastISel's framework. It returns true if it was successful. 160 /// 161 virtual bool 162 TargetSelectInstruction(const Instruction *I) = 0; 163 164 /// FastEmit_r - This method is called by target-independent code 165 /// to request that an instruction with the given type and opcode 166 /// be emitted. 167 virtual unsigned FastEmit_(MVT VT, 168 MVT RetVT, 169 unsigned Opcode); 170 171 /// FastEmit_r - This method is called by target-independent code 172 /// to request that an instruction with the given type, opcode, and 173 /// register operand be emitted. 174 /// 175 virtual unsigned FastEmit_r(MVT VT, 176 MVT RetVT, 177 unsigned Opcode, 178 unsigned Op0, bool Op0IsKill); 179 180 /// FastEmit_rr - This method is called by target-independent code 181 /// to request that an instruction with the given type, opcode, and 182 /// register operands be emitted. 183 /// 184 virtual unsigned FastEmit_rr(MVT VT, 185 MVT RetVT, 186 unsigned Opcode, 187 unsigned Op0, bool Op0IsKill, 188 unsigned Op1, bool Op1IsKill); 189 190 /// FastEmit_ri - This method is called by target-independent code 191 /// to request that an instruction with the given type, opcode, and 192 /// register and immediate operands be emitted. 193 /// 194 virtual unsigned FastEmit_ri(MVT VT, 195 MVT RetVT, 196 unsigned Opcode, 197 unsigned Op0, bool Op0IsKill, 198 uint64_t Imm); 199 200 /// FastEmit_rf - This method is called by target-independent code 201 /// to request that an instruction with the given type, opcode, and 202 /// register and floating-point immediate operands be emitted. 203 /// 204 virtual unsigned FastEmit_rf(MVT VT, 205 MVT RetVT, 206 unsigned Opcode, 207 unsigned Op0, bool Op0IsKill, 208 const ConstantFP *FPImm); 209 210 /// FastEmit_rri - This method is called by target-independent code 211 /// to request that an instruction with the given type, opcode, and 212 /// register and immediate operands be emitted. 213 /// 214 virtual unsigned FastEmit_rri(MVT VT, 215 MVT RetVT, 216 unsigned Opcode, 217 unsigned Op0, bool Op0IsKill, 218 unsigned Op1, bool Op1IsKill, 219 uint64_t Imm); 220 221 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 222 /// to emit an instruction with an immediate operand using FastEmit_ri. 223 /// If that fails, it materializes the immediate into a register and try 224 /// FastEmit_rr instead. 225 unsigned FastEmit_ri_(MVT VT, 226 unsigned Opcode, 227 unsigned Op0, bool Op0IsKill, 228 uint64_t Imm, MVT ImmType); 229 230 /// FastEmit_i - This method is called by target-independent code 231 /// to request that an instruction with the given type, opcode, and 232 /// immediate operand be emitted. 233 virtual unsigned FastEmit_i(MVT VT, 234 MVT RetVT, 235 unsigned Opcode, 236 uint64_t Imm); 237 238 /// FastEmit_f - This method is called by target-independent code 239 /// to request that an instruction with the given type, opcode, and 240 /// floating-point immediate operand be emitted. 241 virtual unsigned FastEmit_f(MVT VT, 242 MVT RetVT, 243 unsigned Opcode, 244 const ConstantFP *FPImm); 245 246 /// FastEmitInst_ - Emit a MachineInstr with no operands and a 247 /// result register in the given register class. 248 /// 249 unsigned FastEmitInst_(unsigned MachineInstOpcode, 250 const TargetRegisterClass *RC); 251 252 /// FastEmitInst_r - Emit a MachineInstr with one register operand 253 /// and a result register in the given register class. 254 /// 255 unsigned FastEmitInst_r(unsigned MachineInstOpcode, 256 const TargetRegisterClass *RC, 257 unsigned Op0, bool Op0IsKill); 258 259 /// FastEmitInst_rr - Emit a MachineInstr with two register operands 260 /// and a result register in the given register class. 261 /// 262 unsigned FastEmitInst_rr(unsigned MachineInstOpcode, 263 const TargetRegisterClass *RC, 264 unsigned Op0, bool Op0IsKill, 265 unsigned Op1, bool Op1IsKill); 266 267 /// FastEmitInst_rrr - Emit a MachineInstr with three register operands 268 /// and a result register in the given register class. 269 /// 270 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode, 271 const TargetRegisterClass *RC, 272 unsigned Op0, bool Op0IsKill, 273 unsigned Op1, bool Op1IsKill, 274 unsigned Op2, bool Op2IsKill); 275 276 /// FastEmitInst_ri - Emit a MachineInstr with a register operand, 277 /// an immediate, and a result register in the given register class. 278 /// 279 unsigned FastEmitInst_ri(unsigned MachineInstOpcode, 280 const TargetRegisterClass *RC, 281 unsigned Op0, bool Op0IsKill, 282 uint64_t Imm); 283 284 /// FastEmitInst_rii - Emit a MachineInstr with one register operand 285 /// and two immediate operands. 286 /// 287 unsigned FastEmitInst_rii(unsigned MachineInstOpcode, 288 const TargetRegisterClass *RC, 289 unsigned Op0, bool Op0IsKill, 290 uint64_t Imm1, uint64_t Imm2); 291 292 /// FastEmitInst_rf - Emit a MachineInstr with two register operands 293 /// and a result register in the given register class. 294 /// 295 unsigned FastEmitInst_rf(unsigned MachineInstOpcode, 296 const TargetRegisterClass *RC, 297 unsigned Op0, bool Op0IsKill, 298 const ConstantFP *FPImm); 299 300 /// FastEmitInst_rri - Emit a MachineInstr with two register operands, 301 /// an immediate, and a result register in the given register class. 302 /// 303 unsigned FastEmitInst_rri(unsigned MachineInstOpcode, 304 const TargetRegisterClass *RC, 305 unsigned Op0, bool Op0IsKill, 306 unsigned Op1, bool Op1IsKill, 307 uint64_t Imm); 308 309 /// FastEmitInst_rrii - Emit a MachineInstr with two register operands, 310 /// two immediates operands, and a result register in the given register 311 /// class. 312 unsigned FastEmitInst_rrii(unsigned MachineInstOpcode, 313 const TargetRegisterClass *RC, 314 unsigned Op0, bool Op0IsKill, 315 unsigned Op1, bool Op1IsKill, 316 uint64_t Imm1, uint64_t Imm2); 317 318 /// FastEmitInst_i - Emit a MachineInstr with a single immediate 319 /// operand, and a result register in the given register class. 320 unsigned FastEmitInst_i(unsigned MachineInstrOpcode, 321 const TargetRegisterClass *RC, 322 uint64_t Imm); 323 324 /// FastEmitInst_ii - Emit a MachineInstr with a two immediate operands. 325 unsigned FastEmitInst_ii(unsigned MachineInstrOpcode, 326 const TargetRegisterClass *RC, 327 uint64_t Imm1, uint64_t Imm2); 328 329 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg 330 /// from a specified index of a superregister to a specified type. 331 unsigned FastEmitInst_extractsubreg(MVT RetVT, 332 unsigned Op0, bool Op0IsKill, 333 uint32_t Idx); 334 335 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 336 /// with all but the least significant bit set to zero. 337 unsigned FastEmitZExtFromI1(MVT VT, 338 unsigned Op0, bool Op0IsKill); 339 340 /// FastEmitBranch - Emit an unconditional branch to the given block, 341 /// unless it is the immediate (fall-through) successor, and update 342 /// the CFG. 343 void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL); 344 345 void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1); 346 347 unsigned createResultReg(const TargetRegisterClass *RC); 348 349 /// TargetMaterializeConstant - Emit a constant in a register using 350 /// target-specific logic, such as constant pool loads. 351 virtual unsigned TargetMaterializeConstant(const Constant* C) { 352 return 0; 353 } 354 355 /// TargetMaterializeAlloca - Emit an alloca address in a register using 356 /// target-specific logic. 357 virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) { 358 return 0; 359 } 360 361 virtual unsigned TargetMaterializeFloatZero(const ConstantFP* CF) { 362 return 0; 363 } 364 365private: 366 bool SelectBinaryOp(const User *I, unsigned ISDOpcode); 367 368 bool SelectFNeg(const User *I); 369 370 bool SelectGetElementPtr(const User *I); 371 372 bool SelectCall(const User *I); 373 374 bool SelectBitCast(const User *I); 375 376 bool SelectCast(const User *I, unsigned Opcode); 377 378 bool SelectExtractValue(const User *I); 379 380 bool SelectInsertValue(const User *I); 381 382 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks. 383 /// Emit code to ensure constants are copied into registers when needed. 384 /// Remember the virtual registers that need to be added to the Machine PHI 385 /// nodes as input. We cannot just directly add them, because expansion 386 /// might result in multiple MBB's for one BB. As such, the start of the 387 /// BB might correspond to a different MBB than the end. 388 bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB); 389 390 /// materializeRegForValue - Helper for getRegForVale. This function is 391 /// called when the value isn't already available in a register and must 392 /// be materialized with new instructions. 393 unsigned materializeRegForValue(const Value *V, MVT VT); 394 395 /// flushLocalValueMap - clears LocalValueMap and moves the area for the 396 /// new local variables to the beginning of the block. It helps to avoid 397 /// spilling cached variables across heavy instructions like calls. 398 void flushLocalValueMap(); 399 400 /// hasTrivialKill - Test whether the given value has exactly one use. 401 bool hasTrivialKill(const Value *V) const; 402}; 403 404} 405 406#endif 407