FastISel.h revision 59fbc80f6b3b5c71dfb84149f589625f7ed510e3 
1//===-- FastISel.h - Definition of the FastISel class ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_FASTISEL_H
15#define LLVM_CODEGEN_FASTISEL_H
16
17#include "llvm/BasicBlock.h"
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/CodeGen/SelectionDAGNodes.h"
20
21namespace llvm {
22
23class ConstantFP;
24class MachineBasicBlock;
25class MachineConstantPool;
26class MachineFunction;
27class MachineRegisterInfo;
28class TargetData;
29class TargetInstrInfo;
30class TargetLowering;
31class TargetMachine;
32class TargetRegisterClass;
33
34/// FastISel - This is a fast-path instruction selection class that
35/// generates poor code and doesn't support illegal types or non-trivial
36/// lowering, but runs quickly.
37class FastISel {
38protected:
39  MachineBasicBlock *MBB;
40  DenseMap<const Value *, unsigned> LocalValueMap;
41  DenseMap<const Value *, unsigned> &ValueMap;
42  DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
43  MachineFunction &MF;
44  MachineRegisterInfo &MRI;
45  const TargetMachine &TM;
46  const TargetData &TD;
47  const TargetInstrInfo &TII;
48  const TargetLowering &TLI;
49
50public:
51  /// setCurrentBlock - Set the current block, to which generated
52  /// machine instructions will be appended.
53  ///
54  void setCurrentBlock(MachineBasicBlock *mbb) {
55    MBB = mbb;
56  }
57
58  /// SelectInstruction - Do "fast" instruction selection for the given
59  /// LLVM IR instruction, and append generated machine instructions to
60  /// the current block. Return true if selection was successful.
61  ///
62  bool SelectInstruction(Instruction *I);
63
64  /// SelectInstruction - Do "fast" instruction selection for the given
65  /// LLVM IR operator (Instruction or ConstantExpr), and append
66  /// generated machine instructions to the current block. Return true
67  /// if selection was successful.
68  ///
69  bool SelectOperator(User *I, unsigned Opcode);
70
71  /// TargetSelectInstruction - This method is called by target-independent
72  /// code when the normal FastISel process fails to select an instruction.
73  /// This gives targets a chance to emit code for anything that doesn't
74  /// fit into FastISel's framework. It returns true if it was successful.
75  ///
76  virtual bool
77  TargetSelectInstruction(Instruction *I) = 0;
78
79  /// getRegForValue - Create a virtual register and arrange for it to
80  /// be assigned the value for the given LLVM value.
81  unsigned getRegForValue(Value *V);
82
83  /// lookUpRegForValue - Look up the value to see if its value is already
84  /// cached in a register. It may be defined by instructions across blocks or
85  /// defined locally.
86  unsigned lookUpRegForValue(Value *V);
87
88  virtual ~FastISel();
89
90protected:
91  FastISel(MachineFunction &mf,
92           DenseMap<const Value *, unsigned> &vm,
93           DenseMap<const BasicBlock *, MachineBasicBlock *> &bm);
94
95  /// FastEmit_r - This method is called by target-independent code
96  /// to request that an instruction with the given type and opcode
97  /// be emitted.
98  virtual unsigned FastEmit_(MVT::SimpleValueType VT,
99                             MVT::SimpleValueType RetVT,
100                             ISD::NodeType Opcode);
101
102  /// FastEmit_r - This method is called by target-independent code
103  /// to request that an instruction with the given type, opcode, and
104  /// register operand be emitted.
105  ///
106  virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
107                              MVT::SimpleValueType RetVT,
108                              ISD::NodeType Opcode, unsigned Op0);
109
110  /// FastEmit_rr - This method is called by target-independent code
111  /// to request that an instruction with the given type, opcode, and
112  /// register operands be emitted.
113  ///
114  virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
115                               MVT::SimpleValueType RetVT,
116                               ISD::NodeType Opcode,
117                               unsigned Op0, unsigned Op1);
118
119  /// FastEmit_ri - This method is called by target-independent code
120  /// to request that an instruction with the given type, opcode, and
121  /// register and immediate operands be emitted.
122  ///
123  virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
124                               MVT::SimpleValueType RetVT,
125                               ISD::NodeType Opcode,
126                               unsigned Op0, uint64_t Imm);
127
128  /// FastEmit_rf - This method is called by target-independent code
129  /// to request that an instruction with the given type, opcode, and
130  /// register and floating-point immediate operands be emitted.
131  ///
132  virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
133                               MVT::SimpleValueType RetVT,
134                               ISD::NodeType Opcode,
135                               unsigned Op0, ConstantFP *FPImm);
136
137  /// FastEmit_rri - This method is called by target-independent code
138  /// to request that an instruction with the given type, opcode, and
139  /// register and immediate operands be emitted.
140  ///
141  virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
142                                MVT::SimpleValueType RetVT,
143                                ISD::NodeType Opcode,
144                                unsigned Op0, unsigned Op1, uint64_t Imm);
145
146  /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
147  /// to emit an instruction with an immediate operand using FastEmit_ri.
148  /// If that fails, it materializes the immediate into a register and try
149  /// FastEmit_rr instead.
150  unsigned FastEmit_ri_(MVT::SimpleValueType VT,
151                        ISD::NodeType Opcode,
152                        unsigned Op0, uint64_t Imm,
153                        MVT::SimpleValueType ImmType);
154
155  /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
156  /// to emit an instruction with an immediate operand using FastEmit_rf.
157  /// If that fails, it materializes the immediate into a register and try
158  /// FastEmit_rr instead.
159  unsigned FastEmit_rf_(MVT::SimpleValueType VT,
160                        ISD::NodeType Opcode,
161                        unsigned Op0, ConstantFP *FPImm,
162                        MVT::SimpleValueType ImmType);
163
164  /// FastEmit_i - This method is called by target-independent code
165  /// to request that an instruction with the given type, opcode, and
166  /// immediate operand be emitted.
167  virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
168                              MVT::SimpleValueType RetVT,
169                              ISD::NodeType Opcode,
170                              uint64_t Imm);
171
172  /// FastEmit_f - This method is called by target-independent code
173  /// to request that an instruction with the given type, opcode, and
174  /// floating-point immediate operand be emitted.
175  virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
176                              MVT::SimpleValueType RetVT,
177                              ISD::NodeType Opcode,
178                              ConstantFP *FPImm);
179
180  /// FastEmitInst_ - Emit a MachineInstr with no operands and a
181  /// result register in the given register class.
182  ///
183  unsigned FastEmitInst_(unsigned MachineInstOpcode,
184                         const TargetRegisterClass *RC);
185
186  /// FastEmitInst_r - Emit a MachineInstr with one register operand
187  /// and a result register in the given register class.
188  ///
189  unsigned FastEmitInst_r(unsigned MachineInstOpcode,
190                          const TargetRegisterClass *RC,
191                          unsigned Op0);
192
193  /// FastEmitInst_rr - Emit a MachineInstr with two register operands
194  /// and a result register in the given register class.
195  ///
196  unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
197                           const TargetRegisterClass *RC,
198                           unsigned Op0, unsigned Op1);
199
200  /// FastEmitInst_ri - Emit a MachineInstr with two register operands
201  /// and a result register in the given register class.
202  ///
203  unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
204                           const TargetRegisterClass *RC,
205                           unsigned Op0, uint64_t Imm);
206
207  /// FastEmitInst_rf - Emit a MachineInstr with two register operands
208  /// and a result register in the given register class.
209  ///
210  unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
211                           const TargetRegisterClass *RC,
212                           unsigned Op0, ConstantFP *FPImm);
213
214  /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
215  /// an immediate, and a result register in the given register class.
216  ///
217  unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
218                            const TargetRegisterClass *RC,
219                            unsigned Op0, unsigned Op1, uint64_t Imm);
220
221  /// FastEmitInst_i - Emit a MachineInstr with a single immediate
222  /// operand, and a result register in the given register class.
223  unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
224                          const TargetRegisterClass *RC,
225                          uint64_t Imm);
226
227  /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
228  /// from a specified index of a superregister.
229  unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
230
231  void UpdateValueMap(Value* I, unsigned Reg);
232
233  unsigned createResultReg(const TargetRegisterClass *RC);
234
235  /// TargetMaterializeConstant - Emit a constant in a register using
236  /// target-specific logic, such as constant pool loads.
237  virtual unsigned TargetMaterializeConstant(Constant* C,
238                                             MachineConstantPool* MCP) {
239    return 0;
240  }
241
242private:
243  bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
244
245  bool SelectGetElementPtr(User *I);
246
247  bool SelectBitCast(User *I);
248
249  bool SelectCast(User *I, ISD::NodeType Opcode);
250};
251
252}
253
254#endif
255