FastISel.h revision 763d89343be210eb62a13318ca0cc9321ce46bfb 
1//===-- FastISel.h - Definition of the FastISel class ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_FASTISEL_H
15#define LLVM_CODEGEN_FASTISEL_H
16
17#include "llvm/BasicBlock.h"
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/CodeGen/SelectionDAGNodes.h"
20
21namespace llvm {
22
23class MachineBasicBlock;
24class MachineFunction;
25class MachineRegisterInfo;
26class TargetData;
27class TargetInstrInfo;
28class TargetLowering;
29class TargetMachine;
30class TargetRegisterClass;
31
32/// FastISel - This is a fast-path instruction selection class that
33/// generates poor code and doesn't support illegal types or non-trivial
34/// lowering, but runs quickly.
35class FastISel {
36protected:
37  MachineBasicBlock *MBB;
38  MachineFunction &MF;
39  MachineRegisterInfo &MRI;
40  const TargetMachine &TM;
41  const TargetData &TD;
42  const TargetInstrInfo &TII;
43  const TargetLowering &TLI;
44
45public:
46  /// SelectInstructions - Do "fast" instruction selection over the
47  /// LLVM IR instructions in the range [Begin, N) where N is either
48  /// End or the first unsupported instruction. Return N.
49  /// ValueMap is filled in with a mapping of LLVM IR Values to
50  /// virtual register numbers. MBB is a block to which to append
51  /// the generated MachineInstrs.
52  BasicBlock::iterator
53  SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
54                     DenseMap<const Value*, unsigned> &ValueMap,
55                     DenseMap<const BasicBlock*, MachineBasicBlock *> &MBBMap,
56                     MachineBasicBlock *MBB);
57
58  virtual ~FastISel();
59
60protected:
61  explicit FastISel(MachineFunction &mf);
62
63  /// FastEmit_r - This method is called by target-independent code
64  /// to request that an instruction with the given type and opcode
65  /// be emitted.
66  virtual unsigned FastEmit_(MVT::SimpleValueType VT,
67                             MVT::SimpleValueType RetVT,
68                             ISD::NodeType Opcode);
69
70  /// FastEmit_r - This method is called by target-independent code
71  /// to request that an instruction with the given type, opcode, and
72  /// register operand be emitted.
73  ///
74  virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
75                              MVT::SimpleValueType RetVT,
76                              ISD::NodeType Opcode, unsigned Op0);
77
78  /// FastEmit_rr - This method is called by target-independent code
79  /// to request that an instruction with the given type, opcode, and
80  /// register operands be emitted.
81  ///
82  virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
83                               MVT::SimpleValueType RetVT,
84                               ISD::NodeType Opcode,
85                               unsigned Op0, unsigned Op1);
86
87  /// FastEmit_ri - This method is called by target-independent code
88  /// to request that an instruction with the given type, opcode, and
89  /// register and immediate operands be emitted.
90  ///
91  virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
92                               MVT::SimpleValueType RetVT,
93                               ISD::NodeType Opcode,
94                               unsigned Op0, uint64_t Imm);
95
96  /// FastEmit_rri - This method is called by target-independent code
97  /// to request that an instruction with the given type, opcode, and
98  /// register and immediate operands be emitted.
99  ///
100  virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
101                                MVT::SimpleValueType RetVT,
102                                ISD::NodeType Opcode,
103                                unsigned Op0, unsigned Op1, uint64_t Imm);
104
105  /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
106  /// to emit an instruction with an immediate operand using FastEmit_ri.
107  /// If that fails, it materializes the immediate into a register and try
108  /// FastEmit_rr instead.
109  unsigned FastEmit_ri_(MVT::SimpleValueType VT,
110                        ISD::NodeType Opcode,
111                        unsigned Op0, uint64_t Imm,
112                        MVT::SimpleValueType ImmType);
113
114  /// FastEmit_i - This method is called by target-independent code
115  /// to request that an instruction with the given type, opcode, and
116  /// immediate operand be emitted.
117  virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
118                              MVT::SimpleValueType RetVT,
119                              ISD::NodeType Opcode,
120                              uint64_t Imm);
121
122  /// FastEmitInst_ - Emit a MachineInstr with no operands and a
123  /// result register in the given register class.
124  ///
125  unsigned FastEmitInst_(unsigned MachineInstOpcode,
126                         const TargetRegisterClass *RC);
127
128  /// FastEmitInst_r - Emit a MachineInstr with one register operand
129  /// and a result register in the given register class.
130  ///
131  unsigned FastEmitInst_r(unsigned MachineInstOpcode,
132                          const TargetRegisterClass *RC,
133                          unsigned Op0);
134
135  /// FastEmitInst_rr - Emit a MachineInstr with two register operands
136  /// and a result register in the given register class.
137  ///
138  unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
139                           const TargetRegisterClass *RC,
140                           unsigned Op0, unsigned Op1);
141
142  /// FastEmitInst_ri - Emit a MachineInstr with two register operands
143  /// and a result register in the given register class.
144  ///
145  unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
146                           const TargetRegisterClass *RC,
147                           unsigned Op0, uint64_t Imm);
148
149  /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
150  /// an immediate, and a result register in the given register class.
151  ///
152  unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
153                            const TargetRegisterClass *RC,
154                            unsigned Op0, unsigned Op1, uint64_t Imm);
155
156  /// FastEmitInst_i - Emit a MachineInstr with a single immediate
157  /// operand, and a result register in the given register class.
158  unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
159                          const TargetRegisterClass *RC,
160                          uint64_t Imm);
161
162private:
163  unsigned createResultReg(const TargetRegisterClass *RC);
164
165  bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
166                      DenseMap<const Value*, unsigned> &ValueMap);
167
168  bool SelectGetElementPtr(Instruction *I,
169                           DenseMap<const Value*, unsigned> &ValueMap);
170
171  bool SelectBitCast(Instruction *I,
172                     DenseMap<const Value*, unsigned> &ValueMap);
173};
174
175}
176
177#endif
178